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accel/tcg: remove link between guest ram and TCG cache size
[qemu/ar7.git] / hw / riscv / virt.c
blob7f9e1e5176f016fbbcd5f3f16a88bc7d4c03e530
1 /*
2 * QEMU RISC-V VirtIO Board
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * RISC-V machine with 16550a UART and VirtIO MMIO
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include "qemu/log.h"
24 #include "qemu/error-report.h"
25 #include "qapi/error.h"
26 #include "hw/boards.h"
27 #include "hw/loader.h"
28 #include "hw/sysbus.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial.h"
31 #include "target/riscv/cpu.h"
32 #include "hw/riscv/riscv_hart.h"
33 #include "hw/riscv/sifive_plic.h"
34 #include "hw/riscv/sifive_clint.h"
35 #include "hw/riscv/sifive_test.h"
36 #include "hw/riscv/virt.h"
37 #include "hw/riscv/boot.h"
38 #include "chardev/char.h"
39 #include "sysemu/arch_init.h"
40 #include "sysemu/device_tree.h"
41 #include "sysemu/sysemu.h"
42 #include "exec/address-spaces.h"
43 #include "hw/pci/pci.h"
44 #include "hw/pci-host/gpex.h"
45
46 #include <libfdt.h>
47
48 #if defined(TARGET_RISCV32)
49 # define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin"
50 #else
51 # define BIOS_FILENAME "opensbi-riscv64-virt-fw_jump.bin"
52 #endif
53
54 static const struct MemmapEntry {
55 hwaddr base;
56 hwaddr size;
57 } virt_memmap[] = {
58 [VIRT_DEBUG] = { 0x0, 0x100 },
59 [VIRT_MROM] = { 0x1000, 0x11000 },
60 [VIRT_TEST] = { 0x100000, 0x1000 },
61 [VIRT_RTC] = { 0x101000, 0x1000 },
62 [VIRT_CLINT] = { 0x2000000, 0x10000 },
63 [VIRT_PLIC] = { 0xc000000, 0x4000000 },
64 [VIRT_UART0] = { 0x10000000, 0x100 },
65 [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
66 [VIRT_FLASH] = { 0x20000000, 0x4000000 },
67 [VIRT_DRAM] = { 0x80000000, 0x0 },
68 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
69 [VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 },
70 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
71 };
72
73 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
74
75 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
76 const char *name,
77 const char *alias_prop_name)
78 {
79 /*
80 * Create a single flash device. We use the same parameters as
81 * the flash devices on the ARM virt board.
82 */
83 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
84
85 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
86 qdev_prop_set_uint8(dev, "width", 4);
87 qdev_prop_set_uint8(dev, "device-width", 2);
88 qdev_prop_set_bit(dev, "big-endian", false);
89 qdev_prop_set_uint16(dev, "id0", 0x89);
90 qdev_prop_set_uint16(dev, "id1", 0x18);
91 qdev_prop_set_uint16(dev, "id2", 0x00);
92 qdev_prop_set_uint16(dev, "id3", 0x00);
93 qdev_prop_set_string(dev, "name", name);
94
95 object_property_add_child(OBJECT(s), name, OBJECT(dev),
96 &error_abort);
97 object_property_add_alias(OBJECT(s), alias_prop_name,
98 OBJECT(dev), "drive", &error_abort);
99
100 return PFLASH_CFI01(dev);
101 }
102
103 static void virt_flash_create(RISCVVirtState *s)
104 {
105 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
106 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
107 }
108
109 static void virt_flash_map1(PFlashCFI01 *flash,
110 hwaddr base, hwaddr size,
111 MemoryRegion *sysmem)
112 {
113 DeviceState *dev = DEVICE(flash);
114
115 assert(size % VIRT_FLASH_SECTOR_SIZE == 0);
116 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
117 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
118 qdev_init_nofail(dev);
119
120 memory_region_add_subregion(sysmem, base,
121 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
122 0));
123 }
124
125 static void virt_flash_map(RISCVVirtState *s,
126 MemoryRegion *sysmem)
127 {
128 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
129 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
130
131 virt_flash_map1(s->flash[0], flashbase, flashsize,
132 sysmem);
133 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
134 sysmem);
135 }
136
137 static void create_pcie_irq_map(void *fdt, char *nodename,
138 uint32_t plic_phandle)
139 {
140 int pin, dev;
141 uint32_t
142 full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
143 uint32_t *irq_map = full_irq_map;
144
145 /* This code creates a standard swizzle of interrupts such that
146 * each device's first interrupt is based on it's PCI_SLOT number.
147 * (See pci_swizzle_map_irq_fn())
148 *
149 * We only need one entry per interrupt in the table (not one per
150 * possible slot) seeing the interrupt-map-mask will allow the table
151 * to wrap to any number of devices.
152 */
153 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
154 int devfn = dev * 0x8;
155
156 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
157 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
158 int i = 0;
159
160 irq_map[i] = cpu_to_be32(devfn << 8);
161
162 i += FDT_PCI_ADDR_CELLS;
163 irq_map[i] = cpu_to_be32(pin + 1);
164
165 i += FDT_PCI_INT_CELLS;
166 irq_map[i++] = cpu_to_be32(plic_phandle);
167
168 i += FDT_PLIC_ADDR_CELLS;
169 irq_map[i] = cpu_to_be32(irq_nr);
170
171 irq_map += FDT_INT_MAP_WIDTH;
172 }
173 }
174
175 qemu_fdt_setprop(fdt, nodename, "interrupt-map",
176 full_irq_map, sizeof(full_irq_map));
177
178 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
179 0x1800, 0, 0, 0x7);
180 }
181
182 static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
183 uint64_t mem_size, const char *cmdline)
184 {
185 void *fdt;
186 int cpu, i;
187 uint32_t *cells;
188 char *nodename;
189 uint32_t plic_phandle, test_phandle, phandle = 1;
190 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
191 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
192
193 fdt = s->fdt = create_device_tree(&s->fdt_size);
194 if (!fdt) {
195 error_report("create_device_tree() failed");
196 exit(1);
197 }
198
199 qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
200 qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
201 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
202 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
203
204 qemu_fdt_add_subnode(fdt, "/soc");
205 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
206 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
207 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
208 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
209
210 nodename = g_strdup_printf("/memory@%lx",
211 (long)memmap[VIRT_DRAM].base);
212 qemu_fdt_add_subnode(fdt, nodename);
213 qemu_fdt_setprop_cells(fdt, nodename, "reg",
214 memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
215 mem_size >> 32, mem_size);
216 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
217 g_free(nodename);
218
219 qemu_fdt_add_subnode(fdt, "/cpus");
220 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
221 SIFIVE_CLINT_TIMEBASE_FREQ);
222 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
223 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
224
225 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
226 int cpu_phandle = phandle++;
227 int intc_phandle;
228 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
229 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
230 char *isa = riscv_isa_string(&s->soc.harts[cpu]);
231 qemu_fdt_add_subnode(fdt, nodename);
232 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
233 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
234 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
235 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
236 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
237 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
238 qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
239 intc_phandle = phandle++;
240 qemu_fdt_add_subnode(fdt, intc);
241 qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
242 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
243 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
244 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
245 g_free(isa);
246 g_free(intc);
247 g_free(nodename);
248 }
249
250 /* Add cpu-topology node */
251 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
252 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0");
253 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
254 char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
255 cpu);
256 char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
257 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename);
258 qemu_fdt_add_subnode(fdt, core_nodename);
259 qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle);
260 g_free(core_nodename);
261 g_free(cpu_nodename);
262 }
263
264 cells = g_new0(uint32_t, s->soc.num_harts * 4);
265 for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
266 nodename =
267 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
268 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
269 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
270 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
271 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
272 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
273 g_free(nodename);
274 }
275 nodename = g_strdup_printf("/soc/clint@%lx",
276 (long)memmap[VIRT_CLINT].base);
277 qemu_fdt_add_subnode(fdt, nodename);
278 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
279 qemu_fdt_setprop_cells(fdt, nodename, "reg",
280 0x0, memmap[VIRT_CLINT].base,
281 0x0, memmap[VIRT_CLINT].size);
282 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
283 cells, s->soc.num_harts * sizeof(uint32_t) * 4);
284 g_free(cells);
285 g_free(nodename);
286
287 plic_phandle = phandle++;
288 cells = g_new0(uint32_t, s->soc.num_harts * 4);
289 for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
290 nodename =
291 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
292 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
293 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
294 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
295 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
296 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
297 g_free(nodename);
298 }
299 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
300 (long)memmap[VIRT_PLIC].base);
301 qemu_fdt_add_subnode(fdt, nodename);
302 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
303 FDT_PLIC_ADDR_CELLS);
304 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
305 FDT_PLIC_INT_CELLS);
306 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
307 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
308 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
309 cells, s->soc.num_harts * sizeof(uint32_t) * 4);
310 qemu_fdt_setprop_cells(fdt, nodename, "reg",
311 0x0, memmap[VIRT_PLIC].base,
312 0x0, memmap[VIRT_PLIC].size);
313 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
314 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
315 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
316 g_free(cells);
317 g_free(nodename);
318
319 for (i = 0; i < VIRTIO_COUNT; i++) {
320 nodename = g_strdup_printf("/virtio_mmio@%lx",
321 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
322 qemu_fdt_add_subnode(fdt, nodename);
323 qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
324 qemu_fdt_setprop_cells(fdt, nodename, "reg",
325 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
326 0x0, memmap[VIRT_VIRTIO].size);
327 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
328 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
329 g_free(nodename);
330 }
331
332 nodename = g_strdup_printf("/soc/pci@%lx",
333 (long) memmap[VIRT_PCIE_ECAM].base);
334 qemu_fdt_add_subnode(fdt, nodename);
335 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
336 FDT_PCI_ADDR_CELLS);
337 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
338 FDT_PCI_INT_CELLS);
339 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2);
340 qemu_fdt_setprop_string(fdt, nodename, "compatible",
341 "pci-host-ecam-generic");
342 qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
343 qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
344 qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
345 memmap[VIRT_PCIE_ECAM].size /
346 PCIE_MMCFG_SIZE_MIN - 1);
347 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
348 qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
349 0, memmap[VIRT_PCIE_ECAM].size);
350 qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges",
351 1, FDT_PCI_RANGE_IOPORT, 2, 0,
352 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
353 1, FDT_PCI_RANGE_MMIO,
354 2, memmap[VIRT_PCIE_MMIO].base,
355 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
356 create_pcie_irq_map(fdt, nodename, plic_phandle);
357 g_free(nodename);
358
359 test_phandle = phandle++;
360 nodename = g_strdup_printf("/test@%lx",
361 (long)memmap[VIRT_TEST].base);
362 qemu_fdt_add_subnode(fdt, nodename);
363 {
364 const char compat[] = "sifive,test1\0sifive,test0\0syscon";
365 qemu_fdt_setprop(fdt, nodename, "compatible", compat, sizeof(compat));
366 }
367 qemu_fdt_setprop_cells(fdt, nodename, "reg",
368 0x0, memmap[VIRT_TEST].base,
369 0x0, memmap[VIRT_TEST].size);
370 qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_phandle);
371 test_phandle = qemu_fdt_get_phandle(fdt, nodename);
372 g_free(nodename);
373
374 nodename = g_strdup_printf("/reboot");
375 qemu_fdt_add_subnode(fdt, nodename);
376 qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot");
377 qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
378 qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
379 qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET);
380 g_free(nodename);
381
382 nodename = g_strdup_printf("/poweroff");
383 qemu_fdt_add_subnode(fdt, nodename);
384 qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff");
385 qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
386 qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
387 qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS);
388 g_free(nodename);
389
390 nodename = g_strdup_printf("/uart@%lx",
391 (long)memmap[VIRT_UART0].base);
392 qemu_fdt_add_subnode(fdt, nodename);
393 qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
394 qemu_fdt_setprop_cells(fdt, nodename, "reg",
395 0x0, memmap[VIRT_UART0].base,
396 0x0, memmap[VIRT_UART0].size);
397 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
398 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
399 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ);
400
401 qemu_fdt_add_subnode(fdt, "/chosen");
402 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
403 if (cmdline) {
404 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
405 }
406 g_free(nodename);
407
408 nodename = g_strdup_printf("/rtc@%lx",
409 (long)memmap[VIRT_RTC].base);
410 qemu_fdt_add_subnode(fdt, nodename);
411 qemu_fdt_setprop_string(fdt, nodename, "compatible",
412 "google,goldfish-rtc");
413 qemu_fdt_setprop_cells(fdt, nodename, "reg",
414 0x0, memmap[VIRT_RTC].base,
415 0x0, memmap[VIRT_RTC].size);
416 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
417 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", RTC_IRQ);
418 g_free(nodename);
419
420 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
421 qemu_fdt_add_subnode(s->fdt, nodename);
422 qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash");
423 qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
424 2, flashbase, 2, flashsize,
425 2, flashbase + flashsize, 2, flashsize);
426 qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4);
427 g_free(nodename);
428 }
429
430
431 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
432 hwaddr ecam_base, hwaddr ecam_size,
433 hwaddr mmio_base, hwaddr mmio_size,
434 hwaddr pio_base,
435 DeviceState *plic, bool link_up)
436 {
437 DeviceState *dev;
438 MemoryRegion *ecam_alias, *ecam_reg;
439 MemoryRegion *mmio_alias, *mmio_reg;
440 qemu_irq irq;
441 int i;
442
443 dev = qdev_create(NULL, TYPE_GPEX_HOST);
444
445 qdev_init_nofail(dev);
446
447 ecam_alias = g_new0(MemoryRegion, 1);
448 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
449 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
450 ecam_reg, 0, ecam_size);
451 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
452
453 mmio_alias = g_new0(MemoryRegion, 1);
454 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
455 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
456 mmio_reg, mmio_base, mmio_size);
457 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
458
459 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
460
461 for (i = 0; i < GPEX_NUM_IRQS; i++) {
462 irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
463
464 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
465 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
466 }
467
468 return dev;
469 }
470
471 static void riscv_virt_board_init(MachineState *machine)
472 {
473 const struct MemmapEntry *memmap = virt_memmap;
474 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
475 MemoryRegion *system_memory = get_system_memory();
476 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
477 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
478 char *plic_hart_config;
479 size_t plic_hart_config_len;
480 target_ulong start_addr = memmap[VIRT_DRAM].base;
481 int i;
482 unsigned int smp_cpus = machine->smp.cpus;
483
484 /* Initialize SOC */
485 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
486 TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
487 object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
488 &error_abort);
489 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
490 &error_abort);
491 object_property_set_bool(OBJECT(&s->soc), true, "realized",
492 &error_abort);
493
494 /* register system main memory (actual RAM) */
495 memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
496 machine->ram_size, &error_fatal);
497 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
498 main_mem);
499
500 /* create device tree */
501 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
502
503 /* boot rom */
504 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
505 memmap[VIRT_MROM].size, &error_fatal);
506 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
507 mask_rom);
508
509 riscv_find_and_load_firmware(machine, BIOS_FILENAME,
510 memmap[VIRT_DRAM].base);
511
512 if (machine->kernel_filename) {
513 uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
514 NULL);
515
516 if (machine->initrd_filename) {
517 hwaddr start;
518 hwaddr end = riscv_load_initrd(machine->initrd_filename,
519 machine->ram_size, kernel_entry,
520 &start);
521 qemu_fdt_setprop_cell(s->fdt, "/chosen",
522 "linux,initrd-start", start);
523 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
524 end);
525 }
526 }
527
528 if (drive_get(IF_PFLASH, 0, 0)) {
529 /*
530 * Pflash was supplied, let's overwrite the address we jump to after
531 * reset to the base of the flash.
532 */
533 start_addr = virt_memmap[VIRT_FLASH].base;
534 }
535
536 /* reset vector */
537 uint32_t reset_vec[8] = {
538 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
539 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
540 0xf1402573, /* csrr a0, mhartid */
541 #if defined(TARGET_RISCV32)
542 0x0182a283, /* lw t0, 24(t0) */
543 #elif defined(TARGET_RISCV64)
544 0x0182b283, /* ld t0, 24(t0) */
545 #endif
546 0x00028067, /* jr t0 */
547 0x00000000,
548 start_addr, /* start: .dword */
549 0x00000000,
550 /* dtb: */
551 };
552
553 /* copy in the reset vector in little_endian byte order */
554 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
555 reset_vec[i] = cpu_to_le32(reset_vec[i]);
556 }
557 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
558 memmap[VIRT_MROM].base, &address_space_memory);
559
560 /* copy in the device tree */
561 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
562 memmap[VIRT_MROM].size - sizeof(reset_vec)) {
563 error_report("not enough space to store device-tree");
564 exit(1);
565 }
566 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
567 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
568 memmap[VIRT_MROM].base + sizeof(reset_vec),
569 &address_space_memory);
570
571 /* create PLIC hart topology configuration string */
572 plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
573 plic_hart_config = g_malloc0(plic_hart_config_len);
574 for (i = 0; i < smp_cpus; i++) {
575 if (i != 0) {
576 strncat(plic_hart_config, ",", plic_hart_config_len);
577 }
578 strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
579 plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
580 }
581
582 /* MMIO */
583 s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
584 plic_hart_config,
585 VIRT_PLIC_NUM_SOURCES,
586 VIRT_PLIC_NUM_PRIORITIES,
587 VIRT_PLIC_PRIORITY_BASE,
588 VIRT_PLIC_PENDING_BASE,
589 VIRT_PLIC_ENABLE_BASE,
590 VIRT_PLIC_ENABLE_STRIDE,
591 VIRT_PLIC_CONTEXT_BASE,
592 VIRT_PLIC_CONTEXT_STRIDE,
593 memmap[VIRT_PLIC].size);
594 sifive_clint_create(memmap[VIRT_CLINT].base,
595 memmap[VIRT_CLINT].size, smp_cpus,
596 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
597 sifive_test_create(memmap[VIRT_TEST].base);
598
599 for (i = 0; i < VIRTIO_COUNT; i++) {
600 sysbus_create_simple("virtio-mmio",
601 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
602 qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
603 }
604
605 gpex_pcie_init(system_memory,
606 memmap[VIRT_PCIE_ECAM].base,
607 memmap[VIRT_PCIE_ECAM].size,
608 memmap[VIRT_PCIE_MMIO].base,
609 memmap[VIRT_PCIE_MMIO].size,
610 memmap[VIRT_PCIE_PIO].base,
611 DEVICE(s->plic), true);
612
613 serial_mm_init(system_memory, memmap[VIRT_UART0].base,
614 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
615 serial_hd(0), DEVICE_LITTLE_ENDIAN);
616
617 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
618 qdev_get_gpio_in(DEVICE(s->plic), RTC_IRQ));
619
620 virt_flash_create(s);
621
622 for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
623 /* Map legacy -drive if=pflash to machine properties */
624 pflash_cfi01_legacy_drive(s->flash[i],
625 drive_get(IF_PFLASH, 0, i));
626 }
627 virt_flash_map(s, system_memory);
628
629 g_free(plic_hart_config);
630 }
631
632 static void riscv_virt_machine_instance_init(Object *obj)
633 {
634 }
635
636 static void riscv_virt_machine_class_init(ObjectClass *oc, void *data)
637 {
638 MachineClass *mc = MACHINE_CLASS(oc);
639
640 mc->desc = "RISC-V VirtIO board";
641 mc->init = riscv_virt_board_init;
642 mc->max_cpus = 8;
643 mc->default_cpu_type = VIRT_CPU;
644 }
645
646 static const TypeInfo riscv_virt_machine_typeinfo = {
647 .name = MACHINE_TYPE_NAME("virt"),
648 .parent = TYPE_MACHINE,
649 .class_init = riscv_virt_machine_class_init,
650 .instance_init = riscv_virt_machine_instance_init,
651 .instance_size = sizeof(RISCVVirtState),
652 };
653
654 static void riscv_virt_machine_init_register_types(void)
655 {
656 type_register_static(&riscv_virt_machine_typeinfo);
657 }
658
659 type_init(riscv_virt_machine_init_register_types)
AR7 emulation for QEMU