?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target/ppc: Generate fence operations
[qemu/ar7.git] / target / ppc / translate.c
blob4a1f24a54f4b135cb385175af5dc71e85dd12990
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg-op.h"
27 #include "qemu/host-utils.h"
28 #include "exec/cpu_ldst.h"
29
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32
33 #include "trace-tcg.h"
34 #include "exec/log.h"
35
36
37 #define CPU_SINGLE_STEP 0x1
38 #define CPU_BRANCH_STEP 0x2
39 #define GDBSTUB_SINGLE_STEP 0x4
40
41 /* Include definitions for instructions classes and implementations flags */
42 //#define PPC_DEBUG_DISAS
43 //#define DO_PPC_STATISTICS
44
45 #ifdef PPC_DEBUG_DISAS
46 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 # define LOG_DISAS(...) do { } while (0)
49 #endif
50 /*****************************************************************************/
51 /* Code translation helpers */
52
53 /* global register indexes */
54 static TCGv_env cpu_env;
55 static char cpu_reg_names[10*3 + 22*4 /* GPR */
56 + 10*4 + 22*5 /* SPE GPRh */
57 + 10*4 + 22*5 /* FPR */
58 + 2*(10*6 + 22*7) /* AVRh, AVRl */
59 + 10*5 + 22*6 /* VSR */
60 + 8*5 /* CRF */];
61 static TCGv cpu_gpr[32];
62 static TCGv cpu_gprh[32];
63 static TCGv_i64 cpu_fpr[32];
64 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
65 static TCGv_i64 cpu_vsr[32];
66 static TCGv_i32 cpu_crf[8];
67 static TCGv cpu_nip;
68 static TCGv cpu_msr;
69 static TCGv cpu_ctr;
70 static TCGv cpu_lr;
71 #if defined(TARGET_PPC64)
72 static TCGv cpu_cfar;
73 #endif
74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
75 static TCGv cpu_reserve;
76 static TCGv cpu_reserve_val;
77 static TCGv cpu_fpscr;
78 static TCGv_i32 cpu_access_type;
79
80 #include "exec/gen-icount.h"
81
82 void ppc_translate_init(void)
83 {
84 int i;
85 char* p;
86 size_t cpu_reg_names_size;
87 static int done_init = 0;
88
89 if (done_init)
90 return;
91
92 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
93 tcg_ctx.tcg_env = cpu_env;
94
95 p = cpu_reg_names;
96 cpu_reg_names_size = sizeof(cpu_reg_names);
97
98 for (i = 0; i < 8; i++) {
99 snprintf(p, cpu_reg_names_size, "crf%d", i);
100 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
101 offsetof(CPUPPCState, crf[i]), p);
102 p += 5;
103 cpu_reg_names_size -= 5;
104 }
105
106 for (i = 0; i < 32; i++) {
107 snprintf(p, cpu_reg_names_size, "r%d", i);
108 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
109 offsetof(CPUPPCState, gpr[i]), p);
110 p += (i < 10) ? 3 : 4;
111 cpu_reg_names_size -= (i < 10) ? 3 : 4;
112 snprintf(p, cpu_reg_names_size, "r%dH", i);
113 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
114 offsetof(CPUPPCState, gprh[i]), p);
115 p += (i < 10) ? 4 : 5;
116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
117
118 snprintf(p, cpu_reg_names_size, "fp%d", i);
119 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
120 offsetof(CPUPPCState, fpr[i]), p);
121 p += (i < 10) ? 4 : 5;
122 cpu_reg_names_size -= (i < 10) ? 4 : 5;
123
124 snprintf(p, cpu_reg_names_size, "avr%dH", i);
125 #ifdef HOST_WORDS_BIGENDIAN
126 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
127 offsetof(CPUPPCState, avr[i].u64[0]), p);
128 #else
129 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
130 offsetof(CPUPPCState, avr[i].u64[1]), p);
131 #endif
132 p += (i < 10) ? 6 : 7;
133 cpu_reg_names_size -= (i < 10) ? 6 : 7;
134
135 snprintf(p, cpu_reg_names_size, "avr%dL", i);
136 #ifdef HOST_WORDS_BIGENDIAN
137 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
138 offsetof(CPUPPCState, avr[i].u64[1]), p);
139 #else
140 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
141 offsetof(CPUPPCState, avr[i].u64[0]), p);
142 #endif
143 p += (i < 10) ? 6 : 7;
144 cpu_reg_names_size -= (i < 10) ? 6 : 7;
145 snprintf(p, cpu_reg_names_size, "vsr%d", i);
146 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
147 offsetof(CPUPPCState, vsr[i]), p);
148 p += (i < 10) ? 5 : 6;
149 cpu_reg_names_size -= (i < 10) ? 5 : 6;
150 }
151
152 cpu_nip = tcg_global_mem_new(cpu_env,
153 offsetof(CPUPPCState, nip), "nip");
154
155 cpu_msr = tcg_global_mem_new(cpu_env,
156 offsetof(CPUPPCState, msr), "msr");
157
158 cpu_ctr = tcg_global_mem_new(cpu_env,
159 offsetof(CPUPPCState, ctr), "ctr");
160
161 cpu_lr = tcg_global_mem_new(cpu_env,
162 offsetof(CPUPPCState, lr), "lr");
163
164 #if defined(TARGET_PPC64)
165 cpu_cfar = tcg_global_mem_new(cpu_env,
166 offsetof(CPUPPCState, cfar), "cfar");
167 #endif
168
169 cpu_xer = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, xer), "xer");
171 cpu_so = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, so), "SO");
173 cpu_ov = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ov), "OV");
175 cpu_ca = tcg_global_mem_new(cpu_env,
176 offsetof(CPUPPCState, ca), "CA");
177 cpu_ov32 = tcg_global_mem_new(cpu_env,
178 offsetof(CPUPPCState, ov32), "OV32");
179 cpu_ca32 = tcg_global_mem_new(cpu_env,
180 offsetof(CPUPPCState, ca32), "CA32");
181
182 cpu_reserve = tcg_global_mem_new(cpu_env,
183 offsetof(CPUPPCState, reserve_addr),
184 "reserve_addr");
185 cpu_reserve_val = tcg_global_mem_new(cpu_env,
186 offsetof(CPUPPCState, reserve_val),
187 "reserve_val");
188
189 cpu_fpscr = tcg_global_mem_new(cpu_env,
190 offsetof(CPUPPCState, fpscr), "fpscr");
191
192 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
193 offsetof(CPUPPCState, access_type), "access_type");
194
195 done_init = 1;
196 }
197
198 /* internal defines */
199 struct DisasContext {
200 struct TranslationBlock *tb;
201 target_ulong nip;
202 uint32_t opcode;
203 uint32_t exception;
204 /* Routine used to access memory */
205 bool pr, hv, dr, le_mode;
206 bool lazy_tlb_flush;
207 bool need_access_type;
208 int mem_idx;
209 int access_type;
210 /* Translation flags */
211 TCGMemOp default_tcg_memop_mask;
212 #if defined(TARGET_PPC64)
213 bool sf_mode;
214 bool has_cfar;
215 #endif
216 bool fpu_enabled;
217 bool altivec_enabled;
218 bool vsx_enabled;
219 bool spe_enabled;
220 bool tm_enabled;
221 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
222 int singlestep_enabled;
223 uint64_t insns_flags;
224 uint64_t insns_flags2;
225 };
226
227 /* Return true iff byteswap is needed in a scalar memop */
228 static inline bool need_byteswap(const DisasContext *ctx)
229 {
230 #if defined(TARGET_WORDS_BIGENDIAN)
231 return ctx->le_mode;
232 #else
233 return !ctx->le_mode;
234 #endif
235 }
236
237 /* True when active word size < size of target_long. */
238 #ifdef TARGET_PPC64
239 # define NARROW_MODE(C) (!(C)->sf_mode)
240 #else
241 # define NARROW_MODE(C) 0
242 #endif
243
244 struct opc_handler_t {
245 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
246 uint32_t inval1;
247 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
248 uint32_t inval2;
249 /* instruction type */
250 uint64_t type;
251 /* extended instruction type */
252 uint64_t type2;
253 /* handler */
254 void (*handler)(DisasContext *ctx);
255 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
256 const char *oname;
257 #endif
258 #if defined(DO_PPC_STATISTICS)
259 uint64_t count;
260 #endif
261 };
262
263 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
264 {
265 if (ctx->need_access_type && ctx->access_type != access_type) {
266 tcg_gen_movi_i32(cpu_access_type, access_type);
267 ctx->access_type = access_type;
268 }
269 }
270
271 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
272 {
273 if (NARROW_MODE(ctx)) {
274 nip = (uint32_t)nip;
275 }
276 tcg_gen_movi_tl(cpu_nip, nip);
277 }
278
279 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
280 {
281 TCGv_i32 t0, t1;
282
283 /* These are all synchronous exceptions, we set the PC back to
284 * the faulting instruction
285 */
286 if (ctx->exception == POWERPC_EXCP_NONE) {
287 gen_update_nip(ctx, ctx->nip - 4);
288 }
289 t0 = tcg_const_i32(excp);
290 t1 = tcg_const_i32(error);
291 gen_helper_raise_exception_err(cpu_env, t0, t1);
292 tcg_temp_free_i32(t0);
293 tcg_temp_free_i32(t1);
294 ctx->exception = (excp);
295 }
296
297 static void gen_exception(DisasContext *ctx, uint32_t excp)
298 {
299 TCGv_i32 t0;
300
301 /* These are all synchronous exceptions, we set the PC back to
302 * the faulting instruction
303 */
304 if (ctx->exception == POWERPC_EXCP_NONE) {
305 gen_update_nip(ctx, ctx->nip - 4);
306 }
307 t0 = tcg_const_i32(excp);
308 gen_helper_raise_exception(cpu_env, t0);
309 tcg_temp_free_i32(t0);
310 ctx->exception = (excp);
311 }
312
313 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
314 target_ulong nip)
315 {
316 TCGv_i32 t0;
317
318 gen_update_nip(ctx, nip);
319 t0 = tcg_const_i32(excp);
320 gen_helper_raise_exception(cpu_env, t0);
321 tcg_temp_free_i32(t0);
322 ctx->exception = (excp);
323 }
324
325 static void gen_debug_exception(DisasContext *ctx)
326 {
327 TCGv_i32 t0;
328
329 /* These are all synchronous exceptions, we set the PC back to
330 * the faulting instruction
331 */
332 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
333 (ctx->exception != POWERPC_EXCP_SYNC)) {
334 gen_update_nip(ctx, ctx->nip);
335 }
336 t0 = tcg_const_i32(EXCP_DEBUG);
337 gen_helper_raise_exception(cpu_env, t0);
338 tcg_temp_free_i32(t0);
339 }
340
341 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
342 {
343 /* Will be converted to program check if needed */
344 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
345 }
346
347 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
348 {
349 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
350 }
351
352 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
353 {
354 /* Will be converted to program check if needed */
355 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
356 }
357
358 /* Stop translation */
359 static inline void gen_stop_exception(DisasContext *ctx)
360 {
361 gen_update_nip(ctx, ctx->nip);
362 ctx->exception = POWERPC_EXCP_STOP;
363 }
364
365 #ifndef CONFIG_USER_ONLY
366 /* No need to update nip here, as execution flow will change */
367 static inline void gen_sync_exception(DisasContext *ctx)
368 {
369 ctx->exception = POWERPC_EXCP_SYNC;
370 }
371 #endif
372
373 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
374 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
375
376 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
377 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
378
379 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
380 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
381
382 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
383 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
384
385 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
386 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
387
388 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
389 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
390
391 typedef struct opcode_t {
392 unsigned char opc1, opc2, opc3, opc4;
393 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
394 unsigned char pad[4];
395 #endif
396 opc_handler_t handler;
397 const char *oname;
398 } opcode_t;
399
400 /* Helpers for priv. check */
401 #define GEN_PRIV \
402 do { \
403 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
404 } while (0)
405
406 #if defined(CONFIG_USER_ONLY)
407 #define CHK_HV GEN_PRIV
408 #define CHK_SV GEN_PRIV
409 #define CHK_HVRM GEN_PRIV
410 #else
411 #define CHK_HV \
412 do { \
413 if (unlikely(ctx->pr || !ctx->hv)) { \
414 GEN_PRIV; \
415 } \
416 } while (0)
417 #define CHK_SV \
418 do { \
419 if (unlikely(ctx->pr)) { \
420 GEN_PRIV; \
421 } \
422 } while (0)
423 #define CHK_HVRM \
424 do { \
425 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
426 GEN_PRIV; \
427 } \
428 } while (0)
429 #endif
430
431 #define CHK_NONE
432
433 /*****************************************************************************/
434 /* PowerPC instructions table */
435
436 #if defined(DO_PPC_STATISTICS)
437 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
438 { \
439 .opc1 = op1, \
440 .opc2 = op2, \
441 .opc3 = op3, \
442 .opc4 = 0xff, \
443 .handler = { \
444 .inval1 = invl, \
445 .type = _typ, \
446 .type2 = _typ2, \
447 .handler = &gen_##name, \
448 .oname = stringify(name), \
449 }, \
450 .oname = stringify(name), \
451 }
452 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
453 { \
454 .opc1 = op1, \
455 .opc2 = op2, \
456 .opc3 = op3, \
457 .opc4 = 0xff, \
458 .handler = { \
459 .inval1 = invl1, \
460 .inval2 = invl2, \
461 .type = _typ, \
462 .type2 = _typ2, \
463 .handler = &gen_##name, \
464 .oname = stringify(name), \
465 }, \
466 .oname = stringify(name), \
467 }
468 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
469 { \
470 .opc1 = op1, \
471 .opc2 = op2, \
472 .opc3 = op3, \
473 .opc4 = 0xff, \
474 .handler = { \
475 .inval1 = invl, \
476 .type = _typ, \
477 .type2 = _typ2, \
478 .handler = &gen_##name, \
479 .oname = onam, \
480 }, \
481 .oname = onam, \
482 }
483 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
484 { \
485 .opc1 = op1, \
486 .opc2 = op2, \
487 .opc3 = op3, \
488 .opc4 = op4, \
489 .handler = { \
490 .inval1 = invl, \
491 .type = _typ, \
492 .type2 = _typ2, \
493 .handler = &gen_##name, \
494 .oname = stringify(name), \
495 }, \
496 .oname = stringify(name), \
497 }
498 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
499 { \
500 .opc1 = op1, \
501 .opc2 = op2, \
502 .opc3 = op3, \
503 .opc4 = op4, \
504 .handler = { \
505 .inval1 = invl, \
506 .type = _typ, \
507 .type2 = _typ2, \
508 .handler = &gen_##name, \
509 .oname = onam, \
510 }, \
511 .oname = onam, \
512 }
513 #else
514 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
515 { \
516 .opc1 = op1, \
517 .opc2 = op2, \
518 .opc3 = op3, \
519 .opc4 = 0xff, \
520 .handler = { \
521 .inval1 = invl, \
522 .type = _typ, \
523 .type2 = _typ2, \
524 .handler = &gen_##name, \
525 }, \
526 .oname = stringify(name), \
527 }
528 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
529 { \
530 .opc1 = op1, \
531 .opc2 = op2, \
532 .opc3 = op3, \
533 .opc4 = 0xff, \
534 .handler = { \
535 .inval1 = invl1, \
536 .inval2 = invl2, \
537 .type = _typ, \
538 .type2 = _typ2, \
539 .handler = &gen_##name, \
540 }, \
541 .oname = stringify(name), \
542 }
543 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
544 { \
545 .opc1 = op1, \
546 .opc2 = op2, \
547 .opc3 = op3, \
548 .opc4 = 0xff, \
549 .handler = { \
550 .inval1 = invl, \
551 .type = _typ, \
552 .type2 = _typ2, \
553 .handler = &gen_##name, \
554 }, \
555 .oname = onam, \
556 }
557 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
558 { \
559 .opc1 = op1, \
560 .opc2 = op2, \
561 .opc3 = op3, \
562 .opc4 = op4, \
563 .handler = { \
564 .inval1 = invl, \
565 .type = _typ, \
566 .type2 = _typ2, \
567 .handler = &gen_##name, \
568 }, \
569 .oname = stringify(name), \
570 }
571 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
572 { \
573 .opc1 = op1, \
574 .opc2 = op2, \
575 .opc3 = op3, \
576 .opc4 = op4, \
577 .handler = { \
578 .inval1 = invl, \
579 .type = _typ, \
580 .type2 = _typ2, \
581 .handler = &gen_##name, \
582 }, \
583 .oname = onam, \
584 }
585 #endif
586
587 /* SPR load/store helpers */
588 static inline void gen_load_spr(TCGv t, int reg)
589 {
590 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
591 }
592
593 static inline void gen_store_spr(int reg, TCGv t)
594 {
595 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
596 }
597
598 /* Invalid instruction */
599 static void gen_invalid(DisasContext *ctx)
600 {
601 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
602 }
603
604 static opc_handler_t invalid_handler = {
605 .inval1 = 0xFFFFFFFF,
606 .inval2 = 0xFFFFFFFF,
607 .type = PPC_NONE,
608 .type2 = PPC_NONE,
609 .handler = gen_invalid,
610 };
611
612 /*** Integer comparison ***/
613
614 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
615 {
616 TCGv t0 = tcg_temp_new();
617 TCGv_i32 t1 = tcg_temp_new_i32();
618
619 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
620
621 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
622 tcg_gen_trunc_tl_i32(t1, t0);
623 tcg_gen_shli_i32(t1, t1, CRF_LT_BIT);
624 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
625
626 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
627 tcg_gen_trunc_tl_i32(t1, t0);
628 tcg_gen_shli_i32(t1, t1, CRF_GT_BIT);
629 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
630
631 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
632 tcg_gen_trunc_tl_i32(t1, t0);
633 tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT);
634 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
635
636 tcg_temp_free(t0);
637 tcg_temp_free_i32(t1);
638 }
639
640 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
641 {
642 TCGv t0 = tcg_const_tl(arg1);
643 gen_op_cmp(arg0, t0, s, crf);
644 tcg_temp_free(t0);
645 }
646
647 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
648 {
649 TCGv t0, t1;
650 t0 = tcg_temp_new();
651 t1 = tcg_temp_new();
652 if (s) {
653 tcg_gen_ext32s_tl(t0, arg0);
654 tcg_gen_ext32s_tl(t1, arg1);
655 } else {
656 tcg_gen_ext32u_tl(t0, arg0);
657 tcg_gen_ext32u_tl(t1, arg1);
658 }
659 gen_op_cmp(t0, t1, s, crf);
660 tcg_temp_free(t1);
661 tcg_temp_free(t0);
662 }
663
664 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
665 {
666 TCGv t0 = tcg_const_tl(arg1);
667 gen_op_cmp32(arg0, t0, s, crf);
668 tcg_temp_free(t0);
669 }
670
671 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
672 {
673 if (NARROW_MODE(ctx)) {
674 gen_op_cmpi32(reg, 0, 1, 0);
675 } else {
676 gen_op_cmpi(reg, 0, 1, 0);
677 }
678 }
679
680 /* cmp */
681 static void gen_cmp(DisasContext *ctx)
682 {
683 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
684 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
685 1, crfD(ctx->opcode));
686 } else {
687 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
688 1, crfD(ctx->opcode));
689 }
690 }
691
692 /* cmpi */
693 static void gen_cmpi(DisasContext *ctx)
694 {
695 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
696 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
697 1, crfD(ctx->opcode));
698 } else {
699 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
700 1, crfD(ctx->opcode));
701 }
702 }
703
704 /* cmpl */
705 static void gen_cmpl(DisasContext *ctx)
706 {
707 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
708 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
709 0, crfD(ctx->opcode));
710 } else {
711 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
712 0, crfD(ctx->opcode));
713 }
714 }
715
716 /* cmpli */
717 static void gen_cmpli(DisasContext *ctx)
718 {
719 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
720 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
721 0, crfD(ctx->opcode));
722 } else {
723 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
724 0, crfD(ctx->opcode));
725 }
726 }
727
728 /* cmprb - range comparison: isupper, isaplha, islower*/
729 static void gen_cmprb(DisasContext *ctx)
730 {
731 TCGv_i32 src1 = tcg_temp_new_i32();
732 TCGv_i32 src2 = tcg_temp_new_i32();
733 TCGv_i32 src2lo = tcg_temp_new_i32();
734 TCGv_i32 src2hi = tcg_temp_new_i32();
735 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
736
737 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
738 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
739
740 tcg_gen_andi_i32(src1, src1, 0xFF);
741 tcg_gen_ext8u_i32(src2lo, src2);
742 tcg_gen_shri_i32(src2, src2, 8);
743 tcg_gen_ext8u_i32(src2hi, src2);
744
745 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
746 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
747 tcg_gen_and_i32(crf, src2lo, src2hi);
748
749 if (ctx->opcode & 0x00200000) {
750 tcg_gen_shri_i32(src2, src2, 8);
751 tcg_gen_ext8u_i32(src2lo, src2);
752 tcg_gen_shri_i32(src2, src2, 8);
753 tcg_gen_ext8u_i32(src2hi, src2);
754 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
755 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
756 tcg_gen_and_i32(src2lo, src2lo, src2hi);
757 tcg_gen_or_i32(crf, crf, src2lo);
758 }
759 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
760 tcg_temp_free_i32(src1);
761 tcg_temp_free_i32(src2);
762 tcg_temp_free_i32(src2lo);
763 tcg_temp_free_i32(src2hi);
764 }
765
766 #if defined(TARGET_PPC64)
767 /* cmpeqb */
768 static void gen_cmpeqb(DisasContext *ctx)
769 {
770 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
771 cpu_gpr[rB(ctx->opcode)]);
772 }
773 #endif
774
775 /* isel (PowerPC 2.03 specification) */
776 static void gen_isel(DisasContext *ctx)
777 {
778 uint32_t bi = rC(ctx->opcode);
779 uint32_t mask = 0x08 >> (bi & 0x03);
780 TCGv t0 = tcg_temp_new();
781 TCGv zr;
782
783 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
784 tcg_gen_andi_tl(t0, t0, mask);
785
786 zr = tcg_const_tl(0);
787 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
788 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
789 cpu_gpr[rB(ctx->opcode)]);
790 tcg_temp_free(zr);
791 tcg_temp_free(t0);
792 }
793
794 /* cmpb: PowerPC 2.05 specification */
795 static void gen_cmpb(DisasContext *ctx)
796 {
797 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
798 cpu_gpr[rB(ctx->opcode)]);
799 }
800
801 /*** Integer arithmetic ***/
802
803 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
804 TCGv arg1, TCGv arg2, int sub)
805 {
806 TCGv t0 = tcg_temp_new();
807
808 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
809 tcg_gen_xor_tl(t0, arg1, arg2);
810 if (sub) {
811 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
812 } else {
813 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
814 }
815 tcg_temp_free(t0);
816 if (NARROW_MODE(ctx)) {
817 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
818 if (is_isa300(ctx)) {
819 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
820 }
821 } else {
822 if (is_isa300(ctx)) {
823 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
824 }
825 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
826 }
827 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
828 }
829
830 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
831 TCGv res, TCGv arg0, TCGv arg1,
832 int sub)
833 {
834 TCGv t0;
835
836 if (!is_isa300(ctx)) {
837 return;
838 }
839
840 t0 = tcg_temp_new();
841 if (sub) {
842 tcg_gen_eqv_tl(t0, arg0, arg1);
843 } else {
844 tcg_gen_xor_tl(t0, arg0, arg1);
845 }
846 tcg_gen_xor_tl(t0, t0, res);
847 tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
848 tcg_temp_free(t0);
849 }
850
851 /* Common add function */
852 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
853 TCGv arg2, bool add_ca, bool compute_ca,
854 bool compute_ov, bool compute_rc0)
855 {
856 TCGv t0 = ret;
857
858 if (compute_ca || compute_ov) {
859 t0 = tcg_temp_new();
860 }
861
862 if (compute_ca) {
863 if (NARROW_MODE(ctx)) {
864 /* Caution: a non-obvious corner case of the spec is that we
865 must produce the *entire* 64-bit addition, but produce the
866 carry into bit 32. */
867 TCGv t1 = tcg_temp_new();
868 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
869 tcg_gen_add_tl(t0, arg1, arg2);
870 if (add_ca) {
871 tcg_gen_add_tl(t0, t0, cpu_ca);
872 }
873 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
874 tcg_temp_free(t1);
875 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
876 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
877 if (is_isa300(ctx)) {
878 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
879 }
880 } else {
881 TCGv zero = tcg_const_tl(0);
882 if (add_ca) {
883 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
884 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
885 } else {
886 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
887 }
888 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0);
889 tcg_temp_free(zero);
890 }
891 } else {
892 tcg_gen_add_tl(t0, arg1, arg2);
893 if (add_ca) {
894 tcg_gen_add_tl(t0, t0, cpu_ca);
895 }
896 }
897
898 if (compute_ov) {
899 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
900 }
901 if (unlikely(compute_rc0)) {
902 gen_set_Rc0(ctx, t0);
903 }
904
905 if (!TCGV_EQUAL(t0, ret)) {
906 tcg_gen_mov_tl(ret, t0);
907 tcg_temp_free(t0);
908 }
909 }
910 /* Add functions with two operands */
911 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
912 static void glue(gen_, name)(DisasContext *ctx) \
913 { \
914 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
915 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
916 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
917 }
918 /* Add functions with one operand and one immediate */
919 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
920 add_ca, compute_ca, compute_ov) \
921 static void glue(gen_, name)(DisasContext *ctx) \
922 { \
923 TCGv t0 = tcg_const_tl(const_val); \
924 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
925 cpu_gpr[rA(ctx->opcode)], t0, \
926 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
927 tcg_temp_free(t0); \
928 }
929
930 /* add add. addo addo. */
931 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
932 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
933 /* addc addc. addco addco. */
934 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
935 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
936 /* adde adde. addeo addeo. */
937 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
938 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
939 /* addme addme. addmeo addmeo. */
940 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
941 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
942 /* addze addze. addzeo addzeo.*/
943 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
944 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
945 /* addi */
946 static void gen_addi(DisasContext *ctx)
947 {
948 target_long simm = SIMM(ctx->opcode);
949
950 if (rA(ctx->opcode) == 0) {
951 /* li case */
952 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
953 } else {
954 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
955 cpu_gpr[rA(ctx->opcode)], simm);
956 }
957 }
958 /* addic addic.*/
959 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
960 {
961 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
962 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
963 c, 0, 1, 0, compute_rc0);
964 tcg_temp_free(c);
965 }
966
967 static void gen_addic(DisasContext *ctx)
968 {
969 gen_op_addic(ctx, 0);
970 }
971
972 static void gen_addic_(DisasContext *ctx)
973 {
974 gen_op_addic(ctx, 1);
975 }
976
977 /* addis */
978 static void gen_addis(DisasContext *ctx)
979 {
980 target_long simm = SIMM(ctx->opcode);
981
982 if (rA(ctx->opcode) == 0) {
983 /* lis case */
984 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
985 } else {
986 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
987 cpu_gpr[rA(ctx->opcode)], simm << 16);
988 }
989 }
990
991 /* addpcis */
992 static void gen_addpcis(DisasContext *ctx)
993 {
994 target_long d = DX(ctx->opcode);
995
996 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
997 }
998
999 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1000 TCGv arg2, int sign, int compute_ov)
1001 {
1002 TCGv_i32 t0 = tcg_temp_new_i32();
1003 TCGv_i32 t1 = tcg_temp_new_i32();
1004 TCGv_i32 t2 = tcg_temp_new_i32();
1005 TCGv_i32 t3 = tcg_temp_new_i32();
1006
1007 tcg_gen_trunc_tl_i32(t0, arg1);
1008 tcg_gen_trunc_tl_i32(t1, arg2);
1009 if (sign) {
1010 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1011 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1012 tcg_gen_and_i32(t2, t2, t3);
1013 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1014 tcg_gen_or_i32(t2, t2, t3);
1015 tcg_gen_movi_i32(t3, 0);
1016 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1017 tcg_gen_div_i32(t3, t0, t1);
1018 tcg_gen_extu_i32_tl(ret, t3);
1019 } else {
1020 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1021 tcg_gen_movi_i32(t3, 0);
1022 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1023 tcg_gen_divu_i32(t3, t0, t1);
1024 tcg_gen_extu_i32_tl(ret, t3);
1025 }
1026 if (compute_ov) {
1027 tcg_gen_extu_i32_tl(cpu_ov, t2);
1028 if (is_isa300(ctx)) {
1029 tcg_gen_extu_i32_tl(cpu_ov32, t2);
1030 }
1031 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1032 }
1033 tcg_temp_free_i32(t0);
1034 tcg_temp_free_i32(t1);
1035 tcg_temp_free_i32(t2);
1036 tcg_temp_free_i32(t3);
1037
1038 if (unlikely(Rc(ctx->opcode) != 0))
1039 gen_set_Rc0(ctx, ret);
1040 }
1041 /* Div functions */
1042 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1043 static void glue(gen_, name)(DisasContext *ctx) \
1044 { \
1045 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1046 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1047 sign, compute_ov); \
1048 }
1049 /* divwu divwu. divwuo divwuo. */
1050 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1051 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1052 /* divw divw. divwo divwo. */
1053 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1054 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1055
1056 /* div[wd]eu[o][.] */
1057 #define GEN_DIVE(name, hlpr, compute_ov) \
1058 static void gen_##name(DisasContext *ctx) \
1059 { \
1060 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1061 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1062 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1063 tcg_temp_free_i32(t0); \
1064 if (unlikely(Rc(ctx->opcode) != 0)) { \
1065 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1066 } \
1067 }
1068
1069 GEN_DIVE(divweu, divweu, 0);
1070 GEN_DIVE(divweuo, divweu, 1);
1071 GEN_DIVE(divwe, divwe, 0);
1072 GEN_DIVE(divweo, divwe, 1);
1073
1074 #if defined(TARGET_PPC64)
1075 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1076 TCGv arg2, int sign, int compute_ov)
1077 {
1078 TCGv_i64 t0 = tcg_temp_new_i64();
1079 TCGv_i64 t1 = tcg_temp_new_i64();
1080 TCGv_i64 t2 = tcg_temp_new_i64();
1081 TCGv_i64 t3 = tcg_temp_new_i64();
1082
1083 tcg_gen_mov_i64(t0, arg1);
1084 tcg_gen_mov_i64(t1, arg2);
1085 if (sign) {
1086 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1087 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1088 tcg_gen_and_i64(t2, t2, t3);
1089 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1090 tcg_gen_or_i64(t2, t2, t3);
1091 tcg_gen_movi_i64(t3, 0);
1092 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1093 tcg_gen_div_i64(ret, t0, t1);
1094 } else {
1095 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1096 tcg_gen_movi_i64(t3, 0);
1097 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1098 tcg_gen_divu_i64(ret, t0, t1);
1099 }
1100 if (compute_ov) {
1101 tcg_gen_mov_tl(cpu_ov, t2);
1102 if (is_isa300(ctx)) {
1103 tcg_gen_mov_tl(cpu_ov32, t2);
1104 }
1105 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1106 }
1107 tcg_temp_free_i64(t0);
1108 tcg_temp_free_i64(t1);
1109 tcg_temp_free_i64(t2);
1110 tcg_temp_free_i64(t3);
1111
1112 if (unlikely(Rc(ctx->opcode) != 0))
1113 gen_set_Rc0(ctx, ret);
1114 }
1115
1116 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1117 static void glue(gen_, name)(DisasContext *ctx) \
1118 { \
1119 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1120 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1121 sign, compute_ov); \
1122 }
1123 /* divdu divdu. divduo divduo. */
1124 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1125 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1126 /* divd divd. divdo divdo. */
1127 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1128 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1129
1130 GEN_DIVE(divdeu, divdeu, 0);
1131 GEN_DIVE(divdeuo, divdeu, 1);
1132 GEN_DIVE(divde, divde, 0);
1133 GEN_DIVE(divdeo, divde, 1);
1134 #endif
1135
1136 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1137 TCGv arg2, int sign)
1138 {
1139 TCGv_i32 t0 = tcg_temp_new_i32();
1140 TCGv_i32 t1 = tcg_temp_new_i32();
1141
1142 tcg_gen_trunc_tl_i32(t0, arg1);
1143 tcg_gen_trunc_tl_i32(t1, arg2);
1144 if (sign) {
1145 TCGv_i32 t2 = tcg_temp_new_i32();
1146 TCGv_i32 t3 = tcg_temp_new_i32();
1147 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1148 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1149 tcg_gen_and_i32(t2, t2, t3);
1150 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1151 tcg_gen_or_i32(t2, t2, t3);
1152 tcg_gen_movi_i32(t3, 0);
1153 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1154 tcg_gen_rem_i32(t3, t0, t1);
1155 tcg_gen_ext_i32_tl(ret, t3);
1156 tcg_temp_free_i32(t2);
1157 tcg_temp_free_i32(t3);
1158 } else {
1159 TCGv_i32 t2 = tcg_const_i32(1);
1160 TCGv_i32 t3 = tcg_const_i32(0);
1161 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1162 tcg_gen_remu_i32(t3, t0, t1);
1163 tcg_gen_extu_i32_tl(ret, t3);
1164 tcg_temp_free_i32(t2);
1165 tcg_temp_free_i32(t3);
1166 }
1167 tcg_temp_free_i32(t0);
1168 tcg_temp_free_i32(t1);
1169 }
1170
1171 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1172 static void glue(gen_, name)(DisasContext *ctx) \
1173 { \
1174 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1175 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1176 sign); \
1177 }
1178
1179 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1180 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1181
1182 #if defined(TARGET_PPC64)
1183 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1184 TCGv arg2, int sign)
1185 {
1186 TCGv_i64 t0 = tcg_temp_new_i64();
1187 TCGv_i64 t1 = tcg_temp_new_i64();
1188
1189 tcg_gen_mov_i64(t0, arg1);
1190 tcg_gen_mov_i64(t1, arg2);
1191 if (sign) {
1192 TCGv_i64 t2 = tcg_temp_new_i64();
1193 TCGv_i64 t3 = tcg_temp_new_i64();
1194 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1195 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1196 tcg_gen_and_i64(t2, t2, t3);
1197 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1198 tcg_gen_or_i64(t2, t2, t3);
1199 tcg_gen_movi_i64(t3, 0);
1200 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1201 tcg_gen_rem_i64(ret, t0, t1);
1202 tcg_temp_free_i64(t2);
1203 tcg_temp_free_i64(t3);
1204 } else {
1205 TCGv_i64 t2 = tcg_const_i64(1);
1206 TCGv_i64 t3 = tcg_const_i64(0);
1207 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1208 tcg_gen_remu_i64(ret, t0, t1);
1209 tcg_temp_free_i64(t2);
1210 tcg_temp_free_i64(t3);
1211 }
1212 tcg_temp_free_i64(t0);
1213 tcg_temp_free_i64(t1);
1214 }
1215
1216 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1217 static void glue(gen_, name)(DisasContext *ctx) \
1218 { \
1219 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1220 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1221 sign); \
1222 }
1223
1224 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1225 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1226 #endif
1227
1228 /* mulhw mulhw. */
1229 static void gen_mulhw(DisasContext *ctx)
1230 {
1231 TCGv_i32 t0 = tcg_temp_new_i32();
1232 TCGv_i32 t1 = tcg_temp_new_i32();
1233
1234 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1235 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1236 tcg_gen_muls2_i32(t0, t1, t0, t1);
1237 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1238 tcg_temp_free_i32(t0);
1239 tcg_temp_free_i32(t1);
1240 if (unlikely(Rc(ctx->opcode) != 0))
1241 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1242 }
1243
1244 /* mulhwu mulhwu. */
1245 static void gen_mulhwu(DisasContext *ctx)
1246 {
1247 TCGv_i32 t0 = tcg_temp_new_i32();
1248 TCGv_i32 t1 = tcg_temp_new_i32();
1249
1250 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1251 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1252 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1253 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1254 tcg_temp_free_i32(t0);
1255 tcg_temp_free_i32(t1);
1256 if (unlikely(Rc(ctx->opcode) != 0))
1257 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1258 }
1259
1260 /* mullw mullw. */
1261 static void gen_mullw(DisasContext *ctx)
1262 {
1263 #if defined(TARGET_PPC64)
1264 TCGv_i64 t0, t1;
1265 t0 = tcg_temp_new_i64();
1266 t1 = tcg_temp_new_i64();
1267 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1268 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1269 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1270 tcg_temp_free(t0);
1271 tcg_temp_free(t1);
1272 #else
1273 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1274 cpu_gpr[rB(ctx->opcode)]);
1275 #endif
1276 if (unlikely(Rc(ctx->opcode) != 0))
1277 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1278 }
1279
1280 /* mullwo mullwo. */
1281 static void gen_mullwo(DisasContext *ctx)
1282 {
1283 TCGv_i32 t0 = tcg_temp_new_i32();
1284 TCGv_i32 t1 = tcg_temp_new_i32();
1285
1286 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1287 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1288 tcg_gen_muls2_i32(t0, t1, t0, t1);
1289 #if defined(TARGET_PPC64)
1290 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1291 #else
1292 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1293 #endif
1294
1295 tcg_gen_sari_i32(t0, t0, 31);
1296 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1297 tcg_gen_extu_i32_tl(cpu_ov, t0);
1298 if (is_isa300(ctx)) {
1299 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1300 }
1301 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1302
1303 tcg_temp_free_i32(t0);
1304 tcg_temp_free_i32(t1);
1305 if (unlikely(Rc(ctx->opcode) != 0))
1306 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1307 }
1308
1309 /* mulli */
1310 static void gen_mulli(DisasContext *ctx)
1311 {
1312 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1313 SIMM(ctx->opcode));
1314 }
1315
1316 #if defined(TARGET_PPC64)
1317 /* mulhd mulhd. */
1318 static void gen_mulhd(DisasContext *ctx)
1319 {
1320 TCGv lo = tcg_temp_new();
1321 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1322 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1323 tcg_temp_free(lo);
1324 if (unlikely(Rc(ctx->opcode) != 0)) {
1325 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1326 }
1327 }
1328
1329 /* mulhdu mulhdu. */
1330 static void gen_mulhdu(DisasContext *ctx)
1331 {
1332 TCGv lo = tcg_temp_new();
1333 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1334 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1335 tcg_temp_free(lo);
1336 if (unlikely(Rc(ctx->opcode) != 0)) {
1337 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1338 }
1339 }
1340
1341 /* mulld mulld. */
1342 static void gen_mulld(DisasContext *ctx)
1343 {
1344 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1345 cpu_gpr[rB(ctx->opcode)]);
1346 if (unlikely(Rc(ctx->opcode) != 0))
1347 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1348 }
1349
1350 /* mulldo mulldo. */
1351 static void gen_mulldo(DisasContext *ctx)
1352 {
1353 TCGv_i64 t0 = tcg_temp_new_i64();
1354 TCGv_i64 t1 = tcg_temp_new_i64();
1355
1356 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1357 cpu_gpr[rB(ctx->opcode)]);
1358 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1359
1360 tcg_gen_sari_i64(t0, t0, 63);
1361 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1362 if (is_isa300(ctx)) {
1363 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1364 }
1365 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1366
1367 tcg_temp_free_i64(t0);
1368 tcg_temp_free_i64(t1);
1369
1370 if (unlikely(Rc(ctx->opcode) != 0)) {
1371 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1372 }
1373 }
1374 #endif
1375
1376 /* Common subf function */
1377 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1378 TCGv arg2, bool add_ca, bool compute_ca,
1379 bool compute_ov, bool compute_rc0)
1380 {
1381 TCGv t0 = ret;
1382
1383 if (compute_ca || compute_ov) {
1384 t0 = tcg_temp_new();
1385 }
1386
1387 if (compute_ca) {
1388 /* dest = ~arg1 + arg2 [+ ca]. */
1389 if (NARROW_MODE(ctx)) {
1390 /* Caution: a non-obvious corner case of the spec is that we
1391 must produce the *entire* 64-bit addition, but produce the
1392 carry into bit 32. */
1393 TCGv inv1 = tcg_temp_new();
1394 TCGv t1 = tcg_temp_new();
1395 tcg_gen_not_tl(inv1, arg1);
1396 if (add_ca) {
1397 tcg_gen_add_tl(t0, arg2, cpu_ca);
1398 } else {
1399 tcg_gen_addi_tl(t0, arg2, 1);
1400 }
1401 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1402 tcg_gen_add_tl(t0, t0, inv1);
1403 tcg_temp_free(inv1);
1404 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1405 tcg_temp_free(t1);
1406 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1407 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1408 if (is_isa300(ctx)) {
1409 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
1410 }
1411 } else if (add_ca) {
1412 TCGv zero, inv1 = tcg_temp_new();
1413 tcg_gen_not_tl(inv1, arg1);
1414 zero = tcg_const_tl(0);
1415 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1416 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1417 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0);
1418 tcg_temp_free(zero);
1419 tcg_temp_free(inv1);
1420 } else {
1421 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1422 tcg_gen_sub_tl(t0, arg2, arg1);
1423 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1);
1424 }
1425 } else if (add_ca) {
1426 /* Since we're ignoring carry-out, we can simplify the
1427 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1428 tcg_gen_sub_tl(t0, arg2, arg1);
1429 tcg_gen_add_tl(t0, t0, cpu_ca);
1430 tcg_gen_subi_tl(t0, t0, 1);
1431 } else {
1432 tcg_gen_sub_tl(t0, arg2, arg1);
1433 }
1434
1435 if (compute_ov) {
1436 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1437 }
1438 if (unlikely(compute_rc0)) {
1439 gen_set_Rc0(ctx, t0);
1440 }
1441
1442 if (!TCGV_EQUAL(t0, ret)) {
1443 tcg_gen_mov_tl(ret, t0);
1444 tcg_temp_free(t0);
1445 }
1446 }
1447 /* Sub functions with Two operands functions */
1448 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1449 static void glue(gen_, name)(DisasContext *ctx) \
1450 { \
1451 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1452 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1453 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1454 }
1455 /* Sub functions with one operand and one immediate */
1456 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1457 add_ca, compute_ca, compute_ov) \
1458 static void glue(gen_, name)(DisasContext *ctx) \
1459 { \
1460 TCGv t0 = tcg_const_tl(const_val); \
1461 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1462 cpu_gpr[rA(ctx->opcode)], t0, \
1463 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1464 tcg_temp_free(t0); \
1465 }
1466 /* subf subf. subfo subfo. */
1467 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1468 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1469 /* subfc subfc. subfco subfco. */
1470 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1471 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1472 /* subfe subfe. subfeo subfo. */
1473 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1474 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1475 /* subfme subfme. subfmeo subfmeo. */
1476 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1477 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1478 /* subfze subfze. subfzeo subfzeo.*/
1479 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1480 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1481
1482 /* subfic */
1483 static void gen_subfic(DisasContext *ctx)
1484 {
1485 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1486 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1487 c, 0, 1, 0, 0);
1488 tcg_temp_free(c);
1489 }
1490
1491 /* neg neg. nego nego. */
1492 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1493 {
1494 TCGv zero = tcg_const_tl(0);
1495 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1496 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1497 tcg_temp_free(zero);
1498 }
1499
1500 static void gen_neg(DisasContext *ctx)
1501 {
1502 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1503 if (unlikely(Rc(ctx->opcode))) {
1504 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1505 }
1506 }
1507
1508 static void gen_nego(DisasContext *ctx)
1509 {
1510 gen_op_arith_neg(ctx, 1);
1511 }
1512
1513 /*** Integer logical ***/
1514 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1515 static void glue(gen_, name)(DisasContext *ctx) \
1516 { \
1517 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1518 cpu_gpr[rB(ctx->opcode)]); \
1519 if (unlikely(Rc(ctx->opcode) != 0)) \
1520 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1521 }
1522
1523 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1524 static void glue(gen_, name)(DisasContext *ctx) \
1525 { \
1526 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1527 if (unlikely(Rc(ctx->opcode) != 0)) \
1528 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1529 }
1530
1531 /* and & and. */
1532 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1533 /* andc & andc. */
1534 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1535
1536 /* andi. */
1537 static void gen_andi_(DisasContext *ctx)
1538 {
1539 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1540 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1541 }
1542
1543 /* andis. */
1544 static void gen_andis_(DisasContext *ctx)
1545 {
1546 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1547 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1548 }
1549
1550 /* cntlzw */
1551 static void gen_cntlzw(DisasContext *ctx)
1552 {
1553 TCGv_i32 t = tcg_temp_new_i32();
1554
1555 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1556 tcg_gen_clzi_i32(t, t, 32);
1557 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1558 tcg_temp_free_i32(t);
1559
1560 if (unlikely(Rc(ctx->opcode) != 0))
1561 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1562 }
1563
1564 /* cnttzw */
1565 static void gen_cnttzw(DisasContext *ctx)
1566 {
1567 TCGv_i32 t = tcg_temp_new_i32();
1568
1569 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1570 tcg_gen_ctzi_i32(t, t, 32);
1571 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1572 tcg_temp_free_i32(t);
1573
1574 if (unlikely(Rc(ctx->opcode) != 0)) {
1575 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1576 }
1577 }
1578
1579 /* eqv & eqv. */
1580 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1581 /* extsb & extsb. */
1582 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1583 /* extsh & extsh. */
1584 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1585 /* nand & nand. */
1586 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1587 /* nor & nor. */
1588 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1589
1590 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1591 static void gen_pause(DisasContext *ctx)
1592 {
1593 TCGv_i32 t0 = tcg_const_i32(0);
1594 tcg_gen_st_i32(t0, cpu_env,
1595 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1596 tcg_temp_free_i32(t0);
1597
1598 /* Stop translation, this gives other CPUs a chance to run */
1599 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1600 }
1601 #endif /* defined(TARGET_PPC64) */
1602
1603 /* or & or. */
1604 static void gen_or(DisasContext *ctx)
1605 {
1606 int rs, ra, rb;
1607
1608 rs = rS(ctx->opcode);
1609 ra = rA(ctx->opcode);
1610 rb = rB(ctx->opcode);
1611 /* Optimisation for mr. ri case */
1612 if (rs != ra || rs != rb) {
1613 if (rs != rb)
1614 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1615 else
1616 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1617 if (unlikely(Rc(ctx->opcode) != 0))
1618 gen_set_Rc0(ctx, cpu_gpr[ra]);
1619 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1620 gen_set_Rc0(ctx, cpu_gpr[rs]);
1621 #if defined(TARGET_PPC64)
1622 } else if (rs != 0) { /* 0 is nop */
1623 int prio = 0;
1624
1625 switch (rs) {
1626 case 1:
1627 /* Set process priority to low */
1628 prio = 2;
1629 break;
1630 case 6:
1631 /* Set process priority to medium-low */
1632 prio = 3;
1633 break;
1634 case 2:
1635 /* Set process priority to normal */
1636 prio = 4;
1637 break;
1638 #if !defined(CONFIG_USER_ONLY)
1639 case 31:
1640 if (!ctx->pr) {
1641 /* Set process priority to very low */
1642 prio = 1;
1643 }
1644 break;
1645 case 5:
1646 if (!ctx->pr) {
1647 /* Set process priority to medium-hight */
1648 prio = 5;
1649 }
1650 break;
1651 case 3:
1652 if (!ctx->pr) {
1653 /* Set process priority to high */
1654 prio = 6;
1655 }
1656 break;
1657 case 7:
1658 if (ctx->hv && !ctx->pr) {
1659 /* Set process priority to very high */
1660 prio = 7;
1661 }
1662 break;
1663 #endif
1664 default:
1665 break;
1666 }
1667 if (prio) {
1668 TCGv t0 = tcg_temp_new();
1669 gen_load_spr(t0, SPR_PPR);
1670 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1671 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1672 gen_store_spr(SPR_PPR, t0);
1673 tcg_temp_free(t0);
1674 }
1675 #if !defined(CONFIG_USER_ONLY)
1676 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1677 * CPU and the kernel hangs. This applies to all encodings other
1678 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1679 * and all currently undefined.
1680 */
1681 gen_pause(ctx);
1682 #endif
1683 #endif
1684 }
1685 }
1686 /* orc & orc. */
1687 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1688
1689 /* xor & xor. */
1690 static void gen_xor(DisasContext *ctx)
1691 {
1692 /* Optimisation for "set to zero" case */
1693 if (rS(ctx->opcode) != rB(ctx->opcode))
1694 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1695 else
1696 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1697 if (unlikely(Rc(ctx->opcode) != 0))
1698 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1699 }
1700
1701 /* ori */
1702 static void gen_ori(DisasContext *ctx)
1703 {
1704 target_ulong uimm = UIMM(ctx->opcode);
1705
1706 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1707 return;
1708 }
1709 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1710 }
1711
1712 /* oris */
1713 static void gen_oris(DisasContext *ctx)
1714 {
1715 target_ulong uimm = UIMM(ctx->opcode);
1716
1717 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1718 /* NOP */
1719 return;
1720 }
1721 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1722 }
1723
1724 /* xori */
1725 static void gen_xori(DisasContext *ctx)
1726 {
1727 target_ulong uimm = UIMM(ctx->opcode);
1728
1729 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1730 /* NOP */
1731 return;
1732 }
1733 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1734 }
1735
1736 /* xoris */
1737 static void gen_xoris(DisasContext *ctx)
1738 {
1739 target_ulong uimm = UIMM(ctx->opcode);
1740
1741 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1742 /* NOP */
1743 return;
1744 }
1745 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1746 }
1747
1748 /* popcntb : PowerPC 2.03 specification */
1749 static void gen_popcntb(DisasContext *ctx)
1750 {
1751 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1752 }
1753
1754 static void gen_popcntw(DisasContext *ctx)
1755 {
1756 #if defined(TARGET_PPC64)
1757 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1758 #else
1759 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1760 #endif
1761 }
1762
1763 #if defined(TARGET_PPC64)
1764 /* popcntd: PowerPC 2.06 specification */
1765 static void gen_popcntd(DisasContext *ctx)
1766 {
1767 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1768 }
1769 #endif
1770
1771 /* prtyw: PowerPC 2.05 specification */
1772 static void gen_prtyw(DisasContext *ctx)
1773 {
1774 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1775 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1776 TCGv t0 = tcg_temp_new();
1777 tcg_gen_shri_tl(t0, rs, 16);
1778 tcg_gen_xor_tl(ra, rs, t0);
1779 tcg_gen_shri_tl(t0, ra, 8);
1780 tcg_gen_xor_tl(ra, ra, t0);
1781 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1782 tcg_temp_free(t0);
1783 }
1784
1785 #if defined(TARGET_PPC64)
1786 /* prtyd: PowerPC 2.05 specification */
1787 static void gen_prtyd(DisasContext *ctx)
1788 {
1789 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1790 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1791 TCGv t0 = tcg_temp_new();
1792 tcg_gen_shri_tl(t0, rs, 32);
1793 tcg_gen_xor_tl(ra, rs, t0);
1794 tcg_gen_shri_tl(t0, ra, 16);
1795 tcg_gen_xor_tl(ra, ra, t0);
1796 tcg_gen_shri_tl(t0, ra, 8);
1797 tcg_gen_xor_tl(ra, ra, t0);
1798 tcg_gen_andi_tl(ra, ra, 1);
1799 tcg_temp_free(t0);
1800 }
1801 #endif
1802
1803 #if defined(TARGET_PPC64)
1804 /* bpermd */
1805 static void gen_bpermd(DisasContext *ctx)
1806 {
1807 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1808 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1809 }
1810 #endif
1811
1812 #if defined(TARGET_PPC64)
1813 /* extsw & extsw. */
1814 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1815
1816 /* cntlzd */
1817 static void gen_cntlzd(DisasContext *ctx)
1818 {
1819 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1820 if (unlikely(Rc(ctx->opcode) != 0))
1821 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1822 }
1823
1824 /* cnttzd */
1825 static void gen_cnttzd(DisasContext *ctx)
1826 {
1827 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1828 if (unlikely(Rc(ctx->opcode) != 0)) {
1829 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1830 }
1831 }
1832
1833 /* darn */
1834 static void gen_darn(DisasContext *ctx)
1835 {
1836 int l = L(ctx->opcode);
1837
1838 if (l == 0) {
1839 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
1840 } else if (l <= 2) {
1841 /* Return 64-bit random for both CRN and RRN */
1842 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
1843 } else {
1844 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1845 }
1846 }
1847 #endif
1848
1849 /*** Integer rotate ***/
1850
1851 /* rlwimi & rlwimi. */
1852 static void gen_rlwimi(DisasContext *ctx)
1853 {
1854 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1855 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1856 uint32_t sh = SH(ctx->opcode);
1857 uint32_t mb = MB(ctx->opcode);
1858 uint32_t me = ME(ctx->opcode);
1859
1860 if (sh == (31-me) && mb <= me) {
1861 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1862 } else {
1863 target_ulong mask;
1864 TCGv t1;
1865
1866 #if defined(TARGET_PPC64)
1867 mb += 32;
1868 me += 32;
1869 #endif
1870 mask = MASK(mb, me);
1871
1872 t1 = tcg_temp_new();
1873 if (mask <= 0xffffffffu) {
1874 TCGv_i32 t0 = tcg_temp_new_i32();
1875 tcg_gen_trunc_tl_i32(t0, t_rs);
1876 tcg_gen_rotli_i32(t0, t0, sh);
1877 tcg_gen_extu_i32_tl(t1, t0);
1878 tcg_temp_free_i32(t0);
1879 } else {
1880 #if defined(TARGET_PPC64)
1881 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1882 tcg_gen_rotli_i64(t1, t1, sh);
1883 #else
1884 g_assert_not_reached();
1885 #endif
1886 }
1887
1888 tcg_gen_andi_tl(t1, t1, mask);
1889 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1890 tcg_gen_or_tl(t_ra, t_ra, t1);
1891 tcg_temp_free(t1);
1892 }
1893 if (unlikely(Rc(ctx->opcode) != 0)) {
1894 gen_set_Rc0(ctx, t_ra);
1895 }
1896 }
1897
1898 /* rlwinm & rlwinm. */
1899 static void gen_rlwinm(DisasContext *ctx)
1900 {
1901 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1902 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1903 int sh = SH(ctx->opcode);
1904 int mb = MB(ctx->opcode);
1905 int me = ME(ctx->opcode);
1906 int len = me - mb + 1;
1907 int rsh = (32 - sh) & 31;
1908
1909 if (sh != 0 && len > 0 && me == (31 - sh)) {
1910 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1911 } else if (me == 31 && rsh + len <= 32) {
1912 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1913 } else {
1914 target_ulong mask;
1915 #if defined(TARGET_PPC64)
1916 mb += 32;
1917 me += 32;
1918 #endif
1919 mask = MASK(mb, me);
1920 if (sh == 0) {
1921 tcg_gen_andi_tl(t_ra, t_rs, mask);
1922 } else if (mask <= 0xffffffffu) {
1923 TCGv_i32 t0 = tcg_temp_new_i32();
1924 tcg_gen_trunc_tl_i32(t0, t_rs);
1925 tcg_gen_rotli_i32(t0, t0, sh);
1926 tcg_gen_andi_i32(t0, t0, mask);
1927 tcg_gen_extu_i32_tl(t_ra, t0);
1928 tcg_temp_free_i32(t0);
1929 } else {
1930 #if defined(TARGET_PPC64)
1931 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1932 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1933 tcg_gen_andi_i64(t_ra, t_ra, mask);
1934 #else
1935 g_assert_not_reached();
1936 #endif
1937 }
1938 }
1939 if (unlikely(Rc(ctx->opcode) != 0)) {
1940 gen_set_Rc0(ctx, t_ra);
1941 }
1942 }
1943
1944 /* rlwnm & rlwnm. */
1945 static void gen_rlwnm(DisasContext *ctx)
1946 {
1947 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1948 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1949 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1950 uint32_t mb = MB(ctx->opcode);
1951 uint32_t me = ME(ctx->opcode);
1952 target_ulong mask;
1953
1954 #if defined(TARGET_PPC64)
1955 mb += 32;
1956 me += 32;
1957 #endif
1958 mask = MASK(mb, me);
1959
1960 if (mask <= 0xffffffffu) {
1961 TCGv_i32 t0 = tcg_temp_new_i32();
1962 TCGv_i32 t1 = tcg_temp_new_i32();
1963 tcg_gen_trunc_tl_i32(t0, t_rb);
1964 tcg_gen_trunc_tl_i32(t1, t_rs);
1965 tcg_gen_andi_i32(t0, t0, 0x1f);
1966 tcg_gen_rotl_i32(t1, t1, t0);
1967 tcg_gen_extu_i32_tl(t_ra, t1);
1968 tcg_temp_free_i32(t0);
1969 tcg_temp_free_i32(t1);
1970 } else {
1971 #if defined(TARGET_PPC64)
1972 TCGv_i64 t0 = tcg_temp_new_i64();
1973 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1974 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1975 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1976 tcg_temp_free_i64(t0);
1977 #else
1978 g_assert_not_reached();
1979 #endif
1980 }
1981
1982 tcg_gen_andi_tl(t_ra, t_ra, mask);
1983
1984 if (unlikely(Rc(ctx->opcode) != 0)) {
1985 gen_set_Rc0(ctx, t_ra);
1986 }
1987 }
1988
1989 #if defined(TARGET_PPC64)
1990 #define GEN_PPC64_R2(name, opc1, opc2) \
1991 static void glue(gen_, name##0)(DisasContext *ctx) \
1992 { \
1993 gen_##name(ctx, 0); \
1994 } \
1995 \
1996 static void glue(gen_, name##1)(DisasContext *ctx) \
1997 { \
1998 gen_##name(ctx, 1); \
1999 }
2000 #define GEN_PPC64_R4(name, opc1, opc2) \
2001 static void glue(gen_, name##0)(DisasContext *ctx) \
2002 { \
2003 gen_##name(ctx, 0, 0); \
2004 } \
2005 \
2006 static void glue(gen_, name##1)(DisasContext *ctx) \
2007 { \
2008 gen_##name(ctx, 0, 1); \
2009 } \
2010 \
2011 static void glue(gen_, name##2)(DisasContext *ctx) \
2012 { \
2013 gen_##name(ctx, 1, 0); \
2014 } \
2015 \
2016 static void glue(gen_, name##3)(DisasContext *ctx) \
2017 { \
2018 gen_##name(ctx, 1, 1); \
2019 }
2020
2021 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2022 {
2023 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2024 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2025 int len = me - mb + 1;
2026 int rsh = (64 - sh) & 63;
2027
2028 if (sh != 0 && len > 0 && me == (63 - sh)) {
2029 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2030 } else if (me == 63 && rsh + len <= 64) {
2031 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2032 } else {
2033 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2034 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2035 }
2036 if (unlikely(Rc(ctx->opcode) != 0)) {
2037 gen_set_Rc0(ctx, t_ra);
2038 }
2039 }
2040
2041 /* rldicl - rldicl. */
2042 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2043 {
2044 uint32_t sh, mb;
2045
2046 sh = SH(ctx->opcode) | (shn << 5);
2047 mb = MB(ctx->opcode) | (mbn << 5);
2048 gen_rldinm(ctx, mb, 63, sh);
2049 }
2050 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2051
2052 /* rldicr - rldicr. */
2053 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2054 {
2055 uint32_t sh, me;
2056
2057 sh = SH(ctx->opcode) | (shn << 5);
2058 me = MB(ctx->opcode) | (men << 5);
2059 gen_rldinm(ctx, 0, me, sh);
2060 }
2061 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2062
2063 /* rldic - rldic. */
2064 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2065 {
2066 uint32_t sh, mb;
2067
2068 sh = SH(ctx->opcode) | (shn << 5);
2069 mb = MB(ctx->opcode) | (mbn << 5);
2070 gen_rldinm(ctx, mb, 63 - sh, sh);
2071 }
2072 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2073
2074 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2075 {
2076 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2077 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2078 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2079 TCGv t0;
2080
2081 t0 = tcg_temp_new();
2082 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2083 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2084 tcg_temp_free(t0);
2085
2086 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2087 if (unlikely(Rc(ctx->opcode) != 0)) {
2088 gen_set_Rc0(ctx, t_ra);
2089 }
2090 }
2091
2092 /* rldcl - rldcl. */
2093 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2094 {
2095 uint32_t mb;
2096
2097 mb = MB(ctx->opcode) | (mbn << 5);
2098 gen_rldnm(ctx, mb, 63);
2099 }
2100 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2101
2102 /* rldcr - rldcr. */
2103 static inline void gen_rldcr(DisasContext *ctx, int men)
2104 {
2105 uint32_t me;
2106
2107 me = MB(ctx->opcode) | (men << 5);
2108 gen_rldnm(ctx, 0, me);
2109 }
2110 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2111
2112 /* rldimi - rldimi. */
2113 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2114 {
2115 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2116 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2117 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2118 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2119 uint32_t me = 63 - sh;
2120
2121 if (mb <= me) {
2122 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2123 } else {
2124 target_ulong mask = MASK(mb, me);
2125 TCGv t1 = tcg_temp_new();
2126
2127 tcg_gen_rotli_tl(t1, t_rs, sh);
2128 tcg_gen_andi_tl(t1, t1, mask);
2129 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2130 tcg_gen_or_tl(t_ra, t_ra, t1);
2131 tcg_temp_free(t1);
2132 }
2133 if (unlikely(Rc(ctx->opcode) != 0)) {
2134 gen_set_Rc0(ctx, t_ra);
2135 }
2136 }
2137 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2138 #endif
2139
2140 /*** Integer shift ***/
2141
2142 /* slw & slw. */
2143 static void gen_slw(DisasContext *ctx)
2144 {
2145 TCGv t0, t1;
2146
2147 t0 = tcg_temp_new();
2148 /* AND rS with a mask that is 0 when rB >= 0x20 */
2149 #if defined(TARGET_PPC64)
2150 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2151 tcg_gen_sari_tl(t0, t0, 0x3f);
2152 #else
2153 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2154 tcg_gen_sari_tl(t0, t0, 0x1f);
2155 #endif
2156 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2157 t1 = tcg_temp_new();
2158 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2159 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2160 tcg_temp_free(t1);
2161 tcg_temp_free(t0);
2162 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2163 if (unlikely(Rc(ctx->opcode) != 0))
2164 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2165 }
2166
2167 /* sraw & sraw. */
2168 static void gen_sraw(DisasContext *ctx)
2169 {
2170 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2171 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2172 if (unlikely(Rc(ctx->opcode) != 0))
2173 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2174 }
2175
2176 /* srawi & srawi. */
2177 static void gen_srawi(DisasContext *ctx)
2178 {
2179 int sh = SH(ctx->opcode);
2180 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2181 TCGv src = cpu_gpr[rS(ctx->opcode)];
2182 if (sh == 0) {
2183 tcg_gen_ext32s_tl(dst, src);
2184 tcg_gen_movi_tl(cpu_ca, 0);
2185 } else {
2186 TCGv t0;
2187 tcg_gen_ext32s_tl(dst, src);
2188 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2189 t0 = tcg_temp_new();
2190 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2191 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2192 tcg_temp_free(t0);
2193 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2194 tcg_gen_sari_tl(dst, dst, sh);
2195 }
2196 if (unlikely(Rc(ctx->opcode) != 0)) {
2197 gen_set_Rc0(ctx, dst);
2198 }
2199 }
2200
2201 /* srw & srw. */
2202 static void gen_srw(DisasContext *ctx)
2203 {
2204 TCGv t0, t1;
2205
2206 t0 = tcg_temp_new();
2207 /* AND rS with a mask that is 0 when rB >= 0x20 */
2208 #if defined(TARGET_PPC64)
2209 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2210 tcg_gen_sari_tl(t0, t0, 0x3f);
2211 #else
2212 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2213 tcg_gen_sari_tl(t0, t0, 0x1f);
2214 #endif
2215 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2216 tcg_gen_ext32u_tl(t0, t0);
2217 t1 = tcg_temp_new();
2218 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2219 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2220 tcg_temp_free(t1);
2221 tcg_temp_free(t0);
2222 if (unlikely(Rc(ctx->opcode) != 0))
2223 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2224 }
2225
2226 #if defined(TARGET_PPC64)
2227 /* sld & sld. */
2228 static void gen_sld(DisasContext *ctx)
2229 {
2230 TCGv t0, t1;
2231
2232 t0 = tcg_temp_new();
2233 /* AND rS with a mask that is 0 when rB >= 0x40 */
2234 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2235 tcg_gen_sari_tl(t0, t0, 0x3f);
2236 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2237 t1 = tcg_temp_new();
2238 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2239 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2240 tcg_temp_free(t1);
2241 tcg_temp_free(t0);
2242 if (unlikely(Rc(ctx->opcode) != 0))
2243 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2244 }
2245
2246 /* srad & srad. */
2247 static void gen_srad(DisasContext *ctx)
2248 {
2249 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2250 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2251 if (unlikely(Rc(ctx->opcode) != 0))
2252 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2253 }
2254 /* sradi & sradi. */
2255 static inline void gen_sradi(DisasContext *ctx, int n)
2256 {
2257 int sh = SH(ctx->opcode) + (n << 5);
2258 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2259 TCGv src = cpu_gpr[rS(ctx->opcode)];
2260 if (sh == 0) {
2261 tcg_gen_mov_tl(dst, src);
2262 tcg_gen_movi_tl(cpu_ca, 0);
2263 } else {
2264 TCGv t0;
2265 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2266 t0 = tcg_temp_new();
2267 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2268 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2269 tcg_temp_free(t0);
2270 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2271 tcg_gen_sari_tl(dst, src, sh);
2272 }
2273 if (unlikely(Rc(ctx->opcode) != 0)) {
2274 gen_set_Rc0(ctx, dst);
2275 }
2276 }
2277
2278 static void gen_sradi0(DisasContext *ctx)
2279 {
2280 gen_sradi(ctx, 0);
2281 }
2282
2283 static void gen_sradi1(DisasContext *ctx)
2284 {
2285 gen_sradi(ctx, 1);
2286 }
2287
2288 /* extswsli & extswsli. */
2289 static inline void gen_extswsli(DisasContext *ctx, int n)
2290 {
2291 int sh = SH(ctx->opcode) + (n << 5);
2292 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2293 TCGv src = cpu_gpr[rS(ctx->opcode)];
2294
2295 tcg_gen_ext32s_tl(dst, src);
2296 tcg_gen_shli_tl(dst, dst, sh);
2297 if (unlikely(Rc(ctx->opcode) != 0)) {
2298 gen_set_Rc0(ctx, dst);
2299 }
2300 }
2301
2302 static void gen_extswsli0(DisasContext *ctx)
2303 {
2304 gen_extswsli(ctx, 0);
2305 }
2306
2307 static void gen_extswsli1(DisasContext *ctx)
2308 {
2309 gen_extswsli(ctx, 1);
2310 }
2311
2312 /* srd & srd. */
2313 static void gen_srd(DisasContext *ctx)
2314 {
2315 TCGv t0, t1;
2316
2317 t0 = tcg_temp_new();
2318 /* AND rS with a mask that is 0 when rB >= 0x40 */
2319 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2320 tcg_gen_sari_tl(t0, t0, 0x3f);
2321 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2322 t1 = tcg_temp_new();
2323 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2324 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2325 tcg_temp_free(t1);
2326 tcg_temp_free(t0);
2327 if (unlikely(Rc(ctx->opcode) != 0))
2328 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2329 }
2330 #endif
2331
2332 /*** Addressing modes ***/
2333 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2334 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2335 target_long maskl)
2336 {
2337 target_long simm = SIMM(ctx->opcode);
2338
2339 simm &= ~maskl;
2340 if (rA(ctx->opcode) == 0) {
2341 if (NARROW_MODE(ctx)) {
2342 simm = (uint32_t)simm;
2343 }
2344 tcg_gen_movi_tl(EA, simm);
2345 } else if (likely(simm != 0)) {
2346 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2347 if (NARROW_MODE(ctx)) {
2348 tcg_gen_ext32u_tl(EA, EA);
2349 }
2350 } else {
2351 if (NARROW_MODE(ctx)) {
2352 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2353 } else {
2354 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2355 }
2356 }
2357 }
2358
2359 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2360 {
2361 if (rA(ctx->opcode) == 0) {
2362 if (NARROW_MODE(ctx)) {
2363 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2364 } else {
2365 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2366 }
2367 } else {
2368 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2369 if (NARROW_MODE(ctx)) {
2370 tcg_gen_ext32u_tl(EA, EA);
2371 }
2372 }
2373 }
2374
2375 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2376 {
2377 if (rA(ctx->opcode) == 0) {
2378 tcg_gen_movi_tl(EA, 0);
2379 } else if (NARROW_MODE(ctx)) {
2380 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2381 } else {
2382 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2383 }
2384 }
2385
2386 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2387 target_long val)
2388 {
2389 tcg_gen_addi_tl(ret, arg1, val);
2390 if (NARROW_MODE(ctx)) {
2391 tcg_gen_ext32u_tl(ret, ret);
2392 }
2393 }
2394
2395 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2396 {
2397 TCGLabel *l1 = gen_new_label();
2398 TCGv t0 = tcg_temp_new();
2399 TCGv_i32 t1, t2;
2400 tcg_gen_andi_tl(t0, EA, mask);
2401 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2402 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2403 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2404 gen_update_nip(ctx, ctx->nip - 4);
2405 gen_helper_raise_exception_err(cpu_env, t1, t2);
2406 tcg_temp_free_i32(t1);
2407 tcg_temp_free_i32(t2);
2408 gen_set_label(l1);
2409 tcg_temp_free(t0);
2410 }
2411
2412 static inline void gen_align_no_le(DisasContext *ctx)
2413 {
2414 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2415 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2416 }
2417
2418 /*** Integer load ***/
2419 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2420 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2421
2422 #define GEN_QEMU_LOAD_TL(ldop, op) \
2423 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2424 TCGv val, \
2425 TCGv addr) \
2426 { \
2427 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2428 }
2429
2430 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2431 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2432 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2433 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2434 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2435
2436 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2437 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2438
2439 #define GEN_QEMU_LOAD_64(ldop, op) \
2440 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2441 TCGv_i64 val, \
2442 TCGv addr) \
2443 { \
2444 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2445 }
2446
2447 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2448 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2449 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2450 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2451 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
2452
2453 #if defined(TARGET_PPC64)
2454 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2455 #endif
2456
2457 #define GEN_QEMU_STORE_TL(stop, op) \
2458 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2459 TCGv val, \
2460 TCGv addr) \
2461 { \
2462 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2463 }
2464
2465 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2466 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2467 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2468
2469 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2470 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2471
2472 #define GEN_QEMU_STORE_64(stop, op) \
2473 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2474 TCGv_i64 val, \
2475 TCGv addr) \
2476 { \
2477 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2478 }
2479
2480 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2481 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2482 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2483 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2484
2485 #if defined(TARGET_PPC64)
2486 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2487 #endif
2488
2489 #define GEN_LD(name, ldop, opc, type) \
2490 static void glue(gen_, name)(DisasContext *ctx) \
2491 { \
2492 TCGv EA; \
2493 gen_set_access_type(ctx, ACCESS_INT); \
2494 EA = tcg_temp_new(); \
2495 gen_addr_imm_index(ctx, EA, 0); \
2496 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2497 tcg_temp_free(EA); \
2498 }
2499
2500 #define GEN_LDU(name, ldop, opc, type) \
2501 static void glue(gen_, name##u)(DisasContext *ctx) \
2502 { \
2503 TCGv EA; \
2504 if (unlikely(rA(ctx->opcode) == 0 || \
2505 rA(ctx->opcode) == rD(ctx->opcode))) { \
2506 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2507 return; \
2508 } \
2509 gen_set_access_type(ctx, ACCESS_INT); \
2510 EA = tcg_temp_new(); \
2511 if (type == PPC_64B) \
2512 gen_addr_imm_index(ctx, EA, 0x03); \
2513 else \
2514 gen_addr_imm_index(ctx, EA, 0); \
2515 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2516 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2517 tcg_temp_free(EA); \
2518 }
2519
2520 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2521 static void glue(gen_, name##ux)(DisasContext *ctx) \
2522 { \
2523 TCGv EA; \
2524 if (unlikely(rA(ctx->opcode) == 0 || \
2525 rA(ctx->opcode) == rD(ctx->opcode))) { \
2526 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2527 return; \
2528 } \
2529 gen_set_access_type(ctx, ACCESS_INT); \
2530 EA = tcg_temp_new(); \
2531 gen_addr_reg_index(ctx, EA); \
2532 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2533 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2534 tcg_temp_free(EA); \
2535 }
2536
2537 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2538 static void glue(gen_, name##x)(DisasContext *ctx) \
2539 { \
2540 TCGv EA; \
2541 chk; \
2542 gen_set_access_type(ctx, ACCESS_INT); \
2543 EA = tcg_temp_new(); \
2544 gen_addr_reg_index(ctx, EA); \
2545 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2546 tcg_temp_free(EA); \
2547 }
2548
2549 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2550 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2551
2552 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2553 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2554
2555 #define GEN_LDS(name, ldop, op, type) \
2556 GEN_LD(name, ldop, op | 0x20, type); \
2557 GEN_LDU(name, ldop, op | 0x21, type); \
2558 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2559 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2560
2561 /* lbz lbzu lbzux lbzx */
2562 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2563 /* lha lhau lhaux lhax */
2564 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2565 /* lhz lhzu lhzux lhzx */
2566 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2567 /* lwz lwzu lwzux lwzx */
2568 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2569 #if defined(TARGET_PPC64)
2570 /* lwaux */
2571 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2572 /* lwax */
2573 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2574 /* ldux */
2575 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2576 /* ldx */
2577 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2578
2579 /* CI load/store variants */
2580 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2581 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2582 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2583 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2584
2585 static void gen_ld(DisasContext *ctx)
2586 {
2587 TCGv EA;
2588 if (Rc(ctx->opcode)) {
2589 if (unlikely(rA(ctx->opcode) == 0 ||
2590 rA(ctx->opcode) == rD(ctx->opcode))) {
2591 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2592 return;
2593 }
2594 }
2595 gen_set_access_type(ctx, ACCESS_INT);
2596 EA = tcg_temp_new();
2597 gen_addr_imm_index(ctx, EA, 0x03);
2598 if (ctx->opcode & 0x02) {
2599 /* lwa (lwau is undefined) */
2600 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2601 } else {
2602 /* ld - ldu */
2603 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2604 }
2605 if (Rc(ctx->opcode))
2606 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2607 tcg_temp_free(EA);
2608 }
2609
2610 /* lq */
2611 static void gen_lq(DisasContext *ctx)
2612 {
2613 int ra, rd;
2614 TCGv EA;
2615
2616 /* lq is a legal user mode instruction starting in ISA 2.07 */
2617 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2618 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2619
2620 if (!legal_in_user_mode && ctx->pr) {
2621 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2622 return;
2623 }
2624
2625 if (!le_is_supported && ctx->le_mode) {
2626 gen_align_no_le(ctx);
2627 return;
2628 }
2629 ra = rA(ctx->opcode);
2630 rd = rD(ctx->opcode);
2631 if (unlikely((rd & 1) || rd == ra)) {
2632 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2633 return;
2634 }
2635
2636 gen_set_access_type(ctx, ACCESS_INT);
2637 EA = tcg_temp_new();
2638 gen_addr_imm_index(ctx, EA, 0x0F);
2639
2640 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does
2641 necessary 64-bit byteswap already. */
2642 if (unlikely(ctx->le_mode)) {
2643 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2644 gen_addr_add(ctx, EA, EA, 8);
2645 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2646 } else {
2647 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2648 gen_addr_add(ctx, EA, EA, 8);
2649 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2650 }
2651 tcg_temp_free(EA);
2652 }
2653 #endif
2654
2655 /*** Integer store ***/
2656 #define GEN_ST(name, stop, opc, type) \
2657 static void glue(gen_, name)(DisasContext *ctx) \
2658 { \
2659 TCGv EA; \
2660 gen_set_access_type(ctx, ACCESS_INT); \
2661 EA = tcg_temp_new(); \
2662 gen_addr_imm_index(ctx, EA, 0); \
2663 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2664 tcg_temp_free(EA); \
2665 }
2666
2667 #define GEN_STU(name, stop, opc, type) \
2668 static void glue(gen_, stop##u)(DisasContext *ctx) \
2669 { \
2670 TCGv EA; \
2671 if (unlikely(rA(ctx->opcode) == 0)) { \
2672 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2673 return; \
2674 } \
2675 gen_set_access_type(ctx, ACCESS_INT); \
2676 EA = tcg_temp_new(); \
2677 if (type == PPC_64B) \
2678 gen_addr_imm_index(ctx, EA, 0x03); \
2679 else \
2680 gen_addr_imm_index(ctx, EA, 0); \
2681 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2682 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2683 tcg_temp_free(EA); \
2684 }
2685
2686 #define GEN_STUX(name, stop, opc2, opc3, type) \
2687 static void glue(gen_, name##ux)(DisasContext *ctx) \
2688 { \
2689 TCGv EA; \
2690 if (unlikely(rA(ctx->opcode) == 0)) { \
2691 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2692 return; \
2693 } \
2694 gen_set_access_type(ctx, ACCESS_INT); \
2695 EA = tcg_temp_new(); \
2696 gen_addr_reg_index(ctx, EA); \
2697 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2698 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2699 tcg_temp_free(EA); \
2700 }
2701
2702 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2703 static void glue(gen_, name##x)(DisasContext *ctx) \
2704 { \
2705 TCGv EA; \
2706 chk; \
2707 gen_set_access_type(ctx, ACCESS_INT); \
2708 EA = tcg_temp_new(); \
2709 gen_addr_reg_index(ctx, EA); \
2710 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2711 tcg_temp_free(EA); \
2712 }
2713 #define GEN_STX(name, stop, opc2, opc3, type) \
2714 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2715
2716 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2717 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2718
2719 #define GEN_STS(name, stop, op, type) \
2720 GEN_ST(name, stop, op | 0x20, type); \
2721 GEN_STU(name, stop, op | 0x21, type); \
2722 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2723 GEN_STX(name, stop, 0x17, op | 0x00, type)
2724
2725 /* stb stbu stbux stbx */
2726 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2727 /* sth sthu sthux sthx */
2728 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2729 /* stw stwu stwux stwx */
2730 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2731 #if defined(TARGET_PPC64)
2732 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2733 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2734 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2735 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2736 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2737 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2738
2739 static void gen_std(DisasContext *ctx)
2740 {
2741 int rs;
2742 TCGv EA;
2743
2744 rs = rS(ctx->opcode);
2745 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2746 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2747 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2748
2749 if (!(ctx->insns_flags & PPC_64BX)) {
2750 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2751 }
2752
2753 if (!legal_in_user_mode && ctx->pr) {
2754 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2755 return;
2756 }
2757
2758 if (!le_is_supported && ctx->le_mode) {
2759 gen_align_no_le(ctx);
2760 return;
2761 }
2762
2763 if (unlikely(rs & 1)) {
2764 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2765 return;
2766 }
2767 gen_set_access_type(ctx, ACCESS_INT);
2768 EA = tcg_temp_new();
2769 gen_addr_imm_index(ctx, EA, 0x03);
2770
2771 /* We only need to swap high and low halves. gen_qemu_st64_i64 does
2772 necessary 64-bit byteswap already. */
2773 if (unlikely(ctx->le_mode)) {
2774 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2775 gen_addr_add(ctx, EA, EA, 8);
2776 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2777 } else {
2778 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2779 gen_addr_add(ctx, EA, EA, 8);
2780 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2781 }
2782 tcg_temp_free(EA);
2783 } else {
2784 /* std / stdu*/
2785 if (Rc(ctx->opcode)) {
2786 if (unlikely(rA(ctx->opcode) == 0)) {
2787 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2788 return;
2789 }
2790 }
2791 gen_set_access_type(ctx, ACCESS_INT);
2792 EA = tcg_temp_new();
2793 gen_addr_imm_index(ctx, EA, 0x03);
2794 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2795 if (Rc(ctx->opcode))
2796 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2797 tcg_temp_free(EA);
2798 }
2799 }
2800 #endif
2801 /*** Integer load and store with byte reverse ***/
2802
2803 /* lhbrx */
2804 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2805
2806 /* lwbrx */
2807 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2808
2809 #if defined(TARGET_PPC64)
2810 /* ldbrx */
2811 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2812 /* stdbrx */
2813 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2814 #endif /* TARGET_PPC64 */
2815
2816 /* sthbrx */
2817 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2818 /* stwbrx */
2819 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2820
2821 /*** Integer load and store multiple ***/
2822
2823 /* lmw */
2824 static void gen_lmw(DisasContext *ctx)
2825 {
2826 TCGv t0;
2827 TCGv_i32 t1;
2828
2829 if (ctx->le_mode) {
2830 gen_align_no_le(ctx);
2831 return;
2832 }
2833 gen_set_access_type(ctx, ACCESS_INT);
2834 t0 = tcg_temp_new();
2835 t1 = tcg_const_i32(rD(ctx->opcode));
2836 gen_addr_imm_index(ctx, t0, 0);
2837 gen_helper_lmw(cpu_env, t0, t1);
2838 tcg_temp_free(t0);
2839 tcg_temp_free_i32(t1);
2840 }
2841
2842 /* stmw */
2843 static void gen_stmw(DisasContext *ctx)
2844 {
2845 TCGv t0;
2846 TCGv_i32 t1;
2847
2848 if (ctx->le_mode) {
2849 gen_align_no_le(ctx);
2850 return;
2851 }
2852 gen_set_access_type(ctx, ACCESS_INT);
2853 t0 = tcg_temp_new();
2854 t1 = tcg_const_i32(rS(ctx->opcode));
2855 gen_addr_imm_index(ctx, t0, 0);
2856 gen_helper_stmw(cpu_env, t0, t1);
2857 tcg_temp_free(t0);
2858 tcg_temp_free_i32(t1);
2859 }
2860
2861 /*** Integer load and store strings ***/
2862
2863 /* lswi */
2864 /* PowerPC32 specification says we must generate an exception if
2865 * rA is in the range of registers to be loaded.
2866 * In an other hand, IBM says this is valid, but rA won't be loaded.
2867 * For now, I'll follow the spec...
2868 */
2869 static void gen_lswi(DisasContext *ctx)
2870 {
2871 TCGv t0;
2872 TCGv_i32 t1, t2;
2873 int nb = NB(ctx->opcode);
2874 int start = rD(ctx->opcode);
2875 int ra = rA(ctx->opcode);
2876 int nr;
2877
2878 if (ctx->le_mode) {
2879 gen_align_no_le(ctx);
2880 return;
2881 }
2882 if (nb == 0)
2883 nb = 32;
2884 nr = (nb + 3) / 4;
2885 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2886 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2887 return;
2888 }
2889 gen_set_access_type(ctx, ACCESS_INT);
2890 t0 = tcg_temp_new();
2891 gen_addr_register(ctx, t0);
2892 t1 = tcg_const_i32(nb);
2893 t2 = tcg_const_i32(start);
2894 gen_helper_lsw(cpu_env, t0, t1, t2);
2895 tcg_temp_free(t0);
2896 tcg_temp_free_i32(t1);
2897 tcg_temp_free_i32(t2);
2898 }
2899
2900 /* lswx */
2901 static void gen_lswx(DisasContext *ctx)
2902 {
2903 TCGv t0;
2904 TCGv_i32 t1, t2, t3;
2905
2906 if (ctx->le_mode) {
2907 gen_align_no_le(ctx);
2908 return;
2909 }
2910 gen_set_access_type(ctx, ACCESS_INT);
2911 t0 = tcg_temp_new();
2912 gen_addr_reg_index(ctx, t0);
2913 t1 = tcg_const_i32(rD(ctx->opcode));
2914 t2 = tcg_const_i32(rA(ctx->opcode));
2915 t3 = tcg_const_i32(rB(ctx->opcode));
2916 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2917 tcg_temp_free(t0);
2918 tcg_temp_free_i32(t1);
2919 tcg_temp_free_i32(t2);
2920 tcg_temp_free_i32(t3);
2921 }
2922
2923 /* stswi */
2924 static void gen_stswi(DisasContext *ctx)
2925 {
2926 TCGv t0;
2927 TCGv_i32 t1, t2;
2928 int nb = NB(ctx->opcode);
2929
2930 if (ctx->le_mode) {
2931 gen_align_no_le(ctx);
2932 return;
2933 }
2934 gen_set_access_type(ctx, ACCESS_INT);
2935 t0 = tcg_temp_new();
2936 gen_addr_register(ctx, t0);
2937 if (nb == 0)
2938 nb = 32;
2939 t1 = tcg_const_i32(nb);
2940 t2 = tcg_const_i32(rS(ctx->opcode));
2941 gen_helper_stsw(cpu_env, t0, t1, t2);
2942 tcg_temp_free(t0);
2943 tcg_temp_free_i32(t1);
2944 tcg_temp_free_i32(t2);
2945 }
2946
2947 /* stswx */
2948 static void gen_stswx(DisasContext *ctx)
2949 {
2950 TCGv t0;
2951 TCGv_i32 t1, t2;
2952
2953 if (ctx->le_mode) {
2954 gen_align_no_le(ctx);
2955 return;
2956 }
2957 gen_set_access_type(ctx, ACCESS_INT);
2958 t0 = tcg_temp_new();
2959 gen_addr_reg_index(ctx, t0);
2960 t1 = tcg_temp_new_i32();
2961 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2962 tcg_gen_andi_i32(t1, t1, 0x7F);
2963 t2 = tcg_const_i32(rS(ctx->opcode));
2964 gen_helper_stsw(cpu_env, t0, t1, t2);
2965 tcg_temp_free(t0);
2966 tcg_temp_free_i32(t1);
2967 tcg_temp_free_i32(t2);
2968 }
2969
2970 /*** Memory synchronisation ***/
2971 /* eieio */
2972 static void gen_eieio(DisasContext *ctx)
2973 {
2974 tcg_gen_mb(TCG_MO_LD_ST | TCG_BAR_SC);
2975 }
2976
2977 #if !defined(CONFIG_USER_ONLY)
2978 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
2979 {
2980 TCGv_i32 t;
2981 TCGLabel *l;
2982
2983 if (!ctx->lazy_tlb_flush) {
2984 return;
2985 }
2986 l = gen_new_label();
2987 t = tcg_temp_new_i32();
2988 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
2989 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
2990 if (global) {
2991 gen_helper_check_tlb_flush_global(cpu_env);
2992 } else {
2993 gen_helper_check_tlb_flush_local(cpu_env);
2994 }
2995 gen_set_label(l);
2996 tcg_temp_free_i32(t);
2997 }
2998 #else
2999 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
3000 #endif
3001
3002 /* isync */
3003 static void gen_isync(DisasContext *ctx)
3004 {
3005 /*
3006 * We need to check for a pending TLB flush. This can only happen in
3007 * kernel mode however so check MSR_PR
3008 */
3009 if (!ctx->pr) {
3010 gen_check_tlb_flush(ctx, false);
3011 }
3012 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3013 gen_stop_exception(ctx);
3014 }
3015
3016 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3017
3018 #define LARX(name, memop) \
3019 static void gen_##name(DisasContext *ctx) \
3020 { \
3021 TCGv t0; \
3022 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3023 int len = MEMOP_GET_SIZE(memop); \
3024 gen_set_access_type(ctx, ACCESS_RES); \
3025 t0 = tcg_temp_local_new(); \
3026 gen_addr_reg_index(ctx, t0); \
3027 if ((len) > 1) { \
3028 gen_check_align(ctx, t0, (len)-1); \
3029 } \
3030 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
3031 tcg_gen_mov_tl(cpu_reserve, t0); \
3032 tcg_gen_mov_tl(cpu_reserve_val, gpr); \
3033 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \
3034 tcg_temp_free(t0); \
3035 }
3036
3037 /* lwarx */
3038 LARX(lbarx, DEF_MEMOP(MO_UB))
3039 LARX(lharx, DEF_MEMOP(MO_UW))
3040 LARX(lwarx, DEF_MEMOP(MO_UL))
3041
3042 #define LD_ATOMIC(name, memop, tp, op, eop) \
3043 static void gen_##name(DisasContext *ctx) \
3044 { \
3045 int len = MEMOP_GET_SIZE(memop); \
3046 uint32_t gpr_FC = FC(ctx->opcode); \
3047 TCGv EA = tcg_temp_local_new(); \
3048 TCGv_##tp t0, t1; \
3049 \
3050 gen_addr_register(ctx, EA); \
3051 if (len > 1) { \
3052 gen_check_align(ctx, EA, len - 1); \
3053 } \
3054 t0 = tcg_temp_new_##tp(); \
3055 t1 = tcg_temp_new_##tp(); \
3056 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3057 \
3058 switch (gpr_FC) { \
3059 case 0: /* Fetch and add */ \
3060 tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3061 break; \
3062 case 1: /* Fetch and xor */ \
3063 tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3064 break; \
3065 case 2: /* Fetch and or */ \
3066 tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3067 break; \
3068 case 3: /* Fetch and 'and' */ \
3069 tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3070 break; \
3071 case 8: /* Swap */ \
3072 tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3073 break; \
3074 case 4: /* Fetch and max unsigned */ \
3075 case 5: /* Fetch and max signed */ \
3076 case 6: /* Fetch and min unsigned */ \
3077 case 7: /* Fetch and min signed */ \
3078 case 16: /* compare and swap not equal */ \
3079 case 24: /* Fetch and increment bounded */ \
3080 case 25: /* Fetch and increment equal */ \
3081 case 28: /* Fetch and decrement bounded */ \
3082 gen_invalid(ctx); \
3083 break; \
3084 default: \
3085 /* invoke data storage error handler */ \
3086 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3087 } \
3088 tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
3089 tcg_temp_free_##tp(t0); \
3090 tcg_temp_free_##tp(t1); \
3091 tcg_temp_free(EA); \
3092 }
3093
3094 LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
3095 #if defined(TARGET_PPC64)
3096 LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
3097 #endif
3098
3099 #define ST_ATOMIC(name, memop, tp, op) \
3100 static void gen_##name(DisasContext *ctx) \
3101 { \
3102 int len = MEMOP_GET_SIZE(memop); \
3103 uint32_t gpr_FC = FC(ctx->opcode); \
3104 TCGv EA = tcg_temp_local_new(); \
3105 TCGv_##tp t0, t1; \
3106 \
3107 gen_addr_register(ctx, EA); \
3108 if (len > 1) { \
3109 gen_check_align(ctx, EA, len - 1); \
3110 } \
3111 t0 = tcg_temp_new_##tp(); \
3112 t1 = tcg_temp_new_##tp(); \
3113 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3114 \
3115 switch (gpr_FC) { \
3116 case 0: /* add and Store */ \
3117 tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3118 break; \
3119 case 1: /* xor and Store */ \
3120 tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3121 break; \
3122 case 2: /* Or and Store */ \
3123 tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3124 break; \
3125 case 3: /* 'and' and Store */ \
3126 tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3127 break; \
3128 case 4: /* Store max unsigned */ \
3129 case 5: /* Store max signed */ \
3130 case 6: /* Store min unsigned */ \
3131 case 7: /* Store min signed */ \
3132 case 24: /* Store twin */ \
3133 gen_invalid(ctx); \
3134 break; \
3135 default: \
3136 /* invoke data storage error handler */ \
3137 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3138 } \
3139 tcg_temp_free_##tp(t0); \
3140 tcg_temp_free_##tp(t1); \
3141 tcg_temp_free(EA); \
3142 }
3143
3144 ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32)
3145 #if defined(TARGET_PPC64)
3146 ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64)
3147 #endif
3148
3149 #if defined(CONFIG_USER_ONLY)
3150 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3151 int reg, int memop)
3152 {
3153 TCGv t0 = tcg_temp_new();
3154
3155 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3156 tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg);
3157 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3158 tcg_temp_free(t0);
3159 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3160 }
3161 #else
3162 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3163 int reg, int memop)
3164 {
3165 TCGLabel *l1 = gen_new_label();
3166 TCGLabel *l2 = gen_new_label();
3167 TCGv t0;
3168
3169 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3170
3171 t0 = tcg_temp_new();
3172 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3173 cpu_gpr[reg], ctx->mem_idx,
3174 DEF_MEMOP(memop) | MO_ALIGN);
3175 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3176 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3177 tcg_gen_or_tl(t0, t0, cpu_so);
3178 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3179 tcg_temp_free(t0);
3180 tcg_gen_br(l2);
3181
3182 gen_set_label(l1);
3183
3184 /* Address mismatch implies failure. But we still need to provide the
3185 memory barrier semantics of the instruction. */
3186 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
3187 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3188
3189 gen_set_label(l2);
3190 tcg_gen_movi_tl(cpu_reserve, -1);
3191 }
3192 #endif
3193
3194 #define STCX(name, memop) \
3195 static void gen_##name(DisasContext *ctx) \
3196 { \
3197 TCGv t0; \
3198 int len = MEMOP_GET_SIZE(memop); \
3199 gen_set_access_type(ctx, ACCESS_RES); \
3200 t0 = tcg_temp_local_new(); \
3201 gen_addr_reg_index(ctx, t0); \
3202 if (len > 1) { \
3203 gen_check_align(ctx, t0, (len) - 1); \
3204 } \
3205 gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
3206 tcg_temp_free(t0); \
3207 }
3208
3209 STCX(stbcx_, DEF_MEMOP(MO_UB))
3210 STCX(sthcx_, DEF_MEMOP(MO_UW))
3211 STCX(stwcx_, DEF_MEMOP(MO_UL))
3212
3213 #if defined(TARGET_PPC64)
3214 /* ldarx */
3215 LARX(ldarx, DEF_MEMOP(MO_Q))
3216 /* stdcx. */
3217 STCX(stdcx_, DEF_MEMOP(MO_Q))
3218
3219 /* lqarx */
3220 static void gen_lqarx(DisasContext *ctx)
3221 {
3222 TCGv EA;
3223 int rd = rD(ctx->opcode);
3224 TCGv gpr1, gpr2;
3225
3226 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3227 (rd == rB(ctx->opcode)))) {
3228 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3229 return;
3230 }
3231
3232 gen_set_access_type(ctx, ACCESS_RES);
3233 EA = tcg_temp_local_new();
3234 gen_addr_reg_index(ctx, EA);
3235 gen_check_align(ctx, EA, 15);
3236 if (unlikely(ctx->le_mode)) {
3237 gpr1 = cpu_gpr[rd+1];
3238 gpr2 = cpu_gpr[rd];
3239 } else {
3240 gpr1 = cpu_gpr[rd];
3241 gpr2 = cpu_gpr[rd+1];
3242 }
3243 tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3244 tcg_gen_mov_tl(cpu_reserve, EA);
3245 gen_addr_add(ctx, EA, EA, 8);
3246 tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3247
3248 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3249 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3250 tcg_temp_free(EA);
3251 }
3252
3253 /* stqcx. */
3254 static void gen_stqcx_(DisasContext *ctx)
3255 {
3256 TCGv EA;
3257 int reg = rS(ctx->opcode);
3258 int len = 16;
3259 #if !defined(CONFIG_USER_ONLY)
3260 TCGLabel *l1;
3261 TCGv gpr1, gpr2;
3262 #endif
3263
3264 if (unlikely((rD(ctx->opcode) & 1))) {
3265 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3266 return;
3267 }
3268 gen_set_access_type(ctx, ACCESS_RES);
3269 EA = tcg_temp_local_new();
3270 gen_addr_reg_index(ctx, EA);
3271 if (len > 1) {
3272 gen_check_align(ctx, EA, (len) - 1);
3273 }
3274
3275 #if defined(CONFIG_USER_ONLY)
3276 gen_conditional_store(ctx, EA, reg, 16);
3277 #else
3278 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3279 l1 = gen_new_label();
3280 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3281 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
3282
3283 if (unlikely(ctx->le_mode)) {
3284 gpr1 = cpu_gpr[reg + 1];
3285 gpr2 = cpu_gpr[reg];
3286 } else {
3287 gpr1 = cpu_gpr[reg];
3288 gpr2 = cpu_gpr[reg + 1];
3289 }
3290 tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3291 gen_addr_add(ctx, EA, EA, 8);
3292 tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3293
3294 gen_set_label(l1);
3295 tcg_gen_movi_tl(cpu_reserve, -1);
3296 #endif
3297 tcg_temp_free(EA);
3298 }
3299
3300 #endif /* defined(TARGET_PPC64) */
3301
3302 /* sync */
3303 static void gen_sync(DisasContext *ctx)
3304 {
3305 uint32_t l = (ctx->opcode >> 21) & 3;
3306
3307 /*
3308 * We may need to check for a pending TLB flush.
3309 *
3310 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3311 *
3312 * Additionally, this can only happen in kernel mode however so
3313 * check MSR_PR as well.
3314 */
3315 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3316 gen_check_tlb_flush(ctx, true);
3317 }
3318 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3319 }
3320
3321 /* wait */
3322 static void gen_wait(DisasContext *ctx)
3323 {
3324 TCGv_i32 t0 = tcg_const_i32(1);
3325 tcg_gen_st_i32(t0, cpu_env,
3326 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3327 tcg_temp_free_i32(t0);
3328 /* Stop translation, as the CPU is supposed to sleep from now */
3329 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3330 }
3331
3332 #if defined(TARGET_PPC64)
3333 static void gen_doze(DisasContext *ctx)
3334 {
3335 #if defined(CONFIG_USER_ONLY)
3336 GEN_PRIV;
3337 #else
3338 TCGv_i32 t;
3339
3340 CHK_HV;
3341 t = tcg_const_i32(PPC_PM_DOZE);
3342 gen_helper_pminsn(cpu_env, t);
3343 tcg_temp_free_i32(t);
3344 gen_stop_exception(ctx);
3345 #endif /* defined(CONFIG_USER_ONLY) */
3346 }
3347
3348 static void gen_nap(DisasContext *ctx)
3349 {
3350 #if defined(CONFIG_USER_ONLY)
3351 GEN_PRIV;
3352 #else
3353 TCGv_i32 t;
3354
3355 CHK_HV;
3356 t = tcg_const_i32(PPC_PM_NAP);
3357 gen_helper_pminsn(cpu_env, t);
3358 tcg_temp_free_i32(t);
3359 gen_stop_exception(ctx);
3360 #endif /* defined(CONFIG_USER_ONLY) */
3361 }
3362
3363 static void gen_stop(DisasContext *ctx)
3364 {
3365 gen_nap(ctx);
3366 }
3367
3368 static void gen_sleep(DisasContext *ctx)
3369 {
3370 #if defined(CONFIG_USER_ONLY)
3371 GEN_PRIV;
3372 #else
3373 TCGv_i32 t;
3374
3375 CHK_HV;
3376 t = tcg_const_i32(PPC_PM_SLEEP);
3377 gen_helper_pminsn(cpu_env, t);
3378 tcg_temp_free_i32(t);
3379 gen_stop_exception(ctx);
3380 #endif /* defined(CONFIG_USER_ONLY) */
3381 }
3382
3383 static void gen_rvwinkle(DisasContext *ctx)
3384 {
3385 #if defined(CONFIG_USER_ONLY)
3386 GEN_PRIV;
3387 #else
3388 TCGv_i32 t;
3389
3390 CHK_HV;
3391 t = tcg_const_i32(PPC_PM_RVWINKLE);
3392 gen_helper_pminsn(cpu_env, t);
3393 tcg_temp_free_i32(t);
3394 gen_stop_exception(ctx);
3395 #endif /* defined(CONFIG_USER_ONLY) */
3396 }
3397 #endif /* #if defined(TARGET_PPC64) */
3398
3399 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3400 {
3401 #if defined(TARGET_PPC64)
3402 if (ctx->has_cfar)
3403 tcg_gen_movi_tl(cpu_cfar, nip);
3404 #endif
3405 }
3406
3407 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3408 {
3409 if (unlikely(ctx->singlestep_enabled)) {
3410 return false;
3411 }
3412
3413 #ifndef CONFIG_USER_ONLY
3414 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3415 #else
3416 return true;
3417 #endif
3418 }
3419
3420 /*** Branch ***/
3421 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3422 {
3423 if (NARROW_MODE(ctx)) {
3424 dest = (uint32_t) dest;
3425 }
3426 if (use_goto_tb(ctx, dest)) {
3427 tcg_gen_goto_tb(n);
3428 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3429 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3430 } else {
3431 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3432 if (unlikely(ctx->singlestep_enabled)) {
3433 if ((ctx->singlestep_enabled &
3434 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3435 (ctx->exception == POWERPC_EXCP_BRANCH ||
3436 ctx->exception == POWERPC_EXCP_TRACE)) {
3437 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3438 }
3439 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3440 gen_debug_exception(ctx);
3441 }
3442 }
3443 tcg_gen_exit_tb(0);
3444 }
3445 }
3446
3447 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3448 {
3449 if (NARROW_MODE(ctx)) {
3450 nip = (uint32_t)nip;
3451 }
3452 tcg_gen_movi_tl(cpu_lr, nip);
3453 }
3454
3455 /* b ba bl bla */
3456 static void gen_b(DisasContext *ctx)
3457 {
3458 target_ulong li, target;
3459
3460 ctx->exception = POWERPC_EXCP_BRANCH;
3461 /* sign extend LI */
3462 li = LI(ctx->opcode);
3463 li = (li ^ 0x02000000) - 0x02000000;
3464 if (likely(AA(ctx->opcode) == 0)) {
3465 target = ctx->nip + li - 4;
3466 } else {
3467 target = li;
3468 }
3469 if (LK(ctx->opcode)) {
3470 gen_setlr(ctx, ctx->nip);
3471 }
3472 gen_update_cfar(ctx, ctx->nip - 4);
3473 gen_goto_tb(ctx, 0, target);
3474 }
3475
3476 #define BCOND_IM 0
3477 #define BCOND_LR 1
3478 #define BCOND_CTR 2
3479 #define BCOND_TAR 3
3480
3481 static inline void gen_bcond(DisasContext *ctx, int type)
3482 {
3483 uint32_t bo = BO(ctx->opcode);
3484 TCGLabel *l1;
3485 TCGv target;
3486
3487 ctx->exception = POWERPC_EXCP_BRANCH;
3488 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3489 target = tcg_temp_local_new();
3490 if (type == BCOND_CTR)
3491 tcg_gen_mov_tl(target, cpu_ctr);
3492 else if (type == BCOND_TAR)
3493 gen_load_spr(target, SPR_TAR);
3494 else
3495 tcg_gen_mov_tl(target, cpu_lr);
3496 } else {
3497 TCGV_UNUSED(target);
3498 }
3499 if (LK(ctx->opcode))
3500 gen_setlr(ctx, ctx->nip);
3501 l1 = gen_new_label();
3502 if ((bo & 0x4) == 0) {
3503 /* Decrement and test CTR */
3504 TCGv temp = tcg_temp_new();
3505 if (unlikely(type == BCOND_CTR)) {
3506 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3507 return;
3508 }
3509 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3510 if (NARROW_MODE(ctx)) {
3511 tcg_gen_ext32u_tl(temp, cpu_ctr);
3512 } else {
3513 tcg_gen_mov_tl(temp, cpu_ctr);
3514 }
3515 if (bo & 0x2) {
3516 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3517 } else {
3518 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3519 }
3520 tcg_temp_free(temp);
3521 }
3522 if ((bo & 0x10) == 0) {
3523 /* Test CR */
3524 uint32_t bi = BI(ctx->opcode);
3525 uint32_t mask = 0x08 >> (bi & 0x03);
3526 TCGv_i32 temp = tcg_temp_new_i32();
3527
3528 if (bo & 0x8) {
3529 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3530 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3531 } else {
3532 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3533 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3534 }
3535 tcg_temp_free_i32(temp);
3536 }
3537 gen_update_cfar(ctx, ctx->nip - 4);
3538 if (type == BCOND_IM) {
3539 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3540 if (likely(AA(ctx->opcode) == 0)) {
3541 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3542 } else {
3543 gen_goto_tb(ctx, 0, li);
3544 }
3545 if ((bo & 0x14) != 0x14) {
3546 gen_set_label(l1);
3547 gen_goto_tb(ctx, 1, ctx->nip);
3548 }
3549 } else {
3550 if (NARROW_MODE(ctx)) {
3551 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3552 } else {
3553 tcg_gen_andi_tl(cpu_nip, target, ~3);
3554 }
3555 tcg_gen_exit_tb(0);
3556 if ((bo & 0x14) != 0x14) {
3557 gen_set_label(l1);
3558 gen_update_nip(ctx, ctx->nip);
3559 tcg_gen_exit_tb(0);
3560 }
3561 }
3562 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3563 tcg_temp_free(target);
3564 }
3565 }
3566
3567 static void gen_bc(DisasContext *ctx)
3568 {
3569 gen_bcond(ctx, BCOND_IM);
3570 }
3571
3572 static void gen_bcctr(DisasContext *ctx)
3573 {
3574 gen_bcond(ctx, BCOND_CTR);
3575 }
3576
3577 static void gen_bclr(DisasContext *ctx)
3578 {
3579 gen_bcond(ctx, BCOND_LR);
3580 }
3581
3582 static void gen_bctar(DisasContext *ctx)
3583 {
3584 gen_bcond(ctx, BCOND_TAR);
3585 }
3586
3587 /*** Condition register logical ***/
3588 #define GEN_CRLOGIC(name, tcg_op, opc) \
3589 static void glue(gen_, name)(DisasContext *ctx) \
3590 { \
3591 uint8_t bitmask; \
3592 int sh; \
3593 TCGv_i32 t0, t1; \
3594 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3595 t0 = tcg_temp_new_i32(); \
3596 if (sh > 0) \
3597 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3598 else if (sh < 0) \
3599 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3600 else \
3601 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3602 t1 = tcg_temp_new_i32(); \
3603 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3604 if (sh > 0) \
3605 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3606 else if (sh < 0) \
3607 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3608 else \
3609 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3610 tcg_op(t0, t0, t1); \
3611 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3612 tcg_gen_andi_i32(t0, t0, bitmask); \
3613 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3614 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3615 tcg_temp_free_i32(t0); \
3616 tcg_temp_free_i32(t1); \
3617 }
3618
3619 /* crand */
3620 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3621 /* crandc */
3622 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3623 /* creqv */
3624 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3625 /* crnand */
3626 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3627 /* crnor */
3628 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3629 /* cror */
3630 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3631 /* crorc */
3632 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3633 /* crxor */
3634 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3635
3636 /* mcrf */
3637 static void gen_mcrf(DisasContext *ctx)
3638 {
3639 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3640 }
3641
3642 /*** System linkage ***/
3643
3644 /* rfi (supervisor only) */
3645 static void gen_rfi(DisasContext *ctx)
3646 {
3647 #if defined(CONFIG_USER_ONLY)
3648 GEN_PRIV;
3649 #else
3650 /* This instruction doesn't exist anymore on 64-bit server
3651 * processors compliant with arch 2.x
3652 */
3653 if (ctx->insns_flags & PPC_SEGMENT_64B) {
3654 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3655 return;
3656 }
3657 /* Restore CPU state */
3658 CHK_SV;
3659 gen_update_cfar(ctx, ctx->nip - 4);
3660 gen_helper_rfi(cpu_env);
3661 gen_sync_exception(ctx);
3662 #endif
3663 }
3664
3665 #if defined(TARGET_PPC64)
3666 static void gen_rfid(DisasContext *ctx)
3667 {
3668 #if defined(CONFIG_USER_ONLY)
3669 GEN_PRIV;
3670 #else
3671 /* Restore CPU state */
3672 CHK_SV;
3673 gen_update_cfar(ctx, ctx->nip - 4);
3674 gen_helper_rfid(cpu_env);
3675 gen_sync_exception(ctx);
3676 #endif
3677 }
3678
3679 static void gen_hrfid(DisasContext *ctx)
3680 {
3681 #if defined(CONFIG_USER_ONLY)
3682 GEN_PRIV;
3683 #else
3684 /* Restore CPU state */
3685 CHK_HV;
3686 gen_helper_hrfid(cpu_env);
3687 gen_sync_exception(ctx);
3688 #endif
3689 }
3690 #endif
3691
3692 /* sc */
3693 #if defined(CONFIG_USER_ONLY)
3694 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3695 #else
3696 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3697 #endif
3698 static void gen_sc(DisasContext *ctx)
3699 {
3700 uint32_t lev;
3701
3702 lev = (ctx->opcode >> 5) & 0x7F;
3703 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3704 }
3705
3706 /*** Trap ***/
3707
3708 /* Check for unconditional traps (always or never) */
3709 static bool check_unconditional_trap(DisasContext *ctx)
3710 {
3711 /* Trap never */
3712 if (TO(ctx->opcode) == 0) {
3713 return true;
3714 }
3715 /* Trap always */
3716 if (TO(ctx->opcode) == 31) {
3717 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3718 return true;
3719 }
3720 return false;
3721 }
3722
3723 /* tw */
3724 static void gen_tw(DisasContext *ctx)
3725 {
3726 TCGv_i32 t0;
3727
3728 if (check_unconditional_trap(ctx)) {
3729 return;
3730 }
3731 t0 = tcg_const_i32(TO(ctx->opcode));
3732 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3733 t0);
3734 tcg_temp_free_i32(t0);
3735 }
3736
3737 /* twi */
3738 static void gen_twi(DisasContext *ctx)
3739 {
3740 TCGv t0;
3741 TCGv_i32 t1;
3742
3743 if (check_unconditional_trap(ctx)) {
3744 return;
3745 }
3746 t0 = tcg_const_tl(SIMM(ctx->opcode));
3747 t1 = tcg_const_i32(TO(ctx->opcode));
3748 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3749 tcg_temp_free(t0);
3750 tcg_temp_free_i32(t1);
3751 }
3752
3753 #if defined(TARGET_PPC64)
3754 /* td */
3755 static void gen_td(DisasContext *ctx)
3756 {
3757 TCGv_i32 t0;
3758
3759 if (check_unconditional_trap(ctx)) {
3760 return;
3761 }
3762 t0 = tcg_const_i32(TO(ctx->opcode));
3763 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3764 t0);
3765 tcg_temp_free_i32(t0);
3766 }
3767
3768 /* tdi */
3769 static void gen_tdi(DisasContext *ctx)
3770 {
3771 TCGv t0;
3772 TCGv_i32 t1;
3773
3774 if (check_unconditional_trap(ctx)) {
3775 return;
3776 }
3777 t0 = tcg_const_tl(SIMM(ctx->opcode));
3778 t1 = tcg_const_i32(TO(ctx->opcode));
3779 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3780 tcg_temp_free(t0);
3781 tcg_temp_free_i32(t1);
3782 }
3783 #endif
3784
3785 /*** Processor control ***/
3786
3787 static void gen_read_xer(DisasContext *ctx, TCGv dst)
3788 {
3789 TCGv t0 = tcg_temp_new();
3790 TCGv t1 = tcg_temp_new();
3791 TCGv t2 = tcg_temp_new();
3792 tcg_gen_mov_tl(dst, cpu_xer);
3793 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3794 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3795 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3796 tcg_gen_or_tl(t0, t0, t1);
3797 tcg_gen_or_tl(dst, dst, t2);
3798 tcg_gen_or_tl(dst, dst, t0);
3799 if (is_isa300(ctx)) {
3800 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
3801 tcg_gen_or_tl(dst, dst, t0);
3802 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
3803 tcg_gen_or_tl(dst, dst, t0);
3804 }
3805 tcg_temp_free(t0);
3806 tcg_temp_free(t1);
3807 tcg_temp_free(t2);
3808 }
3809
3810 static void gen_write_xer(TCGv src)
3811 {
3812 /* Write all flags, while reading back check for isa300 */
3813 tcg_gen_andi_tl(cpu_xer, src,
3814 ~((1u << XER_SO) |
3815 (1u << XER_OV) | (1u << XER_OV32) |
3816 (1u << XER_CA) | (1u << XER_CA32)));
3817 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
3818 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
3819 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
3820 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
3821 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
3822 }
3823
3824 /* mcrxr */
3825 static void gen_mcrxr(DisasContext *ctx)
3826 {
3827 TCGv_i32 t0 = tcg_temp_new_i32();
3828 TCGv_i32 t1 = tcg_temp_new_i32();
3829 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3830
3831 tcg_gen_trunc_tl_i32(t0, cpu_so);
3832 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3833 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3834 tcg_gen_shli_i32(t0, t0, 3);
3835 tcg_gen_shli_i32(t1, t1, 2);
3836 tcg_gen_shli_i32(dst, dst, 1);
3837 tcg_gen_or_i32(dst, dst, t0);
3838 tcg_gen_or_i32(dst, dst, t1);
3839 tcg_temp_free_i32(t0);
3840 tcg_temp_free_i32(t1);
3841
3842 tcg_gen_movi_tl(cpu_so, 0);
3843 tcg_gen_movi_tl(cpu_ov, 0);
3844 tcg_gen_movi_tl(cpu_ca, 0);
3845 }
3846
3847 #ifdef TARGET_PPC64
3848 /* mcrxrx */
3849 static void gen_mcrxrx(DisasContext *ctx)
3850 {
3851 TCGv t0 = tcg_temp_new();
3852 TCGv t1 = tcg_temp_new();
3853 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3854
3855 /* copy OV and OV32 */
3856 tcg_gen_shli_tl(t0, cpu_ov, 1);
3857 tcg_gen_or_tl(t0, t0, cpu_ov32);
3858 tcg_gen_shli_tl(t0, t0, 2);
3859 /* copy CA and CA32 */
3860 tcg_gen_shli_tl(t1, cpu_ca, 1);
3861 tcg_gen_or_tl(t1, t1, cpu_ca32);
3862 tcg_gen_or_tl(t0, t0, t1);
3863 tcg_gen_trunc_tl_i32(dst, t0);
3864 tcg_temp_free(t0);
3865 tcg_temp_free(t1);
3866 }
3867 #endif
3868
3869 /* mfcr mfocrf */
3870 static void gen_mfcr(DisasContext *ctx)
3871 {
3872 uint32_t crm, crn;
3873
3874 if (likely(ctx->opcode & 0x00100000)) {
3875 crm = CRM(ctx->opcode);
3876 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3877 crn = ctz32 (crm);
3878 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3879 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3880 cpu_gpr[rD(ctx->opcode)], crn * 4);
3881 }
3882 } else {
3883 TCGv_i32 t0 = tcg_temp_new_i32();
3884 tcg_gen_mov_i32(t0, cpu_crf[0]);
3885 tcg_gen_shli_i32(t0, t0, 4);
3886 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3887 tcg_gen_shli_i32(t0, t0, 4);
3888 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3889 tcg_gen_shli_i32(t0, t0, 4);
3890 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3891 tcg_gen_shli_i32(t0, t0, 4);
3892 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3893 tcg_gen_shli_i32(t0, t0, 4);
3894 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3895 tcg_gen_shli_i32(t0, t0, 4);
3896 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3897 tcg_gen_shli_i32(t0, t0, 4);
3898 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3899 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3900 tcg_temp_free_i32(t0);
3901 }
3902 }
3903
3904 /* mfmsr */
3905 static void gen_mfmsr(DisasContext *ctx)
3906 {
3907 CHK_SV;
3908 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3909 }
3910
3911 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3912 {
3913 #if 0
3914 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3915 printf("ERROR: try to access SPR %d !\n", sprn);
3916 #endif
3917 }
3918 #define SPR_NOACCESS (&spr_noaccess)
3919
3920 /* mfspr */
3921 static inline void gen_op_mfspr(DisasContext *ctx)
3922 {
3923 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3924 uint32_t sprn = SPR(ctx->opcode);
3925
3926 #if defined(CONFIG_USER_ONLY)
3927 read_cb = ctx->spr_cb[sprn].uea_read;
3928 #else
3929 if (ctx->pr) {
3930 read_cb = ctx->spr_cb[sprn].uea_read;
3931 } else if (ctx->hv) {
3932 read_cb = ctx->spr_cb[sprn].hea_read;
3933 } else {
3934 read_cb = ctx->spr_cb[sprn].oea_read;
3935 }
3936 #endif
3937 if (likely(read_cb != NULL)) {
3938 if (likely(read_cb != SPR_NOACCESS)) {
3939 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3940 } else {
3941 /* Privilege exception */
3942 /* This is a hack to avoid warnings when running Linux:
3943 * this OS breaks the PowerPC virtualisation model,
3944 * allowing userland application to read the PVR
3945 */
3946 if (sprn != SPR_PVR) {
3947 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3948 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3949 if (qemu_log_separate()) {
3950 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3951 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3952 }
3953 }
3954 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3955 }
3956 } else {
3957 /* ISA 2.07 defines these as no-ops */
3958 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3959 (sprn >= 808 && sprn <= 811)) {
3960 /* This is a nop */
3961 return;
3962 }
3963 /* Not defined */
3964 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3965 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3966 if (qemu_log_separate()) {
3967 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3968 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3969 }
3970
3971 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3972 * it can generate a priv, a hv emu or a no-op
3973 */
3974 if (sprn & 0x10) {
3975 if (ctx->pr) {
3976 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3977 }
3978 } else {
3979 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3980 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3981 }
3982 }
3983 }
3984 }
3985
3986 static void gen_mfspr(DisasContext *ctx)
3987 {
3988 gen_op_mfspr(ctx);
3989 }
3990
3991 /* mftb */
3992 static void gen_mftb(DisasContext *ctx)
3993 {
3994 gen_op_mfspr(ctx);
3995 }
3996
3997 /* mtcrf mtocrf*/
3998 static void gen_mtcrf(DisasContext *ctx)
3999 {
4000 uint32_t crm, crn;
4001
4002 crm = CRM(ctx->opcode);
4003 if (likely((ctx->opcode & 0x00100000))) {
4004 if (crm && ((crm & (crm - 1)) == 0)) {
4005 TCGv_i32 temp = tcg_temp_new_i32();
4006 crn = ctz32 (crm);
4007 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4008 tcg_gen_shri_i32(temp, temp, crn * 4);
4009 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4010 tcg_temp_free_i32(temp);
4011 }
4012 } else {
4013 TCGv_i32 temp = tcg_temp_new_i32();
4014 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4015 for (crn = 0 ; crn < 8 ; crn++) {
4016 if (crm & (1 << crn)) {
4017 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4018 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4019 }
4020 }
4021 tcg_temp_free_i32(temp);
4022 }
4023 }
4024
4025 /* mtmsr */
4026 #if defined(TARGET_PPC64)
4027 static void gen_mtmsrd(DisasContext *ctx)
4028 {
4029 CHK_SV;
4030
4031 #if !defined(CONFIG_USER_ONLY)
4032 if (ctx->opcode & 0x00010000) {
4033 /* Special form that does not need any synchronisation */
4034 TCGv t0 = tcg_temp_new();
4035 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4036 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4037 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4038 tcg_temp_free(t0);
4039 } else {
4040 /* XXX: we need to update nip before the store
4041 * if we enter power saving mode, we will exit the loop
4042 * directly from ppc_store_msr
4043 */
4044 gen_update_nip(ctx, ctx->nip);
4045 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4046 /* Must stop the translation as machine state (may have) changed */
4047 /* Note that mtmsr is not always defined as context-synchronizing */
4048 gen_stop_exception(ctx);
4049 }
4050 #endif /* !defined(CONFIG_USER_ONLY) */
4051 }
4052 #endif /* defined(TARGET_PPC64) */
4053
4054 static void gen_mtmsr(DisasContext *ctx)
4055 {
4056 CHK_SV;
4057
4058 #if !defined(CONFIG_USER_ONLY)
4059 if (ctx->opcode & 0x00010000) {
4060 /* Special form that does not need any synchronisation */
4061 TCGv t0 = tcg_temp_new();
4062 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4063 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4064 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4065 tcg_temp_free(t0);
4066 } else {
4067 TCGv msr = tcg_temp_new();
4068
4069 /* XXX: we need to update nip before the store
4070 * if we enter power saving mode, we will exit the loop
4071 * directly from ppc_store_msr
4072 */
4073 gen_update_nip(ctx, ctx->nip);
4074 #if defined(TARGET_PPC64)
4075 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4076 #else
4077 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4078 #endif
4079 gen_helper_store_msr(cpu_env, msr);
4080 tcg_temp_free(msr);
4081 /* Must stop the translation as machine state (may have) changed */
4082 /* Note that mtmsr is not always defined as context-synchronizing */
4083 gen_stop_exception(ctx);
4084 }
4085 #endif
4086 }
4087
4088 /* mtspr */
4089 static void gen_mtspr(DisasContext *ctx)
4090 {
4091 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4092 uint32_t sprn = SPR(ctx->opcode);
4093
4094 #if defined(CONFIG_USER_ONLY)
4095 write_cb = ctx->spr_cb[sprn].uea_write;
4096 #else
4097 if (ctx->pr) {
4098 write_cb = ctx->spr_cb[sprn].uea_write;
4099 } else if (ctx->hv) {
4100 write_cb = ctx->spr_cb[sprn].hea_write;
4101 } else {
4102 write_cb = ctx->spr_cb[sprn].oea_write;
4103 }
4104 #endif
4105 if (likely(write_cb != NULL)) {
4106 if (likely(write_cb != SPR_NOACCESS)) {
4107 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4108 } else {
4109 /* Privilege exception */
4110 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4111 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4112 if (qemu_log_separate()) {
4113 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4114 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4115 }
4116 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4117 }
4118 } else {
4119 /* ISA 2.07 defines these as no-ops */
4120 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4121 (sprn >= 808 && sprn <= 811)) {
4122 /* This is a nop */
4123 return;
4124 }
4125
4126 /* Not defined */
4127 if (qemu_log_separate()) {
4128 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4129 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4130 }
4131 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4132 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4133
4134
4135 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4136 * it can generate a priv, a hv emu or a no-op
4137 */
4138 if (sprn & 0x10) {
4139 if (ctx->pr) {
4140 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4141 }
4142 } else {
4143 if (ctx->pr || sprn == 0) {
4144 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4145 }
4146 }
4147 }
4148 }
4149
4150 #if defined(TARGET_PPC64)
4151 /* setb */
4152 static void gen_setb(DisasContext *ctx)
4153 {
4154 TCGv_i32 t0 = tcg_temp_new_i32();
4155 TCGv_i32 t8 = tcg_temp_new_i32();
4156 TCGv_i32 tm1 = tcg_temp_new_i32();
4157 int crf = crfS(ctx->opcode);
4158
4159 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4160 tcg_gen_movi_i32(t8, 8);
4161 tcg_gen_movi_i32(tm1, -1);
4162 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4163 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4164
4165 tcg_temp_free_i32(t0);
4166 tcg_temp_free_i32(t8);
4167 tcg_temp_free_i32(tm1);
4168 }
4169 #endif
4170
4171 /*** Cache management ***/
4172
4173 /* dcbf */
4174 static void gen_dcbf(DisasContext *ctx)
4175 {
4176 /* XXX: specification says this is treated as a load by the MMU */
4177 TCGv t0;
4178 gen_set_access_type(ctx, ACCESS_CACHE);
4179 t0 = tcg_temp_new();
4180 gen_addr_reg_index(ctx, t0);
4181 gen_qemu_ld8u(ctx, t0, t0);
4182 tcg_temp_free(t0);
4183 }
4184
4185 /* dcbi (Supervisor only) */
4186 static void gen_dcbi(DisasContext *ctx)
4187 {
4188 #if defined(CONFIG_USER_ONLY)
4189 GEN_PRIV;
4190 #else
4191 TCGv EA, val;
4192
4193 CHK_SV;
4194 EA = tcg_temp_new();
4195 gen_set_access_type(ctx, ACCESS_CACHE);
4196 gen_addr_reg_index(ctx, EA);
4197 val = tcg_temp_new();
4198 /* XXX: specification says this should be treated as a store by the MMU */
4199 gen_qemu_ld8u(ctx, val, EA);
4200 gen_qemu_st8(ctx, val, EA);
4201 tcg_temp_free(val);
4202 tcg_temp_free(EA);
4203 #endif /* defined(CONFIG_USER_ONLY) */
4204 }
4205
4206 /* dcdst */
4207 static void gen_dcbst(DisasContext *ctx)
4208 {
4209 /* XXX: specification say this is treated as a load by the MMU */
4210 TCGv t0;
4211 gen_set_access_type(ctx, ACCESS_CACHE);
4212 t0 = tcg_temp_new();
4213 gen_addr_reg_index(ctx, t0);
4214 gen_qemu_ld8u(ctx, t0, t0);
4215 tcg_temp_free(t0);
4216 }
4217
4218 /* dcbt */
4219 static void gen_dcbt(DisasContext *ctx)
4220 {
4221 /* interpreted as no-op */
4222 /* XXX: specification say this is treated as a load by the MMU
4223 * but does not generate any exception
4224 */
4225 }
4226
4227 /* dcbtst */
4228 static void gen_dcbtst(DisasContext *ctx)
4229 {
4230 /* interpreted as no-op */
4231 /* XXX: specification say this is treated as a load by the MMU
4232 * but does not generate any exception
4233 */
4234 }
4235
4236 /* dcbtls */
4237 static void gen_dcbtls(DisasContext *ctx)
4238 {
4239 /* Always fails locking the cache */
4240 TCGv t0 = tcg_temp_new();
4241 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4242 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4243 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4244 tcg_temp_free(t0);
4245 }
4246
4247 /* dcbz */
4248 static void gen_dcbz(DisasContext *ctx)
4249 {
4250 TCGv tcgv_addr;
4251 TCGv_i32 tcgv_op;
4252
4253 gen_set_access_type(ctx, ACCESS_CACHE);
4254 tcgv_addr = tcg_temp_new();
4255 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4256 gen_addr_reg_index(ctx, tcgv_addr);
4257 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4258 tcg_temp_free(tcgv_addr);
4259 tcg_temp_free_i32(tcgv_op);
4260 }
4261
4262 /* dst / dstt */
4263 static void gen_dst(DisasContext *ctx)
4264 {
4265 if (rA(ctx->opcode) == 0) {
4266 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4267 } else {
4268 /* interpreted as no-op */
4269 }
4270 }
4271
4272 /* dstst /dststt */
4273 static void gen_dstst(DisasContext *ctx)
4274 {
4275 if (rA(ctx->opcode) == 0) {
4276 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4277 } else {
4278 /* interpreted as no-op */
4279 }
4280
4281 }
4282
4283 /* dss / dssall */
4284 static void gen_dss(DisasContext *ctx)
4285 {
4286 /* interpreted as no-op */
4287 }
4288
4289 /* icbi */
4290 static void gen_icbi(DisasContext *ctx)
4291 {
4292 TCGv t0;
4293 gen_set_access_type(ctx, ACCESS_CACHE);
4294 t0 = tcg_temp_new();
4295 gen_addr_reg_index(ctx, t0);
4296 gen_helper_icbi(cpu_env, t0);
4297 tcg_temp_free(t0);
4298 }
4299
4300 /* Optional: */
4301 /* dcba */
4302 static void gen_dcba(DisasContext *ctx)
4303 {
4304 /* interpreted as no-op */
4305 /* XXX: specification say this is treated as a store by the MMU
4306 * but does not generate any exception
4307 */
4308 }
4309
4310 /*** Segment register manipulation ***/
4311 /* Supervisor only: */
4312
4313 /* mfsr */
4314 static void gen_mfsr(DisasContext *ctx)
4315 {
4316 #if defined(CONFIG_USER_ONLY)
4317 GEN_PRIV;
4318 #else
4319 TCGv t0;
4320
4321 CHK_SV;
4322 t0 = tcg_const_tl(SR(ctx->opcode));
4323 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4324 tcg_temp_free(t0);
4325 #endif /* defined(CONFIG_USER_ONLY) */
4326 }
4327
4328 /* mfsrin */
4329 static void gen_mfsrin(DisasContext *ctx)
4330 {
4331 #if defined(CONFIG_USER_ONLY)
4332 GEN_PRIV;
4333 #else
4334 TCGv t0;
4335
4336 CHK_SV;
4337 t0 = tcg_temp_new();
4338 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4339 tcg_gen_andi_tl(t0, t0, 0xF);
4340 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4341 tcg_temp_free(t0);
4342 #endif /* defined(CONFIG_USER_ONLY) */
4343 }
4344
4345 /* mtsr */
4346 static void gen_mtsr(DisasContext *ctx)
4347 {
4348 #if defined(CONFIG_USER_ONLY)
4349 GEN_PRIV;
4350 #else
4351 TCGv t0;
4352
4353 CHK_SV;
4354 t0 = tcg_const_tl(SR(ctx->opcode));
4355 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4356 tcg_temp_free(t0);
4357 #endif /* defined(CONFIG_USER_ONLY) */
4358 }
4359
4360 /* mtsrin */
4361 static void gen_mtsrin(DisasContext *ctx)
4362 {
4363 #if defined(CONFIG_USER_ONLY)
4364 GEN_PRIV;
4365 #else
4366 TCGv t0;
4367 CHK_SV;
4368
4369 t0 = tcg_temp_new();
4370 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4371 tcg_gen_andi_tl(t0, t0, 0xF);
4372 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4373 tcg_temp_free(t0);
4374 #endif /* defined(CONFIG_USER_ONLY) */
4375 }
4376
4377 #if defined(TARGET_PPC64)
4378 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4379
4380 /* mfsr */
4381 static void gen_mfsr_64b(DisasContext *ctx)
4382 {
4383 #if defined(CONFIG_USER_ONLY)
4384 GEN_PRIV;
4385 #else
4386 TCGv t0;
4387
4388 CHK_SV;
4389 t0 = tcg_const_tl(SR(ctx->opcode));
4390 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4391 tcg_temp_free(t0);
4392 #endif /* defined(CONFIG_USER_ONLY) */
4393 }
4394
4395 /* mfsrin */
4396 static void gen_mfsrin_64b(DisasContext *ctx)
4397 {
4398 #if defined(CONFIG_USER_ONLY)
4399 GEN_PRIV;
4400 #else
4401 TCGv t0;
4402
4403 CHK_SV;
4404 t0 = tcg_temp_new();
4405 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4406 tcg_gen_andi_tl(t0, t0, 0xF);
4407 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4408 tcg_temp_free(t0);
4409 #endif /* defined(CONFIG_USER_ONLY) */
4410 }
4411
4412 /* mtsr */
4413 static void gen_mtsr_64b(DisasContext *ctx)
4414 {
4415 #if defined(CONFIG_USER_ONLY)
4416 GEN_PRIV;
4417 #else
4418 TCGv t0;
4419
4420 CHK_SV;
4421 t0 = tcg_const_tl(SR(ctx->opcode));
4422 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4423 tcg_temp_free(t0);
4424 #endif /* defined(CONFIG_USER_ONLY) */
4425 }
4426
4427 /* mtsrin */
4428 static void gen_mtsrin_64b(DisasContext *ctx)
4429 {
4430 #if defined(CONFIG_USER_ONLY)
4431 GEN_PRIV;
4432 #else
4433 TCGv t0;
4434
4435 CHK_SV;
4436 t0 = tcg_temp_new();
4437 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4438 tcg_gen_andi_tl(t0, t0, 0xF);
4439 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4440 tcg_temp_free(t0);
4441 #endif /* defined(CONFIG_USER_ONLY) */
4442 }
4443
4444 /* slbmte */
4445 static void gen_slbmte(DisasContext *ctx)
4446 {
4447 #if defined(CONFIG_USER_ONLY)
4448 GEN_PRIV;
4449 #else
4450 CHK_SV;
4451
4452 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4453 cpu_gpr[rS(ctx->opcode)]);
4454 #endif /* defined(CONFIG_USER_ONLY) */
4455 }
4456
4457 static void gen_slbmfee(DisasContext *ctx)
4458 {
4459 #if defined(CONFIG_USER_ONLY)
4460 GEN_PRIV;
4461 #else
4462 CHK_SV;
4463
4464 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4465 cpu_gpr[rB(ctx->opcode)]);
4466 #endif /* defined(CONFIG_USER_ONLY) */
4467 }
4468
4469 static void gen_slbmfev(DisasContext *ctx)
4470 {
4471 #if defined(CONFIG_USER_ONLY)
4472 GEN_PRIV;
4473 #else
4474 CHK_SV;
4475
4476 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4477 cpu_gpr[rB(ctx->opcode)]);
4478 #endif /* defined(CONFIG_USER_ONLY) */
4479 }
4480
4481 static void gen_slbfee_(DisasContext *ctx)
4482 {
4483 #if defined(CONFIG_USER_ONLY)
4484 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4485 #else
4486 TCGLabel *l1, *l2;
4487
4488 if (unlikely(ctx->pr)) {
4489 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4490 return;
4491 }
4492 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4493 cpu_gpr[rB(ctx->opcode)]);
4494 l1 = gen_new_label();
4495 l2 = gen_new_label();
4496 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4497 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4498 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4499 tcg_gen_br(l2);
4500 gen_set_label(l1);
4501 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4502 gen_set_label(l2);
4503 #endif
4504 }
4505 #endif /* defined(TARGET_PPC64) */
4506
4507 /*** Lookaside buffer management ***/
4508 /* Optional & supervisor only: */
4509
4510 /* tlbia */
4511 static void gen_tlbia(DisasContext *ctx)
4512 {
4513 #if defined(CONFIG_USER_ONLY)
4514 GEN_PRIV;
4515 #else
4516 CHK_HV;
4517
4518 gen_helper_tlbia(cpu_env);
4519 #endif /* defined(CONFIG_USER_ONLY) */
4520 }
4521
4522 /* tlbiel */
4523 static void gen_tlbiel(DisasContext *ctx)
4524 {
4525 #if defined(CONFIG_USER_ONLY)
4526 GEN_PRIV;
4527 #else
4528 CHK_SV;
4529
4530 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4531 #endif /* defined(CONFIG_USER_ONLY) */
4532 }
4533
4534 /* tlbie */
4535 static void gen_tlbie(DisasContext *ctx)
4536 {
4537 #if defined(CONFIG_USER_ONLY)
4538 GEN_PRIV;
4539 #else
4540 TCGv_i32 t1;
4541 CHK_HV;
4542
4543 if (NARROW_MODE(ctx)) {
4544 TCGv t0 = tcg_temp_new();
4545 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4546 gen_helper_tlbie(cpu_env, t0);
4547 tcg_temp_free(t0);
4548 } else {
4549 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4550 }
4551 t1 = tcg_temp_new_i32();
4552 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4553 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4554 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4555 tcg_temp_free_i32(t1);
4556 #endif /* defined(CONFIG_USER_ONLY) */
4557 }
4558
4559 /* tlbsync */
4560 static void gen_tlbsync(DisasContext *ctx)
4561 {
4562 #if defined(CONFIG_USER_ONLY)
4563 GEN_PRIV;
4564 #else
4565 CHK_HV;
4566
4567 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4568 if (ctx->insns_flags & PPC_BOOKE) {
4569 gen_check_tlb_flush(ctx, true);
4570 }
4571 #endif /* defined(CONFIG_USER_ONLY) */
4572 }
4573
4574 #if defined(TARGET_PPC64)
4575 /* slbia */
4576 static void gen_slbia(DisasContext *ctx)
4577 {
4578 #if defined(CONFIG_USER_ONLY)
4579 GEN_PRIV;
4580 #else
4581 CHK_SV;
4582
4583 gen_helper_slbia(cpu_env);
4584 #endif /* defined(CONFIG_USER_ONLY) */
4585 }
4586
4587 /* slbie */
4588 static void gen_slbie(DisasContext *ctx)
4589 {
4590 #if defined(CONFIG_USER_ONLY)
4591 GEN_PRIV;
4592 #else
4593 CHK_SV;
4594
4595 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4596 #endif /* defined(CONFIG_USER_ONLY) */
4597 }
4598
4599 /* slbieg */
4600 static void gen_slbieg(DisasContext *ctx)
4601 {
4602 #if defined(CONFIG_USER_ONLY)
4603 GEN_PRIV;
4604 #else
4605 CHK_SV;
4606
4607 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4608 #endif /* defined(CONFIG_USER_ONLY) */
4609 }
4610
4611 /* slbsync */
4612 static void gen_slbsync(DisasContext *ctx)
4613 {
4614 #if defined(CONFIG_USER_ONLY)
4615 GEN_PRIV;
4616 #else
4617 CHK_SV;
4618 gen_check_tlb_flush(ctx, true);
4619 #endif /* defined(CONFIG_USER_ONLY) */
4620 }
4621
4622 #endif /* defined(TARGET_PPC64) */
4623
4624 /*** External control ***/
4625 /* Optional: */
4626
4627 /* eciwx */
4628 static void gen_eciwx(DisasContext *ctx)
4629 {
4630 TCGv t0;
4631 /* Should check EAR[E] ! */
4632 gen_set_access_type(ctx, ACCESS_EXT);
4633 t0 = tcg_temp_new();
4634 gen_addr_reg_index(ctx, t0);
4635 gen_check_align(ctx, t0, 0x03);
4636 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4637 tcg_temp_free(t0);
4638 }
4639
4640 /* ecowx */
4641 static void gen_ecowx(DisasContext *ctx)
4642 {
4643 TCGv t0;
4644 /* Should check EAR[E] ! */
4645 gen_set_access_type(ctx, ACCESS_EXT);
4646 t0 = tcg_temp_new();
4647 gen_addr_reg_index(ctx, t0);
4648 gen_check_align(ctx, t0, 0x03);
4649 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4650 tcg_temp_free(t0);
4651 }
4652
4653 /* PowerPC 601 specific instructions */
4654
4655 /* abs - abs. */
4656 static void gen_abs(DisasContext *ctx)
4657 {
4658 TCGLabel *l1 = gen_new_label();
4659 TCGLabel *l2 = gen_new_label();
4660 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4661 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4662 tcg_gen_br(l2);
4663 gen_set_label(l1);
4664 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4665 gen_set_label(l2);
4666 if (unlikely(Rc(ctx->opcode) != 0))
4667 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4668 }
4669
4670 /* abso - abso. */
4671 static void gen_abso(DisasContext *ctx)
4672 {
4673 TCGLabel *l1 = gen_new_label();
4674 TCGLabel *l2 = gen_new_label();
4675 TCGLabel *l3 = gen_new_label();
4676 /* Start with XER OV disabled, the most likely case */
4677 tcg_gen_movi_tl(cpu_ov, 0);
4678 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4679 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4680 tcg_gen_movi_tl(cpu_ov, 1);
4681 tcg_gen_movi_tl(cpu_so, 1);
4682 tcg_gen_br(l2);
4683 gen_set_label(l1);
4684 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4685 tcg_gen_br(l3);
4686 gen_set_label(l2);
4687 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4688 gen_set_label(l3);
4689 if (unlikely(Rc(ctx->opcode) != 0))
4690 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4691 }
4692
4693 /* clcs */
4694 static void gen_clcs(DisasContext *ctx)
4695 {
4696 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4697 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4698 tcg_temp_free_i32(t0);
4699 /* Rc=1 sets CR0 to an undefined state */
4700 }
4701
4702 /* div - div. */
4703 static void gen_div(DisasContext *ctx)
4704 {
4705 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4706 cpu_gpr[rB(ctx->opcode)]);
4707 if (unlikely(Rc(ctx->opcode) != 0))
4708 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4709 }
4710
4711 /* divo - divo. */
4712 static void gen_divo(DisasContext *ctx)
4713 {
4714 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4715 cpu_gpr[rB(ctx->opcode)]);
4716 if (unlikely(Rc(ctx->opcode) != 0))
4717 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4718 }
4719
4720 /* divs - divs. */
4721 static void gen_divs(DisasContext *ctx)
4722 {
4723 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4724 cpu_gpr[rB(ctx->opcode)]);
4725 if (unlikely(Rc(ctx->opcode) != 0))
4726 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4727 }
4728
4729 /* divso - divso. */
4730 static void gen_divso(DisasContext *ctx)
4731 {
4732 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4733 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4734 if (unlikely(Rc(ctx->opcode) != 0))
4735 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4736 }
4737
4738 /* doz - doz. */
4739 static void gen_doz(DisasContext *ctx)
4740 {
4741 TCGLabel *l1 = gen_new_label();
4742 TCGLabel *l2 = gen_new_label();
4743 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4744 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4745 tcg_gen_br(l2);
4746 gen_set_label(l1);
4747 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4748 gen_set_label(l2);
4749 if (unlikely(Rc(ctx->opcode) != 0))
4750 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4751 }
4752
4753 /* dozo - dozo. */
4754 static void gen_dozo(DisasContext *ctx)
4755 {
4756 TCGLabel *l1 = gen_new_label();
4757 TCGLabel *l2 = gen_new_label();
4758 TCGv t0 = tcg_temp_new();
4759 TCGv t1 = tcg_temp_new();
4760 TCGv t2 = tcg_temp_new();
4761 /* Start with XER OV disabled, the most likely case */
4762 tcg_gen_movi_tl(cpu_ov, 0);
4763 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4764 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4765 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4766 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4767 tcg_gen_andc_tl(t1, t1, t2);
4768 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4769 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4770 tcg_gen_movi_tl(cpu_ov, 1);
4771 tcg_gen_movi_tl(cpu_so, 1);
4772 tcg_gen_br(l2);
4773 gen_set_label(l1);
4774 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4775 gen_set_label(l2);
4776 tcg_temp_free(t0);
4777 tcg_temp_free(t1);
4778 tcg_temp_free(t2);
4779 if (unlikely(Rc(ctx->opcode) != 0))
4780 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4781 }
4782
4783 /* dozi */
4784 static void gen_dozi(DisasContext *ctx)
4785 {
4786 target_long simm = SIMM(ctx->opcode);
4787 TCGLabel *l1 = gen_new_label();
4788 TCGLabel *l2 = gen_new_label();
4789 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4790 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4791 tcg_gen_br(l2);
4792 gen_set_label(l1);
4793 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4794 gen_set_label(l2);
4795 if (unlikely(Rc(ctx->opcode) != 0))
4796 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4797 }
4798
4799 /* lscbx - lscbx. */
4800 static void gen_lscbx(DisasContext *ctx)
4801 {
4802 TCGv t0 = tcg_temp_new();
4803 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4804 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4805 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4806
4807 gen_addr_reg_index(ctx, t0);
4808 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4809 tcg_temp_free_i32(t1);
4810 tcg_temp_free_i32(t2);
4811 tcg_temp_free_i32(t3);
4812 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4813 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4814 if (unlikely(Rc(ctx->opcode) != 0))
4815 gen_set_Rc0(ctx, t0);
4816 tcg_temp_free(t0);
4817 }
4818
4819 /* maskg - maskg. */
4820 static void gen_maskg(DisasContext *ctx)
4821 {
4822 TCGLabel *l1 = gen_new_label();
4823 TCGv t0 = tcg_temp_new();
4824 TCGv t1 = tcg_temp_new();
4825 TCGv t2 = tcg_temp_new();
4826 TCGv t3 = tcg_temp_new();
4827 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4828 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4829 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4830 tcg_gen_addi_tl(t2, t0, 1);
4831 tcg_gen_shr_tl(t2, t3, t2);
4832 tcg_gen_shr_tl(t3, t3, t1);
4833 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4834 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4835 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4836 gen_set_label(l1);
4837 tcg_temp_free(t0);
4838 tcg_temp_free(t1);
4839 tcg_temp_free(t2);
4840 tcg_temp_free(t3);
4841 if (unlikely(Rc(ctx->opcode) != 0))
4842 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4843 }
4844
4845 /* maskir - maskir. */
4846 static void gen_maskir(DisasContext *ctx)
4847 {
4848 TCGv t0 = tcg_temp_new();
4849 TCGv t1 = tcg_temp_new();
4850 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4851 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4852 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4853 tcg_temp_free(t0);
4854 tcg_temp_free(t1);
4855 if (unlikely(Rc(ctx->opcode) != 0))
4856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4857 }
4858
4859 /* mul - mul. */
4860 static void gen_mul(DisasContext *ctx)
4861 {
4862 TCGv_i64 t0 = tcg_temp_new_i64();
4863 TCGv_i64 t1 = tcg_temp_new_i64();
4864 TCGv t2 = tcg_temp_new();
4865 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4866 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4867 tcg_gen_mul_i64(t0, t0, t1);
4868 tcg_gen_trunc_i64_tl(t2, t0);
4869 gen_store_spr(SPR_MQ, t2);
4870 tcg_gen_shri_i64(t1, t0, 32);
4871 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4872 tcg_temp_free_i64(t0);
4873 tcg_temp_free_i64(t1);
4874 tcg_temp_free(t2);
4875 if (unlikely(Rc(ctx->opcode) != 0))
4876 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4877 }
4878
4879 /* mulo - mulo. */
4880 static void gen_mulo(DisasContext *ctx)
4881 {
4882 TCGLabel *l1 = gen_new_label();
4883 TCGv_i64 t0 = tcg_temp_new_i64();
4884 TCGv_i64 t1 = tcg_temp_new_i64();
4885 TCGv t2 = tcg_temp_new();
4886 /* Start with XER OV disabled, the most likely case */
4887 tcg_gen_movi_tl(cpu_ov, 0);
4888 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4889 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4890 tcg_gen_mul_i64(t0, t0, t1);
4891 tcg_gen_trunc_i64_tl(t2, t0);
4892 gen_store_spr(SPR_MQ, t2);
4893 tcg_gen_shri_i64(t1, t0, 32);
4894 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4895 tcg_gen_ext32s_i64(t1, t0);
4896 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4897 tcg_gen_movi_tl(cpu_ov, 1);
4898 tcg_gen_movi_tl(cpu_so, 1);
4899 gen_set_label(l1);
4900 tcg_temp_free_i64(t0);
4901 tcg_temp_free_i64(t1);
4902 tcg_temp_free(t2);
4903 if (unlikely(Rc(ctx->opcode) != 0))
4904 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4905 }
4906
4907 /* nabs - nabs. */
4908 static void gen_nabs(DisasContext *ctx)
4909 {
4910 TCGLabel *l1 = gen_new_label();
4911 TCGLabel *l2 = gen_new_label();
4912 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4913 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4914 tcg_gen_br(l2);
4915 gen_set_label(l1);
4916 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4917 gen_set_label(l2);
4918 if (unlikely(Rc(ctx->opcode) != 0))
4919 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4920 }
4921
4922 /* nabso - nabso. */
4923 static void gen_nabso(DisasContext *ctx)
4924 {
4925 TCGLabel *l1 = gen_new_label();
4926 TCGLabel *l2 = gen_new_label();
4927 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4928 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4929 tcg_gen_br(l2);
4930 gen_set_label(l1);
4931 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4932 gen_set_label(l2);
4933 /* nabs never overflows */
4934 tcg_gen_movi_tl(cpu_ov, 0);
4935 if (unlikely(Rc(ctx->opcode) != 0))
4936 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4937 }
4938
4939 /* rlmi - rlmi. */
4940 static void gen_rlmi(DisasContext *ctx)
4941 {
4942 uint32_t mb = MB(ctx->opcode);
4943 uint32_t me = ME(ctx->opcode);
4944 TCGv t0 = tcg_temp_new();
4945 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4946 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4947 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4948 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4949 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4950 tcg_temp_free(t0);
4951 if (unlikely(Rc(ctx->opcode) != 0))
4952 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4953 }
4954
4955 /* rrib - rrib. */
4956 static void gen_rrib(DisasContext *ctx)
4957 {
4958 TCGv t0 = tcg_temp_new();
4959 TCGv t1 = tcg_temp_new();
4960 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4961 tcg_gen_movi_tl(t1, 0x80000000);
4962 tcg_gen_shr_tl(t1, t1, t0);
4963 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4964 tcg_gen_and_tl(t0, t0, t1);
4965 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4966 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4967 tcg_temp_free(t0);
4968 tcg_temp_free(t1);
4969 if (unlikely(Rc(ctx->opcode) != 0))
4970 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4971 }
4972
4973 /* sle - sle. */
4974 static void gen_sle(DisasContext *ctx)
4975 {
4976 TCGv t0 = tcg_temp_new();
4977 TCGv t1 = tcg_temp_new();
4978 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4979 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4980 tcg_gen_subfi_tl(t1, 32, t1);
4981 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4982 tcg_gen_or_tl(t1, t0, t1);
4983 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4984 gen_store_spr(SPR_MQ, t1);
4985 tcg_temp_free(t0);
4986 tcg_temp_free(t1);
4987 if (unlikely(Rc(ctx->opcode) != 0))
4988 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4989 }
4990
4991 /* sleq - sleq. */
4992 static void gen_sleq(DisasContext *ctx)
4993 {
4994 TCGv t0 = tcg_temp_new();
4995 TCGv t1 = tcg_temp_new();
4996 TCGv t2 = tcg_temp_new();
4997 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4998 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4999 tcg_gen_shl_tl(t2, t2, t0);
5000 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5001 gen_load_spr(t1, SPR_MQ);
5002 gen_store_spr(SPR_MQ, t0);
5003 tcg_gen_and_tl(t0, t0, t2);
5004 tcg_gen_andc_tl(t1, t1, t2);
5005 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5006 tcg_temp_free(t0);
5007 tcg_temp_free(t1);
5008 tcg_temp_free(t2);
5009 if (unlikely(Rc(ctx->opcode) != 0))
5010 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5011 }
5012
5013 /* sliq - sliq. */
5014 static void gen_sliq(DisasContext *ctx)
5015 {
5016 int sh = SH(ctx->opcode);
5017 TCGv t0 = tcg_temp_new();
5018 TCGv t1 = tcg_temp_new();
5019 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5020 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5021 tcg_gen_or_tl(t1, t0, t1);
5022 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5023 gen_store_spr(SPR_MQ, t1);
5024 tcg_temp_free(t0);
5025 tcg_temp_free(t1);
5026 if (unlikely(Rc(ctx->opcode) != 0))
5027 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5028 }
5029
5030 /* slliq - slliq. */
5031 static void gen_slliq(DisasContext *ctx)
5032 {
5033 int sh = SH(ctx->opcode);
5034 TCGv t0 = tcg_temp_new();
5035 TCGv t1 = tcg_temp_new();
5036 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5037 gen_load_spr(t1, SPR_MQ);
5038 gen_store_spr(SPR_MQ, t0);
5039 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5040 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5041 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5042 tcg_temp_free(t0);
5043 tcg_temp_free(t1);
5044 if (unlikely(Rc(ctx->opcode) != 0))
5045 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5046 }
5047
5048 /* sllq - sllq. */
5049 static void gen_sllq(DisasContext *ctx)
5050 {
5051 TCGLabel *l1 = gen_new_label();
5052 TCGLabel *l2 = gen_new_label();
5053 TCGv t0 = tcg_temp_local_new();
5054 TCGv t1 = tcg_temp_local_new();
5055 TCGv t2 = tcg_temp_local_new();
5056 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5057 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5058 tcg_gen_shl_tl(t1, t1, t2);
5059 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5060 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5061 gen_load_spr(t0, SPR_MQ);
5062 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5063 tcg_gen_br(l2);
5064 gen_set_label(l1);
5065 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5066 gen_load_spr(t2, SPR_MQ);
5067 tcg_gen_andc_tl(t1, t2, t1);
5068 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5069 gen_set_label(l2);
5070 tcg_temp_free(t0);
5071 tcg_temp_free(t1);
5072 tcg_temp_free(t2);
5073 if (unlikely(Rc(ctx->opcode) != 0))
5074 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5075 }
5076
5077 /* slq - slq. */
5078 static void gen_slq(DisasContext *ctx)
5079 {
5080 TCGLabel *l1 = gen_new_label();
5081 TCGv t0 = tcg_temp_new();
5082 TCGv t1 = tcg_temp_new();
5083 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5084 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5085 tcg_gen_subfi_tl(t1, 32, t1);
5086 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5087 tcg_gen_or_tl(t1, t0, t1);
5088 gen_store_spr(SPR_MQ, t1);
5089 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5090 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5091 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5092 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5093 gen_set_label(l1);
5094 tcg_temp_free(t0);
5095 tcg_temp_free(t1);
5096 if (unlikely(Rc(ctx->opcode) != 0))
5097 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5098 }
5099
5100 /* sraiq - sraiq. */
5101 static void gen_sraiq(DisasContext *ctx)
5102 {
5103 int sh = SH(ctx->opcode);
5104 TCGLabel *l1 = gen_new_label();
5105 TCGv t0 = tcg_temp_new();
5106 TCGv t1 = tcg_temp_new();
5107 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5108 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5109 tcg_gen_or_tl(t0, t0, t1);
5110 gen_store_spr(SPR_MQ, t0);
5111 tcg_gen_movi_tl(cpu_ca, 0);
5112 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5113 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5114 tcg_gen_movi_tl(cpu_ca, 1);
5115 gen_set_label(l1);
5116 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5117 tcg_temp_free(t0);
5118 tcg_temp_free(t1);
5119 if (unlikely(Rc(ctx->opcode) != 0))
5120 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5121 }
5122
5123 /* sraq - sraq. */
5124 static void gen_sraq(DisasContext *ctx)
5125 {
5126 TCGLabel *l1 = gen_new_label();
5127 TCGLabel *l2 = gen_new_label();
5128 TCGv t0 = tcg_temp_new();
5129 TCGv t1 = tcg_temp_local_new();
5130 TCGv t2 = tcg_temp_local_new();
5131 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5132 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5133 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5134 tcg_gen_subfi_tl(t2, 32, t2);
5135 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5136 tcg_gen_or_tl(t0, t0, t2);
5137 gen_store_spr(SPR_MQ, t0);
5138 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5139 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5140 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5141 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5142 gen_set_label(l1);
5143 tcg_temp_free(t0);
5144 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5145 tcg_gen_movi_tl(cpu_ca, 0);
5146 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5147 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5148 tcg_gen_movi_tl(cpu_ca, 1);
5149 gen_set_label(l2);
5150 tcg_temp_free(t1);
5151 tcg_temp_free(t2);
5152 if (unlikely(Rc(ctx->opcode) != 0))
5153 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5154 }
5155
5156 /* sre - sre. */
5157 static void gen_sre(DisasContext *ctx)
5158 {
5159 TCGv t0 = tcg_temp_new();
5160 TCGv t1 = tcg_temp_new();
5161 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5162 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5163 tcg_gen_subfi_tl(t1, 32, t1);
5164 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5165 tcg_gen_or_tl(t1, t0, t1);
5166 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5167 gen_store_spr(SPR_MQ, t1);
5168 tcg_temp_free(t0);
5169 tcg_temp_free(t1);
5170 if (unlikely(Rc(ctx->opcode) != 0))
5171 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5172 }
5173
5174 /* srea - srea. */
5175 static void gen_srea(DisasContext *ctx)
5176 {
5177 TCGv t0 = tcg_temp_new();
5178 TCGv t1 = tcg_temp_new();
5179 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5180 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5181 gen_store_spr(SPR_MQ, t0);
5182 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5183 tcg_temp_free(t0);
5184 tcg_temp_free(t1);
5185 if (unlikely(Rc(ctx->opcode) != 0))
5186 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5187 }
5188
5189 /* sreq */
5190 static void gen_sreq(DisasContext *ctx)
5191 {
5192 TCGv t0 = tcg_temp_new();
5193 TCGv t1 = tcg_temp_new();
5194 TCGv t2 = tcg_temp_new();
5195 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5196 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5197 tcg_gen_shr_tl(t1, t1, t0);
5198 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5199 gen_load_spr(t2, SPR_MQ);
5200 gen_store_spr(SPR_MQ, t0);
5201 tcg_gen_and_tl(t0, t0, t1);
5202 tcg_gen_andc_tl(t2, t2, t1);
5203 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5204 tcg_temp_free(t0);
5205 tcg_temp_free(t1);
5206 tcg_temp_free(t2);
5207 if (unlikely(Rc(ctx->opcode) != 0))
5208 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5209 }
5210
5211 /* sriq */
5212 static void gen_sriq(DisasContext *ctx)
5213 {
5214 int sh = SH(ctx->opcode);
5215 TCGv t0 = tcg_temp_new();
5216 TCGv t1 = tcg_temp_new();
5217 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5218 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5219 tcg_gen_or_tl(t1, t0, t1);
5220 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5221 gen_store_spr(SPR_MQ, t1);
5222 tcg_temp_free(t0);
5223 tcg_temp_free(t1);
5224 if (unlikely(Rc(ctx->opcode) != 0))
5225 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5226 }
5227
5228 /* srliq */
5229 static void gen_srliq(DisasContext *ctx)
5230 {
5231 int sh = SH(ctx->opcode);
5232 TCGv t0 = tcg_temp_new();
5233 TCGv t1 = tcg_temp_new();
5234 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5235 gen_load_spr(t1, SPR_MQ);
5236 gen_store_spr(SPR_MQ, t0);
5237 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5238 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5239 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5240 tcg_temp_free(t0);
5241 tcg_temp_free(t1);
5242 if (unlikely(Rc(ctx->opcode) != 0))
5243 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5244 }
5245
5246 /* srlq */
5247 static void gen_srlq(DisasContext *ctx)
5248 {
5249 TCGLabel *l1 = gen_new_label();
5250 TCGLabel *l2 = gen_new_label();
5251 TCGv t0 = tcg_temp_local_new();
5252 TCGv t1 = tcg_temp_local_new();
5253 TCGv t2 = tcg_temp_local_new();
5254 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5255 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5256 tcg_gen_shr_tl(t2, t1, t2);
5257 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5258 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5259 gen_load_spr(t0, SPR_MQ);
5260 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5261 tcg_gen_br(l2);
5262 gen_set_label(l1);
5263 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5264 tcg_gen_and_tl(t0, t0, t2);
5265 gen_load_spr(t1, SPR_MQ);
5266 tcg_gen_andc_tl(t1, t1, t2);
5267 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5268 gen_set_label(l2);
5269 tcg_temp_free(t0);
5270 tcg_temp_free(t1);
5271 tcg_temp_free(t2);
5272 if (unlikely(Rc(ctx->opcode) != 0))
5273 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5274 }
5275
5276 /* srq */
5277 static void gen_srq(DisasContext *ctx)
5278 {
5279 TCGLabel *l1 = gen_new_label();
5280 TCGv t0 = tcg_temp_new();
5281 TCGv t1 = tcg_temp_new();
5282 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5283 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5284 tcg_gen_subfi_tl(t1, 32, t1);
5285 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5286 tcg_gen_or_tl(t1, t0, t1);
5287 gen_store_spr(SPR_MQ, t1);
5288 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5289 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5290 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5291 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5292 gen_set_label(l1);
5293 tcg_temp_free(t0);
5294 tcg_temp_free(t1);
5295 if (unlikely(Rc(ctx->opcode) != 0))
5296 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5297 }
5298
5299 /* PowerPC 602 specific instructions */
5300
5301 /* dsa */
5302 static void gen_dsa(DisasContext *ctx)
5303 {
5304 /* XXX: TODO */
5305 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5306 }
5307
5308 /* esa */
5309 static void gen_esa(DisasContext *ctx)
5310 {
5311 /* XXX: TODO */
5312 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5313 }
5314
5315 /* mfrom */
5316 static void gen_mfrom(DisasContext *ctx)
5317 {
5318 #if defined(CONFIG_USER_ONLY)
5319 GEN_PRIV;
5320 #else
5321 CHK_SV;
5322 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5323 #endif /* defined(CONFIG_USER_ONLY) */
5324 }
5325
5326 /* 602 - 603 - G2 TLB management */
5327
5328 /* tlbld */
5329 static void gen_tlbld_6xx(DisasContext *ctx)
5330 {
5331 #if defined(CONFIG_USER_ONLY)
5332 GEN_PRIV;
5333 #else
5334 CHK_SV;
5335 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5336 #endif /* defined(CONFIG_USER_ONLY) */
5337 }
5338
5339 /* tlbli */
5340 static void gen_tlbli_6xx(DisasContext *ctx)
5341 {
5342 #if defined(CONFIG_USER_ONLY)
5343 GEN_PRIV;
5344 #else
5345 CHK_SV;
5346 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5347 #endif /* defined(CONFIG_USER_ONLY) */
5348 }
5349
5350 /* 74xx TLB management */
5351
5352 /* tlbld */
5353 static void gen_tlbld_74xx(DisasContext *ctx)
5354 {
5355 #if defined(CONFIG_USER_ONLY)
5356 GEN_PRIV;
5357 #else
5358 CHK_SV;
5359 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5360 #endif /* defined(CONFIG_USER_ONLY) */
5361 }
5362
5363 /* tlbli */
5364 static void gen_tlbli_74xx(DisasContext *ctx)
5365 {
5366 #if defined(CONFIG_USER_ONLY)
5367 GEN_PRIV;
5368 #else
5369 CHK_SV;
5370 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5371 #endif /* defined(CONFIG_USER_ONLY) */
5372 }
5373
5374 /* POWER instructions not in PowerPC 601 */
5375
5376 /* clf */
5377 static void gen_clf(DisasContext *ctx)
5378 {
5379 /* Cache line flush: implemented as no-op */
5380 }
5381
5382 /* cli */
5383 static void gen_cli(DisasContext *ctx)
5384 {
5385 #if defined(CONFIG_USER_ONLY)
5386 GEN_PRIV;
5387 #else
5388 /* Cache line invalidate: privileged and treated as no-op */
5389 CHK_SV;
5390 #endif /* defined(CONFIG_USER_ONLY) */
5391 }
5392
5393 /* dclst */
5394 static void gen_dclst(DisasContext *ctx)
5395 {
5396 /* Data cache line store: treated as no-op */
5397 }
5398
5399 static void gen_mfsri(DisasContext *ctx)
5400 {
5401 #if defined(CONFIG_USER_ONLY)
5402 GEN_PRIV;
5403 #else
5404 int ra = rA(ctx->opcode);
5405 int rd = rD(ctx->opcode);
5406 TCGv t0;
5407
5408 CHK_SV;
5409 t0 = tcg_temp_new();
5410 gen_addr_reg_index(ctx, t0);
5411 tcg_gen_shri_tl(t0, t0, 28);
5412 tcg_gen_andi_tl(t0, t0, 0xF);
5413 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5414 tcg_temp_free(t0);
5415 if (ra != 0 && ra != rd)
5416 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5417 #endif /* defined(CONFIG_USER_ONLY) */
5418 }
5419
5420 static void gen_rac(DisasContext *ctx)
5421 {
5422 #if defined(CONFIG_USER_ONLY)
5423 GEN_PRIV;
5424 #else
5425 TCGv t0;
5426
5427 CHK_SV;
5428 t0 = tcg_temp_new();
5429 gen_addr_reg_index(ctx, t0);
5430 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5431 tcg_temp_free(t0);
5432 #endif /* defined(CONFIG_USER_ONLY) */
5433 }
5434
5435 static void gen_rfsvc(DisasContext *ctx)
5436 {
5437 #if defined(CONFIG_USER_ONLY)
5438 GEN_PRIV;
5439 #else
5440 CHK_SV;
5441
5442 gen_helper_rfsvc(cpu_env);
5443 gen_sync_exception(ctx);
5444 #endif /* defined(CONFIG_USER_ONLY) */
5445 }
5446
5447 /* svc is not implemented for now */
5448
5449 /* BookE specific instructions */
5450
5451 /* XXX: not implemented on 440 ? */
5452 static void gen_mfapidi(DisasContext *ctx)
5453 {
5454 /* XXX: TODO */
5455 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5456 }
5457
5458 /* XXX: not implemented on 440 ? */
5459 static void gen_tlbiva(DisasContext *ctx)
5460 {
5461 #if defined(CONFIG_USER_ONLY)
5462 GEN_PRIV;
5463 #else
5464 TCGv t0;
5465
5466 CHK_SV;
5467 t0 = tcg_temp_new();
5468 gen_addr_reg_index(ctx, t0);
5469 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5470 tcg_temp_free(t0);
5471 #endif /* defined(CONFIG_USER_ONLY) */
5472 }
5473
5474 /* All 405 MAC instructions are translated here */
5475 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5476 int ra, int rb, int rt, int Rc)
5477 {
5478 TCGv t0, t1;
5479
5480 t0 = tcg_temp_local_new();
5481 t1 = tcg_temp_local_new();
5482
5483 switch (opc3 & 0x0D) {
5484 case 0x05:
5485 /* macchw - macchw. - macchwo - macchwo. */
5486 /* macchws - macchws. - macchwso - macchwso. */
5487 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5488 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5489 /* mulchw - mulchw. */
5490 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5491 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5492 tcg_gen_ext16s_tl(t1, t1);
5493 break;
5494 case 0x04:
5495 /* macchwu - macchwu. - macchwuo - macchwuo. */
5496 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5497 /* mulchwu - mulchwu. */
5498 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5499 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5500 tcg_gen_ext16u_tl(t1, t1);
5501 break;
5502 case 0x01:
5503 /* machhw - machhw. - machhwo - machhwo. */
5504 /* machhws - machhws. - machhwso - machhwso. */
5505 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5506 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5507 /* mulhhw - mulhhw. */
5508 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5509 tcg_gen_ext16s_tl(t0, t0);
5510 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5511 tcg_gen_ext16s_tl(t1, t1);
5512 break;
5513 case 0x00:
5514 /* machhwu - machhwu. - machhwuo - machhwuo. */
5515 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5516 /* mulhhwu - mulhhwu. */
5517 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5518 tcg_gen_ext16u_tl(t0, t0);
5519 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5520 tcg_gen_ext16u_tl(t1, t1);
5521 break;
5522 case 0x0D:
5523 /* maclhw - maclhw. - maclhwo - maclhwo. */
5524 /* maclhws - maclhws. - maclhwso - maclhwso. */
5525 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5526 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5527 /* mullhw - mullhw. */
5528 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5529 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5530 break;
5531 case 0x0C:
5532 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5533 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5534 /* mullhwu - mullhwu. */
5535 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5536 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5537 break;
5538 }
5539 if (opc2 & 0x04) {
5540 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5541 tcg_gen_mul_tl(t1, t0, t1);
5542 if (opc2 & 0x02) {
5543 /* nmultiply-and-accumulate (0x0E) */
5544 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5545 } else {
5546 /* multiply-and-accumulate (0x0C) */
5547 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5548 }
5549
5550 if (opc3 & 0x12) {
5551 /* Check overflow and/or saturate */
5552 TCGLabel *l1 = gen_new_label();
5553
5554 if (opc3 & 0x10) {
5555 /* Start with XER OV disabled, the most likely case */
5556 tcg_gen_movi_tl(cpu_ov, 0);
5557 }
5558 if (opc3 & 0x01) {
5559 /* Signed */
5560 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5561 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5562 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5563 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5564 if (opc3 & 0x02) {
5565 /* Saturate */
5566 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5567 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5568 }
5569 } else {
5570 /* Unsigned */
5571 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5572 if (opc3 & 0x02) {
5573 /* Saturate */
5574 tcg_gen_movi_tl(t0, UINT32_MAX);
5575 }
5576 }
5577 if (opc3 & 0x10) {
5578 /* Check overflow */
5579 tcg_gen_movi_tl(cpu_ov, 1);
5580 tcg_gen_movi_tl(cpu_so, 1);
5581 }
5582 gen_set_label(l1);
5583 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5584 }
5585 } else {
5586 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5587 }
5588 tcg_temp_free(t0);
5589 tcg_temp_free(t1);
5590 if (unlikely(Rc) != 0) {
5591 /* Update Rc0 */
5592 gen_set_Rc0(ctx, cpu_gpr[rt]);
5593 }
5594 }
5595
5596 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5597 static void glue(gen_, name)(DisasContext *ctx) \
5598 { \
5599 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5600 rD(ctx->opcode), Rc(ctx->opcode)); \
5601 }
5602
5603 /* macchw - macchw. */
5604 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5605 /* macchwo - macchwo. */
5606 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5607 /* macchws - macchws. */
5608 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5609 /* macchwso - macchwso. */
5610 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5611 /* macchwsu - macchwsu. */
5612 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5613 /* macchwsuo - macchwsuo. */
5614 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5615 /* macchwu - macchwu. */
5616 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5617 /* macchwuo - macchwuo. */
5618 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5619 /* machhw - machhw. */
5620 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5621 /* machhwo - machhwo. */
5622 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5623 /* machhws - machhws. */
5624 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5625 /* machhwso - machhwso. */
5626 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5627 /* machhwsu - machhwsu. */
5628 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5629 /* machhwsuo - machhwsuo. */
5630 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5631 /* machhwu - machhwu. */
5632 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5633 /* machhwuo - machhwuo. */
5634 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5635 /* maclhw - maclhw. */
5636 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5637 /* maclhwo - maclhwo. */
5638 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5639 /* maclhws - maclhws. */
5640 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5641 /* maclhwso - maclhwso. */
5642 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5643 /* maclhwu - maclhwu. */
5644 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5645 /* maclhwuo - maclhwuo. */
5646 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5647 /* maclhwsu - maclhwsu. */
5648 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5649 /* maclhwsuo - maclhwsuo. */
5650 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5651 /* nmacchw - nmacchw. */
5652 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5653 /* nmacchwo - nmacchwo. */
5654 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5655 /* nmacchws - nmacchws. */
5656 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5657 /* nmacchwso - nmacchwso. */
5658 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5659 /* nmachhw - nmachhw. */
5660 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5661 /* nmachhwo - nmachhwo. */
5662 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5663 /* nmachhws - nmachhws. */
5664 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5665 /* nmachhwso - nmachhwso. */
5666 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5667 /* nmaclhw - nmaclhw. */
5668 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5669 /* nmaclhwo - nmaclhwo. */
5670 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5671 /* nmaclhws - nmaclhws. */
5672 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5673 /* nmaclhwso - nmaclhwso. */
5674 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5675
5676 /* mulchw - mulchw. */
5677 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5678 /* mulchwu - mulchwu. */
5679 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5680 /* mulhhw - mulhhw. */
5681 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5682 /* mulhhwu - mulhhwu. */
5683 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5684 /* mullhw - mullhw. */
5685 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5686 /* mullhwu - mullhwu. */
5687 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5688
5689 /* mfdcr */
5690 static void gen_mfdcr(DisasContext *ctx)
5691 {
5692 #if defined(CONFIG_USER_ONLY)
5693 GEN_PRIV;
5694 #else
5695 TCGv dcrn;
5696
5697 CHK_SV;
5698 dcrn = tcg_const_tl(SPR(ctx->opcode));
5699 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5700 tcg_temp_free(dcrn);
5701 #endif /* defined(CONFIG_USER_ONLY) */
5702 }
5703
5704 /* mtdcr */
5705 static void gen_mtdcr(DisasContext *ctx)
5706 {
5707 #if defined(CONFIG_USER_ONLY)
5708 GEN_PRIV;
5709 #else
5710 TCGv dcrn;
5711
5712 CHK_SV;
5713 dcrn = tcg_const_tl(SPR(ctx->opcode));
5714 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5715 tcg_temp_free(dcrn);
5716 #endif /* defined(CONFIG_USER_ONLY) */
5717 }
5718
5719 /* mfdcrx */
5720 /* XXX: not implemented on 440 ? */
5721 static void gen_mfdcrx(DisasContext *ctx)
5722 {
5723 #if defined(CONFIG_USER_ONLY)
5724 GEN_PRIV;
5725 #else
5726 CHK_SV;
5727 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5728 cpu_gpr[rA(ctx->opcode)]);
5729 /* Note: Rc update flag set leads to undefined state of Rc0 */
5730 #endif /* defined(CONFIG_USER_ONLY) */
5731 }
5732
5733 /* mtdcrx */
5734 /* XXX: not implemented on 440 ? */
5735 static void gen_mtdcrx(DisasContext *ctx)
5736 {
5737 #if defined(CONFIG_USER_ONLY)
5738 GEN_PRIV;
5739 #else
5740 CHK_SV;
5741 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5742 cpu_gpr[rS(ctx->opcode)]);
5743 /* Note: Rc update flag set leads to undefined state of Rc0 */
5744 #endif /* defined(CONFIG_USER_ONLY) */
5745 }
5746
5747 /* mfdcrux (PPC 460) : user-mode access to DCR */
5748 static void gen_mfdcrux(DisasContext *ctx)
5749 {
5750 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5751 cpu_gpr[rA(ctx->opcode)]);
5752 /* Note: Rc update flag set leads to undefined state of Rc0 */
5753 }
5754
5755 /* mtdcrux (PPC 460) : user-mode access to DCR */
5756 static void gen_mtdcrux(DisasContext *ctx)
5757 {
5758 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5759 cpu_gpr[rS(ctx->opcode)]);
5760 /* Note: Rc update flag set leads to undefined state of Rc0 */
5761 }
5762
5763 /* dccci */
5764 static void gen_dccci(DisasContext *ctx)
5765 {
5766 CHK_SV;
5767 /* interpreted as no-op */
5768 }
5769
5770 /* dcread */
5771 static void gen_dcread(DisasContext *ctx)
5772 {
5773 #if defined(CONFIG_USER_ONLY)
5774 GEN_PRIV;
5775 #else
5776 TCGv EA, val;
5777
5778 CHK_SV;
5779 gen_set_access_type(ctx, ACCESS_CACHE);
5780 EA = tcg_temp_new();
5781 gen_addr_reg_index(ctx, EA);
5782 val = tcg_temp_new();
5783 gen_qemu_ld32u(ctx, val, EA);
5784 tcg_temp_free(val);
5785 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5786 tcg_temp_free(EA);
5787 #endif /* defined(CONFIG_USER_ONLY) */
5788 }
5789
5790 /* icbt */
5791 static void gen_icbt_40x(DisasContext *ctx)
5792 {
5793 /* interpreted as no-op */
5794 /* XXX: specification say this is treated as a load by the MMU
5795 * but does not generate any exception
5796 */
5797 }
5798
5799 /* iccci */
5800 static void gen_iccci(DisasContext *ctx)
5801 {
5802 CHK_SV;
5803 /* interpreted as no-op */
5804 }
5805
5806 /* icread */
5807 static void gen_icread(DisasContext *ctx)
5808 {
5809 CHK_SV;
5810 /* interpreted as no-op */
5811 }
5812
5813 /* rfci (supervisor only) */
5814 static void gen_rfci_40x(DisasContext *ctx)
5815 {
5816 #if defined(CONFIG_USER_ONLY)
5817 GEN_PRIV;
5818 #else
5819 CHK_SV;
5820 /* Restore CPU state */
5821 gen_helper_40x_rfci(cpu_env);
5822 gen_sync_exception(ctx);
5823 #endif /* defined(CONFIG_USER_ONLY) */
5824 }
5825
5826 static void gen_rfci(DisasContext *ctx)
5827 {
5828 #if defined(CONFIG_USER_ONLY)
5829 GEN_PRIV;
5830 #else
5831 CHK_SV;
5832 /* Restore CPU state */
5833 gen_helper_rfci(cpu_env);
5834 gen_sync_exception(ctx);
5835 #endif /* defined(CONFIG_USER_ONLY) */
5836 }
5837
5838 /* BookE specific */
5839
5840 /* XXX: not implemented on 440 ? */
5841 static void gen_rfdi(DisasContext *ctx)
5842 {
5843 #if defined(CONFIG_USER_ONLY)
5844 GEN_PRIV;
5845 #else
5846 CHK_SV;
5847 /* Restore CPU state */
5848 gen_helper_rfdi(cpu_env);
5849 gen_sync_exception(ctx);
5850 #endif /* defined(CONFIG_USER_ONLY) */
5851 }
5852
5853 /* XXX: not implemented on 440 ? */
5854 static void gen_rfmci(DisasContext *ctx)
5855 {
5856 #if defined(CONFIG_USER_ONLY)
5857 GEN_PRIV;
5858 #else
5859 CHK_SV;
5860 /* Restore CPU state */
5861 gen_helper_rfmci(cpu_env);
5862 gen_sync_exception(ctx);
5863 #endif /* defined(CONFIG_USER_ONLY) */
5864 }
5865
5866 /* TLB management - PowerPC 405 implementation */
5867
5868 /* tlbre */
5869 static void gen_tlbre_40x(DisasContext *ctx)
5870 {
5871 #if defined(CONFIG_USER_ONLY)
5872 GEN_PRIV;
5873 #else
5874 CHK_SV;
5875 switch (rB(ctx->opcode)) {
5876 case 0:
5877 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5878 cpu_gpr[rA(ctx->opcode)]);
5879 break;
5880 case 1:
5881 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5882 cpu_gpr[rA(ctx->opcode)]);
5883 break;
5884 default:
5885 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5886 break;
5887 }
5888 #endif /* defined(CONFIG_USER_ONLY) */
5889 }
5890
5891 /* tlbsx - tlbsx. */
5892 static void gen_tlbsx_40x(DisasContext *ctx)
5893 {
5894 #if defined(CONFIG_USER_ONLY)
5895 GEN_PRIV;
5896 #else
5897 TCGv t0;
5898
5899 CHK_SV;
5900 t0 = tcg_temp_new();
5901 gen_addr_reg_index(ctx, t0);
5902 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5903 tcg_temp_free(t0);
5904 if (Rc(ctx->opcode)) {
5905 TCGLabel *l1 = gen_new_label();
5906 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5907 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5908 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5909 gen_set_label(l1);
5910 }
5911 #endif /* defined(CONFIG_USER_ONLY) */
5912 }
5913
5914 /* tlbwe */
5915 static void gen_tlbwe_40x(DisasContext *ctx)
5916 {
5917 #if defined(CONFIG_USER_ONLY)
5918 GEN_PRIV;
5919 #else
5920 CHK_SV;
5921
5922 switch (rB(ctx->opcode)) {
5923 case 0:
5924 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5925 cpu_gpr[rS(ctx->opcode)]);
5926 break;
5927 case 1:
5928 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5929 cpu_gpr[rS(ctx->opcode)]);
5930 break;
5931 default:
5932 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5933 break;
5934 }
5935 #endif /* defined(CONFIG_USER_ONLY) */
5936 }
5937
5938 /* TLB management - PowerPC 440 implementation */
5939
5940 /* tlbre */
5941 static void gen_tlbre_440(DisasContext *ctx)
5942 {
5943 #if defined(CONFIG_USER_ONLY)
5944 GEN_PRIV;
5945 #else
5946 CHK_SV;
5947
5948 switch (rB(ctx->opcode)) {
5949 case 0:
5950 case 1:
5951 case 2:
5952 {
5953 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5954 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5955 t0, cpu_gpr[rA(ctx->opcode)]);
5956 tcg_temp_free_i32(t0);
5957 }
5958 break;
5959 default:
5960 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5961 break;
5962 }
5963 #endif /* defined(CONFIG_USER_ONLY) */
5964 }
5965
5966 /* tlbsx - tlbsx. */
5967 static void gen_tlbsx_440(DisasContext *ctx)
5968 {
5969 #if defined(CONFIG_USER_ONLY)
5970 GEN_PRIV;
5971 #else
5972 TCGv t0;
5973
5974 CHK_SV;
5975 t0 = tcg_temp_new();
5976 gen_addr_reg_index(ctx, t0);
5977 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5978 tcg_temp_free(t0);
5979 if (Rc(ctx->opcode)) {
5980 TCGLabel *l1 = gen_new_label();
5981 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5982 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5983 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5984 gen_set_label(l1);
5985 }
5986 #endif /* defined(CONFIG_USER_ONLY) */
5987 }
5988
5989 /* tlbwe */
5990 static void gen_tlbwe_440(DisasContext *ctx)
5991 {
5992 #if defined(CONFIG_USER_ONLY)
5993 GEN_PRIV;
5994 #else
5995 CHK_SV;
5996 switch (rB(ctx->opcode)) {
5997 case 0:
5998 case 1:
5999 case 2:
6000 {
6001 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6002 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6003 cpu_gpr[rS(ctx->opcode)]);
6004 tcg_temp_free_i32(t0);
6005 }
6006 break;
6007 default:
6008 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6009 break;
6010 }
6011 #endif /* defined(CONFIG_USER_ONLY) */
6012 }
6013
6014 /* TLB management - PowerPC BookE 2.06 implementation */
6015
6016 /* tlbre */
6017 static void gen_tlbre_booke206(DisasContext *ctx)
6018 {
6019 #if defined(CONFIG_USER_ONLY)
6020 GEN_PRIV;
6021 #else
6022 CHK_SV;
6023 gen_helper_booke206_tlbre(cpu_env);
6024 #endif /* defined(CONFIG_USER_ONLY) */
6025 }
6026
6027 /* tlbsx - tlbsx. */
6028 static void gen_tlbsx_booke206(DisasContext *ctx)
6029 {
6030 #if defined(CONFIG_USER_ONLY)
6031 GEN_PRIV;
6032 #else
6033 TCGv t0;
6034
6035 CHK_SV;
6036 if (rA(ctx->opcode)) {
6037 t0 = tcg_temp_new();
6038 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6039 } else {
6040 t0 = tcg_const_tl(0);
6041 }
6042
6043 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6044 gen_helper_booke206_tlbsx(cpu_env, t0);
6045 tcg_temp_free(t0);
6046 #endif /* defined(CONFIG_USER_ONLY) */
6047 }
6048
6049 /* tlbwe */
6050 static void gen_tlbwe_booke206(DisasContext *ctx)
6051 {
6052 #if defined(CONFIG_USER_ONLY)
6053 GEN_PRIV;
6054 #else
6055 CHK_SV;
6056 gen_helper_booke206_tlbwe(cpu_env);
6057 #endif /* defined(CONFIG_USER_ONLY) */
6058 }
6059
6060 static void gen_tlbivax_booke206(DisasContext *ctx)
6061 {
6062 #if defined(CONFIG_USER_ONLY)
6063 GEN_PRIV;
6064 #else
6065 TCGv t0;
6066
6067 CHK_SV;
6068 t0 = tcg_temp_new();
6069 gen_addr_reg_index(ctx, t0);
6070 gen_helper_booke206_tlbivax(cpu_env, t0);
6071 tcg_temp_free(t0);
6072 #endif /* defined(CONFIG_USER_ONLY) */
6073 }
6074
6075 static void gen_tlbilx_booke206(DisasContext *ctx)
6076 {
6077 #if defined(CONFIG_USER_ONLY)
6078 GEN_PRIV;
6079 #else
6080 TCGv t0;
6081
6082 CHK_SV;
6083 t0 = tcg_temp_new();
6084 gen_addr_reg_index(ctx, t0);
6085
6086 switch((ctx->opcode >> 21) & 0x3) {
6087 case 0:
6088 gen_helper_booke206_tlbilx0(cpu_env, t0);
6089 break;
6090 case 1:
6091 gen_helper_booke206_tlbilx1(cpu_env, t0);
6092 break;
6093 case 3:
6094 gen_helper_booke206_tlbilx3(cpu_env, t0);
6095 break;
6096 default:
6097 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6098 break;
6099 }
6100
6101 tcg_temp_free(t0);
6102 #endif /* defined(CONFIG_USER_ONLY) */
6103 }
6104
6105
6106 /* wrtee */
6107 static void gen_wrtee(DisasContext *ctx)
6108 {
6109 #if defined(CONFIG_USER_ONLY)
6110 GEN_PRIV;
6111 #else
6112 TCGv t0;
6113
6114 CHK_SV;
6115 t0 = tcg_temp_new();
6116 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6117 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6118 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6119 tcg_temp_free(t0);
6120 /* Stop translation to have a chance to raise an exception
6121 * if we just set msr_ee to 1
6122 */
6123 gen_stop_exception(ctx);
6124 #endif /* defined(CONFIG_USER_ONLY) */
6125 }
6126
6127 /* wrteei */
6128 static void gen_wrteei(DisasContext *ctx)
6129 {
6130 #if defined(CONFIG_USER_ONLY)
6131 GEN_PRIV;
6132 #else
6133 CHK_SV;
6134 if (ctx->opcode & 0x00008000) {
6135 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6136 /* Stop translation to have a chance to raise an exception */
6137 gen_stop_exception(ctx);
6138 } else {
6139 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6140 }
6141 #endif /* defined(CONFIG_USER_ONLY) */
6142 }
6143
6144 /* PowerPC 440 specific instructions */
6145
6146 /* dlmzb */
6147 static void gen_dlmzb(DisasContext *ctx)
6148 {
6149 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6150 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6151 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6152 tcg_temp_free_i32(t0);
6153 }
6154
6155 /* mbar replaces eieio on 440 */
6156 static void gen_mbar(DisasContext *ctx)
6157 {
6158 /* interpreted as no-op */
6159 }
6160
6161 /* msync replaces sync on 440 */
6162 static void gen_msync_4xx(DisasContext *ctx)
6163 {
6164 /* interpreted as no-op */
6165 }
6166
6167 /* icbt */
6168 static void gen_icbt_440(DisasContext *ctx)
6169 {
6170 /* interpreted as no-op */
6171 /* XXX: specification say this is treated as a load by the MMU
6172 * but does not generate any exception
6173 */
6174 }
6175
6176 /* Embedded.Processor Control */
6177
6178 static void gen_msgclr(DisasContext *ctx)
6179 {
6180 #if defined(CONFIG_USER_ONLY)
6181 GEN_PRIV;
6182 #else
6183 CHK_SV;
6184 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6185 #endif /* defined(CONFIG_USER_ONLY) */
6186 }
6187
6188 static void gen_msgsnd(DisasContext *ctx)
6189 {
6190 #if defined(CONFIG_USER_ONLY)
6191 GEN_PRIV;
6192 #else
6193 CHK_SV;
6194 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6195 #endif /* defined(CONFIG_USER_ONLY) */
6196 }
6197
6198
6199 #if defined(TARGET_PPC64)
6200 static void gen_maddld(DisasContext *ctx)
6201 {
6202 TCGv_i64 t1 = tcg_temp_new_i64();
6203
6204 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6205 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6206 tcg_temp_free_i64(t1);
6207 }
6208
6209 /* maddhd maddhdu */
6210 static void gen_maddhd_maddhdu(DisasContext *ctx)
6211 {
6212 TCGv_i64 lo = tcg_temp_new_i64();
6213 TCGv_i64 hi = tcg_temp_new_i64();
6214 TCGv_i64 t1 = tcg_temp_new_i64();
6215
6216 if (Rc(ctx->opcode)) {
6217 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6218 cpu_gpr[rB(ctx->opcode)]);
6219 tcg_gen_movi_i64(t1, 0);
6220 } else {
6221 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6222 cpu_gpr[rB(ctx->opcode)]);
6223 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6224 }
6225 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6226 cpu_gpr[rC(ctx->opcode)], t1);
6227 tcg_temp_free_i64(lo);
6228 tcg_temp_free_i64(hi);
6229 tcg_temp_free_i64(t1);
6230 }
6231 #endif /* defined(TARGET_PPC64) */
6232
6233 static void gen_tbegin(DisasContext *ctx)
6234 {
6235 if (unlikely(!ctx->tm_enabled)) {
6236 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6237 return;
6238 }
6239 gen_helper_tbegin(cpu_env);
6240 }
6241
6242 #define GEN_TM_NOOP(name) \
6243 static inline void gen_##name(DisasContext *ctx) \
6244 { \
6245 if (unlikely(!ctx->tm_enabled)) { \
6246 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6247 return; \
6248 } \
6249 /* Because tbegin always fails in QEMU, these user \
6250 * space instructions all have a simple implementation: \
6251 * \
6252 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6253 * = 0b0 || 0b00 || 0b0 \
6254 */ \
6255 tcg_gen_movi_i32(cpu_crf[0], 0); \
6256 }
6257
6258 GEN_TM_NOOP(tend);
6259 GEN_TM_NOOP(tabort);
6260 GEN_TM_NOOP(tabortwc);
6261 GEN_TM_NOOP(tabortwci);
6262 GEN_TM_NOOP(tabortdc);
6263 GEN_TM_NOOP(tabortdci);
6264 GEN_TM_NOOP(tsr);
6265 static inline void gen_cp_abort(DisasContext *ctx)
6266 {
6267 // Do Nothing
6268 }
6269
6270 #define GEN_CP_PASTE_NOOP(name) \
6271 static inline void gen_##name(DisasContext *ctx) \
6272 { \
6273 /* Generate invalid exception until \
6274 * we have an implementation of the copy \
6275 * paste facility \
6276 */ \
6277 gen_invalid(ctx); \
6278 }
6279
6280 GEN_CP_PASTE_NOOP(copy)
6281 GEN_CP_PASTE_NOOP(paste)
6282
6283 static void gen_tcheck(DisasContext *ctx)
6284 {
6285 if (unlikely(!ctx->tm_enabled)) {
6286 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6287 return;
6288 }
6289 /* Because tbegin always fails, the tcheck implementation
6290 * is simple:
6291 *
6292 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6293 * = 0b1 || 0b00 || 0b0
6294 */
6295 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6296 }
6297
6298 #if defined(CONFIG_USER_ONLY)
6299 #define GEN_TM_PRIV_NOOP(name) \
6300 static inline void gen_##name(DisasContext *ctx) \
6301 { \
6302 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6303 }
6304
6305 #else
6306
6307 #define GEN_TM_PRIV_NOOP(name) \
6308 static inline void gen_##name(DisasContext *ctx) \
6309 { \
6310 CHK_SV; \
6311 if (unlikely(!ctx->tm_enabled)) { \
6312 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6313 return; \
6314 } \
6315 /* Because tbegin always fails, the implementation is \
6316 * simple: \
6317 * \
6318 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6319 * = 0b0 || 0b00 | 0b0 \
6320 */ \
6321 tcg_gen_movi_i32(cpu_crf[0], 0); \
6322 }
6323
6324 #endif
6325
6326 GEN_TM_PRIV_NOOP(treclaim);
6327 GEN_TM_PRIV_NOOP(trechkpt);
6328
6329 #include "translate/fp-impl.inc.c"
6330
6331 #include "translate/vmx-impl.inc.c"
6332
6333 #include "translate/vsx-impl.inc.c"
6334
6335 #include "translate/dfp-impl.inc.c"
6336
6337 #include "translate/spe-impl.inc.c"
6338
6339 /* Handles lfdp, lxsd, lxssp */
6340 static void gen_dform39(DisasContext *ctx)
6341 {
6342 switch (ctx->opcode & 0x3) {
6343 case 0: /* lfdp */
6344 if (ctx->insns_flags2 & PPC2_ISA205) {
6345 return gen_lfdp(ctx);
6346 }
6347 break;
6348 case 2: /* lxsd */
6349 if (ctx->insns_flags2 & PPC2_ISA300) {
6350 return gen_lxsd(ctx);
6351 }
6352 break;
6353 case 3: /* lxssp */
6354 if (ctx->insns_flags2 & PPC2_ISA300) {
6355 return gen_lxssp(ctx);
6356 }
6357 break;
6358 }
6359 return gen_invalid(ctx);
6360 }
6361
6362 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6363 static void gen_dform3D(DisasContext *ctx)
6364 {
6365 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
6366 switch (ctx->opcode & 0x7) {
6367 case 1: /* lxv */
6368 if (ctx->insns_flags2 & PPC2_ISA300) {
6369 return gen_lxv(ctx);
6370 }
6371 break;
6372 case 5: /* stxv */
6373 if (ctx->insns_flags2 & PPC2_ISA300) {
6374 return gen_stxv(ctx);
6375 }
6376 break;
6377 }
6378 } else { /* DS-FORM */
6379 switch (ctx->opcode & 0x3) {
6380 case 0: /* stfdp */
6381 if (ctx->insns_flags2 & PPC2_ISA205) {
6382 return gen_stfdp(ctx);
6383 }
6384 break;
6385 case 2: /* stxsd */
6386 if (ctx->insns_flags2 & PPC2_ISA300) {
6387 return gen_stxsd(ctx);
6388 }
6389 break;
6390 case 3: /* stxssp */
6391 if (ctx->insns_flags2 & PPC2_ISA300) {
6392 return gen_stxssp(ctx);
6393 }
6394 break;
6395 }
6396 }
6397 return gen_invalid(ctx);
6398 }
6399
6400 static opcode_t opcodes[] = {
6401 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6402 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6403 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6404 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
6405 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6406 #if defined(TARGET_PPC64)
6407 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6408 #endif
6409 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6410 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6411 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6412 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6413 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6414 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6415 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6416 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6417 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6418 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6419 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6420 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6421 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6422 #if defined(TARGET_PPC64)
6423 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6424 #endif
6425 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6426 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6427 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6428 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6429 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6430 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6431 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6432 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
6433 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6434 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
6435 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6436 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6437 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6438 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6439 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6440 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6441 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6442 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6443 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6444 #if defined(TARGET_PPC64)
6445 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6446 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6447 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6448 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6449 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6450 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6451 #endif
6452 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6453 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6454 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6455 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6456 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6457 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6458 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6459 #if defined(TARGET_PPC64)
6460 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6461 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6462 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6463 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6464 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6465 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6466 PPC_NONE, PPC2_ISA300),
6467 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6468 PPC_NONE, PPC2_ISA300),
6469 #endif
6470 #if defined(TARGET_PPC64)
6471 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6472 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6473 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6474 #endif
6475 /* handles lfdp, lxsd, lxssp */
6476 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6477 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6478 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6479 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6480 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6481 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6482 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6483 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6484 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6485 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6486 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6487 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6488 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6489 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6490 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
6491 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
6492 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6493 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6494 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6495 #if defined(TARGET_PPC64)
6496 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
6497 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
6498 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6499 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6500 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6501 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6502 #endif
6503 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6504 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6505 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
6506 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6507 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6508 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6509 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6510 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6511 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6512 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6513 #if defined(TARGET_PPC64)
6514 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6515 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6516 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6517 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6518 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6519 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6520 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6521 #endif
6522 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6523 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6524 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6525 #if defined(TARGET_PPC64)
6526 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6527 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6528 #endif
6529 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6530 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6531 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6532 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6533 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6534 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6535 #if defined(TARGET_PPC64)
6536 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6537 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6538 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
6539 #endif
6540 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6541 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6542 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6543 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6544 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6545 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6546 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6547 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6548 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6549 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6550 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6551 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6552 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6553 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6554 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6555 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6556 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6557 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6558 #if defined(TARGET_PPC64)
6559 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6560 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6561 PPC_SEGMENT_64B),
6562 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6563 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6564 PPC_SEGMENT_64B),
6565 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6566 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6567 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6568 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6569 #endif
6570 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6571 /* XXX Those instructions will need to be handled differently for
6572 * different ISA versions */
6573 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6574 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6575 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6576 #if defined(TARGET_PPC64)
6577 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6578 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6579 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
6580 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6581 #endif
6582 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6583 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6584 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6585 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6586 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6587 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6588 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6589 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6590 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6591 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6592 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6593 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6594 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6595 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6596 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6597 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6598 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6599 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6600 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6601 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6602 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6603 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6604 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6605 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6606 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6607 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6608 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6609 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6610 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6611 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6612 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6613 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6614 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6615 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6616 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6617 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6618 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6619 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6620 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6621 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6622 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6623 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6624 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6625 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6626 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6627 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6628 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6629 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6630 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6631 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6632 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6633 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6634 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6635 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6636 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6637 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6638 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6639 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6640 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6641 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6642 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6643 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6644 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6645 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6646 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6647 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6648 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6649 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6650 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6651 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6652 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6653 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6654 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6655 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6656 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6657 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6658 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6659 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6660 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6661 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6662 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6663 PPC_NONE, PPC2_BOOKE206),
6664 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6665 PPC_NONE, PPC2_BOOKE206),
6666 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6667 PPC_NONE, PPC2_BOOKE206),
6668 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6669 PPC_NONE, PPC2_BOOKE206),
6670 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6671 PPC_NONE, PPC2_BOOKE206),
6672 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6673 PPC_NONE, PPC2_PRCNTL),
6674 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6675 PPC_NONE, PPC2_PRCNTL),
6676 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6677 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6678 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6679 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6680 PPC_BOOKE, PPC2_BOOKE206),
6681 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6682 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6683 PPC_BOOKE, PPC2_BOOKE206),
6684 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6685 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6686 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6687 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6688 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6689 #if defined(TARGET_PPC64)
6690 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6691 PPC2_ISA300),
6692 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6693 #endif
6694
6695 #undef GEN_INT_ARITH_ADD
6696 #undef GEN_INT_ARITH_ADD_CONST
6697 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6698 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6699 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6700 add_ca, compute_ca, compute_ov) \
6701 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6702 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6703 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6704 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6705 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6706 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6707 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6708 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6709 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6710 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6711 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6712
6713 #undef GEN_INT_ARITH_DIVW
6714 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6715 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6716 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6717 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6718 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6719 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6720 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6721 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6722 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6723 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6724 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6725 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6726
6727 #if defined(TARGET_PPC64)
6728 #undef GEN_INT_ARITH_DIVD
6729 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6730 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6731 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6732 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6733 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6734 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6735
6736 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6737 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6738 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6739 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6740 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6741 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6742
6743 #undef GEN_INT_ARITH_MUL_HELPER
6744 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6745 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6746 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6747 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6748 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6749 #endif
6750
6751 #undef GEN_INT_ARITH_SUBF
6752 #undef GEN_INT_ARITH_SUBF_CONST
6753 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6754 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6755 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6756 add_ca, compute_ca, compute_ov) \
6757 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6758 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6759 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6760 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6761 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6762 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6763 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6764 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6765 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6766 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6767 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6768
6769 #undef GEN_LOGICAL1
6770 #undef GEN_LOGICAL2
6771 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6772 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6773 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6774 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6775 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6776 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6777 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6778 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6779 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6780 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6781 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6782 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6783 #if defined(TARGET_PPC64)
6784 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6785 #endif
6786
6787 #if defined(TARGET_PPC64)
6788 #undef GEN_PPC64_R2
6789 #undef GEN_PPC64_R4
6790 #define GEN_PPC64_R2(name, opc1, opc2) \
6791 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6792 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6793 PPC_64B)
6794 #define GEN_PPC64_R4(name, opc1, opc2) \
6795 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6796 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6797 PPC_64B), \
6798 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6799 PPC_64B), \
6800 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6801 PPC_64B)
6802 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6803 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6804 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6805 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6806 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6807 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6808 #endif
6809
6810 #undef GEN_LD
6811 #undef GEN_LDU
6812 #undef GEN_LDUX
6813 #undef GEN_LDX_E
6814 #undef GEN_LDS
6815 #define GEN_LD(name, ldop, opc, type) \
6816 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6817 #define GEN_LDU(name, ldop, opc, type) \
6818 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6819 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6820 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6821 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6822 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6823 #define GEN_LDS(name, ldop, op, type) \
6824 GEN_LD(name, ldop, op | 0x20, type) \
6825 GEN_LDU(name, ldop, op | 0x21, type) \
6826 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6827 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6828
6829 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6830 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6831 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6832 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6833 #if defined(TARGET_PPC64)
6834 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6835 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6836 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
6837 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
6838 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6839
6840 /* HV/P7 and later only */
6841 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
6842 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6843 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6844 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6845 #endif
6846 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6847 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6848
6849 #undef GEN_ST
6850 #undef GEN_STU
6851 #undef GEN_STUX
6852 #undef GEN_STX_E
6853 #undef GEN_STS
6854 #define GEN_ST(name, stop, opc, type) \
6855 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6856 #define GEN_STU(name, stop, opc, type) \
6857 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6858 #define GEN_STUX(name, stop, opc2, opc3, type) \
6859 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6860 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6861 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6862 #define GEN_STS(name, stop, op, type) \
6863 GEN_ST(name, stop, op | 0x20, type) \
6864 GEN_STU(name, stop, op | 0x21, type) \
6865 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6866 GEN_STX(name, stop, 0x17, op | 0x00, type)
6867
6868 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6869 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6870 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6871 #if defined(TARGET_PPC64)
6872 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
6873 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
6874 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6875 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
6876 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6877 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6878 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6879 #endif
6880 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6881 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6882
6883 #undef GEN_CRLOGIC
6884 #define GEN_CRLOGIC(name, tcg_op, opc) \
6885 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6886 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6887 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6888 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6889 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6890 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6891 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6892 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6893 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6894
6895 #undef GEN_MAC_HANDLER
6896 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6897 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6898 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6899 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6900 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6901 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6902 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6903 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6904 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6905 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6906 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6907 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6908 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6909 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6910 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6911 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6912 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6913 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6914 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6915 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6916 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6917 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6918 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6919 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6920 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6921 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6922 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6923 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6924 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6925 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6926 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6927 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6928 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6929 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6930 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6931 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6932 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6933 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6934 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6935 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6936 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6937 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6938 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6939 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6940
6941 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6942 PPC_NONE, PPC2_TM),
6943 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6944 PPC_NONE, PPC2_TM),
6945 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6946 PPC_NONE, PPC2_TM),
6947 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6948 PPC_NONE, PPC2_TM),
6949 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6950 PPC_NONE, PPC2_TM),
6951 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6952 PPC_NONE, PPC2_TM),
6953 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6954 PPC_NONE, PPC2_TM),
6955 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6956 PPC_NONE, PPC2_TM),
6957 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6958 PPC_NONE, PPC2_TM),
6959 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6960 PPC_NONE, PPC2_TM),
6961 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6962 PPC_NONE, PPC2_TM),
6963
6964 #include "translate/fp-ops.inc.c"
6965
6966 #include "translate/vmx-ops.inc.c"
6967
6968 #include "translate/vsx-ops.inc.c"
6969
6970 #include "translate/dfp-ops.inc.c"
6971
6972 #include "translate/spe-ops.inc.c"
6973 };
6974
6975 #include "helper_regs.h"
6976 #include "translate_init.c"
6977
6978 /*****************************************************************************/
6979 /* Misc PowerPC helpers */
6980 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6981 int flags)
6982 {
6983 #define RGPL 4
6984 #define RFPL 4
6985
6986 PowerPCCPU *cpu = POWERPC_CPU(cs);
6987 CPUPPCState *env = &cpu->env;
6988 int i;
6989
6990 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
6991 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6992 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6993 cs->cpu_index);
6994 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
6995 TARGET_FMT_lx " iidx %d didx %d\n",
6996 env->msr, env->spr[SPR_HID0],
6997 env->hflags, env->immu_idx, env->dmmu_idx);
6998 #if !defined(NO_TIMER_DUMP)
6999 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7000 #if !defined(CONFIG_USER_ONLY)
7001 " DECR %08" PRIu32
7002 #endif
7003 "\n",
7004 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7005 #if !defined(CONFIG_USER_ONLY)
7006 , cpu_ppc_load_decr(env)
7007 #endif
7008 );
7009 #endif
7010 for (i = 0; i < 32; i++) {
7011 if ((i & (RGPL - 1)) == 0)
7012 cpu_fprintf(f, "GPR%02d", i);
7013 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7014 if ((i & (RGPL - 1)) == (RGPL - 1))
7015 cpu_fprintf(f, "\n");
7016 }
7017 cpu_fprintf(f, "CR ");
7018 for (i = 0; i < 8; i++)
7019 cpu_fprintf(f, "%01x", env->crf[i]);
7020 cpu_fprintf(f, " [");
7021 for (i = 0; i < 8; i++) {
7022 char a = '-';
7023 if (env->crf[i] & 0x08)
7024 a = 'L';
7025 else if (env->crf[i] & 0x04)
7026 a = 'G';
7027 else if (env->crf[i] & 0x02)
7028 a = 'E';
7029 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7030 }
7031 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7032 env->reserve_addr);
7033 for (i = 0; i < 32; i++) {
7034 if ((i & (RFPL - 1)) == 0)
7035 cpu_fprintf(f, "FPR%02d", i);
7036 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
7037 if ((i & (RFPL - 1)) == (RFPL - 1))
7038 cpu_fprintf(f, "\n");
7039 }
7040 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7041 #if !defined(CONFIG_USER_ONLY)
7042 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7043 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7044 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7045 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7046
7047 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7048 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7049 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7050 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7051
7052 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7053 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7054 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7055 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7056
7057 #if defined(TARGET_PPC64)
7058 if (env->excp_model == POWERPC_EXCP_POWER7 ||
7059 env->excp_model == POWERPC_EXCP_POWER8) {
7060 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7061 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7062 }
7063 #endif
7064 if (env->excp_model == POWERPC_EXCP_BOOKE) {
7065 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7066 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7067 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7068 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7069
7070 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7071 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7072 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7073 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7074
7075 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7076 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7077 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7078 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7079
7080 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7081 " EPR " TARGET_FMT_lx "\n",
7082 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7083 env->spr[SPR_BOOKE_EPR]);
7084
7085 /* FSL-specific */
7086 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7087 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7088 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7089 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7090
7091 /*
7092 * IVORs are left out as they are large and do not change often --
7093 * they can be read with "p $ivor0", "p $ivor1", etc.
7094 */
7095 }
7096
7097 #if defined(TARGET_PPC64)
7098 if (env->flags & POWERPC_FLAG_CFAR) {
7099 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7100 }
7101 #endif
7102
7103 if (env->spr_cb[SPR_LPCR].name)
7104 cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7105
7106 switch (POWERPC_MMU_VER(env->mmu_model)) {
7107 case POWERPC_MMU_32B:
7108 case POWERPC_MMU_601:
7109 case POWERPC_MMU_SOFT_6xx:
7110 case POWERPC_MMU_SOFT_74xx:
7111 #if defined(TARGET_PPC64)
7112 case POWERPC_MMU_VER_64B:
7113 case POWERPC_MMU_VER_2_03:
7114 case POWERPC_MMU_VER_2_06:
7115 case POWERPC_MMU_VER_2_07:
7116 case POWERPC_MMU_VER_3_00:
7117 #endif
7118 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7119 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7120 }
7121 cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7122 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7123 break;
7124 case POWERPC_MMU_BOOKE206:
7125 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7126 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7127 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7128 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7129
7130 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7131 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7132 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7133 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7134
7135 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7136 " TLB1CFG " TARGET_FMT_lx "\n",
7137 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7138 env->spr[SPR_BOOKE_TLB1CFG]);
7139 break;
7140 default:
7141 break;
7142 }
7143 #endif
7144
7145 #undef RGPL
7146 #undef RFPL
7147 }
7148
7149 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
7150 fprintf_function cpu_fprintf, int flags)
7151 {
7152 #if defined(DO_PPC_STATISTICS)
7153 PowerPCCPU *cpu = POWERPC_CPU(cs);
7154 opc_handler_t **t1, **t2, **t3, *handler;
7155 int op1, op2, op3;
7156
7157 t1 = cpu->env.opcodes;
7158 for (op1 = 0; op1 < 64; op1++) {
7159 handler = t1[op1];
7160 if (is_indirect_opcode(handler)) {
7161 t2 = ind_table(handler);
7162 for (op2 = 0; op2 < 32; op2++) {
7163 handler = t2[op2];
7164 if (is_indirect_opcode(handler)) {
7165 t3 = ind_table(handler);
7166 for (op3 = 0; op3 < 32; op3++) {
7167 handler = t3[op3];
7168 if (handler->count == 0)
7169 continue;
7170 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7171 "%016" PRIx64 " %" PRId64 "\n",
7172 op1, op2, op3, op1, (op3 << 5) | op2,
7173 handler->oname,
7174 handler->count, handler->count);
7175 }
7176 } else {
7177 if (handler->count == 0)
7178 continue;
7179 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7180 "%016" PRIx64 " %" PRId64 "\n",
7181 op1, op2, op1, op2, handler->oname,
7182 handler->count, handler->count);
7183 }
7184 }
7185 } else {
7186 if (handler->count == 0)
7187 continue;
7188 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
7189 " %" PRId64 "\n",
7190 op1, op1, handler->oname,
7191 handler->count, handler->count);
7192 }
7193 }
7194 #endif
7195 }
7196
7197 /*****************************************************************************/
7198 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
7199 {
7200 PowerPCCPU *cpu = ppc_env_get_cpu(env);
7201 CPUState *cs = CPU(cpu);
7202 DisasContext ctx, *ctxp = &ctx;
7203 opc_handler_t **table, *handler;
7204 target_ulong pc_start;
7205 int num_insns;
7206 int max_insns;
7207
7208 pc_start = tb->pc;
7209 ctx.nip = pc_start;
7210 ctx.tb = tb;
7211 ctx.exception = POWERPC_EXCP_NONE;
7212 ctx.spr_cb = env->spr_cb;
7213 ctx.pr = msr_pr;
7214 ctx.mem_idx = env->dmmu_idx;
7215 ctx.dr = msr_dr;
7216 #if !defined(CONFIG_USER_ONLY)
7217 ctx.hv = msr_hv || !env->has_hv_mode;
7218 #endif
7219 ctx.insns_flags = env->insns_flags;
7220 ctx.insns_flags2 = env->insns_flags2;
7221 ctx.access_type = -1;
7222 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
7223 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
7224 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
7225 #if defined(TARGET_PPC64)
7226 ctx.sf_mode = msr_is_64bit(env, env->msr);
7227 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7228 #endif
7229 if (env->mmu_model == POWERPC_MMU_32B ||
7230 env->mmu_model == POWERPC_MMU_601 ||
7231 (env->mmu_model & POWERPC_MMU_64B))
7232 ctx.lazy_tlb_flush = true;
7233
7234 ctx.fpu_enabled = !!msr_fp;
7235 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7236 ctx.spe_enabled = !!msr_spe;
7237 else
7238 ctx.spe_enabled = false;
7239 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7240 ctx.altivec_enabled = !!msr_vr;
7241 else
7242 ctx.altivec_enabled = false;
7243 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
7244 ctx.vsx_enabled = !!msr_vsx;
7245 } else {
7246 ctx.vsx_enabled = false;
7247 }
7248 #if defined(TARGET_PPC64)
7249 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
7250 ctx.tm_enabled = !!msr_tm;
7251 } else {
7252 ctx.tm_enabled = false;
7253 }
7254 #endif
7255 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7256 ctx.singlestep_enabled = CPU_SINGLE_STEP;
7257 else
7258 ctx.singlestep_enabled = 0;
7259 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7260 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7261 if (unlikely(cs->singlestep_enabled)) {
7262 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7263 }
7264 #if defined (DO_SINGLE_STEP) && 0
7265 /* Single step trace mode */
7266 msr_se = 1;
7267 #endif
7268 num_insns = 0;
7269 max_insns = tb->cflags & CF_COUNT_MASK;
7270 if (max_insns == 0) {
7271 max_insns = CF_COUNT_MASK;
7272 }
7273 if (max_insns > TCG_MAX_INSNS) {
7274 max_insns = TCG_MAX_INSNS;
7275 }
7276
7277 gen_tb_start(tb);
7278 tcg_clear_temp_count();
7279 /* Set env in case of segfault during code fetch */
7280 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
7281 tcg_gen_insn_start(ctx.nip);
7282 num_insns++;
7283
7284 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
7285 gen_debug_exception(ctxp);
7286 /* The address covered by the breakpoint must be included in
7287 [tb->pc, tb->pc + tb->size) in order to for it to be
7288 properly cleared -- thus we increment the PC here so that
7289 the logic setting tb->size below does the right thing. */
7290 ctx.nip += 4;
7291 break;
7292 }
7293
7294 LOG_DISAS("----------------\n");
7295 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7296 ctx.nip, ctx.mem_idx, (int)msr_ir);
7297 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7298 gen_io_start();
7299 if (unlikely(need_byteswap(&ctx))) {
7300 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7301 } else {
7302 ctx.opcode = cpu_ldl_code(env, ctx.nip);
7303 }
7304 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7305 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7306 opc3(ctx.opcode), opc4(ctx.opcode),
7307 ctx.le_mode ? "little" : "big");
7308 ctx.nip += 4;
7309 table = env->opcodes;
7310 handler = table[opc1(ctx.opcode)];
7311 if (is_indirect_opcode(handler)) {
7312 table = ind_table(handler);
7313 handler = table[opc2(ctx.opcode)];
7314 if (is_indirect_opcode(handler)) {
7315 table = ind_table(handler);
7316 handler = table[opc3(ctx.opcode)];
7317 if (is_indirect_opcode(handler)) {
7318 table = ind_table(handler);
7319 handler = table[opc4(ctx.opcode)];
7320 }
7321 }
7322 }
7323 /* Is opcode *REALLY* valid ? */
7324 if (unlikely(handler->handler == &gen_invalid)) {
7325 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7326 "%02x - %02x - %02x - %02x (%08x) "
7327 TARGET_FMT_lx " %d\n",
7328 opc1(ctx.opcode), opc2(ctx.opcode),
7329 opc3(ctx.opcode), opc4(ctx.opcode),
7330 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7331 } else {
7332 uint32_t inval;
7333
7334 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7335 inval = handler->inval2;
7336 } else {
7337 inval = handler->inval1;
7338 }
7339
7340 if (unlikely((ctx.opcode & inval) != 0)) {
7341 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7342 "%02x - %02x - %02x - %02x (%08x) "
7343 TARGET_FMT_lx "\n", ctx.opcode & inval,
7344 opc1(ctx.opcode), opc2(ctx.opcode),
7345 opc3(ctx.opcode), opc4(ctx.opcode),
7346 ctx.opcode, ctx.nip - 4);
7347 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7348 break;
7349 }
7350 }
7351 (*(handler->handler))(&ctx);
7352 #if defined(DO_PPC_STATISTICS)
7353 handler->count++;
7354 #endif
7355 /* Check trace mode exceptions */
7356 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7357 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7358 ctx.exception != POWERPC_SYSCALL &&
7359 ctx.exception != POWERPC_EXCP_TRAP &&
7360 ctx.exception != POWERPC_EXCP_BRANCH)) {
7361 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7362 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7363 (cs->singlestep_enabled) ||
7364 singlestep ||
7365 num_insns >= max_insns)) {
7366 /* if we reach a page boundary or are single stepping, stop
7367 * generation
7368 */
7369 break;
7370 }
7371 if (tcg_check_temp_count()) {
7372 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7373 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7374 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7375 exit(1);
7376 }
7377 }
7378 if (tb->cflags & CF_LAST_IO)
7379 gen_io_end();
7380 if (ctx.exception == POWERPC_EXCP_NONE) {
7381 gen_goto_tb(&ctx, 0, ctx.nip);
7382 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7383 if (unlikely(cs->singlestep_enabled)) {
7384 gen_debug_exception(ctxp);
7385 }
7386 /* Generate the return instruction */
7387 tcg_gen_exit_tb(0);
7388 }
7389 gen_tb_end(tb, num_insns);
7390
7391 tb->size = ctx.nip - pc_start;
7392 tb->icount = num_insns;
7393
7394 #if defined(DEBUG_DISAS)
7395 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7396 && qemu_log_in_addr_range(pc_start)) {
7397 int flags;
7398 flags = env->bfd_mach;
7399 flags |= ctx.le_mode << 16;
7400 qemu_log_lock();
7401 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7402 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7403 qemu_log("\n");
7404 qemu_log_unlock();
7405 }
7406 #endif
7407 }
7408
7409 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7410 target_ulong *data)
7411 {
7412 env->nip = data[0];
7413 }
AR7 emulation for QEMU