hw/timer/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "config-target.h"
  26 #include "hw/hw.h"
  27 #include "qemu/timer.h"
  28 #include "sysemu/sysemu.h"
  29 #include "hw/timer/mc146818rtc.h"
  30 #include "qapi/visitor.h"
  31 #include "qapi-event.h"
  32 #include "qmp-commands.h"
  33
  34 #ifdef TARGET_I386
  35 #include "hw/i386/apic.h"
  36 #endif
  37
  38 //#define DEBUG_CMOS
  39 //#define DEBUG_COALESCED
  40
  41 #ifdef DEBUG_CMOS
  42 # define CMOS_DPRINTF(format, ...)      printf(format, ## __VA_ARGS__)
  43 #else
  44 # define CMOS_DPRINTF(format, ...)      do { } while (0)
  45 #endif
  46
  47 #ifdef DEBUG_COALESCED
  48 # define DPRINTF_C(format, ...)      printf(format, ## __VA_ARGS__)
  49 #else
  50 # define DPRINTF_C(format, ...)      do { } while (0)
  51 #endif
  52
  53 #define SEC_PER_MIN     60
  54 #define MIN_PER_HOUR    60
  55 #define SEC_PER_HOUR    3600
  56 #define HOUR_PER_DAY    24
  57 #define SEC_PER_DAY     86400
  58
  59 #define RTC_REINJECT_ON_ACK_COUNT 20
  60 #define RTC_CLOCK_RATE            32768
  61 #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
  62
  63 #define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
  64
  65 typedef struct RTCState {
  66     ISADevice parent_obj;
  67
  68     MemoryRegion io;
  69     uint8_t cmos_data[128];
  70     uint8_t cmos_index;
  71     int32_t base_year;
  72     uint64_t base_rtc;
  73     uint64_t last_update;
  74     int64_t offset;
  75     qemu_irq irq;
  76     int it_shift;
  77     /* periodic timer */
  78     QEMUTimer *periodic_timer;
  79     int64_t next_periodic_time;
  80     /* update-ended timer */
  81     QEMUTimer *update_timer;
  82     uint64_t next_alarm_time;
  83     uint16_t irq_reinject_on_ack_count;
  84     uint32_t irq_coalesced;
  85     uint32_t period;
  86     QEMUTimer *coalesced_timer;
  87     Notifier clock_reset_notifier;
  88     LostTickPolicy lost_tick_policy;
  89     Notifier suspend_notifier;
  90     QLIST_ENTRY(RTCState) link;
  91 } RTCState;
  92
  93 static void rtc_set_time(RTCState *s);
  94 static void rtc_update_time(RTCState *s);
  95 static void rtc_set_cmos(RTCState *s, const struct tm *tm);
  96 static inline int rtc_from_bcd(RTCState *s, int a);
  97 static uint64_t get_next_alarm(RTCState *s);
  98
  99 static inline bool rtc_running(RTCState *s)
 100 {
 101     return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) &&
 102             (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20);
 103 }
 104
 105 static uint64_t get_guest_rtc_ns(RTCState *s)
 106 {
 107     uint64_t guest_rtc;
 108     uint64_t guest_clock = qemu_clock_get_ns(rtc_clock);
 109
 110     guest_rtc = s->base_rtc * NANOSECONDS_PER_SECOND
 111                  + guest_clock - s->last_update + s->offset;
 112     return guest_rtc;
 113 }
 114
 115 #ifdef TARGET_I386
 116 static void rtc_coalesced_timer_update(RTCState *s)
 117 {
 118     if (s->irq_coalesced == 0) {
 119         timer_del(s->coalesced_timer);
 120     } else {
 121         /* divide each RTC interval to 2 - 8 smaller intervals */
 122         int c = MIN(s->irq_coalesced, 7) + 1;
 123         int64_t next_clock = qemu_clock_get_ns(rtc_clock) +
 124             muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE);
 125         timer_mod(s->coalesced_timer, next_clock);
 126     }
 127 }
 128
 129 static void rtc_coalesced_timer(void *opaque)
 130 {
 131     RTCState *s = opaque;
 132
 133     if (s->irq_coalesced != 0) {
 134         apic_reset_irq_delivered();
 135         s->cmos_data[RTC_REG_C] |= 0xc0;
 136         DPRINTF_C("cmos: injecting from timer\n");
 137         qemu_irq_raise(s->irq);
 138         if (apic_get_irq_delivered()) {
 139             s->irq_coalesced--;
 140             DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 141                       s->irq_coalesced);
 142         }
 143     }
 144
 145     rtc_coalesced_timer_update(s);
 146 }
 147 #endif
 148
 149 /* handle periodic timer */
 150 static void periodic_timer_update(RTCState *s, int64_t current_time)
 151 {
 152     int period_code, period;
 153     int64_t cur_clock, next_irq_clock;
 154
 155     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 156     if (period_code != 0
 157         && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
 158         if (period_code <= 2)
 159             period_code += 7;
 160         /* period in 32 Khz cycles */
 161         period = 1 << (period_code - 1);
 162 #ifdef TARGET_I386
 163         if (period != s->period) {
 164             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 165             DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
 166         }
 167         s->period = period;
 168 #endif
 169         /* compute 32 khz clock */
 170         cur_clock = muldiv64(current_time, RTC_CLOCK_RATE, get_ticks_per_sec());
 171         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 172         s->next_periodic_time =
 173             muldiv64(next_irq_clock, get_ticks_per_sec(), RTC_CLOCK_RATE) + 1;
 174         timer_mod(s->periodic_timer, s->next_periodic_time);
 175     } else {
 176 #ifdef TARGET_I386
 177         s->irq_coalesced = 0;
 178 #endif
 179         timer_del(s->periodic_timer);
 180     }
 181 }
 182
 183 static void rtc_periodic_timer(void *opaque)
 184 {
 185     RTCState *s = opaque;
 186
 187     periodic_timer_update(s, s->next_periodic_time);
 188     s->cmos_data[RTC_REG_C] |= REG_C_PF;
 189     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 190         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 191 #ifdef TARGET_I386
 192         if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
 193             if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
 194                 s->irq_reinject_on_ack_count = 0;
 195             apic_reset_irq_delivered();
 196             qemu_irq_raise(s->irq);
 197             if (!apic_get_irq_delivered()) {
 198                 s->irq_coalesced++;
 199                 rtc_coalesced_timer_update(s);
 200                 DPRINTF_C("cmos: coalesced irqs increased to %d\n",
 201                           s->irq_coalesced);
 202             }
 203         } else
 204 #endif
 205         qemu_irq_raise(s->irq);
 206     }
 207 }
 208
 209 /* handle update-ended timer */
 210 static void check_update_timer(RTCState *s)
 211 {
 212     uint64_t next_update_time;
 213     uint64_t guest_nsec;
 214     int next_alarm_sec;
 215
 216     /* From the data sheet: "Holding the dividers in reset prevents
 217      * interrupts from operating, while setting the SET bit allows"
 218      * them to occur.  However, it will prevent an alarm interrupt
 219      * from occurring, because the time of day is not updated.
 220      */
 221     if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) {
 222         timer_del(s->update_timer);
 223         return;
 224     }
 225     if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
 226         (s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 227         timer_del(s->update_timer);
 228         return;
 229     }
 230     if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
 231         (s->cmos_data[RTC_REG_C] & REG_C_AF)) {
 232         timer_del(s->update_timer);
 233         return;
 234     }
 235
 236     guest_nsec = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND;
 237     /* if UF is clear, reprogram to next second */
 238     next_update_time = qemu_clock_get_ns(rtc_clock)
 239         + NANOSECONDS_PER_SECOND - guest_nsec;
 240
 241     /* Compute time of next alarm.  One second is already accounted
 242      * for in next_update_time.
 243      */
 244     next_alarm_sec = get_next_alarm(s);
 245     s->next_alarm_time = next_update_time +
 246                          (next_alarm_sec - 1) * NANOSECONDS_PER_SECOND;
 247
 248     if (s->cmos_data[RTC_REG_C] & REG_C_UF) {
 249         /* UF is set, but AF is clear.  Program the timer to target
 250          * the alarm time.  */
 251         next_update_time = s->next_alarm_time;
 252     }
 253     if (next_update_time != timer_expire_time_ns(s->update_timer)) {
 254         timer_mod(s->update_timer, next_update_time);
 255     }
 256 }
 257
 258 static inline uint8_t convert_hour(RTCState *s, uint8_t hour)
 259 {
 260     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
 261         hour %= 12;
 262         if (s->cmos_data[RTC_HOURS] & 0x80) {
 263             hour += 12;
 264         }
 265     }
 266     return hour;
 267 }
 268
 269 static uint64_t get_next_alarm(RTCState *s)
 270 {
 271     int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec;
 272     int32_t hour, min, sec;
 273
 274     rtc_update_time(s);
 275
 276     alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]);
 277     alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]);
 278     alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]);
 279     alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour);
 280
 281     cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 282     cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 283     cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]);
 284     cur_hour = convert_hour(s, cur_hour);
 285
 286     if (alarm_hour == -1) {
 287         alarm_hour = cur_hour;
 288         if (alarm_min == -1) {
 289             alarm_min = cur_min;
 290             if (alarm_sec == -1) {
 291                 alarm_sec = cur_sec + 1;
 292             } else if (cur_sec > alarm_sec) {
 293                 alarm_min++;
 294             }
 295         } else if (cur_min == alarm_min) {
 296             if (alarm_sec == -1) {
 297                 alarm_sec = cur_sec + 1;
 298             } else {
 299                 if (cur_sec > alarm_sec) {
 300                     alarm_hour++;
 301                 }
 302             }
 303             if (alarm_sec == SEC_PER_MIN) {
 304                 /* wrap to next hour, minutes is not in don't care mode */
 305                 alarm_sec = 0;
 306                 alarm_hour++;
 307             }
 308         } else if (cur_min > alarm_min) {
 309             alarm_hour++;
 310         }
 311     } else if (cur_hour == alarm_hour) {
 312         if (alarm_min == -1) {
 313             alarm_min = cur_min;
 314             if (alarm_sec == -1) {
 315                 alarm_sec = cur_sec + 1;
 316             } else if (cur_sec > alarm_sec) {
 317                 alarm_min++;
 318             }
 319
 320             if (alarm_sec == SEC_PER_MIN) {
 321                 alarm_sec = 0;
 322                 alarm_min++;
 323             }
 324             /* wrap to next day, hour is not in don't care mode */
 325             alarm_min %= MIN_PER_HOUR;
 326         } else if (cur_min == alarm_min) {
 327             if (alarm_sec == -1) {
 328                 alarm_sec = cur_sec + 1;
 329             }
 330             /* wrap to next day, hours+minutes not in don't care mode */
 331             alarm_sec %= SEC_PER_MIN;
 332         }
 333     }
 334
 335     /* values that are still don't care fire at the next min/sec */
 336     if (alarm_min == -1) {
 337         alarm_min = 0;
 338     }
 339     if (alarm_sec == -1) {
 340         alarm_sec = 0;
 341     }
 342
 343     /* keep values in range */
 344     if (alarm_sec == SEC_PER_MIN) {
 345         alarm_sec = 0;
 346         alarm_min++;
 347     }
 348     if (alarm_min == MIN_PER_HOUR) {
 349         alarm_min = 0;
 350         alarm_hour++;
 351     }
 352     alarm_hour %= HOUR_PER_DAY;
 353
 354     hour = alarm_hour - cur_hour;
 355     min = hour * MIN_PER_HOUR + alarm_min - cur_min;
 356     sec = min * SEC_PER_MIN + alarm_sec - cur_sec;
 357     return sec <= 0 ? sec + SEC_PER_DAY : sec;
 358 }
 359
 360 static void rtc_update_timer(void *opaque)
 361 {
 362     RTCState *s = opaque;
 363     int32_t irqs = REG_C_UF;
 364     int32_t new_irqs;
 365
 366     assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60);
 367
 368     /* UIP might have been latched, update time and clear it.  */
 369     rtc_update_time(s);
 370     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 371
 372     if (qemu_clock_get_ns(rtc_clock) >= s->next_alarm_time) {
 373         irqs |= REG_C_AF;
 374         if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 375             qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
 376         }
 377     }
 378
 379     new_irqs = irqs & ~s->cmos_data[RTC_REG_C];
 380     s->cmos_data[RTC_REG_C] |= irqs;
 381     if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) {
 382         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 383         qemu_irq_raise(s->irq);
 384     }
 385     check_update_timer(s);
 386 }
 387
 388 static void cmos_ioport_write(void *opaque, hwaddr addr,
 389                               uint64_t data, unsigned size)
 390 {
 391     RTCState *s = opaque;
 392
 393     if ((addr & 1) == 0) {
 394         s->cmos_index = data & 0x7f;
 395     } else {
 396         CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02" PRIx64 "\n",
 397                      s->cmos_index, data);
 398         switch(s->cmos_index) {
 399         case RTC_SECONDS_ALARM:
 400         case RTC_MINUTES_ALARM:
 401         case RTC_HOURS_ALARM:
 402             s->cmos_data[s->cmos_index] = data;
 403             check_update_timer(s);
 404             break;
 405         case RTC_IBM_PS2_CENTURY_BYTE:
 406             s->cmos_index = RTC_CENTURY;
 407             /* fall through */
 408         case RTC_CENTURY:
 409         case RTC_SECONDS:
 410         case RTC_MINUTES:
 411         case RTC_HOURS:
 412         case RTC_DAY_OF_WEEK:
 413         case RTC_DAY_OF_MONTH:
 414         case RTC_MONTH:
 415         case RTC_YEAR:
 416             s->cmos_data[s->cmos_index] = data;
 417             /* if in set mode, do not update the time */
 418             if (rtc_running(s)) {
 419                 rtc_set_time(s);
 420                 check_update_timer(s);
 421             }
 422             break;
 423         case RTC_REG_A:
 424             if ((data & 0x60) == 0x60) {
 425                 if (rtc_running(s)) {
 426                     rtc_update_time(s);
 427                 }
 428                 /* What happens to UIP when divider reset is enabled is
 429                  * unclear from the datasheet.  Shouldn't matter much
 430                  * though.
 431                  */
 432                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 433             } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) &&
 434                     (data & 0x70)  <= 0x20) {
 435                 /* when the divider reset is removed, the first update cycle
 436                  * begins one-half second later*/
 437                 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 438                     s->offset = 500000000;
 439                     rtc_set_time(s);
 440                 }
 441                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 442             }
 443             /* UIP bit is read only */
 444             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 445                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 446             periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
 447             check_update_timer(s);
 448             break;
 449         case RTC_REG_B:
 450             if (data & REG_B_SET) {
 451                 /* update cmos to when the rtc was stopping */
 452                 if (rtc_running(s)) {
 453                     rtc_update_time(s);
 454                 }
 455                 /* set mode: reset UIP mode */
 456                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 457                 data &= ~REG_B_UIE;
 458             } else {
 459                 /* if disabling set mode, update the time */
 460                 if ((s->cmos_data[RTC_REG_B] & REG_B_SET) &&
 461                     (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) {
 462                     s->offset = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND;
 463                     rtc_set_time(s);
 464                 }
 465             }
 466             /* if an interrupt flag is already set when the interrupt
 467              * becomes enabled, raise an interrupt immediately.  */
 468             if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) {
 469                 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 470                 qemu_irq_raise(s->irq);
 471             } else {
 472                 s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF;
 473                 qemu_irq_lower(s->irq);
 474             }
 475             s->cmos_data[RTC_REG_B] = data;
 476             periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
 477             check_update_timer(s);
 478             break;
 479         case RTC_REG_C:
 480         case RTC_REG_D:
 481             /* cannot write to them */
 482             break;
 483         default:
 484             s->cmos_data[s->cmos_index] = data;
 485             break;
 486         }
 487     }
 488 }
 489
 490 static inline int rtc_to_bcd(RTCState *s, int a)
 491 {
 492     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 493         return a;
 494     } else {
 495         return ((a / 10) << 4) | (a % 10);
 496     }
 497 }
 498
 499 static inline int rtc_from_bcd(RTCState *s, int a)
 500 {
 501     if ((a & 0xc0) == 0xc0) {
 502         return -1;
 503     }
 504     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 505         return a;
 506     } else {
 507         return ((a >> 4) * 10) + (a & 0x0f);
 508     }
 509 }
 510
 511 static void rtc_get_time(RTCState *s, struct tm *tm)
 512 {
 513     tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 514     tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 515     tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 516     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
 517         tm->tm_hour %= 12;
 518         if (s->cmos_data[RTC_HOURS] & 0x80) {
 519             tm->tm_hour += 12;
 520         }
 521     }
 522     tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 523     tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 524     tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 525     tm->tm_year =
 526         rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year +
 527         rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900;
 528 }
 529
 530 static QLIST_HEAD(, RTCState) rtc_devices =
 531     QLIST_HEAD_INITIALIZER(rtc_devices);
 532
 533 #ifdef TARGET_I386
 534 void qmp_rtc_reset_reinjection(Error **errp)
 535 {
 536     RTCState *s;
 537
 538     QLIST_FOREACH(s, &rtc_devices, link) {
 539         s->irq_coalesced = 0;
 540     }
 541 }
 542 #endif
 543
 544 static void rtc_set_time(RTCState *s)
 545 {
 546     struct tm tm;
 547
 548     rtc_get_time(s, &tm);
 549     s->base_rtc = mktimegm(&tm);
 550     s->last_update = qemu_clock_get_ns(rtc_clock);
 551
 552     qapi_event_send_rtc_change(qemu_timedate_diff(&tm), &error_abort);
 553 }
 554
 555 static void rtc_set_cmos(RTCState *s, const struct tm *tm)
 556 {
 557     int year;
 558
 559     s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
 560     s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
 561     if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
 562         /* 24 hour format */
 563         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
 564     } else {
 565         /* 12 hour format */
 566         int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12;
 567         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h);
 568         if (tm->tm_hour >= 12)
 569             s->cmos_data[RTC_HOURS] |= 0x80;
 570     }
 571     s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
 572     s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
 573     s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
 574     year = tm->tm_year + 1900 - s->base_year;
 575     s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year % 100);
 576     s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100);
 577 }
 578
 579 static void rtc_update_time(RTCState *s)
 580 {
 581     struct tm ret;
 582     time_t guest_sec;
 583     int64_t guest_nsec;
 584
 585     guest_nsec = get_guest_rtc_ns(s);
 586     guest_sec = guest_nsec / NANOSECONDS_PER_SECOND;
 587     gmtime_r(&guest_sec, &ret);
 588
 589     /* Is SET flag of Register B disabled? */
 590     if ((s->cmos_data[RTC_REG_B] & REG_B_SET) == 0) {
 591         rtc_set_cmos(s, &ret);
 592     }
 593 }
 594
 595 static int update_in_progress(RTCState *s)
 596 {
 597     int64_t guest_nsec;
 598
 599     if (!rtc_running(s)) {
 600         return 0;
 601     }
 602     if (timer_pending(s->update_timer)) {
 603         int64_t next_update_time = timer_expire_time_ns(s->update_timer);
 604         /* Latch UIP until the timer expires.  */
 605         if (qemu_clock_get_ns(rtc_clock) >=
 606             (next_update_time - UIP_HOLD_LENGTH)) {
 607             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 608             return 1;
 609         }
 610     }
 611
 612     guest_nsec = get_guest_rtc_ns(s);
 613     /* UIP bit will be set at last 244us of every second. */
 614     if ((guest_nsec % NANOSECONDS_PER_SECOND) >=
 615         (NANOSECONDS_PER_SECOND - UIP_HOLD_LENGTH)) {
 616         return 1;
 617     }
 618     return 0;
 619 }
 620
 621 static uint64_t cmos_ioport_read(void *opaque, hwaddr addr,
 622                                  unsigned size)
 623 {
 624     RTCState *s = opaque;
 625     int ret;
 626     if ((addr & 1) == 0) {
 627         return 0xff;
 628     } else {
 629         switch(s->cmos_index) {
 630         case RTC_IBM_PS2_CENTURY_BYTE:
 631             s->cmos_index = RTC_CENTURY;
 632             /* fall through */
 633         case RTC_CENTURY:
 634         case RTC_SECONDS:
 635         case RTC_MINUTES:
 636         case RTC_HOURS:
 637         case RTC_DAY_OF_WEEK:
 638         case RTC_DAY_OF_MONTH:
 639         case RTC_MONTH:
 640         case RTC_YEAR:
 641             /* if not in set mode, calibrate cmos before
 642              * reading*/
 643             if (rtc_running(s)) {
 644                 rtc_update_time(s);
 645             }
 646             ret = s->cmos_data[s->cmos_index];
 647             break;
 648         case RTC_REG_A:
 649             if (update_in_progress(s)) {
 650                 s->cmos_data[s->cmos_index] |= REG_A_UIP;
 651             } else {
 652                 s->cmos_data[s->cmos_index] &= ~REG_A_UIP;
 653             }
 654             ret = s->cmos_data[s->cmos_index];
 655             break;
 656         case RTC_REG_C:
 657             ret = s->cmos_data[s->cmos_index];
 658             qemu_irq_lower(s->irq);
 659             s->cmos_data[RTC_REG_C] = 0x00;
 660             if (ret & (REG_C_UF | REG_C_AF)) {
 661                 check_update_timer(s);
 662             }
 663 #ifdef TARGET_I386
 664             if(s->irq_coalesced &&
 665                     (s->cmos_data[RTC_REG_B] & REG_B_PIE) &&
 666                     s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
 667                 s->irq_reinject_on_ack_count++;
 668                 s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF;
 669                 apic_reset_irq_delivered();
 670                 DPRINTF_C("cmos: injecting on ack\n");
 671                 qemu_irq_raise(s->irq);
 672                 if (apic_get_irq_delivered()) {
 673                     s->irq_coalesced--;
 674                     DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 675                               s->irq_coalesced);
 676                 }
 677             }
 678 #endif
 679             break;
 680         default:
 681             ret = s->cmos_data[s->cmos_index];
 682             break;
 683         }
 684         CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
 685                      s->cmos_index, ret);
 686         return ret;
 687     }
 688 }
 689
 690 void rtc_set_memory(ISADevice *dev, int addr, int val)
 691 {
 692     RTCState *s = MC146818_RTC(dev);
 693     if (addr >= 0 && addr <= 127)
 694         s->cmos_data[addr] = val;
 695 }
 696
 697 int rtc_get_memory(ISADevice *dev, int addr)
 698 {
 699     RTCState *s = MC146818_RTC(dev);
 700     assert(addr >= 0 && addr <= 127);
 701     return s->cmos_data[addr];
 702 }
 703
 704 static void rtc_set_date_from_host(ISADevice *dev)
 705 {
 706     RTCState *s = MC146818_RTC(dev);
 707     struct tm tm;
 708
 709     qemu_get_timedate(&tm, 0);
 710
 711     s->base_rtc = mktimegm(&tm);
 712     s->last_update = qemu_clock_get_ns(rtc_clock);
 713     s->offset = 0;
 714
 715     /* set the CMOS date */
 716     rtc_set_cmos(s, &tm);
 717 }
 718
 719 static int rtc_post_load(void *opaque, int version_id)
 720 {
 721     RTCState *s = opaque;
 722
 723     if (version_id <= 2) {
 724         rtc_set_time(s);
 725         s->offset = 0;
 726         check_update_timer(s);
 727     }
 728
 729     uint64_t now = qemu_clock_get_ns(rtc_clock);
 730     if (now < s->next_periodic_time ||
 731         now > (s->next_periodic_time + get_max_clock_jump())) {
 732         periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
 733     }
 734
 735 #ifdef TARGET_I386
 736     if (version_id >= 2) {
 737         if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
 738             rtc_coalesced_timer_update(s);
 739         }
 740     }
 741 #endif
 742     return 0;
 743 }
 744
 745 static bool rtc_irq_reinject_on_ack_count_needed(void *opaque)
 746 {
 747     RTCState *s = (RTCState *)opaque;
 748     return s->irq_reinject_on_ack_count != 0;
 749 }
 750
 751 static const VMStateDescription vmstate_rtc_irq_reinject_on_ack_count = {
 752     .name = "mc146818rtc/irq_reinject_on_ack_count",
 753     .version_id = 1,
 754     .minimum_version_id = 1,
 755     .needed = rtc_irq_reinject_on_ack_count_needed,
 756     .fields = (VMStateField[]) {
 757         VMSTATE_UINT16(irq_reinject_on_ack_count, RTCState),
 758         VMSTATE_END_OF_LIST()
 759     }
 760 };
 761
 762 static const VMStateDescription vmstate_rtc = {
 763     .name = "mc146818rtc",
 764     .version_id = 3,
 765     .minimum_version_id = 1,
 766     .post_load = rtc_post_load,
 767     .fields = (VMStateField[]) {
 768         VMSTATE_BUFFER(cmos_data, RTCState),
 769         VMSTATE_UINT8(cmos_index, RTCState),
 770         VMSTATE_UNUSED(7*4),
 771         VMSTATE_TIMER_PTR(periodic_timer, RTCState),
 772         VMSTATE_INT64(next_periodic_time, RTCState),
 773         VMSTATE_UNUSED(3*8),
 774         VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
 775         VMSTATE_UINT32_V(period, RTCState, 2),
 776         VMSTATE_UINT64_V(base_rtc, RTCState, 3),
 777         VMSTATE_UINT64_V(last_update, RTCState, 3),
 778         VMSTATE_INT64_V(offset, RTCState, 3),
 779         VMSTATE_TIMER_PTR_V(update_timer, RTCState, 3),
 780         VMSTATE_UINT64_V(next_alarm_time, RTCState, 3),
 781         VMSTATE_END_OF_LIST()
 782     },
 783     .subsections = (const VMStateDescription*[]) {
 784         &vmstate_rtc_irq_reinject_on_ack_count,
 785         NULL
 786     }
 787 };
 788
 789 static void rtc_notify_clock_reset(Notifier *notifier, void *data)
 790 {
 791     RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
 792     int64_t now = *(int64_t *)data;
 793
 794     rtc_set_date_from_host(ISA_DEVICE(s));
 795     periodic_timer_update(s, now);
 796     check_update_timer(s);
 797 #ifdef TARGET_I386
 798     if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
 799         rtc_coalesced_timer_update(s);
 800     }
 801 #endif
 802 }
 803
 804 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 805    BIOS will read it and start S3 resume at POST Entry */
 806 static void rtc_notify_suspend(Notifier *notifier, void *data)
 807 {
 808     RTCState *s = container_of(notifier, RTCState, suspend_notifier);
 809     rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE);
 810 }
 811
 812 static void rtc_reset(void *opaque)
 813 {
 814     RTCState *s = opaque;
 815
 816     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 817     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 818     check_update_timer(s);
 819
 820     qemu_irq_lower(s->irq);
 821
 822 #ifdef TARGET_I386
 823     if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
 824         s->irq_coalesced = 0;
 825         s->irq_reinject_on_ack_count = 0;
 826     }
 827 #endif
 828 }
 829
 830 static const MemoryRegionOps cmos_ops = {
 831     .read = cmos_ioport_read,
 832     .write = cmos_ioport_write,
 833     .impl = {
 834         .min_access_size = 1,
 835         .max_access_size = 1,
 836     },
 837     .endianness = DEVICE_LITTLE_ENDIAN,
 838 };
 839
 840 static void rtc_get_date(Object *obj, struct tm *current_tm, Error **errp)
 841 {
 842     RTCState *s = MC146818_RTC(obj);
 843
 844     rtc_update_time(s);
 845     rtc_get_time(s, current_tm);
 846 }
 847
 848 static void rtc_realizefn(DeviceState *dev, Error **errp)
 849 {
 850     ISADevice *isadev = ISA_DEVICE(dev);
 851     RTCState *s = MC146818_RTC(dev);
 852     int base = 0x70;
 853
 854     s->cmos_data[RTC_REG_A] = 0x26;
 855     s->cmos_data[RTC_REG_B] = 0x02;
 856     s->cmos_data[RTC_REG_C] = 0x00;
 857     s->cmos_data[RTC_REG_D] = 0x80;
 858
 859     /* This is for historical reasons.  The default base year qdev property
 860      * was set to 2000 for most machine types before the century byte was
 861      * implemented.
 862      *
 863      * This if statement means that the century byte will be always 0
 864      * (at least until 2079...) for base_year = 1980, but will be set
 865      * correctly for base_year = 2000.
 866      */
 867     if (s->base_year == 2000) {
 868         s->base_year = 0;
 869     }
 870
 871     rtc_set_date_from_host(isadev);
 872
 873 #ifdef TARGET_I386
 874     switch (s->lost_tick_policy) {
 875     case LOST_TICK_POLICY_SLEW:
 876         s->coalesced_timer =
 877             timer_new_ns(rtc_clock, rtc_coalesced_timer, s);
 878         break;
 879     case LOST_TICK_POLICY_DISCARD:
 880         break;
 881     default:
 882         error_setg(errp, "Invalid lost tick policy.");
 883         return;
 884     }
 885 #endif
 886
 887     s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s);
 888     s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s);
 889     check_update_timer(s);
 890
 891     s->clock_reset_notifier.notify = rtc_notify_clock_reset;
 892     qemu_clock_register_reset_notifier(rtc_clock,
 893                                        &s->clock_reset_notifier);
 894
 895     s->suspend_notifier.notify = rtc_notify_suspend;
 896     qemu_register_suspend_notifier(&s->suspend_notifier);
 897
 898     memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2);
 899     isa_register_ioport(isadev, &s->io, base);
 900
 901     qdev_set_legacy_instance_id(dev, base, 3);
 902     qemu_register_reset(rtc_reset, s);
 903
 904     object_property_add_tm(OBJECT(s), "date", rtc_get_date, NULL);
 905
 906     object_property_add_alias(qdev_get_machine(), "rtc-time",
 907                               OBJECT(s), "date", NULL);
 908 }
 909
 910 ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
 911 {
 912     DeviceState *dev;
 913     ISADevice *isadev;
 914     RTCState *s;
 915
 916     isadev = isa_create(bus, TYPE_MC146818_RTC);
 917     dev = DEVICE(isadev);
 918     s = MC146818_RTC(isadev);
 919     qdev_prop_set_int32(dev, "base_year", base_year);
 920     qdev_init_nofail(dev);
 921     if (intercept_irq) {
 922         s->irq = intercept_irq;
 923     } else {
 924         isa_init_irq(isadev, &s->irq, RTC_ISA_IRQ);
 925     }
 926     QLIST_INSERT_HEAD(&rtc_devices, s, link);
 927
 928     return isadev;
 929 }
 930
 931 static Property mc146818rtc_properties[] = {
 932     DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 933     DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
 934                                lost_tick_policy, LOST_TICK_POLICY_DISCARD),
 935     DEFINE_PROP_END_OF_LIST(),
 936 };
 937
 938 static void rtc_class_initfn(ObjectClass *klass, void *data)
 939 {
 940     DeviceClass *dc = DEVICE_CLASS(klass);
 941
 942     dc->realize = rtc_realizefn;
 943     dc->vmsd = &vmstate_rtc;
 944     dc->props = mc146818rtc_properties;
 945     /* Reason: needs to be wired up by rtc_init() */
 946     dc->cannot_instantiate_with_device_add_yet = true;
 947 }
 948
 949 static void rtc_finalize(Object *obj)
 950 {
 951     object_property_del(qdev_get_machine(), "rtc", NULL);
 952 }
 953
 954 static const TypeInfo mc146818rtc_info = {
 955     .name          = TYPE_MC146818_RTC,
 956     .parent        = TYPE_ISA_DEVICE,
 957     .instance_size = sizeof(RTCState),
 958     .class_init    = rtc_class_initfn,
 959     .instance_finalize = rtc_finalize,
 960 };
 961
 962 static void mc146818rtc_register_types(void)
 963 {
 964     type_register_static(&mc146818rtc_info);
 965 }
 966
 967 type_init(mc146818rtc_register_types)