include/hw/ppc/xics.h

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #ifndef XICS_H
  29 #define XICS_H
  30
  31 #include "hw/sysbus.h"
  32
  33 #define TYPE_XICS_COMMON "xics-common"
  34 #define XICS_COMMON(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_COMMON)
  35
  36 /*
  37  * Retain xics as the type name to be compatible for migration. Rest all the
  38  * functions, class and variables are renamed as xics_spapr.
  39  */
  40 #define TYPE_XICS_SPAPR "xics"
  41 #define XICS_SPAPR(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_SPAPR)
  42
  43 #define TYPE_XICS_SPAPR_KVM "xics-spapr-kvm"
  44 #define XICS_SPAPR_KVM(obj) \
  45      OBJECT_CHECK(KVMXICSState, (obj), TYPE_XICS_SPAPR_KVM)
  46
  47 #define XICS_COMMON_CLASS(klass) \
  48      OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON)
  49 #define XICS_SPAPR_CLASS(klass) \
  50      OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_SPAPR)
  51 #define XICS_COMMON_GET_CLASS(obj) \
  52      OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON)
  53 #define XICS_SPAPR_GET_CLASS(obj) \
  54      OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_SPAPR)
  55
  56 #define XICS_IPI        0x2
  57 #define XICS_BUID       0x1
  58 #define XICS_IRQ_BASE   (XICS_BUID << 12)
  59
  60 /*
  61  * We currently only support one BUID which is our interrupt base
  62  * (the kernel implementation supports more but we don't exploit
  63  *  that yet)
  64  */
  65 typedef struct XICSStateClass XICSStateClass;
  66 typedef struct XICSState XICSState;
  67 typedef struct ICPStateClass ICPStateClass;
  68 typedef struct ICPState ICPState;
  69 typedef struct ICSStateClass ICSStateClass;
  70 typedef struct ICSState ICSState;
  71 typedef struct ICSIRQState ICSIRQState;
  72
  73 struct XICSStateClass {
  74     DeviceClass parent_class;
  75
  76     void (*cpu_setup)(XICSState *icp, PowerPCCPU *cpu);
  77     void (*set_nr_irqs)(XICSState *icp, uint32_t nr_irqs, Error **errp);
  78     void (*set_nr_servers)(XICSState *icp, uint32_t nr_servers, Error **errp);
  79 };
  80
  81 struct XICSState {
  82     /*< private >*/
  83     SysBusDevice parent_obj;
  84     /*< public >*/
  85     uint32_t nr_servers;
  86     uint32_t nr_irqs;
  87     ICPState *ss;
  88     ICSState *ics;
  89 };
  90
  91 #define TYPE_ICP "icp"
  92 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
  93
  94 #define TYPE_KVM_ICP "icp-kvm"
  95 #define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP)
  96
  97 #define ICP_CLASS(klass) \
  98      OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
  99 #define ICP_GET_CLASS(obj) \
 100      OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
 101
 102 struct ICPStateClass {
 103     DeviceClass parent_class;
 104
 105     void (*pre_save)(ICPState *s);
 106     int (*post_load)(ICPState *s, int version_id);
 107 };
 108
 109 struct ICPState {
 110     /*< private >*/
 111     DeviceState parent_obj;
 112     /*< public >*/
 113     CPUState *cs;
 114     uint32_t xirr;
 115     uint8_t pending_priority;
 116     uint8_t mfrr;
 117     qemu_irq output;
 118     bool cap_irq_xics_enabled;
 119 };
 120
 121 #define TYPE_ICS "ics"
 122 #define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS)
 123
 124 #define TYPE_KVM_ICS "icskvm"
 125 #define KVM_ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_KVM_ICS)
 126
 127 #define ICS_CLASS(klass) \
 128      OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS)
 129 #define ICS_GET_CLASS(obj) \
 130      OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS)
 131
 132 struct ICSStateClass {
 133     DeviceClass parent_class;
 134
 135     void (*pre_save)(ICSState *s);
 136     int (*post_load)(ICSState *s, int version_id);
 137 };
 138
 139 struct ICSState {
 140     /*< private >*/
 141     DeviceState parent_obj;
 142     /*< public >*/
 143     uint32_t nr_irqs;
 144     uint32_t offset;
 145     qemu_irq *qirqs;
 146     ICSIRQState *irqs;
 147     XICSState *xics;
 148 };
 149
 150 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
 151 {
 152     return (nr >= ics->offset)
 153         && (nr < (ics->offset + ics->nr_irqs));
 154 }
 155
 156 struct ICSIRQState {
 157     uint32_t server;
 158     uint8_t priority;
 159     uint8_t saved_priority;
 160 #define XICS_STATUS_ASSERTED           0x1
 161 #define XICS_STATUS_SENT               0x2
 162 #define XICS_STATUS_REJECTED           0x4
 163 #define XICS_STATUS_MASKED_PENDING     0x8
 164     uint8_t status;
 165 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
 166 #define XICS_FLAGS_IRQ_LSI             0x1
 167 #define XICS_FLAGS_IRQ_MSI             0x2
 168 #define XICS_FLAGS_IRQ_MASK            0x3
 169     uint8_t flags;
 170 };
 171
 172 #define XICS_IRQS_SPAPR               1024
 173
 174 qemu_irq xics_get_qirq(XICSState *icp, int irq);
 175 int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
 176                      Error **errp);
 177 int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi,
 178                            bool align, Error **errp);
 179 void xics_spapr_free(XICSState *icp, int irq, int num);
 180
 181 void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
 182 void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu);
 183
 184 /* Internal XICS interfaces */
 185 int xics_get_cpu_index_by_dt_id(int cpu_dt_id);
 186
 187 void icp_set_cppr(XICSState *icp, int server, uint8_t cppr);
 188 void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr);
 189 uint32_t icp_accept(ICPState *ss);
 190 uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
 191 void icp_eoi(XICSState *icp, int server, uint32_t xirr);
 192
 193 void ics_write_xive(ICSState *ics, int nr, int server,
 194                     uint8_t priority, uint8_t saved_priority);
 195
 196 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
 197
 198 int xics_find_source(XICSState *icp, int irq);
 199
 200 #endif /* XICS_H */