include/hw/net/mii.h

   1 /*
   2  * Common network MII address and register definitions.
   3  *
   4  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
   5  *
   6  * Allwinner EMAC register definitions from Linux kernel are:
   7  *   Copyright 2012 Stefan Roese <sr@denx.de>
   8  *   Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
   9  *   Copyright 1997 Sten Wang
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License
  13  * version 2 as published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  */
  21 #ifndef MII_H
  22 #define MII_H
  23
  24 /* PHY registers */
  25 #define MII_BMCR            0
  26 #define MII_BMSR            1
  27 #define MII_PHYID1          2
  28 #define MII_PHYID2          3
  29 #define MII_ANAR            4
  30 #define MII_ANLPAR          5
  31 #define MII_ANER            6
  32 #define MII_NSR             16
  33 #define MII_LBREMR          17
  34 #define MII_REC             18
  35 #define MII_SNRDR           19
  36 #define MII_TEST            25
  37
  38 /* PHY registers fields */
  39 #define MII_BMCR_RESET      (1 << 15)
  40 #define MII_BMCR_LOOPBACK   (1 << 14)
  41 #define MII_BMCR_SPEED      (1 << 13)
  42 #define MII_BMCR_AUTOEN     (1 << 12)
  43 #define MII_BMCR_FD         (1 << 8)
  44
  45 #define MII_BMSR_100TX_FD   (1 << 14)
  46 #define MII_BMSR_100TX_HD   (1 << 13)
  47 #define MII_BMSR_10T_FD     (1 << 12)
  48 #define MII_BMSR_10T_HD     (1 << 11)
  49 #define MII_BMSR_MFPS       (1 << 6)
  50 #define MII_BMSR_AN_COMP    (1 << 5)
  51 #define MII_BMSR_AUTONEG    (1 << 3)
  52 #define MII_BMSR_LINK_ST    (1 << 2)
  53
  54 #define MII_ANAR_TXFD       (1 << 8)
  55 #define MII_ANAR_TX         (1 << 7)
  56 #define MII_ANAR_10FD       (1 << 6)
  57 #define MII_ANAR_10         (1 << 5)
  58 #define MII_ANAR_CSMACD     (1 << 0)
  59
  60 #define MII_ANLPAR_ACK      (1 << 14)
  61 #define MII_ANLPAR_TXFD     (1 << 8)
  62 #define MII_ANLPAR_TX       (1 << 7)
  63 #define MII_ANLPAR_10FD     (1 << 6)
  64 #define MII_ANLPAR_10       (1 << 5)
  65 #define MII_ANLPAR_CSMACD   (1 << 0)
  66
  67 /* List of vendor identifiers */
  68 /* RealTek 8201 */
  69 #define RTL8201CP_PHYID1    0x0000
  70 #define RTL8201CP_PHYID2    0x8201
  71
  72 /* National Semiconductor DP83848 */
  73 #define DP83848_PHYID1      0x2000
  74 #define DP83848_PHYID2      0x5c90
  75
  76 #endif /* MII_H */