target-i386/misc_helper.c

   1 /*
   2  *  x86 misc helpers
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "exec/cpu_ldst.h"
  23 #include "exec/address-spaces.h"
  24
  25 void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
  26 {
  27 #ifdef CONFIG_USER_ONLY
  28     fprintf(stderr, "outb: port=0x%04x, data=%02x\n", port, data);
  29 #else
  30     address_space_stb(&address_space_io, port, data,
  31                       cpu_get_mem_attrs(env), NULL);
  32 #endif
  33 }
  34
  35 target_ulong helper_inb(CPUX86State *env, uint32_t port)
  36 {
  37 #ifdef CONFIG_USER_ONLY
  38     fprintf(stderr, "inb: port=0x%04x\n", port);
  39     return 0;
  40 #else
  41     return address_space_ldub(&address_space_io, port,
  42                               cpu_get_mem_attrs(env), NULL);
  43 #endif
  44 }
  45
  46 void helper_outw(CPUX86State *env, uint32_t port, uint32_t data)
  47 {
  48 #ifdef CONFIG_USER_ONLY
  49     fprintf(stderr, "outw: port=0x%04x, data=%04x\n", port, data);
  50 #else
  51     address_space_stw(&address_space_io, port, data,
  52                       cpu_get_mem_attrs(env), NULL);
  53 #endif
  54 }
  55
  56 target_ulong helper_inw(CPUX86State *env, uint32_t port)
  57 {
  58 #ifdef CONFIG_USER_ONLY
  59     fprintf(stderr, "inw: port=0x%04x\n", port);
  60     return 0;
  61 #else
  62     return address_space_lduw(&address_space_io, port,
  63                               cpu_get_mem_attrs(env), NULL);
  64 #endif
  65 }
  66
  67 void helper_outl(CPUX86State *env, uint32_t port, uint32_t data)
  68 {
  69 #ifdef CONFIG_USER_ONLY
  70     fprintf(stderr, "outw: port=0x%04x, data=%08x\n", port, data);
  71 #else
  72     address_space_stl(&address_space_io, port, data,
  73                       cpu_get_mem_attrs(env), NULL);
  74 #endif
  75 }
  76
  77 target_ulong helper_inl(CPUX86State *env, uint32_t port)
  78 {
  79 #ifdef CONFIG_USER_ONLY
  80     fprintf(stderr, "inl: port=0x%04x\n", port);
  81     return 0;
  82 #else
  83     return address_space_ldl(&address_space_io, port,
  84                              cpu_get_mem_attrs(env), NULL);
  85 #endif
  86 }
  87
  88 void helper_into(CPUX86State *env, int next_eip_addend)
  89 {
  90     int eflags;
  91
  92     eflags = cpu_cc_compute_all(env, CC_OP);
  93     if (eflags & CC_O) {
  94         raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend);
  95     }
  96 }
  97
  98 void helper_single_step(CPUX86State *env)
  99 {
 100 #ifndef CONFIG_USER_ONLY
 101     check_hw_breakpoints(env, true);
 102     env->dr[6] |= DR6_BS;
 103 #endif
 104     raise_exception(env, EXCP01_DB);
 105 }
 106
 107 void helper_cpuid(CPUX86State *env)
 108 {
 109     uint32_t eax, ebx, ecx, edx;
 110
 111     cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);
 112
 113     cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX],
 114                   &eax, &ebx, &ecx, &edx);
 115     env->regs[R_EAX] = eax;
 116     env->regs[R_EBX] = ebx;
 117     env->regs[R_ECX] = ecx;
 118     env->regs[R_EDX] = edx;
 119 }
 120
 121 #if defined(CONFIG_USER_ONLY)
 122 target_ulong helper_read_crN(CPUX86State *env, int reg)
 123 {
 124     return 0;
 125 }
 126
 127 void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
 128 {
 129 }
 130
 131 void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
 132 {
 133 }
 134 #else
 135 target_ulong helper_read_crN(CPUX86State *env, int reg)
 136 {
 137     target_ulong val;
 138
 139     cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0);
 140     switch (reg) {
 141     default:
 142         val = env->cr[reg];
 143         break;
 144     case 8:
 145         if (!(env->hflags2 & HF2_VINTR_MASK)) {
 146             val = cpu_get_apic_tpr(x86_env_get_cpu(env)->apic_state);
 147         } else {
 148             val = env->v_tpr;
 149         }
 150         break;
 151     }
 152     return val;
 153 }
 154
 155 void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
 156 {
 157     cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0);
 158     switch (reg) {
 159     case 0:
 160         cpu_x86_update_cr0(env, t0);
 161         break;
 162     case 3:
 163         cpu_x86_update_cr3(env, t0);
 164         break;
 165     case 4:
 166         cpu_x86_update_cr4(env, t0);
 167         break;
 168     case 8:
 169         if (!(env->hflags2 & HF2_VINTR_MASK)) {
 170             cpu_set_apic_tpr(x86_env_get_cpu(env)->apic_state, t0);
 171         }
 172         env->v_tpr = t0 & 0x0f;
 173         break;
 174     default:
 175         env->cr[reg] = t0;
 176         break;
 177     }
 178 }
 179
 180 void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
 181 {
 182     int i;
 183
 184     if (reg < 4) {
 185         hw_breakpoint_remove(env, reg);
 186         env->dr[reg] = t0;
 187         hw_breakpoint_insert(env, reg);
 188     } else if (reg == 7) {
 189         for (i = 0; i < DR7_MAX_BP; i++) {
 190             hw_breakpoint_remove(env, i);
 191         }
 192         env->dr[7] = t0;
 193         for (i = 0; i < DR7_MAX_BP; i++) {
 194             hw_breakpoint_insert(env, i);
 195         }
 196     } else {
 197         env->dr[reg] = t0;
 198     }
 199 }
 200 #endif
 201
 202 void helper_lmsw(CPUX86State *env, target_ulong t0)
 203 {
 204     /* only 4 lower bits of CR0 are modified. PE cannot be set to zero
 205        if already set to one. */
 206     t0 = (env->cr[0] & ~0xe) | (t0 & 0xf);
 207     helper_write_crN(env, 0, t0);
 208 }
 209
 210 void helper_invlpg(CPUX86State *env, target_ulong addr)
 211 {
 212     X86CPU *cpu = x86_env_get_cpu(env);
 213
 214     cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
 215     tlb_flush_page(CPU(cpu), addr);
 216 }
 217
 218 void helper_rdtsc(CPUX86State *env)
 219 {
 220     uint64_t val;
 221
 222     if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
 223         raise_exception_ra(env, EXCP0D_GPF, GETPC());
 224     }
 225     cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0);
 226
 227     val = cpu_get_tsc(env) + env->tsc_offset;
 228     env->regs[R_EAX] = (uint32_t)(val);
 229     env->regs[R_EDX] = (uint32_t)(val >> 32);
 230 }
 231
 232 void helper_rdtscp(CPUX86State *env)
 233 {
 234     helper_rdtsc(env);
 235     env->regs[R_ECX] = (uint32_t)(env->tsc_aux);
 236 }
 237
 238 void helper_rdpmc(CPUX86State *env)
 239 {
 240     if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
 241         raise_exception_ra(env, EXCP0D_GPF, GETPC());
 242     }
 243     cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0);
 244
 245     /* currently unimplemented */
 246     qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n");
 247     raise_exception_err(env, EXCP06_ILLOP, 0);
 248 }
 249
 250 #if defined(CONFIG_USER_ONLY)
 251 void helper_wrmsr(CPUX86State *env)
 252 {
 253 }
 254
 255 void helper_rdmsr(CPUX86State *env)
 256 {
 257 }
 258 #else
 259 void helper_wrmsr(CPUX86State *env)
 260 {
 261     uint64_t val;
 262
 263     cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
 264
 265     val = ((uint32_t)env->regs[R_EAX]) |
 266         ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
 267
 268     switch ((uint32_t)env->regs[R_ECX]) {
 269     case MSR_IA32_SYSENTER_CS:
 270         env->sysenter_cs = val & 0xffff;
 271         break;
 272     case MSR_IA32_SYSENTER_ESP:
 273         env->sysenter_esp = val;
 274         break;
 275     case MSR_IA32_SYSENTER_EIP:
 276         env->sysenter_eip = val;
 277         break;
 278     case MSR_IA32_APICBASE:
 279         cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val);
 280         break;
 281     case MSR_EFER:
 282         {
 283             uint64_t update_mask;
 284
 285             update_mask = 0;
 286             if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) {
 287                 update_mask |= MSR_EFER_SCE;
 288             }
 289             if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
 290                 update_mask |= MSR_EFER_LME;
 291             }
 292             if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
 293                 update_mask |= MSR_EFER_FFXSR;
 294             }
 295             if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) {
 296                 update_mask |= MSR_EFER_NXE;
 297             }
 298             if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
 299                 update_mask |= MSR_EFER_SVME;
 300             }
 301             if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
 302                 update_mask |= MSR_EFER_FFXSR;
 303             }
 304             cpu_load_efer(env, (env->efer & ~update_mask) |
 305                           (val & update_mask));
 306         }
 307         break;
 308     case MSR_STAR:
 309         env->star = val;
 310         break;
 311     case MSR_PAT:
 312         env->pat = val;
 313         break;
 314     case MSR_VM_HSAVE_PA:
 315         env->vm_hsave = val;
 316         break;
 317 #ifdef TARGET_X86_64
 318     case MSR_LSTAR:
 319         env->lstar = val;
 320         break;
 321     case MSR_CSTAR:
 322         env->cstar = val;
 323         break;
 324     case MSR_FMASK:
 325         env->fmask = val;
 326         break;
 327     case MSR_FSBASE:
 328         env->segs[R_FS].base = val;
 329         break;
 330     case MSR_GSBASE:
 331         env->segs[R_GS].base = val;
 332         break;
 333     case MSR_KERNELGSBASE:
 334         env->kernelgsbase = val;
 335         break;
 336 #endif
 337     case MSR_MTRRphysBase(0):
 338     case MSR_MTRRphysBase(1):
 339     case MSR_MTRRphysBase(2):
 340     case MSR_MTRRphysBase(3):
 341     case MSR_MTRRphysBase(4):
 342     case MSR_MTRRphysBase(5):
 343     case MSR_MTRRphysBase(6):
 344     case MSR_MTRRphysBase(7):
 345         env->mtrr_var[((uint32_t)env->regs[R_ECX] -
 346                        MSR_MTRRphysBase(0)) / 2].base = val;
 347         break;
 348     case MSR_MTRRphysMask(0):
 349     case MSR_MTRRphysMask(1):
 350     case MSR_MTRRphysMask(2):
 351     case MSR_MTRRphysMask(3):
 352     case MSR_MTRRphysMask(4):
 353     case MSR_MTRRphysMask(5):
 354     case MSR_MTRRphysMask(6):
 355     case MSR_MTRRphysMask(7):
 356         env->mtrr_var[((uint32_t)env->regs[R_ECX] -
 357                        MSR_MTRRphysMask(0)) / 2].mask = val;
 358         break;
 359     case MSR_MTRRfix64K_00000:
 360         env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
 361                         MSR_MTRRfix64K_00000] = val;
 362         break;
 363     case MSR_MTRRfix16K_80000:
 364     case MSR_MTRRfix16K_A0000:
 365         env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
 366                         MSR_MTRRfix16K_80000 + 1] = val;
 367         break;
 368     case MSR_MTRRfix4K_C0000:
 369     case MSR_MTRRfix4K_C8000:
 370     case MSR_MTRRfix4K_D0000:
 371     case MSR_MTRRfix4K_D8000:
 372     case MSR_MTRRfix4K_E0000:
 373     case MSR_MTRRfix4K_E8000:
 374     case MSR_MTRRfix4K_F0000:
 375     case MSR_MTRRfix4K_F8000:
 376         env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
 377                         MSR_MTRRfix4K_C0000 + 3] = val;
 378         break;
 379     case MSR_MTRRdefType:
 380         env->mtrr_deftype = val;
 381         break;
 382     case MSR_MCG_STATUS:
 383         env->mcg_status = val;
 384         break;
 385     case MSR_MCG_CTL:
 386         if ((env->mcg_cap & MCG_CTL_P)
 387             && (val == 0 || val == ~(uint64_t)0)) {
 388             env->mcg_ctl = val;
 389         }
 390         break;
 391     case MSR_TSC_AUX:
 392         env->tsc_aux = val;
 393         break;
 394     case MSR_IA32_MISC_ENABLE:
 395         env->msr_ia32_misc_enable = val;
 396         break;
 397     default:
 398         if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
 399             && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
 400             (4 * env->mcg_cap & 0xff)) {
 401             uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
 402             if ((offset & 0x3) != 0
 403                 || (val == 0 || val == ~(uint64_t)0)) {
 404                 env->mce_banks[offset] = val;
 405             }
 406             break;
 407         }
 408         /* XXX: exception? */
 409         break;
 410     }
 411 }
 412
 413 void helper_rdmsr(CPUX86State *env)
 414 {
 415     uint64_t val;
 416
 417     cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0);
 418
 419     switch ((uint32_t)env->regs[R_ECX]) {
 420     case MSR_IA32_SYSENTER_CS:
 421         val = env->sysenter_cs;
 422         break;
 423     case MSR_IA32_SYSENTER_ESP:
 424         val = env->sysenter_esp;
 425         break;
 426     case MSR_IA32_SYSENTER_EIP:
 427         val = env->sysenter_eip;
 428         break;
 429     case MSR_IA32_APICBASE:
 430         val = cpu_get_apic_base(x86_env_get_cpu(env)->apic_state);
 431         break;
 432     case MSR_EFER:
 433         val = env->efer;
 434         break;
 435     case MSR_STAR:
 436         val = env->star;
 437         break;
 438     case MSR_PAT:
 439         val = env->pat;
 440         break;
 441     case MSR_VM_HSAVE_PA:
 442         val = env->vm_hsave;
 443         break;
 444     case MSR_IA32_PERF_STATUS:
 445         /* tsc_increment_by_tick */
 446         val = 1000ULL;
 447         /* CPU multiplier */
 448         val |= (((uint64_t)4ULL) << 40);
 449         break;
 450 #ifdef TARGET_X86_64
 451     case MSR_LSTAR:
 452         val = env->lstar;
 453         break;
 454     case MSR_CSTAR:
 455         val = env->cstar;
 456         break;
 457     case MSR_FMASK:
 458         val = env->fmask;
 459         break;
 460     case MSR_FSBASE:
 461         val = env->segs[R_FS].base;
 462         break;
 463     case MSR_GSBASE:
 464         val = env->segs[R_GS].base;
 465         break;
 466     case MSR_KERNELGSBASE:
 467         val = env->kernelgsbase;
 468         break;
 469     case MSR_TSC_AUX:
 470         val = env->tsc_aux;
 471         break;
 472 #endif
 473     case MSR_MTRRphysBase(0):
 474     case MSR_MTRRphysBase(1):
 475     case MSR_MTRRphysBase(2):
 476     case MSR_MTRRphysBase(3):
 477     case MSR_MTRRphysBase(4):
 478     case MSR_MTRRphysBase(5):
 479     case MSR_MTRRphysBase(6):
 480     case MSR_MTRRphysBase(7):
 481         val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
 482                              MSR_MTRRphysBase(0)) / 2].base;
 483         break;
 484     case MSR_MTRRphysMask(0):
 485     case MSR_MTRRphysMask(1):
 486     case MSR_MTRRphysMask(2):
 487     case MSR_MTRRphysMask(3):
 488     case MSR_MTRRphysMask(4):
 489     case MSR_MTRRphysMask(5):
 490     case MSR_MTRRphysMask(6):
 491     case MSR_MTRRphysMask(7):
 492         val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
 493                              MSR_MTRRphysMask(0)) / 2].mask;
 494         break;
 495     case MSR_MTRRfix64K_00000:
 496         val = env->mtrr_fixed[0];
 497         break;
 498     case MSR_MTRRfix16K_80000:
 499     case MSR_MTRRfix16K_A0000:
 500         val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
 501                               MSR_MTRRfix16K_80000 + 1];
 502         break;
 503     case MSR_MTRRfix4K_C0000:
 504     case MSR_MTRRfix4K_C8000:
 505     case MSR_MTRRfix4K_D0000:
 506     case MSR_MTRRfix4K_D8000:
 507     case MSR_MTRRfix4K_E0000:
 508     case MSR_MTRRfix4K_E8000:
 509     case MSR_MTRRfix4K_F0000:
 510     case MSR_MTRRfix4K_F8000:
 511         val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
 512                               MSR_MTRRfix4K_C0000 + 3];
 513         break;
 514     case MSR_MTRRdefType:
 515         val = env->mtrr_deftype;
 516         break;
 517     case MSR_MTRRcap:
 518         if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
 519             val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT |
 520                 MSR_MTRRcap_WC_SUPPORTED;
 521         } else {
 522             /* XXX: exception? */
 523             val = 0;
 524         }
 525         break;
 526     case MSR_MCG_CAP:
 527         val = env->mcg_cap;
 528         break;
 529     case MSR_MCG_CTL:
 530         if (env->mcg_cap & MCG_CTL_P) {
 531             val = env->mcg_ctl;
 532         } else {
 533             val = 0;
 534         }
 535         break;
 536     case MSR_MCG_STATUS:
 537         val = env->mcg_status;
 538         break;
 539     case MSR_IA32_MISC_ENABLE:
 540         val = env->msr_ia32_misc_enable;
 541         break;
 542     default:
 543         if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
 544             && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
 545             (4 * env->mcg_cap & 0xff)) {
 546             uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
 547             val = env->mce_banks[offset];
 548             break;
 549         }
 550         /* XXX: exception? */
 551         val = 0;
 552         break;
 553     }
 554     env->regs[R_EAX] = (uint32_t)(val);
 555     env->regs[R_EDX] = (uint32_t)(val >> 32);
 556 }
 557 #endif
 558
 559 static void do_pause(X86CPU *cpu)
 560 {
 561     CPUState *cs = CPU(cpu);
 562
 563     /* Just let another CPU run.  */
 564     cs->exception_index = EXCP_INTERRUPT;
 565     cpu_loop_exit(cs);
 566 }
 567
 568 static void do_hlt(X86CPU *cpu)
 569 {
 570     CPUState *cs = CPU(cpu);
 571     CPUX86State *env = &cpu->env;
 572
 573     env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
 574     cs->halted = 1;
 575     cs->exception_index = EXCP_HLT;
 576     cpu_loop_exit(cs);
 577 }
 578
 579 void helper_hlt(CPUX86State *env, int next_eip_addend)
 580 {
 581     X86CPU *cpu = x86_env_get_cpu(env);
 582
 583     cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0);
 584     env->eip += next_eip_addend;
 585
 586     do_hlt(cpu);
 587 }
 588
 589 void helper_monitor(CPUX86State *env, target_ulong ptr)
 590 {
 591     if ((uint32_t)env->regs[R_ECX] != 0) {
 592         raise_exception_ra(env, EXCP0D_GPF, GETPC());
 593     }
 594     /* XXX: store address? */
 595     cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0);
 596 }
 597
 598 void helper_mwait(CPUX86State *env, int next_eip_addend)
 599 {
 600     CPUState *cs;
 601     X86CPU *cpu;
 602
 603     if ((uint32_t)env->regs[R_ECX] != 0) {
 604         raise_exception_ra(env, EXCP0D_GPF, GETPC());
 605     }
 606     cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0);
 607     env->eip += next_eip_addend;
 608
 609     cpu = x86_env_get_cpu(env);
 610     cs = CPU(cpu);
 611     /* XXX: not complete but not completely erroneous */
 612     if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) {
 613         do_pause(cpu);
 614     } else {
 615         do_hlt(cpu);
 616     }
 617 }
 618
 619 void helper_pause(CPUX86State *env, int next_eip_addend)
 620 {
 621     X86CPU *cpu = x86_env_get_cpu(env);
 622
 623     cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0);
 624     env->eip += next_eip_addend;
 625
 626     do_pause(cpu);
 627 }
 628
 629 void helper_debug(CPUX86State *env)
 630 {
 631     CPUState *cs = CPU(x86_env_get_cpu(env));
 632
 633     cs->exception_index = EXCP_DEBUG;
 634     cpu_loop_exit(cs);
 635 }