hw/dma/xilinx_axidma.c

   1 /*
   2  * QEMU model of Xilinx AXI-DMA block.
   3  *
   4  * Copyright (c) 2011 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/sysbus.h"
  27 #include "qapi/error.h"
  28 #include "qemu/timer.h"
  29 #include "hw/hw.h"
  30 #include "hw/irq.h"
  31 #include "hw/ptimer.h"
  32 #include "hw/qdev-properties.h"
  33 #include "qemu/log.h"
  34 #include "qemu/module.h"
  35
  36 #include "sysemu/dma.h"
  37 #include "hw/stream.h"
  38
  39 #define D(x)
  40
  41 #define TYPE_XILINX_AXI_DMA "xlnx.axi-dma"
  42 #define TYPE_XILINX_AXI_DMA_DATA_STREAM "xilinx-axi-dma-data-stream"
  43 #define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream"
  44
  45 #define XILINX_AXI_DMA(obj) \
  46      OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)
  47
  48 #define XILINX_AXI_DMA_DATA_STREAM(obj) \
  49      OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
  50      TYPE_XILINX_AXI_DMA_DATA_STREAM)
  51
  52 #define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
  53      OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
  54      TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
  55
  56 #define R_DMACR             (0x00 / 4)
  57 #define R_DMASR             (0x04 / 4)
  58 #define R_CURDESC           (0x08 / 4)
  59 #define R_TAILDESC          (0x10 / 4)
  60 #define R_MAX               (0x30 / 4)
  61
  62 #define CONTROL_PAYLOAD_WORDS 5
  63 #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
  64
  65 typedef struct XilinxAXIDMA XilinxAXIDMA;
  66 typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
  67
  68 enum {
  69     DMACR_RUNSTOP = 1,
  70     DMACR_TAILPTR_MODE = 2,
  71     DMACR_RESET = 4
  72 };
  73
  74 enum {
  75     DMASR_HALTED = 1,
  76     DMASR_IDLE  = 2,
  77     DMASR_IOC_IRQ  = 1 << 12,
  78     DMASR_DLY_IRQ  = 1 << 13,
  79
  80     DMASR_IRQ_MASK = 7 << 12
  81 };
  82
  83 struct SDesc {
  84     uint64_t nxtdesc;
  85     uint64_t buffer_address;
  86     uint64_t reserved;
  87     uint32_t control;
  88     uint32_t status;
  89     uint8_t app[CONTROL_PAYLOAD_SIZE];
  90 };
  91
  92 enum {
  93     SDESC_CTRL_EOF = (1 << 26),
  94     SDESC_CTRL_SOF = (1 << 27),
  95
  96     SDESC_CTRL_LEN_MASK = (1 << 23) - 1
  97 };
  98
  99 enum {
 100     SDESC_STATUS_EOF = (1 << 26),
 101     SDESC_STATUS_SOF_BIT = 27,
 102     SDESC_STATUS_SOF = (1 << SDESC_STATUS_SOF_BIT),
 103     SDESC_STATUS_COMPLETE = (1 << 31)
 104 };
 105
 106 struct Stream {
 107     struct XilinxAXIDMA *dma;
 108     ptimer_state *ptimer;
 109     qemu_irq irq;
 110
 111     int nr;
 112
 113     struct SDesc desc;
 114     unsigned int complete_cnt;
 115     uint32_t regs[R_MAX];
 116     uint8_t app[20];
 117     unsigned char txbuf[16 * 1024];
 118 };
 119
 120 struct XilinxAXIDMAStreamSlave {
 121     Object parent;
 122
 123     struct XilinxAXIDMA *dma;
 124 };
 125
 126 struct XilinxAXIDMA {
 127     SysBusDevice busdev;
 128     MemoryRegion iomem;
 129     MemoryRegion *dma_mr;
 130     AddressSpace as;
 131
 132     uint32_t freqhz;
 133     StreamSlave *tx_data_dev;
 134     StreamSlave *tx_control_dev;
 135     XilinxAXIDMAStreamSlave rx_data_dev;
 136     XilinxAXIDMAStreamSlave rx_control_dev;
 137
 138     struct Stream streams[2];
 139
 140     StreamCanPushNotifyFn notify;
 141     void *notify_opaque;
 142 };
 143
 144 /*
 145  * Helper calls to extract info from descriptors and other trivial
 146  * state from regs.
 147  */
 148 static inline int stream_desc_sof(struct SDesc *d)
 149 {
 150     return d->control & SDESC_CTRL_SOF;
 151 }
 152
 153 static inline int stream_desc_eof(struct SDesc *d)
 154 {
 155     return d->control & SDESC_CTRL_EOF;
 156 }
 157
 158 static inline int stream_resetting(struct Stream *s)
 159 {
 160     return !!(s->regs[R_DMACR] & DMACR_RESET);
 161 }
 162
 163 static inline int stream_running(struct Stream *s)
 164 {
 165     return s->regs[R_DMACR] & DMACR_RUNSTOP;
 166 }
 167
 168 static inline int stream_idle(struct Stream *s)
 169 {
 170     return !!(s->regs[R_DMASR] & DMASR_IDLE);
 171 }
 172
 173 static void stream_reset(struct Stream *s)
 174 {
 175     s->regs[R_DMASR] = DMASR_HALTED;  /* starts up halted.  */
 176     s->regs[R_DMACR] = 1 << 16; /* Starts with one in compl threshold.  */
 177 }
 178
 179 /* Map an offset addr into a channel index.  */
 180 static inline int streamid_from_addr(hwaddr addr)
 181 {
 182     int sid;
 183
 184     sid = addr / (0x30);
 185     sid &= 1;
 186     return sid;
 187 }
 188
 189 static void stream_desc_load(struct Stream *s, hwaddr addr)
 190 {
 191     struct SDesc *d = &s->desc;
 192
 193     address_space_read(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED, d, sizeof *d);
 194
 195     /* Convert from LE into host endianness.  */
 196     d->buffer_address = le64_to_cpu(d->buffer_address);
 197     d->nxtdesc = le64_to_cpu(d->nxtdesc);
 198     d->control = le32_to_cpu(d->control);
 199     d->status = le32_to_cpu(d->status);
 200 }
 201
 202 static void stream_desc_store(struct Stream *s, hwaddr addr)
 203 {
 204     struct SDesc *d = &s->desc;
 205
 206     /* Convert from host endianness into LE.  */
 207     d->buffer_address = cpu_to_le64(d->buffer_address);
 208     d->nxtdesc = cpu_to_le64(d->nxtdesc);
 209     d->control = cpu_to_le32(d->control);
 210     d->status = cpu_to_le32(d->status);
 211     address_space_write(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED,
 212                         d, sizeof *d);
 213 }
 214
 215 static void stream_update_irq(struct Stream *s)
 216 {
 217     unsigned int pending, mask, irq;
 218
 219     pending = s->regs[R_DMASR] & DMASR_IRQ_MASK;
 220     mask = s->regs[R_DMACR] & DMASR_IRQ_MASK;
 221
 222     irq = pending & mask;
 223
 224     qemu_set_irq(s->irq, !!irq);
 225 }
 226
 227 static void stream_reload_complete_cnt(struct Stream *s)
 228 {
 229     unsigned int comp_th;
 230     comp_th = (s->regs[R_DMACR] >> 16) & 0xff;
 231     s->complete_cnt = comp_th;
 232 }
 233
 234 static void timer_hit(void *opaque)
 235 {
 236     struct Stream *s = opaque;
 237
 238     stream_reload_complete_cnt(s);
 239     s->regs[R_DMASR] |= DMASR_DLY_IRQ;
 240     stream_update_irq(s);
 241 }
 242
 243 static void stream_complete(struct Stream *s)
 244 {
 245     unsigned int comp_delay;
 246
 247     /* Start the delayed timer.  */
 248     ptimer_transaction_begin(s->ptimer);
 249     comp_delay = s->regs[R_DMACR] >> 24;
 250     if (comp_delay) {
 251         ptimer_stop(s->ptimer);
 252         ptimer_set_count(s->ptimer, comp_delay);
 253         ptimer_run(s->ptimer, 1);
 254     }
 255
 256     s->complete_cnt--;
 257     if (s->complete_cnt == 0) {
 258         /* Raise the IOC irq.  */
 259         s->regs[R_DMASR] |= DMASR_IOC_IRQ;
 260         stream_reload_complete_cnt(s);
 261     }
 262     ptimer_transaction_commit(s->ptimer);
 263 }
 264
 265 static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev,
 266                                  StreamSlave *tx_control_dev)
 267 {
 268     uint32_t prev_d;
 269     uint32_t txlen;
 270     uint64_t addr;
 271     bool eop;
 272
 273     if (!stream_running(s) || stream_idle(s)) {
 274         return;
 275     }
 276
 277     while (1) {
 278         stream_desc_load(s, s->regs[R_CURDESC]);
 279
 280         if (s->desc.status & SDESC_STATUS_COMPLETE) {
 281             s->regs[R_DMASR] |= DMASR_HALTED;
 282             break;
 283         }
 284
 285         if (stream_desc_sof(&s->desc)) {
 286             stream_push(tx_control_dev, s->desc.app, sizeof(s->desc.app), true);
 287         }
 288
 289         txlen = s->desc.control & SDESC_CTRL_LEN_MASK;
 290
 291         eop = stream_desc_eof(&s->desc);
 292         addr = s->desc.buffer_address;
 293         while (txlen) {
 294             unsigned int len;
 295
 296             len = txlen > sizeof s->txbuf ? sizeof s->txbuf : txlen;
 297             address_space_read(&s->dma->as, addr,
 298                                MEMTXATTRS_UNSPECIFIED,
 299                                s->txbuf, len);
 300             stream_push(tx_data_dev, s->txbuf, len, eop && len == txlen);
 301             txlen -= len;
 302             addr += len;
 303         }
 304
 305         if (eop) {
 306             stream_complete(s);
 307         }
 308
 309         /* Update the descriptor.  */
 310         s->desc.status = txlen | SDESC_STATUS_COMPLETE;
 311         stream_desc_store(s, s->regs[R_CURDESC]);
 312
 313         /* Advance.  */
 314         prev_d = s->regs[R_CURDESC];
 315         s->regs[R_CURDESC] = s->desc.nxtdesc;
 316         if (prev_d == s->regs[R_TAILDESC]) {
 317             s->regs[R_DMASR] |= DMASR_IDLE;
 318             break;
 319         }
 320     }
 321 }
 322
 323 static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf,
 324                                    size_t len)
 325 {
 326     uint32_t prev_d;
 327     unsigned int rxlen;
 328     size_t pos = 0;
 329     int sof = 1;
 330
 331     if (!stream_running(s) || stream_idle(s)) {
 332         return 0;
 333     }
 334
 335     while (len) {
 336         stream_desc_load(s, s->regs[R_CURDESC]);
 337
 338         if (s->desc.status & SDESC_STATUS_COMPLETE) {
 339             s->regs[R_DMASR] |= DMASR_HALTED;
 340             break;
 341         }
 342
 343         rxlen = s->desc.control & SDESC_CTRL_LEN_MASK;
 344         if (rxlen > len) {
 345             /* It fits.  */
 346             rxlen = len;
 347         }
 348
 349         address_space_write(&s->dma->as, s->desc.buffer_address,
 350                             MEMTXATTRS_UNSPECIFIED, buf + pos, rxlen);
 351         len -= rxlen;
 352         pos += rxlen;
 353
 354         /* Update the descriptor.  */
 355         if (!len) {
 356             stream_complete(s);
 357             memcpy(s->desc.app, s->app, sizeof(s->desc.app));
 358             s->desc.status |= SDESC_STATUS_EOF;
 359         }
 360
 361         s->desc.status |= sof << SDESC_STATUS_SOF_BIT;
 362         s->desc.status |= SDESC_STATUS_COMPLETE;
 363         stream_desc_store(s, s->regs[R_CURDESC]);
 364         sof = 0;
 365
 366         /* Advance.  */
 367         prev_d = s->regs[R_CURDESC];
 368         s->regs[R_CURDESC] = s->desc.nxtdesc;
 369         if (prev_d == s->regs[R_TAILDESC]) {
 370             s->regs[R_DMASR] |= DMASR_IDLE;
 371             break;
 372         }
 373     }
 374
 375     return pos;
 376 }
 377
 378 static void xilinx_axidma_reset(DeviceState *dev)
 379 {
 380     int i;
 381     XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
 382
 383     for (i = 0; i < 2; i++) {
 384         stream_reset(&s->streams[i]);
 385     }
 386 }
 387
 388 static size_t
 389 xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf,
 390                                   size_t len, bool eop)
 391 {
 392     XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
 393     struct Stream *s = &cs->dma->streams[1];
 394
 395     if (len != CONTROL_PAYLOAD_SIZE) {
 396         hw_error("AXI DMA requires %d byte control stream payload\n",
 397                  (int)CONTROL_PAYLOAD_SIZE);
 398     }
 399
 400     memcpy(s->app, buf, len);
 401     return len;
 402 }
 403
 404 static bool
 405 xilinx_axidma_data_stream_can_push(StreamSlave *obj,
 406                                    StreamCanPushNotifyFn notify,
 407                                    void *notify_opaque)
 408 {
 409     XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
 410     struct Stream *s = &ds->dma->streams[1];
 411
 412     if (!stream_running(s) || stream_idle(s)) {
 413         ds->dma->notify = notify;
 414         ds->dma->notify_opaque = notify_opaque;
 415         return false;
 416     }
 417
 418     return true;
 419 }
 420
 421 static size_t
 422 xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len,
 423                                bool eop)
 424 {
 425     XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
 426     struct Stream *s = &ds->dma->streams[1];
 427     size_t ret;
 428
 429     assert(eop);
 430     ret = stream_process_s2mem(s, buf, len);
 431     stream_update_irq(s);
 432     return ret;
 433 }
 434
 435 static uint64_t axidma_read(void *opaque, hwaddr addr,
 436                             unsigned size)
 437 {
 438     XilinxAXIDMA *d = opaque;
 439     struct Stream *s;
 440     uint32_t r = 0;
 441     int sid;
 442
 443     sid = streamid_from_addr(addr);
 444     s = &d->streams[sid];
 445
 446     addr = addr % 0x30;
 447     addr >>= 2;
 448     switch (addr) {
 449         case R_DMACR:
 450             /* Simulate one cycles reset delay.  */
 451             s->regs[addr] &= ~DMACR_RESET;
 452             r = s->regs[addr];
 453             break;
 454         case R_DMASR:
 455             s->regs[addr] &= 0xffff;
 456             s->regs[addr] |= (s->complete_cnt & 0xff) << 16;
 457             s->regs[addr] |= (ptimer_get_count(s->ptimer) & 0xff) << 24;
 458             r = s->regs[addr];
 459             break;
 460         default:
 461             r = s->regs[addr];
 462             D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n",
 463                            __func__, sid, addr * 4, r));
 464             break;
 465     }
 466     return r;
 467
 468 }
 469
 470 static void axidma_write(void *opaque, hwaddr addr,
 471                          uint64_t value, unsigned size)
 472 {
 473     XilinxAXIDMA *d = opaque;
 474     struct Stream *s;
 475     int sid;
 476
 477     sid = streamid_from_addr(addr);
 478     s = &d->streams[sid];
 479
 480     addr = addr % 0x30;
 481     addr >>= 2;
 482     switch (addr) {
 483         case R_DMACR:
 484             /* Tailptr mode is always on.  */
 485             value |= DMACR_TAILPTR_MODE;
 486             /* Remember our previous reset state.  */
 487             value |= (s->regs[addr] & DMACR_RESET);
 488             s->regs[addr] = value;
 489
 490             if (value & DMACR_RESET) {
 491                 stream_reset(s);
 492             }
 493
 494             if ((value & 1) && !stream_resetting(s)) {
 495                 /* Start processing.  */
 496                 s->regs[R_DMASR] &= ~(DMASR_HALTED | DMASR_IDLE);
 497             }
 498             stream_reload_complete_cnt(s);
 499             break;
 500
 501         case R_DMASR:
 502             /* Mask away write to clear irq lines.  */
 503             value &= ~(value & DMASR_IRQ_MASK);
 504             s->regs[addr] = value;
 505             break;
 506
 507         case R_TAILDESC:
 508             s->regs[addr] = value;
 509             s->regs[R_DMASR] &= ~DMASR_IDLE; /* Not idle.  */
 510             if (!sid) {
 511                 stream_process_mem2s(s, d->tx_data_dev, d->tx_control_dev);
 512             }
 513             break;
 514         default:
 515             D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n",
 516                   __func__, sid, addr * 4, (unsigned)value));
 517             s->regs[addr] = value;
 518             break;
 519     }
 520     if (sid == 1 && d->notify) {
 521         StreamCanPushNotifyFn notifytmp = d->notify;
 522         d->notify = NULL;
 523         notifytmp(d->notify_opaque);
 524     }
 525     stream_update_irq(s);
 526 }
 527
 528 static const MemoryRegionOps axidma_ops = {
 529     .read = axidma_read,
 530     .write = axidma_write,
 531     .endianness = DEVICE_NATIVE_ENDIAN,
 532 };
 533
 534 static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
 535 {
 536     XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
 537     XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
 538     XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
 539                                                             &s->rx_control_dev);
 540     Error *local_err = NULL;
 541     int i;
 542
 543     object_property_add_link(OBJECT(ds), "dma", TYPE_XILINX_AXI_DMA,
 544                              (Object **)&ds->dma,
 545                              object_property_allow_set_link,
 546                              OBJ_PROP_LINK_STRONG,
 547                              &local_err);
 548     object_property_add_link(OBJECT(cs), "dma", TYPE_XILINX_AXI_DMA,
 549                              (Object **)&cs->dma,
 550                              object_property_allow_set_link,
 551                              OBJ_PROP_LINK_STRONG,
 552                              &local_err);
 553     if (local_err) {
 554         goto xilinx_axidma_realize_fail;
 555     }
 556     object_property_set_link(OBJECT(ds), OBJECT(s), "dma", &local_err);
 557     object_property_set_link(OBJECT(cs), OBJECT(s), "dma", &local_err);
 558     if (local_err) {
 559         goto xilinx_axidma_realize_fail;
 560     }
 561
 562     for (i = 0; i < 2; i++) {
 563         struct Stream *st = &s->streams[i];
 564
 565         st->dma = s;
 566         st->nr = i;
 567         st->ptimer = ptimer_init(timer_hit, st, PTIMER_POLICY_DEFAULT);
 568         ptimer_transaction_begin(st->ptimer);
 569         ptimer_set_freq(st->ptimer, s->freqhz);
 570         ptimer_transaction_commit(st->ptimer);
 571     }
 572
 573     address_space_init(&s->as,
 574                        s->dma_mr ? s->dma_mr : get_system_memory(), "dma");
 575     return;
 576
 577 xilinx_axidma_realize_fail:
 578     error_propagate(errp, local_err);
 579 }
 580
 581 static void xilinx_axidma_init(Object *obj)
 582 {
 583     XilinxAXIDMA *s = XILINX_AXI_DMA(obj);
 584     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 585
 586     object_initialize_child(OBJECT(s), "axistream-connected-target",
 587                             &s->rx_data_dev, sizeof(s->rx_data_dev),
 588                             TYPE_XILINX_AXI_DMA_DATA_STREAM, &error_abort,
 589                             NULL);
 590     object_initialize_child(OBJECT(s), "axistream-control-connected-target",
 591                             &s->rx_control_dev, sizeof(s->rx_control_dev),
 592                             TYPE_XILINX_AXI_DMA_CONTROL_STREAM, &error_abort,
 593                             NULL);
 594     object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
 595                              (Object **)&s->dma_mr,
 596                              qdev_prop_allow_set_link_before_realize,
 597                              OBJ_PROP_LINK_STRONG,
 598                              &error_abort);
 599
 600     sysbus_init_irq(sbd, &s->streams[0].irq);
 601     sysbus_init_irq(sbd, &s->streams[1].irq);
 602
 603     memory_region_init_io(&s->iomem, obj, &axidma_ops, s,
 604                           "xlnx.axi-dma", R_MAX * 4 * 2);
 605     sysbus_init_mmio(sbd, &s->iomem);
 606 }
 607
 608 static Property axidma_properties[] = {
 609     DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
 610     DEFINE_PROP_LINK("axistream-connected", XilinxAXIDMA,
 611                      tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *),
 612     DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIDMA,
 613                      tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *),
 614     DEFINE_PROP_END_OF_LIST(),
 615 };
 616
 617 static void axidma_class_init(ObjectClass *klass, void *data)
 618 {
 619     DeviceClass *dc = DEVICE_CLASS(klass);
 620
 621     dc->realize = xilinx_axidma_realize,
 622     dc->reset = xilinx_axidma_reset;
 623     device_class_set_props(dc, axidma_properties);
 624 }
 625
 626 static StreamSlaveClass xilinx_axidma_data_stream_class = {
 627     .push = xilinx_axidma_data_stream_push,
 628     .can_push = xilinx_axidma_data_stream_can_push,
 629 };
 630
 631 static StreamSlaveClass xilinx_axidma_control_stream_class = {
 632     .push = xilinx_axidma_control_stream_push,
 633 };
 634
 635 static void xilinx_axidma_stream_class_init(ObjectClass *klass, void *data)
 636 {
 637     StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
 638
 639     ssc->push = ((StreamSlaveClass *)data)->push;
 640     ssc->can_push = ((StreamSlaveClass *)data)->can_push;
 641 }
 642
 643 static const TypeInfo axidma_info = {
 644     .name          = TYPE_XILINX_AXI_DMA,
 645     .parent        = TYPE_SYS_BUS_DEVICE,
 646     .instance_size = sizeof(XilinxAXIDMA),
 647     .class_init    = axidma_class_init,
 648     .instance_init = xilinx_axidma_init,
 649 };
 650
 651 static const TypeInfo xilinx_axidma_data_stream_info = {
 652     .name          = TYPE_XILINX_AXI_DMA_DATA_STREAM,
 653     .parent        = TYPE_OBJECT,
 654     .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
 655     .class_init    = xilinx_axidma_stream_class_init,
 656     .class_data    = &xilinx_axidma_data_stream_class,
 657     .interfaces = (InterfaceInfo[]) {
 658         { TYPE_STREAM_SLAVE },
 659         { }
 660     }
 661 };
 662
 663 static const TypeInfo xilinx_axidma_control_stream_info = {
 664     .name          = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
 665     .parent        = TYPE_OBJECT,
 666     .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
 667     .class_init    = xilinx_axidma_stream_class_init,
 668     .class_data    = &xilinx_axidma_control_stream_class,
 669     .interfaces = (InterfaceInfo[]) {
 670         { TYPE_STREAM_SLAVE },
 671         { }
 672     }
 673 };
 674
 675 static void xilinx_axidma_register_types(void)
 676 {
 677     type_register_static(&axidma_info);
 678     type_register_static(&xilinx_axidma_data_stream_info);
 679     type_register_static(&xilinx_axidma_control_stream_info);
 680 }
 681
 682 type_init(xilinx_axidma_register_types)