hw/rtc/m48t59-isa.c

   1 /*
   2  * QEMU M48T59 and M48T08 NVRAM emulation (ISA bus interface)
   3  *
   4  * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
   5  * Copyright (c) 2013 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/isa/isa.h"
  28 #include "hw/qdev-properties.h"
  29 #include "hw/rtc/m48t59.h"
  30 #include "m48t59-internal.h"
  31 #include "qapi/error.h"
  32 #include "qemu/module.h"
  33 #include "qom/object.h"
  34
  35 #define TYPE_M48TXX_ISA "isa-m48txx"
  36 typedef struct M48txxISADeviceClass M48txxISADeviceClass;
  37 typedef struct M48txxISAState M48txxISAState;
  38 DECLARE_OBJ_CHECKERS(M48txxISAState, M48txxISADeviceClass,
  39                      M48TXX_ISA, TYPE_M48TXX_ISA)
  40
  41 struct M48txxISAState {
  42     ISADevice parent_obj;
  43     M48t59State state;
  44     uint32_t io_base;
  45     MemoryRegion io;
  46 };
  47
  48 struct M48txxISADeviceClass {
  49     ISADeviceClass parent_class;
  50     M48txxInfo info;
  51 };
  52
  53 static M48txxInfo m48txx_isa_info[] = {
  54     {
  55         .bus_name = "isa-m48t59",
  56         .model = 59,
  57         .size = 0x2000,
  58     }
  59 };
  60
  61 Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
  62                        int base_year, int model)
  63 {
  64     ISADevice *isa_dev;
  65     DeviceState *dev;
  66     int i;
  67
  68     for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) {
  69         if (m48txx_isa_info[i].size != size ||
  70             m48txx_isa_info[i].model != model) {
  71             continue;
  72         }
  73
  74         isa_dev = isa_new(m48txx_isa_info[i].bus_name);
  75         dev = DEVICE(isa_dev);
  76         qdev_prop_set_uint32(dev, "iobase", io_base);
  77         qdev_prop_set_int32(dev, "base-year", base_year);
  78         isa_realize_and_unref(isa_dev, bus, &error_fatal);
  79         return NVRAM(dev);
  80     }
  81
  82     assert(false);
  83     return NULL;
  84 }
  85
  86 static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
  87 {
  88     M48txxISAState *d = M48TXX_ISA(obj);
  89     return m48t59_read(&d->state, addr);
  90 }
  91
  92 static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val)
  93 {
  94     M48txxISAState *d = M48TXX_ISA(obj);
  95     m48t59_write(&d->state, addr, val);
  96 }
  97
  98 static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
  99 {
 100     M48txxISAState *d = M48TXX_ISA(obj);
 101     m48t59_toggle_lock(&d->state, lock);
 102 }
 103
 104 static Property m48t59_isa_properties[] = {
 105     DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0),
 106     DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
 107     DEFINE_PROP_END_OF_LIST(),
 108 };
 109
 110 static void m48t59_reset_isa(DeviceState *d)
 111 {
 112     M48txxISAState *isa = M48TXX_ISA(d);
 113     M48t59State *NVRAM = &isa->state;
 114
 115     m48t59_reset_common(NVRAM);
 116 }
 117
 118 static void m48t59_isa_realize(DeviceState *dev, Error **errp)
 119 {
 120     M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
 121     ISADevice *isadev = ISA_DEVICE(dev);
 122     M48txxISAState *d = M48TXX_ISA(dev);
 123     M48t59State *s = &d->state;
 124
 125     s->model = u->info.model;
 126     s->size = u->info.size;
 127     isa_init_irq(isadev, &s->IRQ, 8);
 128     m48t59_realize_common(s, errp);
 129     memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
 130     if (d->io_base != 0) {
 131         isa_register_ioport(isadev, &d->io, d->io_base);
 132     }
 133 }
 134
 135 static void m48txx_isa_class_init(ObjectClass *klass, void *data)
 136 {
 137     DeviceClass *dc = DEVICE_CLASS(klass);
 138     NvramClass *nc = NVRAM_CLASS(klass);
 139
 140     dc->realize = m48t59_isa_realize;
 141     dc->reset = m48t59_reset_isa;
 142     device_class_set_props(dc, m48t59_isa_properties);
 143     nc->read = m48txx_isa_read;
 144     nc->write = m48txx_isa_write;
 145     nc->toggle_lock = m48txx_isa_toggle_lock;
 146 }
 147
 148 static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
 149 {
 150     M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
 151     M48txxInfo *info = data;
 152
 153     u->info = *info;
 154 }
 155
 156 static const TypeInfo m48txx_isa_type_info = {
 157     .name = TYPE_M48TXX_ISA,
 158     .parent = TYPE_ISA_DEVICE,
 159     .instance_size = sizeof(M48txxISAState),
 160     .abstract = true,
 161     .class_init = m48txx_isa_class_init,
 162     .interfaces = (InterfaceInfo[]) {
 163         { TYPE_NVRAM },
 164         { }
 165     }
 166 };
 167
 168 static void m48t59_isa_register_types(void)
 169 {
 170     TypeInfo isa_type_info = {
 171         .parent = TYPE_M48TXX_ISA,
 172         .class_size = sizeof(M48txxISADeviceClass),
 173         .class_init = m48txx_isa_concrete_class_init,
 174     };
 175     int i;
 176
 177     type_register_static(&m48txx_isa_type_info);
 178
 179     for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) {
 180         isa_type_info.name = m48txx_isa_info[i].bus_name;
 181         isa_type_info.class_data = &m48txx_isa_info[i];
 182         type_register(&isa_type_info);
 183     }
 184 }
 185
 186 type_init(m48t59_isa_register_types)