target-microblaze/op_helper.c

   1 /*
   2  *  Microblaze helper routines.
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
   5  *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "exec/helper-proto.h"
  23 #include "qemu/host-utils.h"
  24 #include "exec/cpu_ldst.h"
  25
  26 #define D(x)
  27
  28 #if !defined(CONFIG_USER_ONLY)
  29
  30 /* Try to fill the TLB and return an exception if error. If retaddr is
  31  * NULL, it means that the function was called in C code (i.e. not
  32  * from generated code or from helper.c)
  33  */
  34 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
  35               uintptr_t retaddr)
  36 {
  37     int ret;
  38
  39     ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
  40     if (unlikely(ret)) {
  41         if (retaddr) {
  42             /* now we have a real cpu fault */
  43             cpu_restore_state(cs, retaddr);
  44         }
  45         cpu_loop_exit(cs);
  46     }
  47 }
  48 #endif
  49
  50 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
  51 {
  52     int test = ctrl & STREAM_TEST;
  53     int atomic = ctrl & STREAM_ATOMIC;
  54     int control = ctrl & STREAM_CONTROL;
  55     int nonblock = ctrl & STREAM_NONBLOCK;
  56     int exception = ctrl & STREAM_EXCEPTION;
  57
  58     qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
  59              id, data,
  60              test ? "t" : "",
  61              nonblock ? "n" : "",
  62              exception ? "e" : "",
  63              control ? "c" : "",
  64              atomic ? "a" : "");
  65 }
  66
  67 uint32_t helper_get(uint32_t id, uint32_t ctrl)
  68 {
  69     int test = ctrl & STREAM_TEST;
  70     int atomic = ctrl & STREAM_ATOMIC;
  71     int control = ctrl & STREAM_CONTROL;
  72     int nonblock = ctrl & STREAM_NONBLOCK;
  73     int exception = ctrl & STREAM_EXCEPTION;
  74
  75     qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
  76              id,
  77              test ? "t" : "",
  78              nonblock ? "n" : "",
  79              exception ? "e" : "",
  80              control ? "c" : "",
  81              atomic ? "a" : "");
  82     return 0xdead0000 | id;
  83 }
  84
  85 void helper_raise_exception(CPUMBState *env, uint32_t index)
  86 {
  87     CPUState *cs = CPU(mb_env_get_cpu(env));
  88
  89     cs->exception_index = index;
  90     cpu_loop_exit(cs);
  91 }
  92
  93 void helper_debug(CPUMBState *env)
  94 {
  95     int i;
  96
  97     qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
  98     qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
  99              env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
 100              env->debug, env->imm, env->iflags);
 101     qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
 102              env->btaken, env->btarget,
 103              (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
 104              (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
 105              (env->sregs[SR_MSR] & MSR_EIP),
 106              (env->sregs[SR_MSR] & MSR_IE));
 107     for (i = 0; i < 32; i++) {
 108         qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
 109         if ((i + 1) % 4 == 0)
 110             qemu_log("\n");
 111     }
 112     qemu_log("\n\n");
 113 }
 114
 115 static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
 116 {
 117     uint32_t cout = 0;
 118
 119     if ((b == ~0) && cin)
 120         cout = 1;
 121     else if ((~0 - a) < (b + cin))
 122         cout = 1;
 123     return cout;
 124 }
 125
 126 uint32_t helper_cmp(uint32_t a, uint32_t b)
 127 {
 128     uint32_t t;
 129
 130     t = b + ~a + 1;
 131     if ((b & 0x80000000) ^ (a & 0x80000000))
 132         t = (t & 0x7fffffff) | (b & 0x80000000);
 133     return t;
 134 }
 135
 136 uint32_t helper_cmpu(uint32_t a, uint32_t b)
 137 {
 138     uint32_t t;
 139
 140     t = b + ~a + 1;
 141     if ((b & 0x80000000) ^ (a & 0x80000000))
 142         t = (t & 0x7fffffff) | (a & 0x80000000);
 143     return t;
 144 }
 145
 146 uint32_t helper_clz(uint32_t t0)
 147 {
 148     return clz32(t0);
 149 }
 150
 151 uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
 152 {
 153     uint32_t ncf;
 154     ncf = compute_carry(a, b, cf);
 155     return ncf;
 156 }
 157
 158 static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
 159 {
 160     if (b == 0) {
 161         env->sregs[SR_MSR] |= MSR_DZ;
 162
 163         if ((env->sregs[SR_MSR] & MSR_EE)
 164             && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
 165             env->sregs[SR_ESR] = ESR_EC_DIVZERO;
 166             helper_raise_exception(env, EXCP_HW_EXCP);
 167         }
 168         return 0;
 169     }
 170     env->sregs[SR_MSR] &= ~MSR_DZ;
 171     return 1;
 172 }
 173
 174 uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
 175 {
 176     if (!div_prepare(env, a, b)) {
 177         return 0;
 178     }
 179     return (int32_t)a / (int32_t)b;
 180 }
 181
 182 uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
 183 {
 184     if (!div_prepare(env, a, b)) {
 185         return 0;
 186     }
 187     return a / b;
 188 }
 189
 190 /* raise FPU exception.  */
 191 static void raise_fpu_exception(CPUMBState *env)
 192 {
 193     env->sregs[SR_ESR] = ESR_EC_FPU;
 194     helper_raise_exception(env, EXCP_HW_EXCP);
 195 }
 196
 197 static void update_fpu_flags(CPUMBState *env, int flags)
 198 {
 199     int raise = 0;
 200
 201     if (flags & float_flag_invalid) {
 202         env->sregs[SR_FSR] |= FSR_IO;
 203         raise = 1;
 204     }
 205     if (flags & float_flag_divbyzero) {
 206         env->sregs[SR_FSR] |= FSR_DZ;
 207         raise = 1;
 208     }
 209     if (flags & float_flag_overflow) {
 210         env->sregs[SR_FSR] |= FSR_OF;
 211         raise = 1;
 212     }
 213     if (flags & float_flag_underflow) {
 214         env->sregs[SR_FSR] |= FSR_UF;
 215         raise = 1;
 216     }
 217     if (raise
 218         && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
 219         && (env->sregs[SR_MSR] & MSR_EE)) {
 220         raise_fpu_exception(env);
 221     }
 222 }
 223
 224 uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
 225 {
 226     CPU_FloatU fd, fa, fb;
 227     int flags;
 228
 229     set_float_exception_flags(0, &env->fp_status);
 230     fa.l = a;
 231     fb.l = b;
 232     fd.f = float32_add(fa.f, fb.f, &env->fp_status);
 233
 234     flags = get_float_exception_flags(&env->fp_status);
 235     update_fpu_flags(env, flags);
 236     return fd.l;
 237 }
 238
 239 uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
 240 {
 241     CPU_FloatU fd, fa, fb;
 242     int flags;
 243
 244     set_float_exception_flags(0, &env->fp_status);
 245     fa.l = a;
 246     fb.l = b;
 247     fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
 248     flags = get_float_exception_flags(&env->fp_status);
 249     update_fpu_flags(env, flags);
 250     return fd.l;
 251 }
 252
 253 uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
 254 {
 255     CPU_FloatU fd, fa, fb;
 256     int flags;
 257
 258     set_float_exception_flags(0, &env->fp_status);
 259     fa.l = a;
 260     fb.l = b;
 261     fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
 262     flags = get_float_exception_flags(&env->fp_status);
 263     update_fpu_flags(env, flags);
 264
 265     return fd.l;
 266 }
 267
 268 uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
 269 {
 270     CPU_FloatU fd, fa, fb;
 271     int flags;
 272
 273     set_float_exception_flags(0, &env->fp_status);
 274     fa.l = a;
 275     fb.l = b;
 276     fd.f = float32_div(fb.f, fa.f, &env->fp_status);
 277     flags = get_float_exception_flags(&env->fp_status);
 278     update_fpu_flags(env, flags);
 279
 280     return fd.l;
 281 }
 282
 283 uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
 284 {
 285     CPU_FloatU fa, fb;
 286     uint32_t r = 0;
 287
 288     fa.l = a;
 289     fb.l = b;
 290
 291     if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
 292         update_fpu_flags(env, float_flag_invalid);
 293         r = 1;
 294     }
 295
 296     if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
 297         r = 1;
 298     }
 299
 300     return r;
 301 }
 302
 303 uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
 304 {
 305     CPU_FloatU fa, fb;
 306     int r;
 307     int flags;
 308
 309     set_float_exception_flags(0, &env->fp_status);
 310     fa.l = a;
 311     fb.l = b;
 312     r = float32_lt(fb.f, fa.f, &env->fp_status);
 313     flags = get_float_exception_flags(&env->fp_status);
 314     update_fpu_flags(env, flags & float_flag_invalid);
 315
 316     return r;
 317 }
 318
 319 uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
 320 {
 321     CPU_FloatU fa, fb;
 322     int flags;
 323     int r;
 324
 325     set_float_exception_flags(0, &env->fp_status);
 326     fa.l = a;
 327     fb.l = b;
 328     r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
 329     flags = get_float_exception_flags(&env->fp_status);
 330     update_fpu_flags(env, flags & float_flag_invalid);
 331
 332     return r;
 333 }
 334
 335 uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
 336 {
 337     CPU_FloatU fa, fb;
 338     int flags;
 339     int r;
 340
 341     fa.l = a;
 342     fb.l = b;
 343     set_float_exception_flags(0, &env->fp_status);
 344     r = float32_le(fa.f, fb.f, &env->fp_status);
 345     flags = get_float_exception_flags(&env->fp_status);
 346     update_fpu_flags(env, flags & float_flag_invalid);
 347
 348
 349     return r;
 350 }
 351
 352 uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
 353 {
 354     CPU_FloatU fa, fb;
 355     int flags, r;
 356
 357     fa.l = a;
 358     fb.l = b;
 359     set_float_exception_flags(0, &env->fp_status);
 360     r = float32_lt(fa.f, fb.f, &env->fp_status);
 361     flags = get_float_exception_flags(&env->fp_status);
 362     update_fpu_flags(env, flags & float_flag_invalid);
 363     return r;
 364 }
 365
 366 uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
 367 {
 368     CPU_FloatU fa, fb;
 369     int flags, r;
 370
 371     fa.l = a;
 372     fb.l = b;
 373     set_float_exception_flags(0, &env->fp_status);
 374     r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
 375     flags = get_float_exception_flags(&env->fp_status);
 376     update_fpu_flags(env, flags & float_flag_invalid);
 377
 378     return r;
 379 }
 380
 381 uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
 382 {
 383     CPU_FloatU fa, fb;
 384     int flags, r;
 385
 386     fa.l = a;
 387     fb.l = b;
 388     set_float_exception_flags(0, &env->fp_status);
 389     r = !float32_lt(fa.f, fb.f, &env->fp_status);
 390     flags = get_float_exception_flags(&env->fp_status);
 391     update_fpu_flags(env, flags & float_flag_invalid);
 392
 393     return r;
 394 }
 395
 396 uint32_t helper_flt(CPUMBState *env, uint32_t a)
 397 {
 398     CPU_FloatU fd, fa;
 399
 400     fa.l = a;
 401     fd.f = int32_to_float32(fa.l, &env->fp_status);
 402     return fd.l;
 403 }
 404
 405 uint32_t helper_fint(CPUMBState *env, uint32_t a)
 406 {
 407     CPU_FloatU fa;
 408     uint32_t r;
 409     int flags;
 410
 411     set_float_exception_flags(0, &env->fp_status);
 412     fa.l = a;
 413     r = float32_to_int32(fa.f, &env->fp_status);
 414     flags = get_float_exception_flags(&env->fp_status);
 415     update_fpu_flags(env, flags);
 416
 417     return r;
 418 }
 419
 420 uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
 421 {
 422     CPU_FloatU fd, fa;
 423     int flags;
 424
 425     set_float_exception_flags(0, &env->fp_status);
 426     fa.l = a;
 427     fd.l = float32_sqrt(fa.f, &env->fp_status);
 428     flags = get_float_exception_flags(&env->fp_status);
 429     update_fpu_flags(env, flags);
 430
 431     return fd.l;
 432 }
 433
 434 uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
 435 {
 436     unsigned int i;
 437     uint32_t mask = 0xff000000;
 438
 439     for (i = 0; i < 4; i++) {
 440         if ((a & mask) == (b & mask))
 441             return i + 1;
 442         mask >>= 8;
 443     }
 444     return 0;
 445 }
 446
 447 void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
 448                      uint32_t mask)
 449 {
 450     if (addr & mask) {
 451             qemu_log_mask(CPU_LOG_INT,
 452                           "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
 453                           addr, mask, wr, dr);
 454             env->sregs[SR_EAR] = addr;
 455             env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
 456                                  | (dr & 31) << 5;
 457             if (mask == 3) {
 458                 env->sregs[SR_ESR] |= 1 << 11;
 459             }
 460             if (!(env->sregs[SR_MSR] & MSR_EE)) {
 461                 return;
 462             }
 463             helper_raise_exception(env, EXCP_HW_EXCP);
 464     }
 465 }
 466
 467 void helper_stackprot(CPUMBState *env, uint32_t addr)
 468 {
 469     if (addr < env->slr || addr > env->shr) {
 470         qemu_log("Stack protector violation at %x %x %x\n",
 471                  addr, env->slr, env->shr);
 472         env->sregs[SR_EAR] = addr;
 473         env->sregs[SR_ESR] = ESR_EC_STACKPROT;
 474         helper_raise_exception(env, EXCP_HW_EXCP);
 475     }
 476 }
 477
 478 #if !defined(CONFIG_USER_ONLY)
 479 /* Writes/reads to the MMU's special regs end up here.  */
 480 uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
 481 {
 482     return mmu_read(env, rn);
 483 }
 484
 485 void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
 486 {
 487     mmu_write(env, rn, v);
 488 }
 489
 490 void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
 491                               bool is_write, bool is_exec, int is_asi,
 492                               unsigned size)
 493 {
 494     MicroBlazeCPU *cpu;
 495     CPUMBState *env;
 496
 497     qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
 498              addr, is_write ? 1 : 0, is_exec ? 1 : 0);
 499     if (cs == NULL) {
 500         return;
 501     }
 502     cpu = MICROBLAZE_CPU(cs);
 503     env = &cpu->env;
 504     if (!(env->sregs[SR_MSR] & MSR_EE)) {
 505         return;
 506     }
 507
 508     env->sregs[SR_EAR] = addr;
 509     if (is_exec) {
 510         if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
 511             env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
 512             helper_raise_exception(env, EXCP_HW_EXCP);
 513         }
 514     } else {
 515         if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
 516             env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
 517             helper_raise_exception(env, EXCP_HW_EXCP);
 518         }
 519     }
 520 }
 521 #endif