hw/pci/pci_bridge.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to dea
   8
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM
  22
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 /*
  27  * split out from pci.c
  28  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
  29  *                    VA Linux Systems Japan K.K.
  30  */
  31
  32 #include "hw/pci/pci_bridge.h"
  33 #include "hw/pci/pci_bus.h"
  34 #include "qemu/range.h"
  35
  36 /* PCI bridge subsystem vendor ID helper functions */
  37 #define PCI_SSVID_SIZEOF        8
  38 #define PCI_SSVID_SVID          4
  39 #define PCI_SSVID_SSID          6
  40
  41 int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
  42                           uint16_t svid, uint16_t ssid)
  43 {
  44     int pos;
  45     pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SIZEOF);
  46     if (pos < 0) {
  47         return pos;
  48     }
  49
  50     pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid);
  51     pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid);
  52     return pos;
  53 }
  54
  55 /* Accessor function to get parent bridge device from pci bus. */
  56 PCIDevice *pci_bridge_get_device(PCIBus *bus)
  57 {
  58     return bus->parent_dev;
  59 }
  60
  61 /* Accessor function to get secondary bus from pci-to-pci bridge device */
  62 PCIBus *pci_bridge_get_sec_bus(PCIBridge *br)
  63 {
  64     return &br->sec_bus;
  65 }
  66
  67 static uint32_t pci_config_get_io_base(const PCIDevice *d,
  68                                        uint32_t base, uint32_t base_upper16)
  69 {
  70     uint32_t val;
  71
  72     val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
  73     if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
  74         val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
  75     }
  76     return val;
  77 }
  78
  79 static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base)
  80 {
  81     return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
  82         << 16;
  83 }
  84
  85 static pcibus_t pci_config_get_pref_base(const PCIDevice *d,
  86                                          uint32_t base, uint32_t upper)
  87 {
  88     pcibus_t tmp;
  89     pcibus_t val;
  90
  91     tmp = (pcibus_t)pci_get_word(d->config + base);
  92     val = (tmp & PCI_PREF_RANGE_MASK) << 16;
  93     if (tmp & PCI_PREF_RANGE_TYPE_64) {
  94         val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
  95     }
  96     return val;
  97 }
  98
  99 /* accessor function to get bridge filtering base address */
 100 pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type)
 101 {
 102     pcibus_t base;
 103     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 104         base = pci_config_get_io_base(bridge,
 105                                       PCI_IO_BASE, PCI_IO_BASE_UPPER16);
 106     } else {
 107         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 108             base = pci_config_get_pref_base(
 109                 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
 110         } else {
 111             base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
 112         }
 113     }
 114
 115     return base;
 116 }
 117
 118 /* accessor funciton to get bridge filtering limit */
 119 pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type)
 120 {
 121     pcibus_t limit;
 122     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 123         limit = pci_config_get_io_base(bridge,
 124                                       PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
 125         limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */
 126     } else {
 127         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 128             limit = pci_config_get_pref_base(
 129                 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
 130         } else {
 131             limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
 132         }
 133         limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */
 134     }
 135     return limit;
 136 }
 137
 138 static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias,
 139                                   uint8_t type, const char *name,
 140                                   MemoryRegion *space,
 141                                   MemoryRegion *parent_space,
 142                                   bool enabled)
 143 {
 144     PCIDevice *bridge_dev = PCI_DEVICE(bridge);
 145     pcibus_t base = pci_bridge_get_base(bridge_dev, type);
 146     pcibus_t limit = pci_bridge_get_limit(bridge_dev, type);
 147     /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly.
 148      * Apparently no way to do this with existing memory APIs. */
 149     pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0;
 150
 151     memory_region_init_alias(alias, OBJECT(bridge), name, space, base, size);
 152     memory_region_add_subregion_overlap(parent_space, base, alias, 1);
 153 }
 154
 155 static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent,
 156                                         MemoryRegion *alias_vga)
 157 {
 158     PCIDevice *pd = PCI_DEVICE(br);
 159     uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL);
 160
 161     memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br),
 162                              "pci_bridge_vga_io_lo", &br->address_space_io,
 163                              QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE);
 164     memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], OBJECT(br),
 165                              "pci_bridge_vga_io_hi", &br->address_space_io,
 166                              QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE);
 167     memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], OBJECT(br),
 168                              "pci_bridge_vga_mem", &br->address_space_mem,
 169                              QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE);
 170
 171     if (brctl & PCI_BRIDGE_CTL_VGA) {
 172         pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM],
 173                          &alias_vga[QEMU_PCI_VGA_IO_LO],
 174                          &alias_vga[QEMU_PCI_VGA_IO_HI]);
 175     }
 176 }
 177
 178 static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br)
 179 {
 180     PCIDevice *pd = PCI_DEVICE(br);
 181     PCIBus *parent = pd->bus;
 182     PCIBridgeWindows *w = g_new(PCIBridgeWindows, 1);
 183     uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND);
 184
 185     pci_bridge_init_alias(br, &w->alias_pref_mem,
 186                           PCI_BASE_ADDRESS_MEM_PREFETCH,
 187                           "pci_bridge_pref_mem",
 188                           &br->address_space_mem,
 189                           parent->address_space_mem,
 190                           cmd & PCI_COMMAND_MEMORY);
 191     pci_bridge_init_alias(br, &w->alias_mem,
 192                           PCI_BASE_ADDRESS_SPACE_MEMORY,
 193                           "pci_bridge_mem",
 194                           &br->address_space_mem,
 195                           parent->address_space_mem,
 196                           cmd & PCI_COMMAND_MEMORY);
 197     pci_bridge_init_alias(br, &w->alias_io,
 198                           PCI_BASE_ADDRESS_SPACE_IO,
 199                           "pci_bridge_io",
 200                           &br->address_space_io,
 201                           parent->address_space_io,
 202                           cmd & PCI_COMMAND_IO);
 203
 204     pci_bridge_init_vga_aliases(br, parent, w->alias_vga);
 205
 206     return w;
 207 }
 208
 209 static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w)
 210 {
 211     PCIDevice *pd = PCI_DEVICE(br);
 212     PCIBus *parent = pd->bus;
 213
 214     memory_region_del_subregion(parent->address_space_io, &w->alias_io);
 215     memory_region_del_subregion(parent->address_space_mem, &w->alias_mem);
 216     memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem);
 217     pci_unregister_vga(pd);
 218 }
 219
 220 static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w)
 221 {
 222     g_free(w);
 223 }
 224
 225 void pci_bridge_update_mappings(PCIBridge *br)
 226 {
 227     PCIBridgeWindows *w = br->windows;
 228
 229     /* Make updates atomic to: handle the case of one VCPU updating the bridge
 230      * while another accesses an unaffected region. */
 231     memory_region_transaction_begin();
 232     pci_bridge_region_del(br, br->windows);
 233     br->windows = pci_bridge_region_init(br);
 234     memory_region_transaction_commit();
 235     pci_bridge_region_cleanup(br, w);
 236 }
 237
 238 /* default write_config function for PCI-to-PCI bridge */
 239 void pci_bridge_write_config(PCIDevice *d,
 240                              uint32_t address, uint32_t val, int len)
 241 {
 242     PCIBridge *s = PCI_BRIDGE(d);
 243     uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
 244     uint16_t newctl;
 245
 246     pci_default_write_config(d, address, val, len);
 247
 248     if (ranges_overlap(address, len, PCI_COMMAND, 2) ||
 249
 250         /* io base/limit */
 251         ranges_overlap(address, len, PCI_IO_BASE, 2) ||
 252
 253         /* memory base/limit, prefetchable base/limit and
 254            io base/limit upper 16 */
 255         ranges_overlap(address, len, PCI_MEMORY_BASE, 20) ||
 256
 257         /* vga enable */
 258         ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) {
 259         pci_bridge_update_mappings(s);
 260     }
 261
 262     newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
 263     if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {
 264         /* Trigger hot reset on 0->1 transition. */
 265         qbus_reset_all(&s->sec_bus.qbus);
 266     }
 267 }
 268
 269 void pci_bridge_disable_base_limit(PCIDevice *dev)
 270 {
 271     uint8_t *conf = dev->config;
 272
 273     pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
 274                                PCI_IO_RANGE_MASK & 0xff);
 275     pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
 276                                  PCI_IO_RANGE_MASK & 0xff);
 277     pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE,
 278                                PCI_MEMORY_RANGE_MASK & 0xffff);
 279     pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
 280                                  PCI_MEMORY_RANGE_MASK & 0xffff);
 281     pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE,
 282                                PCI_PREF_RANGE_MASK & 0xffff);
 283     pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
 284                                  PCI_PREF_RANGE_MASK & 0xffff);
 285     pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
 286     pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
 287 }
 288
 289 /* reset bridge specific configuration registers */
 290 void pci_bridge_reset(DeviceState *qdev)
 291 {
 292     PCIDevice *dev = PCI_DEVICE(qdev);
 293     uint8_t *conf = dev->config;
 294
 295     conf[PCI_PRIMARY_BUS] = 0;
 296     conf[PCI_SECONDARY_BUS] = 0;
 297     conf[PCI_SUBORDINATE_BUS] = 0;
 298     conf[PCI_SEC_LATENCY_TIMER] = 0;
 299
 300     /*
 301      * the default values for base/limit registers aren't specified
 302      * in the PCI-to-PCI-bridge spec. So we don't thouch them here.
 303      * Each implementation can override it.
 304      * typical implementation does
 305      * zero base/limit registers or
 306      * disable forwarding: pci_bridge_disable_base_limit()
 307      * If disable forwarding is wanted, call pci_bridge_disable_base_limit()
 308      * after this function.
 309      */
 310     pci_byte_test_and_clear_mask(conf + PCI_IO_BASE,
 311                                  PCI_IO_RANGE_MASK & 0xff);
 312     pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
 313                                  PCI_IO_RANGE_MASK & 0xff);
 314     pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE,
 315                                  PCI_MEMORY_RANGE_MASK & 0xffff);
 316     pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
 317                                  PCI_MEMORY_RANGE_MASK & 0xffff);
 318     pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE,
 319                                  PCI_PREF_RANGE_MASK & 0xffff);
 320     pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
 321                                  PCI_PREF_RANGE_MASK & 0xffff);
 322     pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
 323     pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
 324
 325     pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
 326 }
 327
 328 /* default qdev initialization function for PCI-to-PCI bridge */
 329 int pci_bridge_initfn(PCIDevice *dev, const char *typename)
 330 {
 331     PCIBus *parent = dev->bus;
 332     PCIBridge *br = PCI_BRIDGE(dev);
 333     PCIBus *sec_bus = &br->sec_bus;
 334
 335     pci_word_test_and_set_mask(dev->config + PCI_STATUS,
 336                                PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
 337
 338     /*
 339      * TODO: We implement VGA Enable in the Bridge Control Register
 340      * therefore per the PCI to PCI bridge spec we must also implement
 341      * VGA Palette Snooping.  When done, set this bit writable:
 342      *
 343      * pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND,
 344      *                            PCI_COMMAND_VGA_PALETTE);
 345      */
 346
 347     pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
 348     dev->config[PCI_HEADER_TYPE] =
 349         (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
 350         PCI_HEADER_TYPE_BRIDGE;
 351     pci_set_word(dev->config + PCI_SEC_STATUS,
 352                  PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
 353
 354     /*
 355      * If we don't specify the name, the bus will be addressed as <id>.0, where
 356      * id is the device id.
 357      * Since PCI Bridge devices have a single bus each, we don't need the index:
 358      * let users address the bus using the device name.
 359      */
 360     if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
 361             br->bus_name = dev->qdev.id;
 362     }
 363
 364     qbus_create_inplace(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
 365                         br->bus_name);
 366     sec_bus->parent_dev = dev;
 367     sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
 368     sec_bus->address_space_mem = &br->address_space_mem;
 369     memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX);
 370     sec_bus->address_space_io = &br->address_space_io;
 371     memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io", 65536);
 372     br->windows = pci_bridge_region_init(br);
 373     QLIST_INIT(&sec_bus->child);
 374     QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);
 375     return 0;
 376 }
 377
 378 /* default qdev clean up function for PCI-to-PCI bridge */
 379 void pci_bridge_exitfn(PCIDevice *pci_dev)
 380 {
 381     PCIBridge *s = PCI_BRIDGE(pci_dev);
 382     assert(QLIST_EMPTY(&s->sec_bus.child));
 383     QLIST_REMOVE(&s->sec_bus, sibling);
 384     pci_bridge_region_del(s, s->windows);
 385     pci_bridge_region_cleanup(s, s->windows);
 386     /* object_unparent() is called automatically during device deletion */
 387 }
 388
 389 /*
 390  * before qdev initialization(qdev_init()), this function sets bus_name and
 391  * map_irq callback which are necessry for pci_bridge_initfn() to
 392  * initialize bus.
 393  */
 394 void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
 395                         pci_map_irq_fn map_irq)
 396 {
 397     br->map_irq = map_irq;
 398     br->bus_name = bus_name;
 399 }
 400
 401 static const TypeInfo pci_bridge_type_info = {
 402     .name = TYPE_PCI_BRIDGE,
 403     .parent = TYPE_PCI_DEVICE,
 404     .instance_size = sizeof(PCIBridge),
 405     .abstract = true,
 406 };
 407
 408 static void pci_bridge_register_types(void)
 409 {
 410     type_register_static(&pci_bridge_type_info);
 411 }
 412
 413 type_init(pci_bridge_register_types)