2 * USB UHCI controller emulation
4 * Copyright (c) 2005 Fabrice Bellard
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "qemu-timer.h"
34 //#define DEBUG_DUMP_DATA
36 #define UHCI_CMD_FGR (1 << 4)
37 #define UHCI_CMD_EGSM (1 << 3)
38 #define UHCI_CMD_GRESET (1 << 2)
39 #define UHCI_CMD_HCRESET (1 << 1)
40 #define UHCI_CMD_RS (1 << 0)
42 #define UHCI_STS_HCHALTED (1 << 5)
43 #define UHCI_STS_HCPERR (1 << 4)
44 #define UHCI_STS_HSERR (1 << 3)
45 #define UHCI_STS_RD (1 << 2)
46 #define UHCI_STS_USBERR (1 << 1)
47 #define UHCI_STS_USBINT (1 << 0)
49 #define TD_CTRL_SPD (1 << 29)
50 #define TD_CTRL_ERROR_SHIFT 27
51 #define TD_CTRL_IOS (1 << 25)
52 #define TD_CTRL_IOC (1 << 24)
53 #define TD_CTRL_ACTIVE (1 << 23)
54 #define TD_CTRL_STALL (1 << 22)
55 #define TD_CTRL_BABBLE (1 << 20)
56 #define TD_CTRL_NAK (1 << 19)
57 #define TD_CTRL_TIMEOUT (1 << 18)
59 #define UHCI_PORT_RESET (1 << 9)
60 #define UHCI_PORT_LSDA (1 << 8)
61 #define UHCI_PORT_ENC (1 << 3)
62 #define UHCI_PORT_EN (1 << 2)
63 #define UHCI_PORT_CSC (1 << 1)
64 #define UHCI_PORT_CCS (1 << 0)
66 #define FRAME_TIMER_FREQ 1000
68 #define FRAME_MAX_LOOPS 100
73 #define dprintf printf
75 static const char *pid2str(int pid
)
78 case USB_TOKEN_SETUP
: return "SETUP";
79 case USB_TOKEN_IN
: return "IN";
80 case USB_TOKEN_OUT
: return "OUT";
89 #ifdef DEBUG_DUMP_DATA
90 static void dump_data(const uint8_t *data
, int len
)
94 printf("uhci: data: ");
95 for(i
= 0; i
< len
; i
++)
96 printf(" %02x", data
[i
]);
100 static void dump_data(const uint8_t *data
, int len
) {}
104 * Pending async transaction.
105 * 'packet' must be the first field because completion
106 * handler does "(UHCIAsync *) pkt" cast.
108 typedef struct UHCIAsync
{
110 struct UHCIAsync
*next
;
115 uint8_t buffer
[2048];
118 typedef struct UHCIPort
{
123 typedef struct UHCIState
{
126 uint16_t cmd
; /* cmd register */
128 uint16_t intr
; /* interrupt enable register */
129 uint16_t frnum
; /* frame number */
130 uint32_t fl_base_addr
; /* frame list base address */
132 uint8_t status2
; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
133 QEMUTimer
*frame_timer
;
134 UHCIPort ports
[NB_PORTS
];
136 /* Interrupts that should be raised at the end of the current frame. */
137 uint32_t pending_int_mask
;
140 UHCIAsync
*async_pending
;
141 UHCIAsync
*async_pool
;
142 uint8_t num_ports_vmstate
;
145 typedef struct UHCI_TD
{
147 uint32_t ctrl
; /* see TD_CTRL_xxx */
152 typedef struct UHCI_QH
{
157 static UHCIAsync
*uhci_async_alloc(UHCIState
*s
)
159 UHCIAsync
*async
= qemu_malloc(sizeof(UHCIAsync
));
161 memset(&async
->packet
, 0, sizeof(async
->packet
));
171 static void uhci_async_free(UHCIState
*s
, UHCIAsync
*async
)
176 static void uhci_async_link(UHCIState
*s
, UHCIAsync
*async
)
178 async
->next
= s
->async_pending
;
179 s
->async_pending
= async
;
182 static void uhci_async_unlink(UHCIState
*s
, UHCIAsync
*async
)
184 UHCIAsync
*curr
= s
->async_pending
;
185 UHCIAsync
**prev
= &s
->async_pending
;
198 static void uhci_async_cancel(UHCIState
*s
, UHCIAsync
*async
)
200 dprintf("uhci: cancel td 0x%x token 0x%x done %u\n",
201 async
->td
, async
->token
, async
->done
);
204 usb_cancel_packet(&async
->packet
);
205 uhci_async_free(s
, async
);
209 * Mark all outstanding async packets as invalid.
210 * This is used for canceling them when TDs are removed by the HCD.
212 static UHCIAsync
*uhci_async_validate_begin(UHCIState
*s
)
214 UHCIAsync
*async
= s
->async_pending
;
224 * Cancel async packets that are no longer valid
226 static void uhci_async_validate_end(UHCIState
*s
)
228 UHCIAsync
*curr
= s
->async_pending
;
229 UHCIAsync
**prev
= &s
->async_pending
;
233 if (curr
->valid
> 0) {
244 uhci_async_cancel(s
, curr
);
250 static void uhci_async_cancel_all(UHCIState
*s
)
252 UHCIAsync
*curr
= s
->async_pending
;
258 uhci_async_cancel(s
, curr
);
263 s
->async_pending
= NULL
;
266 static UHCIAsync
*uhci_async_find_td(UHCIState
*s
, uint32_t addr
, uint32_t token
)
268 UHCIAsync
*async
= s
->async_pending
;
269 UHCIAsync
*match
= NULL
;
273 * We're looking for the best match here. ie both td addr and token.
274 * Otherwise we return last good match. ie just token.
275 * It's ok to match just token because it identifies the transaction
276 * rather well, token includes: device addr, endpoint, size, etc.
278 * Also since we queue async transactions in reverse order by returning
279 * last good match we restores the order.
281 * It's expected that we wont have a ton of outstanding transactions.
282 * If we ever do we'd want to optimize this algorithm.
286 if (async
->token
== token
) {
290 if (async
->td
== addr
) {
301 fprintf(stderr
, "uhci: warning lots of async transactions\n");
306 static void uhci_attach(USBPort
*port1
, USBDevice
*dev
);
308 static void uhci_update_irq(UHCIState
*s
)
311 if (((s
->status2
& 1) && (s
->intr
& (1 << 2))) ||
312 ((s
->status2
& 2) && (s
->intr
& (1 << 3))) ||
313 ((s
->status
& UHCI_STS_USBERR
) && (s
->intr
& (1 << 0))) ||
314 ((s
->status
& UHCI_STS_RD
) && (s
->intr
& (1 << 1))) ||
315 (s
->status
& UHCI_STS_HSERR
) ||
316 (s
->status
& UHCI_STS_HCPERR
)) {
321 qemu_set_irq(s
->dev
.irq
[3], level
);
324 static void uhci_reset(void *opaque
)
326 UHCIState
*s
= opaque
;
331 dprintf("uhci: full reset\n");
333 pci_conf
= s
->dev
.config
;
335 pci_conf
[0x6a] = 0x01; /* usb clock */
336 pci_conf
[0x6b] = 0x00;
344 for(i
= 0; i
< NB_PORTS
; i
++) {
348 uhci_attach(&port
->port
, port
->port
.dev
);
351 uhci_async_cancel_all(s
);
354 static void uhci_pre_save(void *opaque
)
356 UHCIState
*s
= opaque
;
358 uhci_async_cancel_all(s
);
361 static const VMStateDescription vmstate_uhci_port
= {
364 .minimum_version_id
= 1,
365 .minimum_version_id_old
= 1,
366 .fields
= (VMStateField
[]) {
367 VMSTATE_UINT16(ctrl
, UHCIPort
),
368 VMSTATE_END_OF_LIST()
372 static const VMStateDescription vmstate_uhci
= {
375 .minimum_version_id
= 1,
376 .minimum_version_id_old
= 1,
377 .pre_save
= uhci_pre_save
,
378 .fields
= (VMStateField
[]) {
379 VMSTATE_PCI_DEVICE(dev
, UHCIState
),
380 VMSTATE_UINT8_EQUAL(num_ports_vmstate
, UHCIState
),
381 VMSTATE_STRUCT_ARRAY(ports
, UHCIState
, NB_PORTS
, 1,
382 vmstate_uhci_port
, UHCIPort
),
383 VMSTATE_UINT16(cmd
, UHCIState
),
384 VMSTATE_UINT16(status
, UHCIState
),
385 VMSTATE_UINT16(intr
, UHCIState
),
386 VMSTATE_UINT16(frnum
, UHCIState
),
387 VMSTATE_UINT32(fl_base_addr
, UHCIState
),
388 VMSTATE_UINT8(sof_timing
, UHCIState
),
389 VMSTATE_UINT8(status2
, UHCIState
),
390 VMSTATE_TIMER(frame_timer
, UHCIState
),
391 VMSTATE_END_OF_LIST()
395 static void uhci_ioport_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
397 UHCIState
*s
= opaque
;
407 static uint32_t uhci_ioport_readb(void *opaque
, uint32_t addr
)
409 UHCIState
*s
= opaque
;
424 static void uhci_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
426 UHCIState
*s
= opaque
;
429 dprintf("uhci: writew port=0x%04x val=0x%04x\n", addr
, val
);
433 if ((val
& UHCI_CMD_RS
) && !(s
->cmd
& UHCI_CMD_RS
)) {
434 /* start frame processing */
435 qemu_mod_timer(s
->frame_timer
, qemu_get_clock(vm_clock
));
436 s
->status
&= ~UHCI_STS_HCHALTED
;
437 } else if (!(val
& UHCI_CMD_RS
)) {
438 s
->status
|= UHCI_STS_HCHALTED
;
440 if (val
& UHCI_CMD_GRESET
) {
445 /* send reset on the USB bus */
446 for(i
= 0; i
< NB_PORTS
; i
++) {
448 dev
= port
->port
.dev
;
450 usb_send_msg(dev
, USB_MSG_RESET
);
456 if (val
& UHCI_CMD_HCRESET
) {
464 /* XXX: the chip spec is not coherent, so we add a hidden
465 register to distinguish between IOC and SPD */
466 if (val
& UHCI_STS_USBINT
)
475 if (s
->status
& UHCI_STS_HCHALTED
)
476 s
->frnum
= val
& 0x7ff;
488 dev
= port
->port
.dev
;
491 if ( (val
& UHCI_PORT_RESET
) &&
492 !(port
->ctrl
& UHCI_PORT_RESET
) ) {
493 usb_send_msg(dev
, USB_MSG_RESET
);
496 port
->ctrl
= (port
->ctrl
& 0x01fb) | (val
& ~0x01fb);
497 /* some bits are reset when a '1' is written to them */
498 port
->ctrl
&= ~(val
& 0x000a);
504 static uint32_t uhci_ioport_readw(void *opaque
, uint32_t addr
)
506 UHCIState
*s
= opaque
;
536 val
= 0xff7f; /* disabled port */
540 dprintf("uhci: readw port=0x%04x val=0x%04x\n", addr
, val
);
545 static void uhci_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
547 UHCIState
*s
= opaque
;
550 dprintf("uhci: writel port=0x%04x val=0x%08x\n", addr
, val
);
554 s
->fl_base_addr
= val
& ~0xfff;
559 static uint32_t uhci_ioport_readl(void *opaque
, uint32_t addr
)
561 UHCIState
*s
= opaque
;
567 val
= s
->fl_base_addr
;
576 /* signal resume if controller suspended */
577 static void uhci_resume (void *opaque
)
579 UHCIState
*s
= (UHCIState
*)opaque
;
584 if (s
->cmd
& UHCI_CMD_EGSM
) {
585 s
->cmd
|= UHCI_CMD_FGR
;
586 s
->status
|= UHCI_STS_RD
;
591 static void uhci_attach(USBPort
*port1
, USBDevice
*dev
)
593 UHCIState
*s
= port1
->opaque
;
594 UHCIPort
*port
= &s
->ports
[port1
->index
];
597 if (port
->port
.dev
) {
598 usb_attach(port1
, NULL
);
600 /* set connect status */
601 port
->ctrl
|= UHCI_PORT_CCS
| UHCI_PORT_CSC
;
604 if (dev
->speed
== USB_SPEED_LOW
)
605 port
->ctrl
|= UHCI_PORT_LSDA
;
607 port
->ctrl
&= ~UHCI_PORT_LSDA
;
611 port
->port
.dev
= dev
;
612 /* send the attach message */
613 usb_send_msg(dev
, USB_MSG_ATTACH
);
615 /* set connect status */
616 if (port
->ctrl
& UHCI_PORT_CCS
) {
617 port
->ctrl
&= ~UHCI_PORT_CCS
;
618 port
->ctrl
|= UHCI_PORT_CSC
;
621 if (port
->ctrl
& UHCI_PORT_EN
) {
622 port
->ctrl
&= ~UHCI_PORT_EN
;
623 port
->ctrl
|= UHCI_PORT_ENC
;
628 dev
= port
->port
.dev
;
630 /* send the detach message */
631 usb_send_msg(dev
, USB_MSG_DETACH
);
633 port
->port
.dev
= NULL
;
637 static int uhci_broadcast_packet(UHCIState
*s
, USBPacket
*p
)
641 dprintf("uhci: packet enter. pid %s addr 0x%02x ep %d len %d\n",
642 pid2str(p
->pid
), p
->devaddr
, p
->devep
, p
->len
);
643 if (p
->pid
== USB_TOKEN_OUT
|| p
->pid
== USB_TOKEN_SETUP
)
644 dump_data(p
->data
, p
->len
);
647 for (i
= 0; i
< NB_PORTS
&& ret
== USB_RET_NODEV
; i
++) {
648 UHCIPort
*port
= &s
->ports
[i
];
649 USBDevice
*dev
= port
->port
.dev
;
651 if (dev
&& (port
->ctrl
& UHCI_PORT_EN
))
652 ret
= dev
->info
->handle_packet(dev
, p
);
655 dprintf("uhci: packet exit. ret %d len %d\n", ret
, p
->len
);
656 if (p
->pid
== USB_TOKEN_IN
&& ret
> 0)
657 dump_data(p
->data
, ret
);
662 static void uhci_async_complete(USBPacket
* packet
, void *opaque
);
663 static void uhci_process_frame(UHCIState
*s
);
665 /* return -1 if fatal error (frame must be stopped)
667 1 if TD unsuccessful or inactive
669 static int uhci_complete_td(UHCIState
*s
, UHCI_TD
*td
, UHCIAsync
*async
, uint32_t *int_mask
)
671 int len
= 0, max_len
, err
, ret
;
674 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
675 pid
= td
->token
& 0xff;
677 ret
= async
->packet
.len
;
679 if (td
->ctrl
& TD_CTRL_IOC
)
682 if (td
->ctrl
& TD_CTRL_IOS
)
683 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
688 len
= async
->packet
.len
;
689 td
->ctrl
= (td
->ctrl
& ~0x7ff) | ((len
- 1) & 0x7ff);
691 /* The NAK bit may have been set by a previous frame, so clear it
692 here. The docs are somewhat unclear, but win2k relies on this
694 td
->ctrl
&= ~(TD_CTRL_ACTIVE
| TD_CTRL_NAK
);
696 if (pid
== USB_TOKEN_IN
) {
699 ret
= USB_RET_BABBLE
;
704 /* write the data back */
705 cpu_physical_memory_write(td
->buffer
, async
->buffer
, len
);
708 if ((td
->ctrl
& TD_CTRL_SPD
) && len
< max_len
) {
710 /* short packet: do not update QH */
711 dprintf("uhci: short packet. td 0x%x token 0x%x\n", async
->td
, async
->token
);
722 td
->ctrl
|= TD_CTRL_STALL
;
723 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
727 td
->ctrl
|= TD_CTRL_BABBLE
| TD_CTRL_STALL
;
728 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
729 /* frame interrupted */
733 td
->ctrl
|= TD_CTRL_NAK
;
734 if (pid
== USB_TOKEN_SETUP
)
743 /* Retry the TD if error count is not zero */
745 td
->ctrl
|= TD_CTRL_TIMEOUT
;
746 err
= (td
->ctrl
>> TD_CTRL_ERROR_SHIFT
) & 3;
750 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
751 s
->status
|= UHCI_STS_USBERR
;
755 td
->ctrl
= (td
->ctrl
& ~(3 << TD_CTRL_ERROR_SHIFT
)) |
756 (err
<< TD_CTRL_ERROR_SHIFT
);
760 static int uhci_handle_td(UHCIState
*s
, uint32_t addr
, UHCI_TD
*td
, uint32_t *int_mask
)
763 int len
= 0, max_len
;
767 if (!(td
->ctrl
& TD_CTRL_ACTIVE
))
770 async
= uhci_async_find_td(s
, addr
, td
->token
);
772 /* Already submitted */
778 uhci_async_unlink(s
, async
);
782 /* Allocate new packet */
783 async
= uhci_async_alloc(s
);
789 async
->token
= td
->token
;
791 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
792 pid
= td
->token
& 0xff;
794 async
->packet
.pid
= pid
;
795 async
->packet
.devaddr
= (td
->token
>> 8) & 0x7f;
796 async
->packet
.devep
= (td
->token
>> 15) & 0xf;
797 async
->packet
.data
= async
->buffer
;
798 async
->packet
.len
= max_len
;
799 async
->packet
.complete_cb
= uhci_async_complete
;
800 async
->packet
.complete_opaque
= s
;
804 case USB_TOKEN_SETUP
:
805 cpu_physical_memory_read(td
->buffer
, async
->buffer
, max_len
);
806 len
= uhci_broadcast_packet(s
, &async
->packet
);
812 len
= uhci_broadcast_packet(s
, &async
->packet
);
816 /* invalid pid : frame interrupted */
817 uhci_async_free(s
, async
);
818 s
->status
|= UHCI_STS_HCPERR
;
823 if (len
== USB_RET_ASYNC
) {
824 uhci_async_link(s
, async
);
828 async
->packet
.len
= len
;
831 len
= uhci_complete_td(s
, td
, async
, int_mask
);
832 uhci_async_free(s
, async
);
836 static void uhci_async_complete(USBPacket
*packet
, void *opaque
)
838 UHCIState
*s
= opaque
;
839 UHCIAsync
*async
= (UHCIAsync
*) packet
;
841 dprintf("uhci: async complete. td 0x%x token 0x%x\n", async
->td
, async
->token
);
845 uhci_process_frame(s
);
848 static int is_valid(uint32_t link
)
850 return (link
& 1) == 0;
853 static int is_qh(uint32_t link
)
855 return (link
& 2) != 0;
858 static int depth_first(uint32_t link
)
860 return (link
& 4) != 0;
863 /* QH DB used for detecting QH loops */
864 #define UHCI_MAX_QUEUES 128
866 uint32_t addr
[UHCI_MAX_QUEUES
];
870 static void qhdb_reset(QhDb
*db
)
875 /* Add QH to DB. Returns 1 if already present or DB is full. */
876 static int qhdb_insert(QhDb
*db
, uint32_t addr
)
879 for (i
= 0; i
< db
->count
; i
++)
880 if (db
->addr
[i
] == addr
)
883 if (db
->count
>= UHCI_MAX_QUEUES
)
886 db
->addr
[db
->count
++] = addr
;
890 static void uhci_process_frame(UHCIState
*s
)
892 uint32_t frame_addr
, link
, old_td_ctrl
, val
, int_mask
;
899 frame_addr
= s
->fl_base_addr
+ ((s
->frnum
& 0x3ff) << 2);
901 dprintf("uhci: processing frame %d addr 0x%x\n" , s
->frnum
, frame_addr
);
903 cpu_physical_memory_read(frame_addr
, (uint8_t *)&link
, 4);
911 for (cnt
= FRAME_MAX_LOOPS
; is_valid(link
) && cnt
; cnt
--) {
915 if (qhdb_insert(&qhdb
, link
)) {
917 * We're going in circles. Which is not a bug because
918 * HCD is allowed to do that as part of the BW management.
919 * In our case though it makes no sense to spin here. Sync transations
920 * are already done, and async completion handler will re-process
921 * the frame when something is ready.
923 dprintf("uhci: detected loop. qh 0x%x\n", link
);
927 cpu_physical_memory_read(link
& ~0xf, (uint8_t *) &qh
, sizeof(qh
));
928 le32_to_cpus(&qh
.link
);
929 le32_to_cpus(&qh
.el_link
);
931 dprintf("uhci: QH 0x%x load. link 0x%x elink 0x%x\n",
932 link
, qh
.link
, qh
.el_link
);
934 if (!is_valid(qh
.el_link
)) {
935 /* QH w/o elements */
939 /* QH with elements */
947 cpu_physical_memory_read(link
& ~0xf, (uint8_t *) &td
, sizeof(td
));
948 le32_to_cpus(&td
.link
);
949 le32_to_cpus(&td
.ctrl
);
950 le32_to_cpus(&td
.token
);
951 le32_to_cpus(&td
.buffer
);
953 dprintf("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
954 link
, td
.link
, td
.ctrl
, td
.token
, curr_qh
);
956 old_td_ctrl
= td
.ctrl
;
957 ret
= uhci_handle_td(s
, link
, &td
, &int_mask
);
958 if (old_td_ctrl
!= td
.ctrl
) {
959 /* update the status bits of the TD */
960 val
= cpu_to_le32(td
.ctrl
);
961 cpu_physical_memory_write((link
& ~0xf) + 4,
962 (const uint8_t *)&val
, sizeof(val
));
966 /* interrupted frame */
970 if (ret
== 2 || ret
== 1) {
971 dprintf("uhci: TD 0x%x %s. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
972 link
, ret
== 2 ? "pend" : "skip",
973 td
.link
, td
.ctrl
, td
.token
, curr_qh
);
975 link
= curr_qh
? qh
.link
: td
.link
;
981 dprintf("uhci: TD 0x%x done. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
982 link
, td
.link
, td
.ctrl
, td
.token
, curr_qh
);
987 /* update QH element link */
989 val
= cpu_to_le32(qh
.el_link
);
990 cpu_physical_memory_write((curr_qh
& ~0xf) + 4,
991 (const uint8_t *)&val
, sizeof(val
));
993 if (!depth_first(link
)) {
994 /* done with this QH */
996 dprintf("uhci: QH 0x%x done. link 0x%x elink 0x%x\n",
997 curr_qh
, qh
.link
, qh
.el_link
);
1004 /* go to the next entry */
1007 s
->pending_int_mask
= int_mask
;
1010 static void uhci_frame_timer(void *opaque
)
1012 UHCIState
*s
= opaque
;
1013 int64_t expire_time
;
1015 if (!(s
->cmd
& UHCI_CMD_RS
)) {
1017 qemu_del_timer(s
->frame_timer
);
1018 /* set hchalted bit in status - UHCI11D 2.1.2 */
1019 s
->status
|= UHCI_STS_HCHALTED
;
1021 dprintf("uhci: halted\n");
1025 /* Complete the previous frame */
1026 if (s
->pending_int_mask
) {
1027 s
->status2
|= s
->pending_int_mask
;
1028 s
->status
|= UHCI_STS_USBINT
;
1032 /* Start new frame */
1033 s
->frnum
= (s
->frnum
+ 1) & 0x7ff;
1035 dprintf("uhci: new frame #%u\n" , s
->frnum
);
1037 uhci_async_validate_begin(s
);
1039 uhci_process_frame(s
);
1041 uhci_async_validate_end(s
);
1043 /* prepare the timer for the next frame */
1044 expire_time
= qemu_get_clock(vm_clock
) +
1045 (get_ticks_per_sec() / FRAME_TIMER_FREQ
);
1046 qemu_mod_timer(s
->frame_timer
, expire_time
);
1049 static void uhci_map(PCIDevice
*pci_dev
, int region_num
,
1050 uint32_t addr
, uint32_t size
, int type
)
1052 UHCIState
*s
= (UHCIState
*)pci_dev
;
1054 register_ioport_write(addr
, 32, 2, uhci_ioport_writew
, s
);
1055 register_ioport_read(addr
, 32, 2, uhci_ioport_readw
, s
);
1056 register_ioport_write(addr
, 32, 4, uhci_ioport_writel
, s
);
1057 register_ioport_read(addr
, 32, 4, uhci_ioport_readl
, s
);
1058 register_ioport_write(addr
, 32, 1, uhci_ioport_writeb
, s
);
1059 register_ioport_read(addr
, 32, 1, uhci_ioport_readb
, s
);
1062 static int usb_uhci_common_initfn(UHCIState
*s
)
1064 uint8_t *pci_conf
= s
->dev
.config
;
1067 pci_conf
[0x08] = 0x01; // revision number
1068 pci_conf
[0x09] = 0x00;
1069 pci_config_set_class(pci_conf
, PCI_CLASS_SERIAL_USB
);
1070 pci_conf
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_NORMAL
; // header_type
1071 pci_conf
[0x3d] = 4; // interrupt pin 3
1072 pci_conf
[0x60] = 0x10; // release number
1074 usb_bus_new(&s
->bus
, &s
->dev
.qdev
);
1075 for(i
= 0; i
< NB_PORTS
; i
++) {
1076 usb_register_port(&s
->bus
, &s
->ports
[i
].port
, s
, i
, uhci_attach
);
1078 s
->frame_timer
= qemu_new_timer(vm_clock
, uhci_frame_timer
, s
);
1079 s
->num_ports_vmstate
= NB_PORTS
;
1081 qemu_register_reset(uhci_reset
, s
);
1084 /* Use region 4 for consistency with real hardware. BSD guests seem
1086 pci_register_bar(&s
->dev
, 4, 0x20,
1087 PCI_ADDRESS_SPACE_IO
, uhci_map
);
1089 vmstate_register(0, &vmstate_uhci
, s
);
1093 static int usb_uhci_piix3_initfn(PCIDevice
*dev
)
1095 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1096 uint8_t *pci_conf
= s
->dev
.config
;
1098 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_INTEL
);
1099 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82371SB_2
);
1100 return usb_uhci_common_initfn(s
);
1103 static int usb_uhci_piix4_initfn(PCIDevice
*dev
)
1105 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1106 uint8_t *pci_conf
= s
->dev
.config
;
1108 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_INTEL
);
1109 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82371AB_2
);
1110 return usb_uhci_common_initfn(s
);
1113 static PCIDeviceInfo uhci_info
[] = {
1115 .qdev
.name
= "PIIX3 USB-UHCI",
1116 .qdev
.size
= sizeof(UHCIState
),
1117 .init
= usb_uhci_piix3_initfn
,
1119 .qdev
.name
= "PIIX4 USB-UHCI",
1120 .qdev
.size
= sizeof(UHCIState
),
1121 .init
= usb_uhci_piix4_initfn
,
1127 static void uhci_register(void)
1129 pci_qdev_register_many(uhci_info
);
1131 device_init(uhci_register
);
1133 void usb_uhci_piix3_init(PCIBus
*bus
, int devfn
)
1135 pci_create_simple(bus
, devfn
, "PIIX3 USB-UHCI");
1138 void usb_uhci_piix4_init(PCIBus
*bus
, int devfn
)
1140 pci_create_simple(bus
, devfn
, "PIIX4 USB-UHCI");