target-ppc/machine.c

   1 #include "qemu/osdep.h"
   2 #include "hw/hw.h"
   3 #include "hw/boards.h"
   4 #include "sysemu/kvm.h"
   5 #include "helper_regs.h"
   6 #include "mmu-hash64.h"
   7
   8 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
   9 {
  10     PowerPCCPU *cpu = opaque;
  11     CPUPPCState *env = &cpu->env;
  12     unsigned int i, j;
  13     target_ulong sdr1;
  14     uint32_t fpscr;
  15     target_ulong xer;
  16
  17     for (i = 0; i < 32; i++)
  18         qemu_get_betls(f, &env->gpr[i]);
  19 #if !defined(TARGET_PPC64)
  20     for (i = 0; i < 32; i++)
  21         qemu_get_betls(f, &env->gprh[i]);
  22 #endif
  23     qemu_get_betls(f, &env->lr);
  24     qemu_get_betls(f, &env->ctr);
  25     for (i = 0; i < 8; i++)
  26         qemu_get_be32s(f, &env->crf[i]);
  27     qemu_get_betls(f, &xer);
  28     cpu_write_xer(env, xer);
  29     qemu_get_betls(f, &env->reserve_addr);
  30     qemu_get_betls(f, &env->msr);
  31     for (i = 0; i < 4; i++)
  32         qemu_get_betls(f, &env->tgpr[i]);
  33     for (i = 0; i < 32; i++) {
  34         union {
  35             float64 d;
  36             uint64_t l;
  37         } u;
  38         u.l = qemu_get_be64(f);
  39         env->fpr[i] = u.d;
  40     }
  41     qemu_get_be32s(f, &fpscr);
  42     env->fpscr = fpscr;
  43     qemu_get_sbe32s(f, &env->access_type);
  44 #if defined(TARGET_PPC64)
  45     qemu_get_betls(f, &env->spr[SPR_ASR]);
  46     qemu_get_sbe32s(f, &env->slb_nr);
  47 #endif
  48     qemu_get_betls(f, &sdr1);
  49     for (i = 0; i < 32; i++)
  50         qemu_get_betls(f, &env->sr[i]);
  51     for (i = 0; i < 2; i++)
  52         for (j = 0; j < 8; j++)
  53             qemu_get_betls(f, &env->DBAT[i][j]);
  54     for (i = 0; i < 2; i++)
  55         for (j = 0; j < 8; j++)
  56             qemu_get_betls(f, &env->IBAT[i][j]);
  57     qemu_get_sbe32s(f, &env->nb_tlb);
  58     qemu_get_sbe32s(f, &env->tlb_per_way);
  59     qemu_get_sbe32s(f, &env->nb_ways);
  60     qemu_get_sbe32s(f, &env->last_way);
  61     qemu_get_sbe32s(f, &env->id_tlbs);
  62     qemu_get_sbe32s(f, &env->nb_pids);
  63     if (env->tlb.tlb6) {
  64         // XXX assumes 6xx
  65         for (i = 0; i < env->nb_tlb; i++) {
  66             qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
  67             qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
  68             qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
  69         }
  70     }
  71     for (i = 0; i < 4; i++)
  72         qemu_get_betls(f, &env->pb[i]);
  73     for (i = 0; i < 1024; i++)
  74         qemu_get_betls(f, &env->spr[i]);
  75     if (!env->external_htab) {
  76         ppc_store_sdr1(env, sdr1);
  77     }
  78     qemu_get_be32s(f, &env->vscr);
  79     qemu_get_be64s(f, &env->spe_acc);
  80     qemu_get_be32s(f, &env->spe_fscr);
  81     qemu_get_betls(f, &env->msr_mask);
  82     qemu_get_be32s(f, &env->flags);
  83     qemu_get_sbe32s(f, &env->error_code);
  84     qemu_get_be32s(f, &env->pending_interrupts);
  85     qemu_get_be32s(f, &env->irq_input_state);
  86     for (i = 0; i < POWERPC_EXCP_NB; i++)
  87         qemu_get_betls(f, &env->excp_vectors[i]);
  88     qemu_get_betls(f, &env->excp_prefix);
  89     qemu_get_betls(f, &env->ivor_mask);
  90     qemu_get_betls(f, &env->ivpr_mask);
  91     qemu_get_betls(f, &env->hreset_vector);
  92     qemu_get_betls(f, &env->nip);
  93     qemu_get_betls(f, &env->hflags);
  94     qemu_get_betls(f, &env->hflags_nmsr);
  95     qemu_get_sbe32s(f, &env->mmu_idx);
  96     qemu_get_sbe32(f); /* Discard unused power_mode */
  97
  98     return 0;
  99 }
 100
 101 static int get_avr(QEMUFile *f, void *pv, size_t size)
 102 {
 103     ppc_avr_t *v = pv;
 104
 105     v->u64[0] = qemu_get_be64(f);
 106     v->u64[1] = qemu_get_be64(f);
 107
 108     return 0;
 109 }
 110
 111 static void put_avr(QEMUFile *f, void *pv, size_t size)
 112 {
 113     ppc_avr_t *v = pv;
 114
 115     qemu_put_be64(f, v->u64[0]);
 116     qemu_put_be64(f, v->u64[1]);
 117 }
 118
 119 static const VMStateInfo vmstate_info_avr = {
 120     .name = "avr",
 121     .get  = get_avr,
 122     .put  = put_avr,
 123 };
 124
 125 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
 126     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
 127
 128 #define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
 129     VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
 130
 131 static void cpu_pre_save(void *opaque)
 132 {
 133     PowerPCCPU *cpu = opaque;
 134     CPUPPCState *env = &cpu->env;
 135     int i;
 136
 137     env->spr[SPR_LR] = env->lr;
 138     env->spr[SPR_CTR] = env->ctr;
 139     env->spr[SPR_XER] = env->xer;
 140 #if defined(TARGET_PPC64)
 141     env->spr[SPR_CFAR] = env->cfar;
 142 #endif
 143     env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
 144
 145     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 146         env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
 147         env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
 148         env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
 149         env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
 150     }
 151     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 152         env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
 153         env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
 154         env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
 155         env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
 156     }
 157 }
 158
 159 static int cpu_post_load(void *opaque, int version_id)
 160 {
 161     PowerPCCPU *cpu = opaque;
 162     CPUPPCState *env = &cpu->env;
 163     int i;
 164     target_ulong msr;
 165
 166     /*
 167      * We always ignore the source PVR. The user or management
 168      * software has to take care of running QEMU in a compatible mode.
 169      */
 170     env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
 171     env->lr = env->spr[SPR_LR];
 172     env->ctr = env->spr[SPR_CTR];
 173     cpu_write_xer(env, env->spr[SPR_XER]);
 174 #if defined(TARGET_PPC64)
 175     env->cfar = env->spr[SPR_CFAR];
 176 #endif
 177     env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
 178
 179     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 180         env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
 181         env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
 182         env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
 183         env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
 184     }
 185     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 186         env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
 187         env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
 188         env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
 189         env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
 190     }
 191
 192     if (!env->external_htab) {
 193         /* Restore htab_base and htab_mask variables */
 194         ppc_store_sdr1(env, env->spr[SPR_SDR1]);
 195     }
 196
 197     /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
 198     msr = env->msr;
 199     env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB);
 200     ppc_store_msr(env, msr);
 201
 202     hreg_compute_mem_idx(env);
 203
 204     return 0;
 205 }
 206
 207 static bool fpu_needed(void *opaque)
 208 {
 209     PowerPCCPU *cpu = opaque;
 210
 211     return (cpu->env.insns_flags & PPC_FLOAT);
 212 }
 213
 214 static const VMStateDescription vmstate_fpu = {
 215     .name = "cpu/fpu",
 216     .version_id = 1,
 217     .minimum_version_id = 1,
 218     .needed = fpu_needed,
 219     .fields = (VMStateField[]) {
 220         VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
 221         VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
 222         VMSTATE_END_OF_LIST()
 223     },
 224 };
 225
 226 static bool altivec_needed(void *opaque)
 227 {
 228     PowerPCCPU *cpu = opaque;
 229
 230     return (cpu->env.insns_flags & PPC_ALTIVEC);
 231 }
 232
 233 static const VMStateDescription vmstate_altivec = {
 234     .name = "cpu/altivec",
 235     .version_id = 1,
 236     .minimum_version_id = 1,
 237     .needed = altivec_needed,
 238     .fields = (VMStateField[]) {
 239         VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
 240         VMSTATE_UINT32(env.vscr, PowerPCCPU),
 241         VMSTATE_END_OF_LIST()
 242     },
 243 };
 244
 245 static bool vsx_needed(void *opaque)
 246 {
 247     PowerPCCPU *cpu = opaque;
 248
 249     return (cpu->env.insns_flags2 & PPC2_VSX);
 250 }
 251
 252 static const VMStateDescription vmstate_vsx = {
 253     .name = "cpu/vsx",
 254     .version_id = 1,
 255     .minimum_version_id = 1,
 256     .needed = vsx_needed,
 257     .fields = (VMStateField[]) {
 258         VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
 259         VMSTATE_END_OF_LIST()
 260     },
 261 };
 262
 263 #ifdef TARGET_PPC64
 264 /* Transactional memory state */
 265 static bool tm_needed(void *opaque)
 266 {
 267     PowerPCCPU *cpu = opaque;
 268     CPUPPCState *env = &cpu->env;
 269     return msr_ts;
 270 }
 271
 272 static const VMStateDescription vmstate_tm = {
 273     .name = "cpu/tm",
 274     .version_id = 1,
 275     .minimum_version_id = 1,
 276     .minimum_version_id_old = 1,
 277     .needed = tm_needed,
 278     .fields      = (VMStateField []) {
 279         VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
 280         VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
 281         VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
 282         VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
 283         VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
 284         VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
 285         VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
 286         VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
 287         VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
 288         VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
 289         VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
 290         VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
 291         VMSTATE_END_OF_LIST()
 292     },
 293 };
 294 #endif
 295
 296 static bool sr_needed(void *opaque)
 297 {
 298 #ifdef TARGET_PPC64
 299     PowerPCCPU *cpu = opaque;
 300
 301     return !(cpu->env.mmu_model & POWERPC_MMU_64);
 302 #else
 303     return true;
 304 #endif
 305 }
 306
 307 static const VMStateDescription vmstate_sr = {
 308     .name = "cpu/sr",
 309     .version_id = 1,
 310     .minimum_version_id = 1,
 311     .needed = sr_needed,
 312     .fields = (VMStateField[]) {
 313         VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
 314         VMSTATE_END_OF_LIST()
 315     },
 316 };
 317
 318 #ifdef TARGET_PPC64
 319 static int get_slbe(QEMUFile *f, void *pv, size_t size)
 320 {
 321     ppc_slb_t *v = pv;
 322
 323     v->esid = qemu_get_be64(f);
 324     v->vsid = qemu_get_be64(f);
 325
 326     return 0;
 327 }
 328
 329 static void put_slbe(QEMUFile *f, void *pv, size_t size)
 330 {
 331     ppc_slb_t *v = pv;
 332
 333     qemu_put_be64(f, v->esid);
 334     qemu_put_be64(f, v->vsid);
 335 }
 336
 337 static const VMStateInfo vmstate_info_slbe = {
 338     .name = "slbe",
 339     .get  = get_slbe,
 340     .put  = put_slbe,
 341 };
 342
 343 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
 344     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
 345
 346 #define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
 347     VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
 348
 349 static bool slb_needed(void *opaque)
 350 {
 351     PowerPCCPU *cpu = opaque;
 352
 353     /* We don't support any of the old segment table based 64-bit CPUs */
 354     return (cpu->env.mmu_model & POWERPC_MMU_64);
 355 }
 356
 357 static int slb_post_load(void *opaque, int version_id)
 358 {
 359     PowerPCCPU *cpu = opaque;
 360     CPUPPCState *env = &cpu->env;
 361     int i;
 362
 363     /* We've pulled in the raw esid and vsid values from the migration
 364      * stream, but we need to recompute the page size pointers */
 365     for (i = 0; i < env->slb_nr; i++) {
 366         if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
 367             /* Migration source had bad values in its SLB */
 368             return -1;
 369         }
 370     }
 371
 372     return 0;
 373 }
 374
 375 static const VMStateDescription vmstate_slb = {
 376     .name = "cpu/slb",
 377     .version_id = 1,
 378     .minimum_version_id = 1,
 379     .needed = slb_needed,
 380     .post_load = slb_post_load,
 381     .fields = (VMStateField[]) {
 382         VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
 383         VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
 384         VMSTATE_END_OF_LIST()
 385     }
 386 };
 387 #endif /* TARGET_PPC64 */
 388
 389 static const VMStateDescription vmstate_tlb6xx_entry = {
 390     .name = "cpu/tlb6xx_entry",
 391     .version_id = 1,
 392     .minimum_version_id = 1,
 393     .fields = (VMStateField[]) {
 394         VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
 395         VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
 396         VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
 397         VMSTATE_END_OF_LIST()
 398     },
 399 };
 400
 401 static bool tlb6xx_needed(void *opaque)
 402 {
 403     PowerPCCPU *cpu = opaque;
 404     CPUPPCState *env = &cpu->env;
 405
 406     return env->nb_tlb && (env->tlb_type == TLB_6XX);
 407 }
 408
 409 static const VMStateDescription vmstate_tlb6xx = {
 410     .name = "cpu/tlb6xx",
 411     .version_id = 1,
 412     .minimum_version_id = 1,
 413     .needed = tlb6xx_needed,
 414     .fields = (VMStateField[]) {
 415         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 416         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
 417                                             env.nb_tlb,
 418                                             vmstate_tlb6xx_entry,
 419                                             ppc6xx_tlb_t),
 420         VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
 421         VMSTATE_END_OF_LIST()
 422     }
 423 };
 424
 425 static const VMStateDescription vmstate_tlbemb_entry = {
 426     .name = "cpu/tlbemb_entry",
 427     .version_id = 1,
 428     .minimum_version_id = 1,
 429     .fields = (VMStateField[]) {
 430         VMSTATE_UINT64(RPN, ppcemb_tlb_t),
 431         VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
 432         VMSTATE_UINTTL(PID, ppcemb_tlb_t),
 433         VMSTATE_UINTTL(size, ppcemb_tlb_t),
 434         VMSTATE_UINT32(prot, ppcemb_tlb_t),
 435         VMSTATE_UINT32(attr, ppcemb_tlb_t),
 436         VMSTATE_END_OF_LIST()
 437     },
 438 };
 439
 440 static bool tlbemb_needed(void *opaque)
 441 {
 442     PowerPCCPU *cpu = opaque;
 443     CPUPPCState *env = &cpu->env;
 444
 445     return env->nb_tlb && (env->tlb_type == TLB_EMB);
 446 }
 447
 448 static bool pbr403_needed(void *opaque)
 449 {
 450     PowerPCCPU *cpu = opaque;
 451     uint32_t pvr = cpu->env.spr[SPR_PVR];
 452
 453     return (pvr & 0xffff0000) == 0x00200000;
 454 }
 455
 456 static const VMStateDescription vmstate_pbr403 = {
 457     .name = "cpu/pbr403",
 458     .version_id = 1,
 459     .minimum_version_id = 1,
 460     .needed = pbr403_needed,
 461     .fields = (VMStateField[]) {
 462         VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
 463         VMSTATE_END_OF_LIST()
 464     },
 465 };
 466
 467 static const VMStateDescription vmstate_tlbemb = {
 468     .name = "cpu/tlb6xx",
 469     .version_id = 1,
 470     .minimum_version_id = 1,
 471     .needed = tlbemb_needed,
 472     .fields = (VMStateField[]) {
 473         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 474         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
 475                                             env.nb_tlb,
 476                                             vmstate_tlbemb_entry,
 477                                             ppcemb_tlb_t),
 478         /* 403 protection registers */
 479         VMSTATE_END_OF_LIST()
 480     },
 481     .subsections = (const VMStateDescription*[]) {
 482         &vmstate_pbr403,
 483         NULL
 484     }
 485 };
 486
 487 static const VMStateDescription vmstate_tlbmas_entry = {
 488     .name = "cpu/tlbmas_entry",
 489     .version_id = 1,
 490     .minimum_version_id = 1,
 491     .fields = (VMStateField[]) {
 492         VMSTATE_UINT32(mas8, ppcmas_tlb_t),
 493         VMSTATE_UINT32(mas1, ppcmas_tlb_t),
 494         VMSTATE_UINT64(mas2, ppcmas_tlb_t),
 495         VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
 496         VMSTATE_END_OF_LIST()
 497     },
 498 };
 499
 500 static bool tlbmas_needed(void *opaque)
 501 {
 502     PowerPCCPU *cpu = opaque;
 503     CPUPPCState *env = &cpu->env;
 504
 505     return env->nb_tlb && (env->tlb_type == TLB_MAS);
 506 }
 507
 508 static const VMStateDescription vmstate_tlbmas = {
 509     .name = "cpu/tlbmas",
 510     .version_id = 1,
 511     .minimum_version_id = 1,
 512     .needed = tlbmas_needed,
 513     .fields = (VMStateField[]) {
 514         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 515         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
 516                                             env.nb_tlb,
 517                                             vmstate_tlbmas_entry,
 518                                             ppcmas_tlb_t),
 519         VMSTATE_END_OF_LIST()
 520     }
 521 };
 522
 523 const VMStateDescription vmstate_ppc_cpu = {
 524     .name = "cpu",
 525     .version_id = 5,
 526     .minimum_version_id = 5,
 527     .minimum_version_id_old = 4,
 528     .load_state_old = cpu_load_old,
 529     .pre_save = cpu_pre_save,
 530     .post_load = cpu_post_load,
 531     .fields = (VMStateField[]) {
 532         VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
 533
 534         /* User mode architected state */
 535         VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
 536 #if !defined(TARGET_PPC64)
 537         VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
 538 #endif
 539         VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
 540         VMSTATE_UINTTL(env.nip, PowerPCCPU),
 541
 542         /* SPRs */
 543         VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
 544         VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
 545
 546         /* Reservation */
 547         VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
 548
 549         /* Supervisor mode architected state */
 550         VMSTATE_UINTTL(env.msr, PowerPCCPU),
 551
 552         /* Internal state */
 553         VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
 554         /* FIXME: access_type? */
 555
 556         /* Sanity checking */
 557         VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
 558         VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
 559         VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
 560         VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
 561         VMSTATE_END_OF_LIST()
 562     },
 563     .subsections = (const VMStateDescription*[]) {
 564         &vmstate_fpu,
 565         &vmstate_altivec,
 566         &vmstate_vsx,
 567         &vmstate_sr,
 568 #ifdef TARGET_PPC64
 569         &vmstate_tm,
 570         &vmstate_slb,
 571 #endif /* TARGET_PPC64 */
 572         &vmstate_tlb6xx,
 573         &vmstate_tlbemb,
 574         &vmstate_tlbmas,
 575         NULL
 576     }
 577 };