hw/pci/msix.c

   1 /*
   2  * MSI-X device support
   3  *
   4  * This module includes support for MSI-X in pci devices.
   5  *
   6  * Author: Michael S. Tsirkin <mst@redhat.com>
   7  *
   8  *  Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2.  See
  11  * the COPYING file in the top-level directory.
  12  *
  13  * Contributions after 2012-01-13 are licensed under the terms of the
  14  * GNU GPL, version 2 or (at your option) any later version.
  15  */
  16
  17 #include "hw/hw.h"
  18 #include "hw/pci/msi.h"
  19 #include "hw/pci/msix.h"
  20 #include "hw/pci/pci.h"
  21 #include "qemu/range.h"
  22
  23 #define MSIX_CAP_LENGTH 12
  24
  25 /* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
  26 #define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
  27 #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
  28 #define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
  29
  30 MSIMessage msix_get_message(PCIDevice *dev, unsigned vector)
  31 {
  32     uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
  33     MSIMessage msg;
  34
  35     msg.address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
  36     msg.data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
  37     return msg;
  38 }
  39
  40 /*
  41  * Special API for POWER to configure the vectors through
  42  * a side channel. Should never be used by devices.
  43  */
  44 void msix_set_message(PCIDevice *dev, int vector, struct MSIMessage msg)
  45 {
  46     uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
  47
  48     pci_set_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR, msg.address);
  49     pci_set_long(table_entry + PCI_MSIX_ENTRY_DATA, msg.data);
  50     table_entry[PCI_MSIX_ENTRY_VECTOR_CTRL] &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
  51 }
  52
  53 static uint8_t msix_pending_mask(int vector)
  54 {
  55     return 1 << (vector % 8);
  56 }
  57
  58 static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
  59 {
  60     return dev->msix_pba + vector / 8;
  61 }
  62
  63 static int msix_is_pending(PCIDevice *dev, int vector)
  64 {
  65     return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
  66 }
  67
  68 void msix_set_pending(PCIDevice *dev, unsigned int vector)
  69 {
  70     *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
  71 }
  72
  73 static void msix_clr_pending(PCIDevice *dev, int vector)
  74 {
  75     *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
  76 }
  77
  78 static bool msix_vector_masked(PCIDevice *dev, unsigned int vector, bool fmask)
  79 {
  80     unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
  81     return fmask || dev->msix_table[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
  82 }
  83
  84 bool msix_is_masked(PCIDevice *dev, unsigned int vector)
  85 {
  86     return msix_vector_masked(dev, vector, dev->msix_function_masked);
  87 }
  88
  89 static void msix_fire_vector_notifier(PCIDevice *dev,
  90                                       unsigned int vector, bool is_masked)
  91 {
  92     MSIMessage msg;
  93     int ret;
  94
  95     if (!dev->msix_vector_use_notifier) {
  96         return;
  97     }
  98     if (is_masked) {
  99         dev->msix_vector_release_notifier(dev, vector);
 100     } else {
 101         msg = msix_get_message(dev, vector);
 102         ret = dev->msix_vector_use_notifier(dev, vector, msg);
 103         assert(ret >= 0);
 104     }
 105 }
 106
 107 static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
 108 {
 109     bool is_masked = msix_is_masked(dev, vector);
 110
 111     if (is_masked == was_masked) {
 112         return;
 113     }
 114
 115     msix_fire_vector_notifier(dev, vector, is_masked);
 116
 117     if (!is_masked && msix_is_pending(dev, vector)) {
 118         msix_clr_pending(dev, vector);
 119         msix_notify(dev, vector);
 120     }
 121 }
 122
 123 static void msix_update_function_masked(PCIDevice *dev)
 124 {
 125     dev->msix_function_masked = !msix_enabled(dev) ||
 126         (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
 127 }
 128
 129 /* Handle MSI-X capability config write. */
 130 void msix_write_config(PCIDevice *dev, uint32_t addr,
 131                        uint32_t val, int len)
 132 {
 133     unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
 134     int vector;
 135     bool was_masked;
 136
 137     if (!msix_present(dev) || !range_covers_byte(addr, len, enable_pos)) {
 138         return;
 139     }
 140
 141     was_masked = dev->msix_function_masked;
 142     msix_update_function_masked(dev);
 143
 144     if (!msix_enabled(dev)) {
 145         return;
 146     }
 147
 148     pci_device_deassert_intx(dev);
 149
 150     if (dev->msix_function_masked == was_masked) {
 151         return;
 152     }
 153
 154     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 155         msix_handle_mask_update(dev, vector,
 156                                 msix_vector_masked(dev, vector, was_masked));
 157     }
 158 }
 159
 160 static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
 161                                      unsigned size)
 162 {
 163     PCIDevice *dev = opaque;
 164
 165     return pci_get_long(dev->msix_table + addr);
 166 }
 167
 168 static void msix_table_mmio_write(void *opaque, hwaddr addr,
 169                                   uint64_t val, unsigned size)
 170 {
 171     PCIDevice *dev = opaque;
 172     int vector = addr / PCI_MSIX_ENTRY_SIZE;
 173     bool was_masked;
 174
 175     was_masked = msix_is_masked(dev, vector);
 176     pci_set_long(dev->msix_table + addr, val);
 177     msix_handle_mask_update(dev, vector, was_masked);
 178 }
 179
 180 static const MemoryRegionOps msix_table_mmio_ops = {
 181     .read = msix_table_mmio_read,
 182     .write = msix_table_mmio_write,
 183     .endianness = DEVICE_LITTLE_ENDIAN,
 184     .valid = {
 185         .min_access_size = 4,
 186         .max_access_size = 4,
 187     },
 188 };
 189
 190 static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
 191                                    unsigned size)
 192 {
 193     PCIDevice *dev = opaque;
 194     if (dev->msix_vector_poll_notifier) {
 195         unsigned vector_start = addr * 8;
 196         unsigned vector_end = MIN(addr + size * 8, dev->msix_entries_nr);
 197         dev->msix_vector_poll_notifier(dev, vector_start, vector_end);
 198     }
 199
 200     return pci_get_long(dev->msix_pba + addr);
 201 }
 202
 203 static const MemoryRegionOps msix_pba_mmio_ops = {
 204     .read = msix_pba_mmio_read,
 205     .endianness = DEVICE_LITTLE_ENDIAN,
 206     .valid = {
 207         .min_access_size = 4,
 208         .max_access_size = 4,
 209     },
 210 };
 211
 212 static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
 213 {
 214     int vector;
 215
 216     for (vector = 0; vector < nentries; ++vector) {
 217         unsigned offset =
 218             vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
 219         bool was_masked = msix_is_masked(dev, vector);
 220
 221         dev->msix_table[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
 222         msix_handle_mask_update(dev, vector, was_masked);
 223     }
 224 }
 225
 226 /* Initialize the MSI-X structures */
 227 int msix_init(struct PCIDevice *dev, unsigned short nentries,
 228               MemoryRegion *table_bar, uint8_t table_bar_nr,
 229               unsigned table_offset, MemoryRegion *pba_bar,
 230               uint8_t pba_bar_nr, unsigned pba_offset, uint8_t cap_pos)
 231 {
 232     int cap;
 233     unsigned table_size, pba_size;
 234     uint8_t *config;
 235
 236     /* Nothing to do if MSI is not supported by interrupt controller */
 237     if (!msi_supported) {
 238         return -ENOTSUP;
 239     }
 240
 241     if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1) {
 242         return -EINVAL;
 243     }
 244
 245     table_size = nentries * PCI_MSIX_ENTRY_SIZE;
 246     pba_size = QEMU_ALIGN_UP(nentries, 64) / 8;
 247
 248     /* Sanity test: table & pba don't overlap, fit within BARs, min aligned */
 249     if ((table_bar_nr == pba_bar_nr &&
 250          ranges_overlap(table_offset, table_size, pba_offset, pba_size)) ||
 251         table_offset + table_size > memory_region_size(table_bar) ||
 252         pba_offset + pba_size > memory_region_size(pba_bar) ||
 253         (table_offset | pba_offset) & PCI_MSIX_FLAGS_BIRMASK) {
 254         return -EINVAL;
 255     }
 256
 257     cap = pci_add_capability(dev, PCI_CAP_ID_MSIX, cap_pos, MSIX_CAP_LENGTH);
 258     if (cap < 0) {
 259         return cap;
 260     }
 261
 262     dev->msix_cap = cap;
 263     dev->cap_present |= QEMU_PCI_CAP_MSIX;
 264     config = dev->config + cap;
 265
 266     pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
 267     dev->msix_entries_nr = nentries;
 268     dev->msix_function_masked = true;
 269
 270     pci_set_long(config + PCI_MSIX_TABLE, table_offset | table_bar_nr);
 271     pci_set_long(config + PCI_MSIX_PBA, pba_offset | pba_bar_nr);
 272
 273     /* Make flags bit writable. */
 274     dev->wmask[cap + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
 275                                              MSIX_MASKALL_MASK;
 276
 277     dev->msix_table = g_malloc0(table_size);
 278     dev->msix_pba = g_malloc0(pba_size);
 279     dev->msix_entry_used = g_malloc0(nentries * sizeof *dev->msix_entry_used);
 280
 281     msix_mask_all(dev, nentries);
 282
 283     memory_region_init_io(&dev->msix_table_mmio, OBJECT(dev), &msix_table_mmio_ops, dev,
 284                           "msix-table", table_size);
 285     memory_region_add_subregion(table_bar, table_offset, &dev->msix_table_mmio);
 286     memory_region_init_io(&dev->msix_pba_mmio, OBJECT(dev), &msix_pba_mmio_ops, dev,
 287                           "msix-pba", pba_size);
 288     memory_region_add_subregion(pba_bar, pba_offset, &dev->msix_pba_mmio);
 289
 290     return 0;
 291 }
 292
 293 int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,
 294                             uint8_t bar_nr)
 295 {
 296     int ret;
 297     char *name;
 298     uint32_t bar_size = 4096;
 299     uint32_t bar_pba_offset = bar_size / 2;
 300     uint32_t bar_pba_size = (nentries / 8 + 1) * 8;
 301
 302     /*
 303      * Migration compatibility dictates that this remains a 4k
 304      * BAR with the vector table in the lower half and PBA in
 305      * the upper half for nentries which is lower or equal to 128.
 306      * No need to care about using more than 65 entries for legacy
 307      * machine types who has at most 64 queues.
 308      */
 309     if (nentries * PCI_MSIX_ENTRY_SIZE > bar_pba_offset) {
 310         bar_pba_offset = nentries * PCI_MSIX_ENTRY_SIZE;
 311     }
 312
 313     if (bar_pba_offset + bar_pba_size > 4096) {
 314         bar_size = bar_pba_offset + bar_pba_size;
 315     }
 316
 317     bar_size = pow2ceil(bar_size);
 318
 319     name = g_strdup_printf("%s-msix", dev->name);
 320     memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev), name, bar_size);
 321     g_free(name);
 322
 323     ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr,
 324                     0, &dev->msix_exclusive_bar,
 325                     bar_nr, bar_pba_offset,
 326                     0);
 327     if (ret) {
 328         return ret;
 329     }
 330
 331     pci_register_bar(dev, bar_nr, PCI_BASE_ADDRESS_SPACE_MEMORY,
 332                      &dev->msix_exclusive_bar);
 333
 334     return 0;
 335 }
 336
 337 static void msix_free_irq_entries(PCIDevice *dev)
 338 {
 339     int vector;
 340
 341     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 342         dev->msix_entry_used[vector] = 0;
 343         msix_clr_pending(dev, vector);
 344     }
 345 }
 346
 347 static void msix_clear_all_vectors(PCIDevice *dev)
 348 {
 349     int vector;
 350
 351     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 352         msix_clr_pending(dev, vector);
 353     }
 354 }
 355
 356 /* Clean up resources for the device. */
 357 void msix_uninit(PCIDevice *dev, MemoryRegion *table_bar, MemoryRegion *pba_bar)
 358 {
 359     if (!msix_present(dev)) {
 360         return;
 361     }
 362     pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
 363     dev->msix_cap = 0;
 364     msix_free_irq_entries(dev);
 365     dev->msix_entries_nr = 0;
 366     memory_region_del_subregion(pba_bar, &dev->msix_pba_mmio);
 367     g_free(dev->msix_pba);
 368     dev->msix_pba = NULL;
 369     memory_region_del_subregion(table_bar, &dev->msix_table_mmio);
 370     g_free(dev->msix_table);
 371     dev->msix_table = NULL;
 372     g_free(dev->msix_entry_used);
 373     dev->msix_entry_used = NULL;
 374     dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
 375 }
 376
 377 void msix_uninit_exclusive_bar(PCIDevice *dev)
 378 {
 379     if (msix_present(dev)) {
 380         msix_uninit(dev, &dev->msix_exclusive_bar, &dev->msix_exclusive_bar);
 381     }
 382 }
 383
 384 void msix_save(PCIDevice *dev, QEMUFile *f)
 385 {
 386     unsigned n = dev->msix_entries_nr;
 387
 388     if (!msix_present(dev)) {
 389         return;
 390     }
 391
 392     qemu_put_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);
 393     qemu_put_buffer(f, dev->msix_pba, (n + 7) / 8);
 394 }
 395
 396 /* Should be called after restoring the config space. */
 397 void msix_load(PCIDevice *dev, QEMUFile *f)
 398 {
 399     unsigned n = dev->msix_entries_nr;
 400     unsigned int vector;
 401
 402     if (!msix_present(dev)) {
 403         return;
 404     }
 405
 406     msix_clear_all_vectors(dev);
 407     qemu_get_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);
 408     qemu_get_buffer(f, dev->msix_pba, (n + 7) / 8);
 409     msix_update_function_masked(dev);
 410
 411     for (vector = 0; vector < n; vector++) {
 412         msix_handle_mask_update(dev, vector, true);
 413     }
 414 }
 415
 416 /* Does device support MSI-X? */
 417 int msix_present(PCIDevice *dev)
 418 {
 419     return dev->cap_present & QEMU_PCI_CAP_MSIX;
 420 }
 421
 422 /* Is MSI-X enabled? */
 423 int msix_enabled(PCIDevice *dev)
 424 {
 425     return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
 426         (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
 427          MSIX_ENABLE_MASK);
 428 }
 429
 430 /* Send an MSI-X message */
 431 void msix_notify(PCIDevice *dev, unsigned vector)
 432 {
 433     MSIMessage msg;
 434
 435     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
 436         return;
 437     if (msix_is_masked(dev, vector)) {
 438         msix_set_pending(dev, vector);
 439         return;
 440     }
 441
 442     msg = msix_get_message(dev, vector);
 443
 444     msi_send_message(dev, msg);
 445 }
 446
 447 void msix_reset(PCIDevice *dev)
 448 {
 449     if (!msix_present(dev)) {
 450         return;
 451     }
 452     msix_clear_all_vectors(dev);
 453     dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
 454             ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
 455     memset(dev->msix_table, 0, dev->msix_entries_nr * PCI_MSIX_ENTRY_SIZE);
 456     memset(dev->msix_pba, 0, QEMU_ALIGN_UP(dev->msix_entries_nr, 64) / 8);
 457     msix_mask_all(dev, dev->msix_entries_nr);
 458 }
 459
 460 /* PCI spec suggests that devices make it possible for software to configure
 461  * less vectors than supported by the device, but does not specify a standard
 462  * mechanism for devices to do so.
 463  *
 464  * We support this by asking devices to declare vectors software is going to
 465  * actually use, and checking this on the notification path. Devices that
 466  * don't want to follow the spec suggestion can declare all vectors as used. */
 467
 468 /* Mark vector as used. */
 469 int msix_vector_use(PCIDevice *dev, unsigned vector)
 470 {
 471     if (vector >= dev->msix_entries_nr)
 472         return -EINVAL;
 473     dev->msix_entry_used[vector]++;
 474     return 0;
 475 }
 476
 477 /* Mark vector as unused. */
 478 void msix_vector_unuse(PCIDevice *dev, unsigned vector)
 479 {
 480     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
 481         return;
 482     }
 483     if (--dev->msix_entry_used[vector]) {
 484         return;
 485     }
 486     msix_clr_pending(dev, vector);
 487 }
 488
 489 void msix_unuse_all_vectors(PCIDevice *dev)
 490 {
 491     if (!msix_present(dev)) {
 492         return;
 493     }
 494     msix_free_irq_entries(dev);
 495 }
 496
 497 unsigned int msix_nr_vectors_allocated(const PCIDevice *dev)
 498 {
 499     return dev->msix_entries_nr;
 500 }
 501
 502 static int msix_set_notifier_for_vector(PCIDevice *dev, unsigned int vector)
 503 {
 504     MSIMessage msg;
 505
 506     if (msix_is_masked(dev, vector)) {
 507         return 0;
 508     }
 509     msg = msix_get_message(dev, vector);
 510     return dev->msix_vector_use_notifier(dev, vector, msg);
 511 }
 512
 513 static void msix_unset_notifier_for_vector(PCIDevice *dev, unsigned int vector)
 514 {
 515     if (msix_is_masked(dev, vector)) {
 516         return;
 517     }
 518     dev->msix_vector_release_notifier(dev, vector);
 519 }
 520
 521 int msix_set_vector_notifiers(PCIDevice *dev,
 522                               MSIVectorUseNotifier use_notifier,
 523                               MSIVectorReleaseNotifier release_notifier,
 524                               MSIVectorPollNotifier poll_notifier)
 525 {
 526     int vector, ret;
 527
 528     assert(use_notifier && release_notifier);
 529
 530     dev->msix_vector_use_notifier = use_notifier;
 531     dev->msix_vector_release_notifier = release_notifier;
 532     dev->msix_vector_poll_notifier = poll_notifier;
 533
 534     if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
 535         (MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) {
 536         for (vector = 0; vector < dev->msix_entries_nr; vector++) {
 537             ret = msix_set_notifier_for_vector(dev, vector);
 538             if (ret < 0) {
 539                 goto undo;
 540             }
 541         }
 542     }
 543     if (dev->msix_vector_poll_notifier) {
 544         dev->msix_vector_poll_notifier(dev, 0, dev->msix_entries_nr);
 545     }
 546     return 0;
 547
 548 undo:
 549     while (--vector >= 0) {
 550         msix_unset_notifier_for_vector(dev, vector);
 551     }
 552     dev->msix_vector_use_notifier = NULL;
 553     dev->msix_vector_release_notifier = NULL;
 554     return ret;
 555 }
 556
 557 void msix_unset_vector_notifiers(PCIDevice *dev)
 558 {
 559     int vector;
 560
 561     assert(dev->msix_vector_use_notifier &&
 562            dev->msix_vector_release_notifier);
 563
 564     if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
 565         (MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) {
 566         for (vector = 0; vector < dev->msix_entries_nr; vector++) {
 567             msix_unset_notifier_for_vector(dev, vector);
 568         }
 569     }
 570     dev->msix_vector_use_notifier = NULL;
 571     dev->msix_vector_release_notifier = NULL;
 572     dev->msix_vector_poll_notifier = NULL;
 573 }
 574
 575 static void put_msix_state(QEMUFile *f, void *pv, size_t size)
 576 {
 577     msix_save(pv, f);
 578 }
 579
 580 static int get_msix_state(QEMUFile *f, void *pv, size_t size)
 581 {
 582     msix_load(pv, f);
 583     return 0;
 584 }
 585
 586 static VMStateInfo vmstate_info_msix = {
 587     .name = "msix state",
 588     .get  = get_msix_state,
 589     .put  = put_msix_state,
 590 };
 591
 592 const VMStateDescription vmstate_msix = {
 593     .name = "msix",
 594     .fields = (VMStateField[]) {
 595         {
 596             .name         = "msix",
 597             .version_id   = 0,
 598             .field_exists = NULL,
 599             .size         = 0,   /* ouch */
 600             .info         = &vmstate_info_msix,
 601             .flags        = VMS_SINGLE,
 602             .offset       = 0,
 603         },
 604         VMSTATE_END_OF_LIST()
 605     }
 606 };