2 * Copyright (C) 2014-2016 Broadcom Corporation
3 * Copyright (c) 2017 Red Hat, Inc.
4 * Written by Prem Mallappa, Eric Auger
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/bitops.h"
22 #include "hw/sysbus.h"
23 #include "migration/vmstate.h"
24 #include "hw/qdev-properties.h"
25 #include "hw/qdev-core.h"
26 #include "hw/pci/pci.h"
30 #include "qemu/error-report.h"
31 #include "qapi/error.h"
33 #include "hw/arm/smmuv3.h"
34 #include "smmuv3-internal.h"
35 #include "smmu-internal.h"
37 #define PTW_RECORD_FAULT(cfg) (((cfg)->stage == SMMU_STAGE_1) ? \
38 (cfg)->record_faults : \
39 (cfg)->s2cfg.record_faults)
42 * smmuv3_trigger_irq - pulse @irq if enabled and update
43 * GERROR register in case of GERROR interrupt
46 * @gerror_mask: mask of gerrors to toggle (relevant if @irq is GERROR)
48 static void smmuv3_trigger_irq(SMMUv3State
*s
, SMMUIrq irq
,
56 pulse
= smmuv3_eventq_irq_enabled(s
);
59 qemu_log_mask(LOG_UNIMP
, "PRI not yet supported\n");
61 case SMMU_IRQ_CMD_SYNC
:
66 uint32_t pending
= s
->gerror
^ s
->gerrorn
;
67 uint32_t new_gerrors
= ~pending
& gerror_mask
;
70 /* only toggle non pending errors */
73 s
->gerror
^= new_gerrors
;
74 trace_smmuv3_write_gerror(new_gerrors
, s
->gerror
);
76 pulse
= smmuv3_gerror_irq_enabled(s
);
81 trace_smmuv3_trigger_irq(irq
);
82 qemu_irq_pulse(s
->irq
[irq
]);
86 static void smmuv3_write_gerrorn(SMMUv3State
*s
, uint32_t new_gerrorn
)
88 uint32_t pending
= s
->gerror
^ s
->gerrorn
;
89 uint32_t toggled
= s
->gerrorn
^ new_gerrorn
;
91 if (toggled
& ~pending
) {
92 qemu_log_mask(LOG_GUEST_ERROR
,
93 "guest toggles non pending errors = 0x%x\n",
98 * We do not raise any error in case guest toggles bits corresponding
99 * to not active IRQs (CONSTRAINED UNPREDICTABLE)
101 s
->gerrorn
= new_gerrorn
;
103 trace_smmuv3_write_gerrorn(toggled
& pending
, s
->gerrorn
);
106 static inline MemTxResult
queue_read(SMMUQueue
*q
, Cmd
*cmd
)
108 dma_addr_t addr
= Q_CONS_ENTRY(q
);
112 ret
= dma_memory_read(&address_space_memory
, addr
, cmd
, sizeof(Cmd
),
113 MEMTXATTRS_UNSPECIFIED
);
114 if (ret
!= MEMTX_OK
) {
117 for (i
= 0; i
< ARRAY_SIZE(cmd
->word
); i
++) {
118 le32_to_cpus(&cmd
->word
[i
]);
123 static MemTxResult
queue_write(SMMUQueue
*q
, Evt
*evt_in
)
125 dma_addr_t addr
= Q_PROD_ENTRY(q
);
130 for (i
= 0; i
< ARRAY_SIZE(evt
.word
); i
++) {
131 cpu_to_le32s(&evt
.word
[i
]);
133 ret
= dma_memory_write(&address_space_memory
, addr
, &evt
, sizeof(Evt
),
134 MEMTXATTRS_UNSPECIFIED
);
135 if (ret
!= MEMTX_OK
) {
143 static MemTxResult
smmuv3_write_eventq(SMMUv3State
*s
, Evt
*evt
)
145 SMMUQueue
*q
= &s
->eventq
;
148 if (!smmuv3_eventq_enabled(s
)) {
152 if (smmuv3_q_full(q
)) {
156 r
= queue_write(q
, evt
);
161 if (!smmuv3_q_empty(q
)) {
162 smmuv3_trigger_irq(s
, SMMU_IRQ_EVTQ
, 0);
167 void smmuv3_record_event(SMMUv3State
*s
, SMMUEventInfo
*info
)
172 if (!smmuv3_eventq_enabled(s
)) {
176 EVT_SET_TYPE(&evt
, info
->type
);
177 EVT_SET_SID(&evt
, info
->sid
);
179 switch (info
->type
) {
183 EVT_SET_SSID(&evt
, info
->u
.f_uut
.ssid
);
184 EVT_SET_SSV(&evt
, info
->u
.f_uut
.ssv
);
185 EVT_SET_ADDR(&evt
, info
->u
.f_uut
.addr
);
186 EVT_SET_RNW(&evt
, info
->u
.f_uut
.rnw
);
187 EVT_SET_PNU(&evt
, info
->u
.f_uut
.pnu
);
188 EVT_SET_IND(&evt
, info
->u
.f_uut
.ind
);
190 case SMMU_EVT_C_BAD_STREAMID
:
191 EVT_SET_SSID(&evt
, info
->u
.c_bad_streamid
.ssid
);
192 EVT_SET_SSV(&evt
, info
->u
.c_bad_streamid
.ssv
);
194 case SMMU_EVT_F_STE_FETCH
:
195 EVT_SET_SSID(&evt
, info
->u
.f_ste_fetch
.ssid
);
196 EVT_SET_SSV(&evt
, info
->u
.f_ste_fetch
.ssv
);
197 EVT_SET_ADDR2(&evt
, info
->u
.f_ste_fetch
.addr
);
199 case SMMU_EVT_C_BAD_STE
:
200 EVT_SET_SSID(&evt
, info
->u
.c_bad_ste
.ssid
);
201 EVT_SET_SSV(&evt
, info
->u
.c_bad_ste
.ssv
);
203 case SMMU_EVT_F_STREAM_DISABLED
:
205 case SMMU_EVT_F_TRANS_FORBIDDEN
:
206 EVT_SET_ADDR(&evt
, info
->u
.f_transl_forbidden
.addr
);
207 EVT_SET_RNW(&evt
, info
->u
.f_transl_forbidden
.rnw
);
209 case SMMU_EVT_C_BAD_SUBSTREAMID
:
210 EVT_SET_SSID(&evt
, info
->u
.c_bad_substream
.ssid
);
212 case SMMU_EVT_F_CD_FETCH
:
213 EVT_SET_SSID(&evt
, info
->u
.f_cd_fetch
.ssid
);
214 EVT_SET_SSV(&evt
, info
->u
.f_cd_fetch
.ssv
);
215 EVT_SET_ADDR(&evt
, info
->u
.f_cd_fetch
.addr
);
217 case SMMU_EVT_C_BAD_CD
:
218 EVT_SET_SSID(&evt
, info
->u
.c_bad_cd
.ssid
);
219 EVT_SET_SSV(&evt
, info
->u
.c_bad_cd
.ssv
);
221 case SMMU_EVT_F_WALK_EABT
:
222 case SMMU_EVT_F_TRANSLATION
:
223 case SMMU_EVT_F_ADDR_SIZE
:
224 case SMMU_EVT_F_ACCESS
:
225 case SMMU_EVT_F_PERMISSION
:
226 EVT_SET_STALL(&evt
, info
->u
.f_walk_eabt
.stall
);
227 EVT_SET_STAG(&evt
, info
->u
.f_walk_eabt
.stag
);
228 EVT_SET_SSID(&evt
, info
->u
.f_walk_eabt
.ssid
);
229 EVT_SET_SSV(&evt
, info
->u
.f_walk_eabt
.ssv
);
230 EVT_SET_S2(&evt
, info
->u
.f_walk_eabt
.s2
);
231 EVT_SET_ADDR(&evt
, info
->u
.f_walk_eabt
.addr
);
232 EVT_SET_RNW(&evt
, info
->u
.f_walk_eabt
.rnw
);
233 EVT_SET_PNU(&evt
, info
->u
.f_walk_eabt
.pnu
);
234 EVT_SET_IND(&evt
, info
->u
.f_walk_eabt
.ind
);
235 EVT_SET_CLASS(&evt
, info
->u
.f_walk_eabt
.class);
236 EVT_SET_ADDR2(&evt
, info
->u
.f_walk_eabt
.addr2
);
238 case SMMU_EVT_F_CFG_CONFLICT
:
239 EVT_SET_SSID(&evt
, info
->u
.f_cfg_conflict
.ssid
);
240 EVT_SET_SSV(&evt
, info
->u
.f_cfg_conflict
.ssv
);
242 /* rest is not implemented */
243 case SMMU_EVT_F_BAD_ATS_TREQ
:
244 case SMMU_EVT_F_TLB_CONFLICT
:
245 case SMMU_EVT_E_PAGE_REQ
:
247 g_assert_not_reached();
250 trace_smmuv3_record_event(smmu_event_string(info
->type
), info
->sid
);
251 r
= smmuv3_write_eventq(s
, &evt
);
253 smmuv3_trigger_irq(s
, SMMU_IRQ_GERROR
, R_GERROR_EVENTQ_ABT_ERR_MASK
);
255 info
->recorded
= true;
258 static void smmuv3_init_regs(SMMUv3State
*s
)
260 /* Based on sys property, the stages supported in smmu will be advertised.*/
261 if (s
->stage
&& !strcmp("2", s
->stage
)) {
262 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, S2P
, 1);
264 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, S1P
, 1);
267 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, TTF
, 2); /* AArch64 PTW only */
268 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, COHACC
, 1); /* IO coherent */
269 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, ASID16
, 1); /* 16-bit ASID */
270 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, VMID16
, 1); /* 16-bit VMID */
271 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, TTENDIAN
, 2); /* little endian */
272 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, STALL_MODEL
, 1); /* No stall */
273 /* terminated transaction will always be aborted/error returned */
274 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, TERM_MODEL
, 1);
275 /* 2-level stream table supported */
276 s
->idr
[0] = FIELD_DP32(s
->idr
[0], IDR0
, STLEVEL
, 1);
278 s
->idr
[1] = FIELD_DP32(s
->idr
[1], IDR1
, SIDSIZE
, SMMU_IDR1_SIDSIZE
);
279 s
->idr
[1] = FIELD_DP32(s
->idr
[1], IDR1
, EVENTQS
, SMMU_EVENTQS
);
280 s
->idr
[1] = FIELD_DP32(s
->idr
[1], IDR1
, CMDQS
, SMMU_CMDQS
);
282 s
->idr
[3] = FIELD_DP32(s
->idr
[3], IDR3
, HAD
, 1);
283 if (FIELD_EX32(s
->idr
[0], IDR0
, S2P
)) {
284 /* XNX is a stage-2-specific feature */
285 s
->idr
[3] = FIELD_DP32(s
->idr
[3], IDR3
, XNX
, 1);
287 s
->idr
[3] = FIELD_DP32(s
->idr
[3], IDR3
, RIL
, 1);
288 s
->idr
[3] = FIELD_DP32(s
->idr
[3], IDR3
, BBML
, 2);
290 s
->idr
[5] = FIELD_DP32(s
->idr
[5], IDR5
, OAS
, SMMU_IDR5_OAS
); /* 44 bits */
291 /* 4K, 16K and 64K granule support */
292 s
->idr
[5] = FIELD_DP32(s
->idr
[5], IDR5
, GRAN4K
, 1);
293 s
->idr
[5] = FIELD_DP32(s
->idr
[5], IDR5
, GRAN16K
, 1);
294 s
->idr
[5] = FIELD_DP32(s
->idr
[5], IDR5
, GRAN64K
, 1);
296 s
->cmdq
.base
= deposit64(s
->cmdq
.base
, 0, 5, SMMU_CMDQS
);
299 s
->cmdq
.entry_size
= sizeof(struct Cmd
);
300 s
->eventq
.base
= deposit64(s
->eventq
.base
, 0, 5, SMMU_EVENTQS
);
303 s
->eventq
.entry_size
= sizeof(struct Evt
);
314 s
->gbpa
= SMMU_GBPA_RESET_VAL
;
317 static int smmu_get_ste(SMMUv3State
*s
, dma_addr_t addr
, STE
*buf
,
318 SMMUEventInfo
*event
)
322 trace_smmuv3_get_ste(addr
);
323 /* TODO: guarantee 64-bit single-copy atomicity */
324 ret
= dma_memory_read(&address_space_memory
, addr
, buf
, sizeof(*buf
),
325 MEMTXATTRS_UNSPECIFIED
);
326 if (ret
!= MEMTX_OK
) {
327 qemu_log_mask(LOG_GUEST_ERROR
,
328 "Cannot fetch pte at address=0x%"PRIx64
"\n", addr
);
329 event
->type
= SMMU_EVT_F_STE_FETCH
;
330 event
->u
.f_ste_fetch
.addr
= addr
;
333 for (i
= 0; i
< ARRAY_SIZE(buf
->word
); i
++) {
334 le32_to_cpus(&buf
->word
[i
]);
340 static SMMUTranslationStatus
smmuv3_do_translate(SMMUv3State
*s
, hwaddr addr
,
342 SMMUEventInfo
*event
,
343 IOMMUAccessFlags flag
,
344 SMMUTLBEntry
**out_entry
,
345 SMMUTranslationClass
class);
346 /* @ssid > 0 not supported yet */
347 static int smmu_get_cd(SMMUv3State
*s
, STE
*ste
, SMMUTransCfg
*cfg
,
348 uint32_t ssid
, CD
*buf
, SMMUEventInfo
*event
)
350 dma_addr_t addr
= STE_CTXPTR(ste
);
352 SMMUTranslationStatus status
;
355 trace_smmuv3_get_cd(addr
);
357 if (cfg
->stage
== SMMU_NESTED
) {
358 status
= smmuv3_do_translate(s
, addr
, cfg
, event
,
359 IOMMU_RO
, &entry
, SMMU_CLASS_CD
);
361 /* Same PTW faults are reported but with CLASS = CD. */
362 if (status
!= SMMU_TRANS_SUCCESS
) {
366 addr
= CACHED_ENTRY_TO_ADDR(entry
, addr
);
369 /* TODO: guarantee 64-bit single-copy atomicity */
370 ret
= dma_memory_read(&address_space_memory
, addr
, buf
, sizeof(*buf
),
371 MEMTXATTRS_UNSPECIFIED
);
372 if (ret
!= MEMTX_OK
) {
373 qemu_log_mask(LOG_GUEST_ERROR
,
374 "Cannot fetch pte at address=0x%"PRIx64
"\n", addr
);
375 event
->type
= SMMU_EVT_F_CD_FETCH
;
376 event
->u
.f_ste_fetch
.addr
= addr
;
379 for (i
= 0; i
< ARRAY_SIZE(buf
->word
); i
++) {
380 le32_to_cpus(&buf
->word
[i
]);
386 * Max valid value is 39 when SMMU_IDR3.STT == 0.
387 * In architectures after SMMUv3.0:
388 * - If STE.S2TG selects a 4KB or 16KB granule, the minimum valid value for this
389 * field is MAX(16, 64-IAS)
390 * - If STE.S2TG selects a 64KB granule, the minimum valid value for this field
392 * As we only support AA64, IAS = OAS.
394 static bool s2t0sz_valid(SMMUTransCfg
*cfg
)
396 if (cfg
->s2cfg
.tsz
> 39) {
400 if (cfg
->s2cfg
.granule_sz
== 16) {
401 return (cfg
->s2cfg
.tsz
>= 64 - oas2bits(SMMU_IDR5_OAS
));
404 return (cfg
->s2cfg
.tsz
>= MAX(64 - oas2bits(SMMU_IDR5_OAS
), 16));
408 * Return true if s2 page table config is valid.
409 * This checks with the configured start level, ias_bits and granularity we can
410 * have a valid page table as described in ARM ARM D8.2 Translation process.
411 * The idea here is to see for the highest possible number of IPA bits, how
412 * many concatenated tables we would need, if it is more than 16, then this is
415 static bool s2_pgtable_config_valid(uint8_t sl0
, uint8_t t0sz
, uint8_t gran
)
417 int level
= get_start_level(sl0
, gran
);
418 uint64_t ipa_bits
= 64 - t0sz
;
419 uint64_t max_ipa
= (1ULL << ipa_bits
) - 1;
420 int nr_concat
= pgd_concat_idx(level
, gran
, max_ipa
) + 1;
422 return nr_concat
<= VMSA_MAX_S2_CONCAT
;
425 static int decode_ste_s2_cfg(SMMUTransCfg
*cfg
, STE
*ste
)
427 cfg
->stage
= SMMU_STAGE_2
;
429 if (STE_S2AA64(ste
) == 0x0) {
430 qemu_log_mask(LOG_UNIMP
,
431 "SMMUv3 AArch32 tables not supported\n");
432 g_assert_not_reached();
435 switch (STE_S2TG(ste
)) {
437 cfg
->s2cfg
.granule_sz
= 12;
440 cfg
->s2cfg
.granule_sz
= 16;
443 cfg
->s2cfg
.granule_sz
= 14;
446 qemu_log_mask(LOG_GUEST_ERROR
,
447 "SMMUv3 bad STE S2TG: %x\n", STE_S2TG(ste
));
451 cfg
->s2cfg
.vttb
= STE_S2TTB(ste
);
453 cfg
->s2cfg
.sl0
= STE_S2SL0(ste
);
454 /* FEAT_TTST not supported. */
455 if (cfg
->s2cfg
.sl0
== 0x3) {
456 qemu_log_mask(LOG_UNIMP
, "SMMUv3 S2SL0 = 0x3 has no meaning!\n");
460 /* For AA64, The effective S2PS size is capped to the OAS. */
461 cfg
->s2cfg
.eff_ps
= oas2bits(MIN(STE_S2PS(ste
), SMMU_IDR5_OAS
));
463 * It is ILLEGAL for the address in S2TTB to be outside the range
464 * described by the effective S2PS value.
466 if (cfg
->s2cfg
.vttb
& ~(MAKE_64BIT_MASK(0, cfg
->s2cfg
.eff_ps
))) {
467 qemu_log_mask(LOG_GUEST_ERROR
,
468 "SMMUv3 S2TTB too large 0x%" PRIx64
469 ", effective PS %d bits\n",
470 cfg
->s2cfg
.vttb
, cfg
->s2cfg
.eff_ps
);
474 cfg
->s2cfg
.tsz
= STE_S2T0SZ(ste
);
476 if (!s2t0sz_valid(cfg
)) {
477 qemu_log_mask(LOG_GUEST_ERROR
, "SMMUv3 bad STE S2T0SZ = %d\n",
482 if (!s2_pgtable_config_valid(cfg
->s2cfg
.sl0
, cfg
->s2cfg
.tsz
,
483 cfg
->s2cfg
.granule_sz
)) {
484 qemu_log_mask(LOG_GUEST_ERROR
,
485 "SMMUv3 STE stage 2 config not valid!\n");
489 /* Only LE supported(IDR0.TTENDIAN). */
490 if (STE_S2ENDI(ste
)) {
491 qemu_log_mask(LOG_GUEST_ERROR
,
492 "SMMUv3 STE_S2ENDI only supports LE!\n");
496 cfg
->s2cfg
.affd
= STE_S2AFFD(ste
);
498 cfg
->s2cfg
.record_faults
= STE_S2R(ste
);
499 /* As stall is not supported. */
501 qemu_log_mask(LOG_UNIMP
, "SMMUv3 Stall not implemented!\n");
511 /* Returns < 0 in case of invalid STE, 0 otherwise */
512 static int decode_ste(SMMUv3State
*s
, SMMUTransCfg
*cfg
,
513 STE
*ste
, SMMUEventInfo
*event
)
518 if (!STE_VALID(ste
)) {
519 if (!event
->inval_ste_allowed
) {
520 qemu_log_mask(LOG_GUEST_ERROR
, "invalid STE\n");
525 config
= STE_CONFIG(ste
);
527 if (STE_CFG_ABORT(config
)) {
532 if (STE_CFG_BYPASS(config
)) {
533 cfg
->bypassed
= true;
538 * If a stage is enabled in SW while not advertised, throw bad ste
539 * according to user manual(IHI0070E) "5.2 Stream Table Entry".
541 if (!STAGE1_SUPPORTED(s
) && STE_CFG_S1_ENABLED(config
)) {
542 qemu_log_mask(LOG_GUEST_ERROR
, "SMMUv3 S1 used but not supported.\n");
545 if (!STAGE2_SUPPORTED(s
) && STE_CFG_S2_ENABLED(config
)) {
546 qemu_log_mask(LOG_GUEST_ERROR
, "SMMUv3 S2 used but not supported.\n");
550 if (STAGE2_SUPPORTED(s
)) {
551 /* VMID is considered even if s2 is disabled. */
552 cfg
->s2cfg
.vmid
= STE_S2VMID(ste
);
555 cfg
->s2cfg
.vmid
= -1;
558 if (STE_CFG_S2_ENABLED(config
)) {
560 * Stage-1 OAS defaults to OAS even if not enabled as it would be used
561 * in input address check for stage-2.
563 cfg
->oas
= oas2bits(SMMU_IDR5_OAS
);
564 ret
= decode_ste_s2_cfg(cfg
, ste
);
570 if (STE_S1CDMAX(ste
) != 0) {
571 qemu_log_mask(LOG_UNIMP
,
572 "SMMUv3 does not support multiple context descriptors yet\n");
576 if (STE_S1STALLD(ste
)) {
577 qemu_log_mask(LOG_UNIMP
,
578 "SMMUv3 S1 stalling fault model not allowed yet\n");
584 event
->type
= SMMU_EVT_C_BAD_STE
;
589 * smmu_find_ste - Return the stream table entry associated
594 * @ste: returned stream table entry
595 * @event: handle to an event info
597 * Supports linear and 2-level stream table
598 * Return 0 on success, -EINVAL otherwise
600 static int smmu_find_ste(SMMUv3State
*s
, uint32_t sid
, STE
*ste
,
601 SMMUEventInfo
*event
)
603 dma_addr_t addr
, strtab_base
;
605 int strtab_size_shift
;
608 trace_smmuv3_find_ste(sid
, s
->features
, s
->sid_split
);
609 log2size
= FIELD_EX32(s
->strtab_base_cfg
, STRTAB_BASE_CFG
, LOG2SIZE
);
611 * Check SID range against both guest-configured and implementation limits
613 if (sid
>= (1 << MIN(log2size
, SMMU_IDR1_SIDSIZE
))) {
614 event
->type
= SMMU_EVT_C_BAD_STREAMID
;
617 if (s
->features
& SMMU_FEATURE_2LVL_STE
) {
618 int l1_ste_offset
, l2_ste_offset
, max_l2_ste
, span
, i
;
619 dma_addr_t l1ptr
, l2ptr
;
623 * Align strtab base address to table size. For this purpose, assume it
624 * is not bounded by SMMU_IDR1_SIDSIZE.
626 strtab_size_shift
= MAX(5, (int)log2size
- s
->sid_split
- 1 + 3);
627 strtab_base
= s
->strtab_base
& SMMU_BASE_ADDR_MASK
&
628 ~MAKE_64BIT_MASK(0, strtab_size_shift
);
629 l1_ste_offset
= sid
>> s
->sid_split
;
630 l2_ste_offset
= sid
& ((1 << s
->sid_split
) - 1);
631 l1ptr
= (dma_addr_t
)(strtab_base
+ l1_ste_offset
* sizeof(l1std
));
632 /* TODO: guarantee 64-bit single-copy atomicity */
633 ret
= dma_memory_read(&address_space_memory
, l1ptr
, &l1std
,
634 sizeof(l1std
), MEMTXATTRS_UNSPECIFIED
);
635 if (ret
!= MEMTX_OK
) {
636 qemu_log_mask(LOG_GUEST_ERROR
,
637 "Could not read L1PTR at 0X%"PRIx64
"\n", l1ptr
);
638 event
->type
= SMMU_EVT_F_STE_FETCH
;
639 event
->u
.f_ste_fetch
.addr
= l1ptr
;
642 for (i
= 0; i
< ARRAY_SIZE(l1std
.word
); i
++) {
643 le32_to_cpus(&l1std
.word
[i
]);
646 span
= L1STD_SPAN(&l1std
);
649 /* l2ptr is not valid */
650 if (!event
->inval_ste_allowed
) {
651 qemu_log_mask(LOG_GUEST_ERROR
,
652 "invalid sid=%d (L1STD span=0)\n", sid
);
654 event
->type
= SMMU_EVT_C_BAD_STREAMID
;
657 max_l2_ste
= (1 << span
) - 1;
658 l2ptr
= l1std_l2ptr(&l1std
);
659 trace_smmuv3_find_ste_2lvl(s
->strtab_base
, l1ptr
, l1_ste_offset
,
660 l2ptr
, l2_ste_offset
, max_l2_ste
);
661 if (l2_ste_offset
> max_l2_ste
) {
662 qemu_log_mask(LOG_GUEST_ERROR
,
663 "l2_ste_offset=%d > max_l2_ste=%d\n",
664 l2_ste_offset
, max_l2_ste
);
665 event
->type
= SMMU_EVT_C_BAD_STE
;
668 addr
= l2ptr
+ l2_ste_offset
* sizeof(*ste
);
670 strtab_size_shift
= log2size
+ 5;
671 strtab_base
= s
->strtab_base
& SMMU_BASE_ADDR_MASK
&
672 ~MAKE_64BIT_MASK(0, strtab_size_shift
);
673 addr
= strtab_base
+ sid
* sizeof(*ste
);
676 if (smmu_get_ste(s
, addr
, ste
, event
)) {
683 static int decode_cd(SMMUv3State
*s
, SMMUTransCfg
*cfg
,
684 CD
*cd
, SMMUEventInfo
*event
)
688 SMMUTranslationStatus status
;
691 if (!CD_VALID(cd
) || !CD_AARCH64(cd
)) {
695 goto bad_cd
; /* SMMU_IDR0.TERM_MODEL == 1 */
698 goto bad_cd
; /* !STE_SECURE && SMMU_IDR0.STALL_MODEL == 1 */
700 if (CD_HA(cd
) || CD_HD(cd
)) {
701 goto bad_cd
; /* HTTU = 0 */
704 /* we support only those at the moment */
706 cfg
->stage
= SMMU_STAGE_1
;
708 cfg
->oas
= oas2bits(CD_IPS(cd
));
709 cfg
->oas
= MIN(oas2bits(SMMU_IDR5_OAS
), cfg
->oas
);
710 cfg
->tbi
= CD_TBI(cd
);
711 cfg
->asid
= CD_ASID(cd
);
712 cfg
->affd
= CD_AFFD(cd
);
714 trace_smmuv3_decode_cd(cfg
->oas
);
716 /* decode data dependent on TT */
717 for (i
= 0; i
<= 1; i
++) {
719 SMMUTransTableInfo
*tt
= &cfg
->tt
[i
];
721 cfg
->tt
[i
].disabled
= CD_EPD(cd
, i
);
722 if (cfg
->tt
[i
].disabled
) {
727 if (tsz
< 16 || tsz
> 39) {
732 tt
->granule_sz
= tg2granule(tg
, i
);
733 if ((tt
->granule_sz
!= 12 && tt
->granule_sz
!= 14 &&
734 tt
->granule_sz
!= 16) || CD_ENDI(cd
)) {
739 tt
->ttb
= CD_TTB(cd
, i
);
741 if (tt
->ttb
& ~(MAKE_64BIT_MASK(0, cfg
->oas
))) {
745 /* Translate the TTBx, from IPA to PA if nesting is enabled. */
746 if (cfg
->stage
== SMMU_NESTED
) {
747 status
= smmuv3_do_translate(s
, tt
->ttb
, cfg
, event
, IOMMU_RO
,
748 &entry
, SMMU_CLASS_TT
);
750 * Same PTW faults are reported but with CLASS = TT.
751 * If TTBx is larger than the effective stage 1 output addres
752 * size, it reports C_BAD_CD, which is handled by the above case.
754 if (status
!= SMMU_TRANS_SUCCESS
) {
757 tt
->ttb
= CACHED_ENTRY_TO_ADDR(entry
, tt
->ttb
);
760 tt
->had
= CD_HAD(cd
, i
);
761 trace_smmuv3_decode_cd_tt(i
, tt
->tsz
, tt
->ttb
, tt
->granule_sz
, tt
->had
);
764 cfg
->record_faults
= CD_R(cd
);
769 event
->type
= SMMU_EVT_C_BAD_CD
;
774 * smmuv3_decode_config - Prepare the translation configuration
775 * for the @mr iommu region
776 * @mr: iommu memory region the translation config must be prepared for
777 * @cfg: output translation configuration which is populated through
778 * the different configuration decoding steps
779 * @event: must be zero'ed by the caller
781 * return < 0 in case of config decoding error (@event is filled
782 * accordingly). Return 0 otherwise.
784 static int smmuv3_decode_config(IOMMUMemoryRegion
*mr
, SMMUTransCfg
*cfg
,
785 SMMUEventInfo
*event
)
787 SMMUDevice
*sdev
= container_of(mr
, SMMUDevice
, iommu
);
788 uint32_t sid
= smmu_get_sid(sdev
);
789 SMMUv3State
*s
= sdev
->smmu
;
794 /* ASID defaults to -1 (if s1 is not supported). */
797 ret
= smmu_find_ste(s
, sid
, &ste
, event
);
802 ret
= decode_ste(s
, cfg
, &ste
, event
);
807 if (cfg
->aborted
|| cfg
->bypassed
|| (cfg
->stage
== SMMU_STAGE_2
)) {
811 ret
= smmu_get_cd(s
, &ste
, cfg
, 0 /* ssid */, &cd
, event
);
816 return decode_cd(s
, cfg
, &cd
, event
);
820 * smmuv3_get_config - Look up for a cached copy of configuration data for
821 * @sdev and on cache miss performs a configuration structure decoding from
824 * @sdev: SMMUDevice handle
825 * @event: output event info
827 * The configuration cache contains data resulting from both STE and CD
828 * decoding under the form of an SMMUTransCfg struct. The hash table is indexed
829 * by the SMMUDevice handle.
831 static SMMUTransCfg
*smmuv3_get_config(SMMUDevice
*sdev
, SMMUEventInfo
*event
)
833 SMMUv3State
*s
= sdev
->smmu
;
834 SMMUState
*bc
= &s
->smmu_state
;
837 cfg
= g_hash_table_lookup(bc
->configs
, sdev
);
839 sdev
->cfg_cache_hits
++;
840 trace_smmuv3_config_cache_hit(smmu_get_sid(sdev
),
841 sdev
->cfg_cache_hits
, sdev
->cfg_cache_misses
,
842 100 * sdev
->cfg_cache_hits
/
843 (sdev
->cfg_cache_hits
+ sdev
->cfg_cache_misses
));
845 sdev
->cfg_cache_misses
++;
846 trace_smmuv3_config_cache_miss(smmu_get_sid(sdev
),
847 sdev
->cfg_cache_hits
, sdev
->cfg_cache_misses
,
848 100 * sdev
->cfg_cache_hits
/
849 (sdev
->cfg_cache_hits
+ sdev
->cfg_cache_misses
));
850 cfg
= g_new0(SMMUTransCfg
, 1);
852 if (!smmuv3_decode_config(&sdev
->iommu
, cfg
, event
)) {
853 g_hash_table_insert(bc
->configs
, sdev
, cfg
);
862 static void smmuv3_flush_config(SMMUDevice
*sdev
)
864 SMMUv3State
*s
= sdev
->smmu
;
865 SMMUState
*bc
= &s
->smmu_state
;
867 trace_smmuv3_config_cache_inv(smmu_get_sid(sdev
));
868 g_hash_table_remove(bc
->configs
, sdev
);
871 /* Do translation with TLB lookup. */
872 static SMMUTranslationStatus
smmuv3_do_translate(SMMUv3State
*s
, hwaddr addr
,
874 SMMUEventInfo
*event
,
875 IOMMUAccessFlags flag
,
876 SMMUTLBEntry
**out_entry
,
877 SMMUTranslationClass
class)
879 SMMUPTWEventInfo ptw_info
= {};
880 SMMUState
*bs
= ARM_SMMU(s
);
881 SMMUTLBEntry
*cached_entry
= NULL
;
883 bool desc_s2_translation
= class != SMMU_CLASS_IN
;
886 * The function uses the argument class to identify which stage is used:
887 * - CLASS = IN: Means an input translation, determine the stage from STE.
888 * - CLASS = CD: Means the addr is an IPA of the CD, and it would be
889 * translated using the stage-2.
890 * - CLASS = TT: Means the addr is an IPA of the stage-1 translation table
891 * and it would be translated using the stage-2.
892 * For the last 2 cases instead of having intrusive changes in the common
893 * logic, we modify the cfg to be a stage-2 translation only in case of
894 * nested, and then restore it after.
896 if (desc_s2_translation
) {
900 cfg
->stage
= SMMU_STAGE_2
;
903 cached_entry
= smmu_translate(bs
, cfg
, addr
, flag
, &ptw_info
);
905 if (desc_s2_translation
) {
911 /* All faults from PTW has S2 field. */
912 event
->u
.f_walk_eabt
.s2
= (ptw_info
.stage
== SMMU_STAGE_2
);
914 * Fault class is set as follows based on "class" input to
915 * the function and to "ptw_info" from "smmu_translate()"
917 * - EABT => CLASS_TT (hardcoded)
918 * - other events => CLASS_IN (input to function)
919 * For stage-2 => CLASS_IN (input to function)
920 * For nested, for all events:
921 * - CD fetch => CLASS_CD (input to function)
922 * - walking stage 1 translation table => CLASS_TT (from
923 * is_ipa_descriptor or input in case of TTBx)
924 * - s2 translation => CLASS_IN (input to function)
926 class = ptw_info
.is_ipa_descriptor
? SMMU_CLASS_TT
: class;
927 switch (ptw_info
.type
) {
928 case SMMU_PTW_ERR_WALK_EABT
:
929 event
->type
= SMMU_EVT_F_WALK_EABT
;
930 event
->u
.f_walk_eabt
.rnw
= flag
& 0x1;
931 event
->u
.f_walk_eabt
.class = (ptw_info
.stage
== SMMU_STAGE_2
) ?
932 class : SMMU_CLASS_TT
;
933 event
->u
.f_walk_eabt
.addr2
= ptw_info
.addr
;
935 case SMMU_PTW_ERR_TRANSLATION
:
936 if (PTW_RECORD_FAULT(cfg
)) {
937 event
->type
= SMMU_EVT_F_TRANSLATION
;
938 event
->u
.f_translation
.addr2
= ptw_info
.addr
;
939 event
->u
.f_translation
.class = class;
940 event
->u
.f_translation
.rnw
= flag
& 0x1;
943 case SMMU_PTW_ERR_ADDR_SIZE
:
944 if (PTW_RECORD_FAULT(cfg
)) {
945 event
->type
= SMMU_EVT_F_ADDR_SIZE
;
946 event
->u
.f_addr_size
.addr2
= ptw_info
.addr
;
947 event
->u
.f_addr_size
.class = class;
948 event
->u
.f_addr_size
.rnw
= flag
& 0x1;
951 case SMMU_PTW_ERR_ACCESS
:
952 if (PTW_RECORD_FAULT(cfg
)) {
953 event
->type
= SMMU_EVT_F_ACCESS
;
954 event
->u
.f_access
.addr2
= ptw_info
.addr
;
955 event
->u
.f_access
.class = class;
956 event
->u
.f_access
.rnw
= flag
& 0x1;
959 case SMMU_PTW_ERR_PERMISSION
:
960 if (PTW_RECORD_FAULT(cfg
)) {
961 event
->type
= SMMU_EVT_F_PERMISSION
;
962 event
->u
.f_permission
.addr2
= ptw_info
.addr
;
963 event
->u
.f_permission
.class = class;
964 event
->u
.f_permission
.rnw
= flag
& 0x1;
968 g_assert_not_reached();
970 return SMMU_TRANS_ERROR
;
972 *out_entry
= cached_entry
;
973 return SMMU_TRANS_SUCCESS
;
977 * Sets the InputAddr for an SMMU_TRANS_ERROR, as it can't be
978 * set from all contexts, as smmuv3_get_config() can return
979 * translation faults in case of nested translation (for CD
980 * and TTBx). But in that case the iova is not known.
982 static void smmuv3_fixup_event(SMMUEventInfo
*event
, hwaddr iova
)
984 switch (event
->type
) {
985 case SMMU_EVT_F_WALK_EABT
:
986 case SMMU_EVT_F_TRANSLATION
:
987 case SMMU_EVT_F_ADDR_SIZE
:
988 case SMMU_EVT_F_ACCESS
:
989 case SMMU_EVT_F_PERMISSION
:
990 event
->u
.f_walk_eabt
.addr
= iova
;
997 /* Entry point to SMMU, does everything. */
998 static IOMMUTLBEntry
smmuv3_translate(IOMMUMemoryRegion
*mr
, hwaddr addr
,
999 IOMMUAccessFlags flag
, int iommu_idx
)
1001 SMMUDevice
*sdev
= container_of(mr
, SMMUDevice
, iommu
);
1002 SMMUv3State
*s
= sdev
->smmu
;
1003 uint32_t sid
= smmu_get_sid(sdev
);
1004 SMMUEventInfo event
= {.type
= SMMU_EVT_NONE
,
1006 .inval_ste_allowed
= false};
1007 SMMUTranslationStatus status
;
1008 SMMUTransCfg
*cfg
= NULL
;
1009 IOMMUTLBEntry entry
= {
1010 .target_as
= &address_space_memory
,
1012 .translated_addr
= addr
,
1013 .addr_mask
= ~(hwaddr
)0,
1016 SMMUTLBEntry
*cached_entry
= NULL
;
1018 qemu_mutex_lock(&s
->mutex
);
1020 if (!smmu_enabled(s
)) {
1021 if (FIELD_EX32(s
->gbpa
, GBPA
, ABORT
)) {
1022 status
= SMMU_TRANS_ABORT
;
1024 status
= SMMU_TRANS_DISABLE
;
1029 cfg
= smmuv3_get_config(sdev
, &event
);
1031 status
= SMMU_TRANS_ERROR
;
1036 status
= SMMU_TRANS_ABORT
;
1040 if (cfg
->bypassed
) {
1041 status
= SMMU_TRANS_BYPASS
;
1045 status
= smmuv3_do_translate(s
, addr
, cfg
, &event
, flag
,
1046 &cached_entry
, SMMU_CLASS_IN
);
1049 qemu_mutex_unlock(&s
->mutex
);
1051 case SMMU_TRANS_SUCCESS
:
1052 entry
.perm
= cached_entry
->entry
.perm
;
1053 entry
.translated_addr
= CACHED_ENTRY_TO_ADDR(cached_entry
, addr
);
1054 entry
.addr_mask
= cached_entry
->entry
.addr_mask
;
1055 trace_smmuv3_translate_success(mr
->parent_obj
.name
, sid
, addr
,
1056 entry
.translated_addr
, entry
.perm
,
1059 case SMMU_TRANS_DISABLE
:
1061 entry
.addr_mask
= ~TARGET_PAGE_MASK
;
1062 trace_smmuv3_translate_disable(mr
->parent_obj
.name
, sid
, addr
,
1065 case SMMU_TRANS_BYPASS
:
1067 entry
.addr_mask
= ~TARGET_PAGE_MASK
;
1068 trace_smmuv3_translate_bypass(mr
->parent_obj
.name
, sid
, addr
,
1071 case SMMU_TRANS_ABORT
:
1072 /* no event is recorded on abort */
1073 trace_smmuv3_translate_abort(mr
->parent_obj
.name
, sid
, addr
,
1076 case SMMU_TRANS_ERROR
:
1077 smmuv3_fixup_event(&event
, addr
);
1078 qemu_log_mask(LOG_GUEST_ERROR
,
1079 "%s translation failed for iova=0x%"PRIx64
" (%s)\n",
1080 mr
->parent_obj
.name
, addr
, smmu_event_string(event
.type
));
1081 smmuv3_record_event(s
, &event
);
1089 * smmuv3_notify_iova - call the notifier @n for a given
1090 * @asid and @iova tuple.
1092 * @mr: IOMMU mr region handle
1093 * @n: notifier to be called
1094 * @asid: address space ID or negative value if we don't care
1095 * @vmid: virtual machine ID or negative value if we don't care
1097 * @tg: translation granule (if communicated through range invalidation)
1098 * @num_pages: number of @granule sized pages (if tg != 0), otherwise 1
1099 * @stage: Which stage(1 or 2) is used
1101 static void smmuv3_notify_iova(IOMMUMemoryRegion
*mr
,
1104 dma_addr_t iova
, uint8_t tg
,
1105 uint64_t num_pages
, int stage
)
1107 SMMUDevice
*sdev
= container_of(mr
, SMMUDevice
, iommu
);
1108 SMMUEventInfo eventinfo
= {.inval_ste_allowed
= true};
1109 SMMUTransCfg
*cfg
= smmuv3_get_config(sdev
, &eventinfo
);
1110 IOMMUTLBEvent event
;
1118 * stage is passed from TLB invalidation commands which can be either
1119 * stage-1 or stage-2.
1120 * However, IOMMUTLBEvent only understands IOVA, for stage-1 or stage-2
1121 * SMMU instances we consider the input address as the IOVA, but when
1122 * nesting is used, we can't mix stage-1 and stage-2 addresses, so for
1123 * nesting only stage-1 is considered the IOVA and would be notified.
1125 if ((stage
== SMMU_STAGE_2
) && (cfg
->stage
== SMMU_NESTED
))
1129 SMMUTransTableInfo
*tt
;
1131 if (asid
>= 0 && cfg
->asid
!= asid
) {
1135 if (vmid
>= 0 && cfg
->s2cfg
.vmid
!= vmid
) {
1139 if (stage
== SMMU_STAGE_1
) {
1140 tt
= select_tt(cfg
, iova
);
1144 granule
= tt
->granule_sz
;
1146 granule
= cfg
->s2cfg
.granule_sz
;
1150 granule
= tg
* 2 + 10;
1153 event
.type
= IOMMU_NOTIFIER_UNMAP
;
1154 event
.entry
.target_as
= &address_space_memory
;
1155 event
.entry
.iova
= iova
;
1156 event
.entry
.addr_mask
= num_pages
* (1 << granule
) - 1;
1157 event
.entry
.perm
= IOMMU_NONE
;
1159 memory_region_notify_iommu_one(n
, &event
);
1162 /* invalidate an asid/vmid/iova range tuple in all mr's */
1163 static void smmuv3_inv_notifiers_iova(SMMUState
*s
, int asid
, int vmid
,
1164 dma_addr_t iova
, uint8_t tg
,
1165 uint64_t num_pages
, int stage
)
1169 QLIST_FOREACH(sdev
, &s
->devices_with_notifiers
, next
) {
1170 IOMMUMemoryRegion
*mr
= &sdev
->iommu
;
1173 trace_smmuv3_inv_notifiers_iova(mr
->parent_obj
.name
, asid
, vmid
,
1174 iova
, tg
, num_pages
, stage
);
1176 IOMMU_NOTIFIER_FOREACH(n
, mr
) {
1177 smmuv3_notify_iova(mr
, n
, asid
, vmid
, iova
, tg
, num_pages
, stage
);
1182 static void smmuv3_range_inval(SMMUState
*s
, Cmd
*cmd
, SMMUStage stage
)
1184 dma_addr_t end
, addr
= CMD_ADDR(cmd
);
1185 uint8_t type
= CMD_TYPE(cmd
);
1187 uint8_t scale
= CMD_SCALE(cmd
);
1188 uint8_t num
= CMD_NUM(cmd
);
1189 uint8_t ttl
= CMD_TTL(cmd
);
1190 bool leaf
= CMD_LEAF(cmd
);
1191 uint8_t tg
= CMD_TG(cmd
);
1195 SMMUv3State
*smmuv3
= ARM_SMMUV3(s
);
1197 /* Only consider VMID if stage-2 is supported. */
1198 if (STAGE2_SUPPORTED(smmuv3
)) {
1199 vmid
= CMD_VMID(cmd
);
1202 if (type
== SMMU_CMD_TLBI_NH_VA
) {
1203 asid
= CMD_ASID(cmd
);
1207 trace_smmuv3_range_inval(vmid
, asid
, addr
, tg
, 1, ttl
, leaf
, stage
);
1208 smmuv3_inv_notifiers_iova(s
, asid
, vmid
, addr
, tg
, 1, stage
);
1209 if (stage
== SMMU_STAGE_1
) {
1210 smmu_iotlb_inv_iova(s
, asid
, vmid
, addr
, tg
, 1, ttl
);
1212 smmu_iotlb_inv_ipa(s
, vmid
, addr
, tg
, 1, ttl
);
1219 num_pages
= (num
+ 1) * BIT_ULL(scale
);
1220 granule
= tg
* 2 + 10;
1222 /* Split invalidations into ^2 range invalidations */
1223 end
= addr
+ (num_pages
<< granule
) - 1;
1225 while (addr
!= end
+ 1) {
1226 uint64_t mask
= dma_aligned_pow2_mask(addr
, end
, 64);
1228 num_pages
= (mask
+ 1) >> granule
;
1229 trace_smmuv3_range_inval(vmid
, asid
, addr
, tg
, num_pages
,
1231 smmuv3_inv_notifiers_iova(s
, asid
, vmid
, addr
, tg
, num_pages
, stage
);
1232 if (stage
== SMMU_STAGE_1
) {
1233 smmu_iotlb_inv_iova(s
, asid
, vmid
, addr
, tg
, num_pages
, ttl
);
1235 smmu_iotlb_inv_ipa(s
, vmid
, addr
, tg
, num_pages
, ttl
);
1242 smmuv3_invalidate_ste(gpointer key
, gpointer value
, gpointer user_data
)
1244 SMMUDevice
*sdev
= (SMMUDevice
*)key
;
1245 uint32_t sid
= smmu_get_sid(sdev
);
1246 SMMUSIDRange
*sid_range
= (SMMUSIDRange
*)user_data
;
1248 if (sid
< sid_range
->start
|| sid
> sid_range
->end
) {
1251 trace_smmuv3_config_cache_inv(sid
);
1255 static int smmuv3_cmdq_consume(SMMUv3State
*s
)
1257 SMMUState
*bs
= ARM_SMMU(s
);
1258 SMMUCmdError cmd_error
= SMMU_CERROR_NONE
;
1259 SMMUQueue
*q
= &s
->cmdq
;
1260 SMMUCommandType type
= 0;
1262 if (!smmuv3_cmdq_enabled(s
)) {
1266 * some commands depend on register values, typically CR0. In case those
1267 * register values change while handling the command, spec says it
1268 * is UNPREDICTABLE whether the command is interpreted under the new
1272 while (!smmuv3_q_empty(q
)) {
1273 uint32_t pending
= s
->gerror
^ s
->gerrorn
;
1276 trace_smmuv3_cmdq_consume(Q_PROD(q
), Q_CONS(q
),
1277 Q_PROD_WRAP(q
), Q_CONS_WRAP(q
));
1279 if (FIELD_EX32(pending
, GERROR
, CMDQ_ERR
)) {
1283 if (queue_read(q
, &cmd
) != MEMTX_OK
) {
1284 cmd_error
= SMMU_CERROR_ABT
;
1288 type
= CMD_TYPE(&cmd
);
1290 trace_smmuv3_cmdq_opcode(smmu_cmd_string(type
));
1292 qemu_mutex_lock(&s
->mutex
);
1295 if (CMD_SYNC_CS(&cmd
) & CMD_SYNC_SIG_IRQ
) {
1296 smmuv3_trigger_irq(s
, SMMU_IRQ_CMD_SYNC
, 0);
1299 case SMMU_CMD_PREFETCH_CONFIG
:
1300 case SMMU_CMD_PREFETCH_ADDR
:
1302 case SMMU_CMD_CFGI_STE
:
1304 uint32_t sid
= CMD_SID(&cmd
);
1305 SMMUDevice
*sdev
= smmu_find_sdev(bs
, sid
);
1307 if (CMD_SSEC(&cmd
)) {
1308 cmd_error
= SMMU_CERROR_ILL
;
1316 trace_smmuv3_cmdq_cfgi_ste(sid
);
1317 smmuv3_flush_config(sdev
);
1321 case SMMU_CMD_CFGI_STE_RANGE
: /* same as SMMU_CMD_CFGI_ALL */
1323 uint32_t sid
= CMD_SID(&cmd
), mask
;
1324 uint8_t range
= CMD_STE_RANGE(&cmd
);
1325 SMMUSIDRange sid_range
;
1327 if (CMD_SSEC(&cmd
)) {
1328 cmd_error
= SMMU_CERROR_ILL
;
1332 mask
= (1ULL << (range
+ 1)) - 1;
1333 sid_range
.start
= sid
& ~mask
;
1334 sid_range
.end
= sid_range
.start
+ mask
;
1336 trace_smmuv3_cmdq_cfgi_ste_range(sid_range
.start
, sid_range
.end
);
1337 g_hash_table_foreach_remove(bs
->configs
, smmuv3_invalidate_ste
,
1341 case SMMU_CMD_CFGI_CD
:
1342 case SMMU_CMD_CFGI_CD_ALL
:
1344 uint32_t sid
= CMD_SID(&cmd
);
1345 SMMUDevice
*sdev
= smmu_find_sdev(bs
, sid
);
1347 if (CMD_SSEC(&cmd
)) {
1348 cmd_error
= SMMU_CERROR_ILL
;
1356 trace_smmuv3_cmdq_cfgi_cd(sid
);
1357 smmuv3_flush_config(sdev
);
1360 case SMMU_CMD_TLBI_NH_ASID
:
1362 int asid
= CMD_ASID(&cmd
);
1365 if (!STAGE1_SUPPORTED(s
)) {
1366 cmd_error
= SMMU_CERROR_ILL
;
1371 * VMID is only matched when stage 2 is supported, otherwise set it
1372 * to -1 as the value used for stage-1 only VMIDs.
1374 if (STAGE2_SUPPORTED(s
)) {
1375 vmid
= CMD_VMID(&cmd
);
1378 trace_smmuv3_cmdq_tlbi_nh_asid(asid
);
1379 smmu_inv_notifiers_all(&s
->smmu_state
);
1380 smmu_iotlb_inv_asid_vmid(bs
, asid
, vmid
);
1383 case SMMU_CMD_TLBI_NH_ALL
:
1387 if (!STAGE1_SUPPORTED(s
)) {
1388 cmd_error
= SMMU_CERROR_ILL
;
1393 * If stage-2 is supported, invalidate for this VMID only, otherwise
1394 * invalidate the whole thing.
1396 if (STAGE2_SUPPORTED(s
)) {
1397 vmid
= CMD_VMID(&cmd
);
1398 trace_smmuv3_cmdq_tlbi_nh(vmid
);
1399 smmu_iotlb_inv_vmid_s1(bs
, vmid
);
1404 case SMMU_CMD_TLBI_NSNH_ALL
:
1405 trace_smmuv3_cmdq_tlbi_nsnh();
1406 smmu_inv_notifiers_all(&s
->smmu_state
);
1407 smmu_iotlb_inv_all(bs
);
1409 case SMMU_CMD_TLBI_NH_VAA
:
1410 case SMMU_CMD_TLBI_NH_VA
:
1411 if (!STAGE1_SUPPORTED(s
)) {
1412 cmd_error
= SMMU_CERROR_ILL
;
1415 smmuv3_range_inval(bs
, &cmd
, SMMU_STAGE_1
);
1417 case SMMU_CMD_TLBI_S12_VMALL
:
1419 int vmid
= CMD_VMID(&cmd
);
1421 if (!STAGE2_SUPPORTED(s
)) {
1422 cmd_error
= SMMU_CERROR_ILL
;
1426 trace_smmuv3_cmdq_tlbi_s12_vmid(vmid
);
1427 smmu_inv_notifiers_all(&s
->smmu_state
);
1428 smmu_iotlb_inv_vmid(bs
, vmid
);
1431 case SMMU_CMD_TLBI_S2_IPA
:
1432 if (!STAGE2_SUPPORTED(s
)) {
1433 cmd_error
= SMMU_CERROR_ILL
;
1437 * As currently only either s1 or s2 are supported
1438 * we can reuse same function for s2.
1440 smmuv3_range_inval(bs
, &cmd
, SMMU_STAGE_2
);
1442 case SMMU_CMD_TLBI_EL3_ALL
:
1443 case SMMU_CMD_TLBI_EL3_VA
:
1444 case SMMU_CMD_TLBI_EL2_ALL
:
1445 case SMMU_CMD_TLBI_EL2_ASID
:
1446 case SMMU_CMD_TLBI_EL2_VA
:
1447 case SMMU_CMD_TLBI_EL2_VAA
:
1448 case SMMU_CMD_ATC_INV
:
1449 case SMMU_CMD_PRI_RESP
:
1450 case SMMU_CMD_RESUME
:
1451 case SMMU_CMD_STALL_TERM
:
1452 trace_smmuv3_unhandled_cmd(type
);
1455 cmd_error
= SMMU_CERROR_ILL
;
1458 qemu_mutex_unlock(&s
->mutex
);
1460 if (cmd_error
== SMMU_CERROR_ILL
) {
1461 qemu_log_mask(LOG_GUEST_ERROR
,
1462 "Illegal command type: %d\n", CMD_TYPE(&cmd
));
1467 * We only increment the cons index after the completion of
1468 * the command. We do that because the SYNC returns immediately
1469 * and does not check the completion of previous commands
1475 trace_smmuv3_cmdq_consume_error(smmu_cmd_string(type
), cmd_error
);
1476 smmu_write_cmdq_err(s
, cmd_error
);
1477 smmuv3_trigger_irq(s
, SMMU_IRQ_GERROR
, R_GERROR_CMDQ_ERR_MASK
);
1480 trace_smmuv3_cmdq_consume_out(Q_PROD(q
), Q_CONS(q
),
1481 Q_PROD_WRAP(q
), Q_CONS_WRAP(q
));
1486 static MemTxResult
smmu_writell(SMMUv3State
*s
, hwaddr offset
,
1487 uint64_t data
, MemTxAttrs attrs
)
1490 case A_GERROR_IRQ_CFG0
:
1491 s
->gerror_irq_cfg0
= data
;
1494 s
->strtab_base
= data
;
1497 s
->cmdq
.base
= data
;
1498 s
->cmdq
.log2size
= extract64(s
->cmdq
.base
, 0, 5);
1499 if (s
->cmdq
.log2size
> SMMU_CMDQS
) {
1500 s
->cmdq
.log2size
= SMMU_CMDQS
;
1504 s
->eventq
.base
= data
;
1505 s
->eventq
.log2size
= extract64(s
->eventq
.base
, 0, 5);
1506 if (s
->eventq
.log2size
> SMMU_EVENTQS
) {
1507 s
->eventq
.log2size
= SMMU_EVENTQS
;
1510 case A_EVENTQ_IRQ_CFG0
:
1511 s
->eventq_irq_cfg0
= data
;
1514 qemu_log_mask(LOG_UNIMP
,
1515 "%s Unexpected 64-bit access to 0x%"PRIx64
" (WI)\n",
1521 static MemTxResult
smmu_writel(SMMUv3State
*s
, hwaddr offset
,
1522 uint64_t data
, MemTxAttrs attrs
)
1527 s
->cr0ack
= data
& ~SMMU_CR0_RESERVED
;
1528 /* in case the command queue has been enabled */
1529 smmuv3_cmdq_consume(s
);
1541 smmuv3_write_gerrorn(s
, data
);
1543 * By acknowledging the CMDQ_ERR, SW may notify cmds can
1544 * be processed again
1546 smmuv3_cmdq_consume(s
);
1548 case A_GERROR_IRQ_CFG0
: /* 64b */
1549 s
->gerror_irq_cfg0
= deposit64(s
->gerror_irq_cfg0
, 0, 32, data
);
1551 case A_GERROR_IRQ_CFG0
+ 4:
1552 s
->gerror_irq_cfg0
= deposit64(s
->gerror_irq_cfg0
, 32, 32, data
);
1554 case A_GERROR_IRQ_CFG1
:
1555 s
->gerror_irq_cfg1
= data
;
1557 case A_GERROR_IRQ_CFG2
:
1558 s
->gerror_irq_cfg2
= data
;
1562 * If UPDATE is not set, the write is ignored. This is the only
1563 * permitted behavior in SMMUv3.2 and later.
1565 if (data
& R_GBPA_UPDATE_MASK
) {
1566 /* Ignore update bit as write is synchronous. */
1567 s
->gbpa
= data
& ~R_GBPA_UPDATE_MASK
;
1570 case A_STRTAB_BASE
: /* 64b */
1571 s
->strtab_base
= deposit64(s
->strtab_base
, 0, 32, data
);
1573 case A_STRTAB_BASE
+ 4:
1574 s
->strtab_base
= deposit64(s
->strtab_base
, 32, 32, data
);
1576 case A_STRTAB_BASE_CFG
:
1577 s
->strtab_base_cfg
= data
;
1578 if (FIELD_EX32(data
, STRTAB_BASE_CFG
, FMT
) == 1) {
1579 s
->sid_split
= FIELD_EX32(data
, STRTAB_BASE_CFG
, SPLIT
);
1580 s
->features
|= SMMU_FEATURE_2LVL_STE
;
1583 case A_CMDQ_BASE
: /* 64b */
1584 s
->cmdq
.base
= deposit64(s
->cmdq
.base
, 0, 32, data
);
1585 s
->cmdq
.log2size
= extract64(s
->cmdq
.base
, 0, 5);
1586 if (s
->cmdq
.log2size
> SMMU_CMDQS
) {
1587 s
->cmdq
.log2size
= SMMU_CMDQS
;
1590 case A_CMDQ_BASE
+ 4: /* 64b */
1591 s
->cmdq
.base
= deposit64(s
->cmdq
.base
, 32, 32, data
);
1594 s
->cmdq
.prod
= data
;
1595 smmuv3_cmdq_consume(s
);
1598 s
->cmdq
.cons
= data
;
1600 case A_EVENTQ_BASE
: /* 64b */
1601 s
->eventq
.base
= deposit64(s
->eventq
.base
, 0, 32, data
);
1602 s
->eventq
.log2size
= extract64(s
->eventq
.base
, 0, 5);
1603 if (s
->eventq
.log2size
> SMMU_EVENTQS
) {
1604 s
->eventq
.log2size
= SMMU_EVENTQS
;
1607 case A_EVENTQ_BASE
+ 4:
1608 s
->eventq
.base
= deposit64(s
->eventq
.base
, 32, 32, data
);
1611 s
->eventq
.prod
= data
;
1614 s
->eventq
.cons
= data
;
1616 case A_EVENTQ_IRQ_CFG0
: /* 64b */
1617 s
->eventq_irq_cfg0
= deposit64(s
->eventq_irq_cfg0
, 0, 32, data
);
1619 case A_EVENTQ_IRQ_CFG0
+ 4:
1620 s
->eventq_irq_cfg0
= deposit64(s
->eventq_irq_cfg0
, 32, 32, data
);
1622 case A_EVENTQ_IRQ_CFG1
:
1623 s
->eventq_irq_cfg1
= data
;
1625 case A_EVENTQ_IRQ_CFG2
:
1626 s
->eventq_irq_cfg2
= data
;
1629 qemu_log_mask(LOG_UNIMP
,
1630 "%s Unexpected 32-bit access to 0x%"PRIx64
" (WI)\n",
1636 static MemTxResult
smmu_write_mmio(void *opaque
, hwaddr offset
, uint64_t data
,
1637 unsigned size
, MemTxAttrs attrs
)
1639 SMMUState
*sys
= opaque
;
1640 SMMUv3State
*s
= ARM_SMMUV3(sys
);
1643 /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */
1648 r
= smmu_writell(s
, offset
, data
, attrs
);
1651 r
= smmu_writel(s
, offset
, data
, attrs
);
1658 trace_smmuv3_write_mmio(offset
, data
, size
, r
);
1662 static MemTxResult
smmu_readll(SMMUv3State
*s
, hwaddr offset
,
1663 uint64_t *data
, MemTxAttrs attrs
)
1666 case A_GERROR_IRQ_CFG0
:
1667 *data
= s
->gerror_irq_cfg0
;
1670 *data
= s
->strtab_base
;
1673 *data
= s
->cmdq
.base
;
1676 *data
= s
->eventq
.base
;
1680 qemu_log_mask(LOG_UNIMP
,
1681 "%s Unexpected 64-bit access to 0x%"PRIx64
" (RAZ)\n",
1687 static MemTxResult
smmu_readl(SMMUv3State
*s
, hwaddr offset
,
1688 uint64_t *data
, MemTxAttrs attrs
)
1691 case A_IDREGS
... A_IDREGS
+ 0x2f:
1692 *data
= smmuv3_idreg(offset
- A_IDREGS
);
1694 case A_IDR0
... A_IDR5
:
1695 *data
= s
->idr
[(offset
- A_IDR0
) / 4];
1722 case A_IRQ_CTRL_ACK
:
1723 *data
= s
->irq_ctrl
;
1731 case A_GERROR_IRQ_CFG0
: /* 64b */
1732 *data
= extract64(s
->gerror_irq_cfg0
, 0, 32);
1734 case A_GERROR_IRQ_CFG0
+ 4:
1735 *data
= extract64(s
->gerror_irq_cfg0
, 32, 32);
1737 case A_GERROR_IRQ_CFG1
:
1738 *data
= s
->gerror_irq_cfg1
;
1740 case A_GERROR_IRQ_CFG2
:
1741 *data
= s
->gerror_irq_cfg2
;
1743 case A_STRTAB_BASE
: /* 64b */
1744 *data
= extract64(s
->strtab_base
, 0, 32);
1746 case A_STRTAB_BASE
+ 4: /* 64b */
1747 *data
= extract64(s
->strtab_base
, 32, 32);
1749 case A_STRTAB_BASE_CFG
:
1750 *data
= s
->strtab_base_cfg
;
1752 case A_CMDQ_BASE
: /* 64b */
1753 *data
= extract64(s
->cmdq
.base
, 0, 32);
1755 case A_CMDQ_BASE
+ 4:
1756 *data
= extract64(s
->cmdq
.base
, 32, 32);
1759 *data
= s
->cmdq
.prod
;
1762 *data
= s
->cmdq
.cons
;
1764 case A_EVENTQ_BASE
: /* 64b */
1765 *data
= extract64(s
->eventq
.base
, 0, 32);
1767 case A_EVENTQ_BASE
+ 4: /* 64b */
1768 *data
= extract64(s
->eventq
.base
, 32, 32);
1771 *data
= s
->eventq
.prod
;
1774 *data
= s
->eventq
.cons
;
1778 qemu_log_mask(LOG_UNIMP
,
1779 "%s unhandled 32-bit access at 0x%"PRIx64
" (RAZ)\n",
1785 static MemTxResult
smmu_read_mmio(void *opaque
, hwaddr offset
, uint64_t *data
,
1786 unsigned size
, MemTxAttrs attrs
)
1788 SMMUState
*sys
= opaque
;
1789 SMMUv3State
*s
= ARM_SMMUV3(sys
);
1792 /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */
1797 r
= smmu_readll(s
, offset
, data
, attrs
);
1800 r
= smmu_readl(s
, offset
, data
, attrs
);
1807 trace_smmuv3_read_mmio(offset
, *data
, size
, r
);
1811 static const MemoryRegionOps smmu_mem_ops
= {
1812 .read_with_attrs
= smmu_read_mmio
,
1813 .write_with_attrs
= smmu_write_mmio
,
1814 .endianness
= DEVICE_LITTLE_ENDIAN
,
1816 .min_access_size
= 4,
1817 .max_access_size
= 8,
1820 .min_access_size
= 4,
1821 .max_access_size
= 8,
1825 static void smmu_init_irq(SMMUv3State
*s
, SysBusDevice
*dev
)
1829 for (i
= 0; i
< ARRAY_SIZE(s
->irq
); i
++) {
1830 sysbus_init_irq(dev
, &s
->irq
[i
]);
1834 static void smmu_reset_hold(Object
*obj
, ResetType type
)
1836 SMMUv3State
*s
= ARM_SMMUV3(obj
);
1837 SMMUv3Class
*c
= ARM_SMMUV3_GET_CLASS(s
);
1839 if (c
->parent_phases
.hold
) {
1840 c
->parent_phases
.hold(obj
, type
);
1843 smmuv3_init_regs(s
);
1846 static void smmu_realize(DeviceState
*d
, Error
**errp
)
1848 SMMUState
*sys
= ARM_SMMU(d
);
1849 SMMUv3State
*s
= ARM_SMMUV3(sys
);
1850 SMMUv3Class
*c
= ARM_SMMUV3_GET_CLASS(s
);
1851 SysBusDevice
*dev
= SYS_BUS_DEVICE(d
);
1852 Error
*local_err
= NULL
;
1854 c
->parent_realize(d
, &local_err
);
1856 error_propagate(errp
, local_err
);
1860 qemu_mutex_init(&s
->mutex
);
1862 memory_region_init_io(&sys
->iomem
, OBJECT(s
),
1863 &smmu_mem_ops
, sys
, TYPE_ARM_SMMUV3
, 0x20000);
1865 sys
->mrtypename
= TYPE_SMMUV3_IOMMU_MEMORY_REGION
;
1867 sysbus_init_mmio(dev
, &sys
->iomem
);
1869 smmu_init_irq(s
, dev
);
1872 static const VMStateDescription vmstate_smmuv3_queue
= {
1873 .name
= "smmuv3_queue",
1875 .minimum_version_id
= 1,
1876 .fields
= (const VMStateField
[]) {
1877 VMSTATE_UINT64(base
, SMMUQueue
),
1878 VMSTATE_UINT32(prod
, SMMUQueue
),
1879 VMSTATE_UINT32(cons
, SMMUQueue
),
1880 VMSTATE_UINT8(log2size
, SMMUQueue
),
1881 VMSTATE_END_OF_LIST(),
1885 static bool smmuv3_gbpa_needed(void *opaque
)
1887 SMMUv3State
*s
= opaque
;
1889 /* Only migrate GBPA if it has different reset value. */
1890 return s
->gbpa
!= SMMU_GBPA_RESET_VAL
;
1893 static const VMStateDescription vmstate_gbpa
= {
1894 .name
= "smmuv3/gbpa",
1896 .minimum_version_id
= 1,
1897 .needed
= smmuv3_gbpa_needed
,
1898 .fields
= (const VMStateField
[]) {
1899 VMSTATE_UINT32(gbpa
, SMMUv3State
),
1900 VMSTATE_END_OF_LIST()
1904 static const VMStateDescription vmstate_smmuv3
= {
1907 .minimum_version_id
= 1,
1908 .priority
= MIG_PRI_IOMMU
,
1909 .fields
= (const VMStateField
[]) {
1910 VMSTATE_UINT32(features
, SMMUv3State
),
1911 VMSTATE_UINT8(sid_size
, SMMUv3State
),
1912 VMSTATE_UINT8(sid_split
, SMMUv3State
),
1914 VMSTATE_UINT32_ARRAY(cr
, SMMUv3State
, 3),
1915 VMSTATE_UINT32(cr0ack
, SMMUv3State
),
1916 VMSTATE_UINT32(statusr
, SMMUv3State
),
1917 VMSTATE_UINT32(irq_ctrl
, SMMUv3State
),
1918 VMSTATE_UINT32(gerror
, SMMUv3State
),
1919 VMSTATE_UINT32(gerrorn
, SMMUv3State
),
1920 VMSTATE_UINT64(gerror_irq_cfg0
, SMMUv3State
),
1921 VMSTATE_UINT32(gerror_irq_cfg1
, SMMUv3State
),
1922 VMSTATE_UINT32(gerror_irq_cfg2
, SMMUv3State
),
1923 VMSTATE_UINT64(strtab_base
, SMMUv3State
),
1924 VMSTATE_UINT32(strtab_base_cfg
, SMMUv3State
),
1925 VMSTATE_UINT64(eventq_irq_cfg0
, SMMUv3State
),
1926 VMSTATE_UINT32(eventq_irq_cfg1
, SMMUv3State
),
1927 VMSTATE_UINT32(eventq_irq_cfg2
, SMMUv3State
),
1929 VMSTATE_STRUCT(cmdq
, SMMUv3State
, 0, vmstate_smmuv3_queue
, SMMUQueue
),
1930 VMSTATE_STRUCT(eventq
, SMMUv3State
, 0, vmstate_smmuv3_queue
, SMMUQueue
),
1932 VMSTATE_END_OF_LIST(),
1934 .subsections
= (const VMStateDescription
* const []) {
1940 static Property smmuv3_properties
[] = {
1942 * Stages of translation advertised.
1945 * Defaults to stage 1
1947 DEFINE_PROP_STRING("stage", SMMUv3State
, stage
),
1948 DEFINE_PROP_END_OF_LIST()
1951 static void smmuv3_instance_init(Object
*obj
)
1953 /* Nothing much to do here as of now */
1956 static void smmuv3_class_init(ObjectClass
*klass
, void *data
)
1958 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1959 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
1960 SMMUv3Class
*c
= ARM_SMMUV3_CLASS(klass
);
1962 dc
->vmsd
= &vmstate_smmuv3
;
1963 resettable_class_set_parent_phases(rc
, NULL
, smmu_reset_hold
, NULL
,
1965 device_class_set_parent_realize(dc
, smmu_realize
,
1966 &c
->parent_realize
);
1967 device_class_set_props(dc
, smmuv3_properties
);
1970 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion
*iommu
,
1971 IOMMUNotifierFlag old
,
1972 IOMMUNotifierFlag
new,
1975 SMMUDevice
*sdev
= container_of(iommu
, SMMUDevice
, iommu
);
1976 SMMUv3State
*s3
= sdev
->smmu
;
1977 SMMUState
*s
= &(s3
->smmu_state
);
1979 if (new & IOMMU_NOTIFIER_DEVIOTLB_UNMAP
) {
1980 error_setg(errp
, "SMMUv3 does not support dev-iotlb yet");
1984 if (new & IOMMU_NOTIFIER_MAP
) {
1986 "device %02x.%02x.%x requires iommu MAP notifier which is "
1987 "not currently supported", pci_bus_num(sdev
->bus
),
1988 PCI_SLOT(sdev
->devfn
), PCI_FUNC(sdev
->devfn
));
1992 if (old
== IOMMU_NOTIFIER_NONE
) {
1993 trace_smmuv3_notify_flag_add(iommu
->parent_obj
.name
);
1994 QLIST_INSERT_HEAD(&s
->devices_with_notifiers
, sdev
, next
);
1995 } else if (new == IOMMU_NOTIFIER_NONE
) {
1996 trace_smmuv3_notify_flag_del(iommu
->parent_obj
.name
);
1997 QLIST_REMOVE(sdev
, next
);
2002 static void smmuv3_iommu_memory_region_class_init(ObjectClass
*klass
,
2005 IOMMUMemoryRegionClass
*imrc
= IOMMU_MEMORY_REGION_CLASS(klass
);
2007 imrc
->translate
= smmuv3_translate
;
2008 imrc
->notify_flag_changed
= smmuv3_notify_flag_changed
;
2011 static const TypeInfo smmuv3_type_info
= {
2012 .name
= TYPE_ARM_SMMUV3
,
2013 .parent
= TYPE_ARM_SMMU
,
2014 .instance_size
= sizeof(SMMUv3State
),
2015 .instance_init
= smmuv3_instance_init
,
2016 .class_size
= sizeof(SMMUv3Class
),
2017 .class_init
= smmuv3_class_init
,
2020 static const TypeInfo smmuv3_iommu_memory_region_info
= {
2021 .parent
= TYPE_IOMMU_MEMORY_REGION
,
2022 .name
= TYPE_SMMUV3_IOMMU_MEMORY_REGION
,
2023 .class_init
= smmuv3_iommu_memory_region_class_init
,
2026 static void smmuv3_register_types(void)
2028 type_register(&smmuv3_type_info
);
2029 type_register(&smmuv3_iommu_memory_region_info
);
2032 type_init(smmuv3_register_types
)