2 * Samsung exynos4210 Real Time Clock
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * Ogurtsov Oleg <o.ogurtsov@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
24 * CLKSEL Bit[1] not used
25 * CLKOUTEN Bit[9] not used
28 #include "hw/sysbus.h"
29 #include "qemu/timer.h"
30 #include "qemu-common.h"
31 #include "hw/ptimer.h"
34 #include "sysemu/sysemu.h"
36 #include "hw/arm/exynos4210.h"
41 #define DPRINTF(fmt, ...) \
42 do { fprintf(stdout, "RTC: [%24s:%5d] " fmt, __func__, __LINE__, \
43 ## __VA_ARGS__); } while (0)
45 #define DPRINTF(fmt, ...) do {} while (0)
48 #define EXYNOS4210_RTC_REG_MEM_SIZE 0x0100
56 #define ALMHOUR 0x005C
59 #define ALMYEAR 0x0068
62 #define BCDHOUR 0x0078
64 #define BCDDAYWEEK 0x0080
66 #define BCDYEAR 0x0088
67 #define CURTICNT 0x0090
69 #define TICK_TIMER_ENABLE 0x0100
70 #define TICNT_THRESHHOLD 2
73 #define RTC_ENABLE 0x0001
75 #define INTP_TICK_ENABLE 0x0001
76 #define INTP_ALM_ENABLE 0x0002
78 #define ALARM_INT_ENABLE 0x0040
80 #define RTC_BASE_FREQ 32768
82 typedef struct Exynos4210RTCState
{
97 uint32_t reg_curticcnt
;
99 ptimer_state
*ptimer
; /* tick timer */
100 ptimer_state
*ptimer_1Hz
; /* clock timer */
103 qemu_irq tick_irq
; /* Time Tick Generator irq */
104 qemu_irq alm_irq
; /* alarm irq */
106 struct tm current_tm
; /* current time */
107 } Exynos4210RTCState
;
109 #define TICCKSEL(value) ((value & (0x0F << 4)) >> 4)
112 static const VMStateDescription vmstate_exynos4210_rtc_state
= {
113 .name
= "exynos4210.rtc",
115 .minimum_version_id
= 1,
116 .minimum_version_id_old
= 1,
117 .fields
= (VMStateField
[]) {
118 VMSTATE_UINT32(reg_intp
, Exynos4210RTCState
),
119 VMSTATE_UINT32(reg_rtccon
, Exynos4210RTCState
),
120 VMSTATE_UINT32(reg_ticcnt
, Exynos4210RTCState
),
121 VMSTATE_UINT32(reg_rtcalm
, Exynos4210RTCState
),
122 VMSTATE_UINT32(reg_almsec
, Exynos4210RTCState
),
123 VMSTATE_UINT32(reg_almmin
, Exynos4210RTCState
),
124 VMSTATE_UINT32(reg_almhour
, Exynos4210RTCState
),
125 VMSTATE_UINT32(reg_almday
, Exynos4210RTCState
),
126 VMSTATE_UINT32(reg_almmon
, Exynos4210RTCState
),
127 VMSTATE_UINT32(reg_almyear
, Exynos4210RTCState
),
128 VMSTATE_UINT32(reg_curticcnt
, Exynos4210RTCState
),
129 VMSTATE_PTIMER(ptimer
, Exynos4210RTCState
),
130 VMSTATE_PTIMER(ptimer_1Hz
, Exynos4210RTCState
),
131 VMSTATE_UINT32(freq
, Exynos4210RTCState
),
132 VMSTATE_INT32(current_tm
.tm_sec
, Exynos4210RTCState
),
133 VMSTATE_INT32(current_tm
.tm_min
, Exynos4210RTCState
),
134 VMSTATE_INT32(current_tm
.tm_hour
, Exynos4210RTCState
),
135 VMSTATE_INT32(current_tm
.tm_wday
, Exynos4210RTCState
),
136 VMSTATE_INT32(current_tm
.tm_mday
, Exynos4210RTCState
),
137 VMSTATE_INT32(current_tm
.tm_mon
, Exynos4210RTCState
),
138 VMSTATE_INT32(current_tm
.tm_year
, Exynos4210RTCState
),
139 VMSTATE_END_OF_LIST()
143 #define BCD3DIGITS(x) \
144 ((uint32_t)to_bcd((uint8_t)(x % 100)) + \
145 ((uint32_t)to_bcd((uint8_t)((x % 1000) / 100)) << 8))
147 static void check_alarm_raise(Exynos4210RTCState
*s
)
149 unsigned int alarm_raise
= 0;
150 struct tm stm
= s
->current_tm
;
152 if ((s
->reg_rtcalm
& 0x01) &&
153 (to_bcd((uint8_t)stm
.tm_sec
) == (uint8_t)s
->reg_almsec
)) {
156 if ((s
->reg_rtcalm
& 0x02) &&
157 (to_bcd((uint8_t)stm
.tm_min
) == (uint8_t)s
->reg_almmin
)) {
160 if ((s
->reg_rtcalm
& 0x04) &&
161 (to_bcd((uint8_t)stm
.tm_hour
) == (uint8_t)s
->reg_almhour
)) {
164 if ((s
->reg_rtcalm
& 0x08) &&
165 (to_bcd((uint8_t)stm
.tm_mday
) == (uint8_t)s
->reg_almday
)) {
168 if ((s
->reg_rtcalm
& 0x10) &&
169 (to_bcd((uint8_t)stm
.tm_mon
) == (uint8_t)s
->reg_almmon
)) {
172 if ((s
->reg_rtcalm
& 0x20) &&
173 (BCD3DIGITS(stm
.tm_year
) == s
->reg_almyear
)) {
178 DPRINTF("ALARM IRQ\n");
180 s
->reg_intp
|= INTP_ALM_ENABLE
;
181 qemu_irq_raise(s
->alm_irq
);
186 * RTC update frequency
188 * reg_value - current RTCCON register or his new value
190 static void exynos4210_rtc_update_freq(Exynos4210RTCState
*s
,
196 /* set frequncy for time generator */
197 s
->freq
= RTC_BASE_FREQ
/ (1 << TICCKSEL(reg_value
));
199 if (freq
!= s
->freq
) {
200 ptimer_set_freq(s
->ptimer
, s
->freq
);
201 DPRINTF("freq=%dHz\n", s
->freq
);
205 /* month is between 0 and 11. */
206 static int get_days_in_month(int month
, int year
)
208 static const int days_tab
[12] = {
209 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
212 if ((unsigned)month
>= 12) {
217 if ((year
% 4) == 0 && ((year
% 100) != 0 || (year
% 400) == 0)) {
224 /* update 'tm' to the next second */
225 static void rtc_next_second(struct tm
*tm
)
230 if ((unsigned)tm
->tm_sec
>= 60) {
233 if ((unsigned)tm
->tm_min
>= 60) {
236 if ((unsigned)tm
->tm_hour
>= 24) {
240 if ((unsigned)tm
->tm_wday
>= 7) {
243 days_in_month
= get_days_in_month(tm
->tm_mon
,
246 if (tm
->tm_mday
< 1) {
248 } else if (tm
->tm_mday
> days_in_month
) {
251 if (tm
->tm_mon
>= 12) {
264 static void exynos4210_rtc_tick(void *opaque
)
266 Exynos4210RTCState
*s
= (Exynos4210RTCState
*)opaque
;
268 DPRINTF("TICK IRQ\n");
270 s
->reg_intp
|= INTP_TICK_ENABLE
;
272 qemu_irq_raise(s
->tick_irq
);
275 ptimer_set_count(s
->ptimer
, s
->reg_ticcnt
);
276 ptimer_run(s
->ptimer
, 1);
282 static void exynos4210_rtc_1Hz_tick(void *opaque
)
284 Exynos4210RTCState
*s
= (Exynos4210RTCState
*)opaque
;
286 rtc_next_second(&s
->current_tm
);
287 /* DPRINTF("1Hz tick\n"); */
290 if (s
->reg_rtcalm
& ALARM_INT_ENABLE
) {
291 check_alarm_raise(s
);
294 ptimer_set_count(s
->ptimer_1Hz
, RTC_BASE_FREQ
);
295 ptimer_run(s
->ptimer_1Hz
, 1);
301 static uint64_t exynos4210_rtc_read(void *opaque
, hwaddr offset
,
305 Exynos4210RTCState
*s
= (Exynos4210RTCState
*)opaque
;
312 value
= s
->reg_rtccon
;
315 value
= s
->reg_ticcnt
;
318 value
= s
->reg_rtcalm
;
321 value
= s
->reg_almsec
;
324 value
= s
->reg_almmin
;
327 value
= s
->reg_almhour
;
330 value
= s
->reg_almday
;
333 value
= s
->reg_almmon
;
336 value
= s
->reg_almyear
;
340 value
= (uint32_t)to_bcd((uint8_t)s
->current_tm
.tm_sec
);
343 value
= (uint32_t)to_bcd((uint8_t)s
->current_tm
.tm_min
);
346 value
= (uint32_t)to_bcd((uint8_t)s
->current_tm
.tm_hour
);
349 value
= (uint32_t)to_bcd((uint8_t)s
->current_tm
.tm_wday
);
352 value
= (uint32_t)to_bcd((uint8_t)s
->current_tm
.tm_mday
);
355 value
= (uint32_t)to_bcd((uint8_t)s
->current_tm
.tm_mon
+ 1);
358 value
= BCD3DIGITS(s
->current_tm
.tm_year
);
362 s
->reg_curticcnt
= ptimer_get_count(s
->ptimer
);
363 value
= s
->reg_curticcnt
;
368 "[exynos4210.rtc: bad read offset " TARGET_FMT_plx
"]\n",
378 static void exynos4210_rtc_write(void *opaque
, hwaddr offset
,
379 uint64_t value
, unsigned size
)
381 Exynos4210RTCState
*s
= (Exynos4210RTCState
*)opaque
;
385 if (value
& INTP_ALM_ENABLE
) {
386 qemu_irq_lower(s
->alm_irq
);
387 s
->reg_intp
&= (~INTP_ALM_ENABLE
);
389 if (value
& INTP_TICK_ENABLE
) {
390 qemu_irq_lower(s
->tick_irq
);
391 s
->reg_intp
&= (~INTP_TICK_ENABLE
);
395 if (value
& RTC_ENABLE
) {
396 exynos4210_rtc_update_freq(s
, value
);
398 if ((value
& RTC_ENABLE
) > (s
->reg_rtccon
& RTC_ENABLE
)) {
400 ptimer_set_count(s
->ptimer_1Hz
, RTC_BASE_FREQ
);
401 ptimer_run(s
->ptimer_1Hz
, 1);
402 DPRINTF("run clock timer\n");
404 if ((value
& RTC_ENABLE
) < (s
->reg_rtccon
& RTC_ENABLE
)) {
406 ptimer_stop(s
->ptimer
);
408 ptimer_stop(s
->ptimer_1Hz
);
409 DPRINTF("stop all timers\n");
411 if (value
& RTC_ENABLE
) {
412 if ((value
& TICK_TIMER_ENABLE
) >
413 (s
->reg_rtccon
& TICK_TIMER_ENABLE
) &&
415 ptimer_set_count(s
->ptimer
, s
->reg_ticcnt
);
416 ptimer_run(s
->ptimer
, 1);
417 DPRINTF("run tick timer\n");
419 if ((value
& TICK_TIMER_ENABLE
) <
420 (s
->reg_rtccon
& TICK_TIMER_ENABLE
)) {
421 ptimer_stop(s
->ptimer
);
424 s
->reg_rtccon
= value
;
427 if (value
> TICNT_THRESHHOLD
) {
428 s
->reg_ticcnt
= value
;
431 "[exynos4210.rtc: bad TICNT value %u ]\n",
437 s
->reg_rtcalm
= value
;
440 s
->reg_almsec
= (value
& 0x7f);
443 s
->reg_almmin
= (value
& 0x7f);
446 s
->reg_almhour
= (value
& 0x3f);
449 s
->reg_almday
= (value
& 0x3f);
452 s
->reg_almmon
= (value
& 0x1f);
455 s
->reg_almyear
= (value
& 0x0fff);
459 if (s
->reg_rtccon
& RTC_ENABLE
) {
460 s
->current_tm
.tm_sec
= (int)from_bcd((uint8_t)value
);
464 if (s
->reg_rtccon
& RTC_ENABLE
) {
465 s
->current_tm
.tm_min
= (int)from_bcd((uint8_t)value
);
469 if (s
->reg_rtccon
& RTC_ENABLE
) {
470 s
->current_tm
.tm_hour
= (int)from_bcd((uint8_t)value
);
474 if (s
->reg_rtccon
& RTC_ENABLE
) {
475 s
->current_tm
.tm_wday
= (int)from_bcd((uint8_t)value
);
479 if (s
->reg_rtccon
& RTC_ENABLE
) {
480 s
->current_tm
.tm_mday
= (int)from_bcd((uint8_t)value
);
484 if (s
->reg_rtccon
& RTC_ENABLE
) {
485 s
->current_tm
.tm_mon
= (int)from_bcd((uint8_t)value
) - 1;
489 if (s
->reg_rtccon
& RTC_ENABLE
) {
491 s
->current_tm
.tm_year
= (int)from_bcd((uint8_t)value
) +
492 (int)from_bcd((uint8_t)((value
>> 8) & 0x0f)) * 100;
498 "[exynos4210.rtc: bad write offset " TARGET_FMT_plx
"]\n",
506 * Set default values to timer fields and registers
508 static void exynos4210_rtc_reset(DeviceState
*d
)
510 Exynos4210RTCState
*s
= (Exynos4210RTCState
*)d
;
512 qemu_get_timedate(&s
->current_tm
, 0);
514 DPRINTF("Get time from host: %d-%d-%d %2d:%02d:%02d\n",
515 s
->current_tm
.tm_year
, s
->current_tm
.tm_mon
, s
->current_tm
.tm_mday
,
516 s
->current_tm
.tm_hour
, s
->current_tm
.tm_min
, s
->current_tm
.tm_sec
);
529 s
->reg_curticcnt
= 0;
531 exynos4210_rtc_update_freq(s
, s
->reg_rtccon
);
532 ptimer_stop(s
->ptimer
);
533 ptimer_stop(s
->ptimer_1Hz
);
536 static const MemoryRegionOps exynos4210_rtc_ops
= {
537 .read
= exynos4210_rtc_read
,
538 .write
= exynos4210_rtc_write
,
539 .endianness
= DEVICE_NATIVE_ENDIAN
,
543 * RTC timer initialization
545 static int exynos4210_rtc_init(SysBusDevice
*dev
)
547 Exynos4210RTCState
*s
= FROM_SYSBUS(Exynos4210RTCState
, dev
);
550 bh
= qemu_bh_new(exynos4210_rtc_tick
, s
);
551 s
->ptimer
= ptimer_init(bh
);
552 ptimer_set_freq(s
->ptimer
, RTC_BASE_FREQ
);
553 exynos4210_rtc_update_freq(s
, 0);
555 bh
= qemu_bh_new(exynos4210_rtc_1Hz_tick
, s
);
556 s
->ptimer_1Hz
= ptimer_init(bh
);
557 ptimer_set_freq(s
->ptimer_1Hz
, RTC_BASE_FREQ
);
559 sysbus_init_irq(dev
, &s
->alm_irq
);
560 sysbus_init_irq(dev
, &s
->tick_irq
);
562 memory_region_init_io(&s
->iomem
, NULL
, &exynos4210_rtc_ops
, s
, "exynos4210-rtc",
563 EXYNOS4210_RTC_REG_MEM_SIZE
);
564 sysbus_init_mmio(dev
, &s
->iomem
);
569 static void exynos4210_rtc_class_init(ObjectClass
*klass
, void *data
)
571 DeviceClass
*dc
= DEVICE_CLASS(klass
);
572 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
574 k
->init
= exynos4210_rtc_init
;
575 dc
->reset
= exynos4210_rtc_reset
;
576 dc
->vmsd
= &vmstate_exynos4210_rtc_state
;
579 static const TypeInfo exynos4210_rtc_info
= {
580 .name
= "exynos4210.rtc",
581 .parent
= TYPE_SYS_BUS_DEVICE
,
582 .instance_size
= sizeof(Exynos4210RTCState
),
583 .class_init
= exynos4210_rtc_class_init
,
586 static void exynos4210_rtc_register_types(void)
588 type_register_static(&exynos4210_rtc_info
);
591 type_init(exynos4210_rtc_register_types
)