target-openrisc/cpu.c

   1 /*
   2  * QEMU OpenRISC CPU
   3  *
   4  * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "qemu-common.h"
  22
  23 /* CPUClass::reset() */
  24 static void openrisc_cpu_reset(CPUState *s)
  25 {
  26     OpenRISCCPU *cpu = OPENRISC_CPU(s);
  27     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
  28
  29     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
  30         qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
  31         log_cpu_state(&cpu->env, 0);
  32     }
  33
  34     occ->parent_reset(s);
  35
  36     memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));
  37
  38     tlb_flush(&cpu->env, 1);
  39     /*tb_flush(&cpu->env);    FIXME: Do we need it?  */
  40
  41     cpu->env.pc = 0x100;
  42     cpu->env.sr = SR_FO | SR_SM;
  43     cpu->env.exception_index = -1;
  44
  45     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
  46     cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
  47     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
  48     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
  49
  50 #ifndef CONFIG_USER_ONLY
  51     cpu->env.picmr = 0x00000000;
  52     cpu->env.picsr = 0x00000000;
  53
  54     cpu->env.ttmr = 0x00000000;
  55     cpu->env.ttcr = 0x00000000;
  56 #endif
  57 }
  58
  59 static inline void set_feature(OpenRISCCPU *cpu, int feature)
  60 {
  61     cpu->feature |= feature;
  62     cpu->env.cpucfgr = cpu->feature;
  63 }
  64
  65 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
  66 {
  67     OpenRISCCPU *cpu = OPENRISC_CPU(dev);
  68     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
  69
  70     cpu_reset(CPU(cpu));
  71
  72     occ->parent_realize(dev, errp);
  73 }
  74
  75 static void openrisc_cpu_initfn(Object *obj)
  76 {
  77     CPUState *cs = CPU(obj);
  78     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
  79     static int inited;
  80
  81     cs->env_ptr = &cpu->env;
  82     cpu_exec_init(&cpu->env);
  83
  84 #ifndef CONFIG_USER_ONLY
  85     cpu_openrisc_mmu_init(cpu);
  86 #endif
  87
  88     if (tcg_enabled() && !inited) {
  89         inited = 1;
  90         openrisc_translate_init();
  91     }
  92 }
  93
  94 /* CPU models */
  95
  96 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
  97 {
  98     ObjectClass *oc;
  99
 100     if (cpu_model == NULL) {
 101         return NULL;
 102     }
 103
 104     oc = object_class_by_name(cpu_model);
 105     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
 106                        object_class_is_abstract(oc))) {
 107         return NULL;
 108     }
 109     return oc;
 110 }
 111
 112 static void or1200_initfn(Object *obj)
 113 {
 114     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 115
 116     set_feature(cpu, OPENRISC_FEATURE_OB32S);
 117     set_feature(cpu, OPENRISC_FEATURE_OF32S);
 118 }
 119
 120 static void openrisc_any_initfn(Object *obj)
 121 {
 122     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 123
 124     set_feature(cpu, OPENRISC_FEATURE_OB32S);
 125 }
 126
 127 typedef struct OpenRISCCPUInfo {
 128     const char *name;
 129     void (*initfn)(Object *obj);
 130 } OpenRISCCPUInfo;
 131
 132 static const OpenRISCCPUInfo openrisc_cpus[] = {
 133     { .name = "or1200",      .initfn = or1200_initfn },
 134     { .name = "any",         .initfn = openrisc_any_initfn },
 135 };
 136
 137 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
 138 {
 139     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
 140     CPUClass *cc = CPU_CLASS(occ);
 141     DeviceClass *dc = DEVICE_CLASS(oc);
 142
 143     occ->parent_realize = dc->realize;
 144     dc->realize = openrisc_cpu_realizefn;
 145
 146     occ->parent_reset = cc->reset;
 147     cc->reset = openrisc_cpu_reset;
 148
 149     cc->class_by_name = openrisc_cpu_class_by_name;
 150     cc->do_interrupt = openrisc_cpu_do_interrupt;
 151     cc->dump_state = openrisc_cpu_dump_state;
 152     device_class_set_vmsd(dc, &vmstate_openrisc_cpu);
 153 }
 154
 155 static void cpu_register(const OpenRISCCPUInfo *info)
 156 {
 157     TypeInfo type_info = {
 158         .parent = TYPE_OPENRISC_CPU,
 159         .instance_size = sizeof(OpenRISCCPU),
 160         .instance_init = info->initfn,
 161         .class_size = sizeof(OpenRISCCPUClass),
 162     };
 163
 164     type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
 165     type_register(&type_info);
 166     g_free((void *)type_info.name);
 167 }
 168
 169 static const TypeInfo openrisc_cpu_type_info = {
 170     .name = TYPE_OPENRISC_CPU,
 171     .parent = TYPE_CPU,
 172     .instance_size = sizeof(OpenRISCCPU),
 173     .instance_init = openrisc_cpu_initfn,
 174     .abstract = true,
 175     .class_size = sizeof(OpenRISCCPUClass),
 176     .class_init = openrisc_cpu_class_init,
 177 };
 178
 179 static void openrisc_cpu_register_types(void)
 180 {
 181     int i;
 182
 183     type_register_static(&openrisc_cpu_type_info);
 184     for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
 185         cpu_register(&openrisc_cpus[i]);
 186     }
 187 }
 188
 189 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
 190 {
 191     OpenRISCCPU *cpu;
 192     ObjectClass *oc;
 193
 194     oc = openrisc_cpu_class_by_name(cpu_model);
 195     if (oc == NULL) {
 196         return NULL;
 197     }
 198     cpu = OPENRISC_CPU(object_new(object_class_get_name(oc)));
 199     cpu->env.cpu_model_str = cpu_model;
 200
 201     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 202
 203     return cpu;
 204 }
 205
 206 /* Sort alphabetically by type name, except for "any". */
 207 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
 208 {
 209     ObjectClass *class_a = (ObjectClass *)a;
 210     ObjectClass *class_b = (ObjectClass *)b;
 211     const char *name_a, *name_b;
 212
 213     name_a = object_class_get_name(class_a);
 214     name_b = object_class_get_name(class_b);
 215     if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
 216         return 1;
 217     } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
 218         return -1;
 219     } else {
 220         return strcmp(name_a, name_b);
 221     }
 222 }
 223
 224 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
 225 {
 226     ObjectClass *oc = data;
 227     CPUListState *s = user_data;
 228     const char *typename;
 229     char *name;
 230
 231     typename = object_class_get_name(oc);
 232     name = g_strndup(typename,
 233                      strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
 234     (*s->cpu_fprintf)(s->file, "  %s\n",
 235                       name);
 236     g_free(name);
 237 }
 238
 239 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
 240 {
 241     CPUListState s = {
 242         .file = f,
 243         .cpu_fprintf = cpu_fprintf,
 244     };
 245     GSList *list;
 246
 247     list = object_class_get_list(TYPE_OPENRISC_CPU, false);
 248     list = g_slist_sort(list, openrisc_cpu_list_compare);
 249     (*cpu_fprintf)(f, "Available CPUs:\n");
 250     g_slist_foreach(list, openrisc_cpu_list_entry, &s);
 251     g_slist_free(list);
 252 }
 253
 254 type_init(openrisc_cpu_register_types)