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RAMBlocks: qemu_ram_is_shared
[qemu/ar7.git] / hw / i2c / aspeed_i2c.c
blobce5b1f0fa493021758557a7af333cb8c9ef87521
1 /*
2 * ARM Aspeed I2C controller
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 *
19 */
20
21 #include "qemu/osdep.h"
22 #include "hw/sysbus.h"
23 #include "qemu/log.h"
24 #include "hw/i2c/aspeed_i2c.h"
25
26 /* I2C Global Register */
27
28 #define I2C_CTRL_STATUS 0x00 /* Device Interrupt Status */
29 #define I2C_CTRL_ASSIGN 0x08 /* Device Interrupt Target
30 Assignment */
31
32 /* I2C Device (Bus) Register */
33
34 #define I2CD_FUN_CTRL_REG 0x00 /* I2CD Function Control */
35 #define I2CD_BUFF_SEL_MASK (0x7 << 20)
36 #define I2CD_BUFF_SEL(x) (x << 20)
37 #define I2CD_M_SDA_LOCK_EN (0x1 << 16)
38 #define I2CD_MULTI_MASTER_DIS (0x1 << 15)
39 #define I2CD_M_SCL_DRIVE_EN (0x1 << 14)
40 #define I2CD_MSB_STS (0x1 << 9)
41 #define I2CD_SDA_DRIVE_1T_EN (0x1 << 8)
42 #define I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7)
43 #define I2CD_M_HIGH_SPEED_EN (0x1 << 6)
44 #define I2CD_DEF_ADDR_EN (0x1 << 5)
45 #define I2CD_DEF_ALERT_EN (0x1 << 4)
46 #define I2CD_DEF_ARP_EN (0x1 << 3)
47 #define I2CD_DEF_GCALL_EN (0x1 << 2)
48 #define I2CD_SLAVE_EN (0x1 << 1)
49 #define I2CD_MASTER_EN (0x1)
50
51 #define I2CD_AC_TIMING_REG1 0x04 /* Clock and AC Timing Control #1 */
52 #define I2CD_AC_TIMING_REG2 0x08 /* Clock and AC Timing Control #1 */
53 #define I2CD_INTR_CTRL_REG 0x0c /* I2CD Interrupt Control */
54 #define I2CD_INTR_STS_REG 0x10 /* I2CD Interrupt Status */
55 #define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14)
56 #define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13)
57 #define I2CD_INTR_SMBUS_ALERT (0x1 << 12) /* Bus [0-3] only */
58 #define I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) /* Removed */
59 #define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) /* Removed */
60 #define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) /* Removed */
61 #define I2CD_INTR_GCALL_ADDR (0x1 << 8) /* Removed */
62 #define I2CD_INTR_SLAVE_MATCH (0x1 << 7) /* use RX_DONE */
63 #define I2CD_INTR_SCL_TIMEOUT (0x1 << 6)
64 #define I2CD_INTR_ABNORMAL (0x1 << 5)
65 #define I2CD_INTR_NORMAL_STOP (0x1 << 4)
66 #define I2CD_INTR_ARBIT_LOSS (0x1 << 3)
67 #define I2CD_INTR_RX_DONE (0x1 << 2)
68 #define I2CD_INTR_TX_NAK (0x1 << 1)
69 #define I2CD_INTR_TX_ACK (0x1 << 0)
70
71 #define I2CD_CMD_REG 0x14 /* I2CD Command/Status */
72 #define I2CD_SDA_OE (0x1 << 28)
73 #define I2CD_SDA_O (0x1 << 27)
74 #define I2CD_SCL_OE (0x1 << 26)
75 #define I2CD_SCL_O (0x1 << 25)
76 #define I2CD_TX_TIMING (0x1 << 24)
77 #define I2CD_TX_STATUS (0x1 << 23)
78
79 #define I2CD_TX_STATE_SHIFT 19 /* Tx State Machine */
80 #define I2CD_TX_STATE_MASK 0xf
81 #define I2CD_IDLE 0x0
82 #define I2CD_MACTIVE 0x8
83 #define I2CD_MSTART 0x9
84 #define I2CD_MSTARTR 0xa
85 #define I2CD_MSTOP 0xb
86 #define I2CD_MTXD 0xc
87 #define I2CD_MRXACK 0xd
88 #define I2CD_MRXD 0xe
89 #define I2CD_MTXACK 0xf
90 #define I2CD_SWAIT 0x1
91 #define I2CD_SRXD 0x4
92 #define I2CD_STXACK 0x5
93 #define I2CD_STXD 0x6
94 #define I2CD_SRXACK 0x7
95 #define I2CD_RECOVER 0x3
96
97 #define I2CD_SCL_LINE_STS (0x1 << 18)
98 #define I2CD_SDA_LINE_STS (0x1 << 17)
99 #define I2CD_BUS_BUSY_STS (0x1 << 16)
100 #define I2CD_SDA_OE_OUT_DIR (0x1 << 15)
101 #define I2CD_SDA_O_OUT_DIR (0x1 << 14)
102 #define I2CD_SCL_OE_OUT_DIR (0x1 << 13)
103 #define I2CD_SCL_O_OUT_DIR (0x1 << 12)
104 #define I2CD_BUS_RECOVER_CMD_EN (0x1 << 11)
105 #define I2CD_S_ALT_EN (0x1 << 10)
106 #define I2CD_RX_DMA_ENABLE (0x1 << 9)
107 #define I2CD_TX_DMA_ENABLE (0x1 << 8)
108
109 /* Command Bit */
110 #define I2CD_M_STOP_CMD (0x1 << 5)
111 #define I2CD_M_S_RX_CMD_LAST (0x1 << 4)
112 #define I2CD_M_RX_CMD (0x1 << 3)
113 #define I2CD_S_TX_CMD (0x1 << 2)
114 #define I2CD_M_TX_CMD (0x1 << 1)
115 #define I2CD_M_START_CMD (0x1)
116
117 #define I2CD_DEV_ADDR_REG 0x18 /* Slave Device Address */
118 #define I2CD_BUF_CTRL_REG 0x1c /* Pool Buffer Control */
119 #define I2CD_BYTE_BUF_REG 0x20 /* Transmit/Receive Byte Buffer */
120 #define I2CD_BYTE_BUF_TX_SHIFT 0
121 #define I2CD_BYTE_BUF_TX_MASK 0xff
122 #define I2CD_BYTE_BUF_RX_SHIFT 8
123 #define I2CD_BYTE_BUF_RX_MASK 0xff
124
125
126 static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus)
127 {
128 return bus->ctrl & I2CD_MASTER_EN;
129 }
130
131 static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus)
132 {
133 return bus->ctrl & (I2CD_MASTER_EN | I2CD_SLAVE_EN);
134 }
135
136 static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus)
137 {
138 bus->intr_status &= bus->intr_ctrl;
139 if (bus->intr_status) {
140 bus->controller->intr_status |= 1 << bus->id;
141 qemu_irq_raise(bus->controller->irq);
142 }
143 }
144
145 static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
146 unsigned size)
147 {
148 AspeedI2CBus *bus = opaque;
149
150 switch (offset) {
151 case I2CD_FUN_CTRL_REG:
152 return bus->ctrl;
153 case I2CD_AC_TIMING_REG1:
154 return bus->timing[0];
155 case I2CD_AC_TIMING_REG2:
156 return bus->timing[1];
157 case I2CD_INTR_CTRL_REG:
158 return bus->intr_ctrl;
159 case I2CD_INTR_STS_REG:
160 return bus->intr_status;
161 case I2CD_BYTE_BUF_REG:
162 return bus->buf;
163 case I2CD_CMD_REG:
164 return bus->cmd | (i2c_bus_busy(bus->bus) << 16);
165 default:
166 qemu_log_mask(LOG_GUEST_ERROR,
167 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);
168 return -1;
169 }
170 }
171
172 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
173 {
174 bus->cmd |= value & 0xFFFF;
175 bus->intr_status = 0;
176
177 if (bus->cmd & I2CD_M_START_CMD) {
178 if (i2c_start_transfer(bus->bus, extract32(bus->buf, 1, 7),
179 extract32(bus->buf, 0, 1))) {
180 bus->intr_status |= I2CD_INTR_TX_NAK;
181 } else {
182 bus->intr_status |= I2CD_INTR_TX_ACK;
183 }
184
185 } else if (bus->cmd & I2CD_M_TX_CMD) {
186 if (i2c_send(bus->bus, bus->buf)) {
187 bus->intr_status |= (I2CD_INTR_TX_NAK | I2CD_INTR_ABNORMAL);
188 i2c_end_transfer(bus->bus);
189 } else {
190 bus->intr_status |= I2CD_INTR_TX_ACK;
191 }
192
193 } else if (bus->cmd & I2CD_M_RX_CMD) {
194 int ret = i2c_recv(bus->bus);
195 if (ret < 0) {
196 qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
197 ret = 0xff;
198 } else {
199 bus->intr_status |= I2CD_INTR_RX_DONE;
200 }
201 bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
202 }
203
204 if (bus->cmd & (I2CD_M_STOP_CMD | I2CD_M_S_RX_CMD_LAST)) {
205 if (!i2c_bus_busy(bus->bus)) {
206 bus->intr_status |= I2CD_INTR_ABNORMAL;
207 } else {
208 i2c_end_transfer(bus->bus);
209 bus->intr_status |= I2CD_INTR_NORMAL_STOP;
210 }
211 }
212
213 /* command is handled, reset it and check for interrupts */
214 bus->cmd &= ~0xFFFF;
215 aspeed_i2c_bus_raise_interrupt(bus);
216 }
217
218 static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
219 uint64_t value, unsigned size)
220 {
221 AspeedI2CBus *bus = opaque;
222
223 switch (offset) {
224 case I2CD_FUN_CTRL_REG:
225 if (value & I2CD_SLAVE_EN) {
226 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
227 __func__);
228 break;
229 }
230 bus->ctrl = value & 0x0071C3FF;
231 break;
232 case I2CD_AC_TIMING_REG1:
233 bus->timing[0] = value & 0xFFFFF0F;
234 break;
235 case I2CD_AC_TIMING_REG2:
236 bus->timing[1] = value & 0x7;
237 break;
238 case I2CD_INTR_CTRL_REG:
239 bus->intr_ctrl = value & 0x7FFF;
240 break;
241 case I2CD_INTR_STS_REG:
242 bus->intr_status &= ~(value & 0x7FFF);
243 bus->controller->intr_status &= ~(1 << bus->id);
244 qemu_irq_lower(bus->controller->irq);
245 break;
246 case I2CD_DEV_ADDR_REG:
247 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
248 __func__);
249 break;
250 case I2CD_BYTE_BUF_REG:
251 bus->buf = (value & I2CD_BYTE_BUF_TX_MASK) << I2CD_BYTE_BUF_TX_SHIFT;
252 break;
253 case I2CD_CMD_REG:
254 if (!aspeed_i2c_bus_is_enabled(bus)) {
255 break;
256 }
257
258 if (!aspeed_i2c_bus_is_master(bus)) {
259 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
260 __func__);
261 break;
262 }
263
264 aspeed_i2c_bus_handle_cmd(bus, value);
265 break;
266
267 default:
268 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
269 __func__, offset);
270 }
271 }
272
273 static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset,
274 unsigned size)
275 {
276 AspeedI2CState *s = opaque;
277
278 switch (offset) {
279 case I2C_CTRL_STATUS:
280 return s->intr_status;
281 default:
282 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
283 __func__, offset);
284 break;
285 }
286
287 return -1;
288 }
289
290 static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset,
291 uint64_t value, unsigned size)
292 {
293 switch (offset) {
294 case I2C_CTRL_STATUS:
295 default:
296 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
297 __func__, offset);
298 break;
299 }
300 }
301
302 static const MemoryRegionOps aspeed_i2c_bus_ops = {
303 .read = aspeed_i2c_bus_read,
304 .write = aspeed_i2c_bus_write,
305 .endianness = DEVICE_LITTLE_ENDIAN,
306 };
307
308 static const MemoryRegionOps aspeed_i2c_ctrl_ops = {
309 .read = aspeed_i2c_ctrl_read,
310 .write = aspeed_i2c_ctrl_write,
311 .endianness = DEVICE_LITTLE_ENDIAN,
312 };
313
314 static const VMStateDescription aspeed_i2c_bus_vmstate = {
315 .name = TYPE_ASPEED_I2C,
316 .version_id = 1,
317 .minimum_version_id = 1,
318 .fields = (VMStateField[]) {
319 VMSTATE_UINT8(id, AspeedI2CBus),
320 VMSTATE_UINT32(ctrl, AspeedI2CBus),
321 VMSTATE_UINT32_ARRAY(timing, AspeedI2CBus, 2),
322 VMSTATE_UINT32(intr_ctrl, AspeedI2CBus),
323 VMSTATE_UINT32(intr_status, AspeedI2CBus),
324 VMSTATE_UINT32(cmd, AspeedI2CBus),
325 VMSTATE_UINT32(buf, AspeedI2CBus),
326 VMSTATE_END_OF_LIST()
327 }
328 };
329
330 static const VMStateDescription aspeed_i2c_vmstate = {
331 .name = TYPE_ASPEED_I2C,
332 .version_id = 1,
333 .minimum_version_id = 1,
334 .fields = (VMStateField[]) {
335 VMSTATE_UINT32(intr_status, AspeedI2CState),
336 VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState,
337 ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate,
338 AspeedI2CBus),
339 VMSTATE_END_OF_LIST()
340 }
341 };
342
343 static void aspeed_i2c_reset(DeviceState *dev)
344 {
345 int i;
346 AspeedI2CState *s = ASPEED_I2C(dev);
347
348 s->intr_status = 0;
349
350 for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) {
351 s->busses[i].intr_ctrl = 0;
352 s->busses[i].intr_status = 0;
353 s->busses[i].cmd = 0;
354 s->busses[i].buf = 0;
355 i2c_end_transfer(s->busses[i].bus);
356 }
357 }
358
359 /*
360 * Address Definitions
361 *
362 * 0x000 ... 0x03F: Global Register
363 * 0x040 ... 0x07F: Device 1
364 * 0x080 ... 0x0BF: Device 2
365 * 0x0C0 ... 0x0FF: Device 3
366 * 0x100 ... 0x13F: Device 4
367 * 0x140 ... 0x17F: Device 5
368 * 0x180 ... 0x1BF: Device 6
369 * 0x1C0 ... 0x1FF: Device 7
370 * 0x200 ... 0x2FF: Buffer Pool (unused in linux driver)
371 * 0x300 ... 0x33F: Device 8
372 * 0x340 ... 0x37F: Device 9
373 * 0x380 ... 0x3BF: Device 10
374 * 0x3C0 ... 0x3FF: Device 11
375 * 0x400 ... 0x43F: Device 12
376 * 0x440 ... 0x47F: Device 13
377 * 0x480 ... 0x4BF: Device 14
378 * 0x800 ... 0xFFF: Buffer Pool (unused in linux driver)
379 */
380 static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
381 {
382 int i;
383 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
384 AspeedI2CState *s = ASPEED_I2C(dev);
385
386 sysbus_init_irq(sbd, &s->irq);
387 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s,
388 "aspeed.i2c", 0x1000);
389 sysbus_init_mmio(sbd, &s->iomem);
390
391 for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) {
392 char name[16];
393 int offset = i < 7 ? 1 : 5;
394 snprintf(name, sizeof(name), "aspeed.i2c.%d", i);
395 s->busses[i].controller = s;
396 s->busses[i].id = i;
397 s->busses[i].bus = i2c_init_bus(dev, name);
398 memory_region_init_io(&s->busses[i].mr, OBJECT(dev),
399 &aspeed_i2c_bus_ops, &s->busses[i], name, 0x40);
400 memory_region_add_subregion(&s->iomem, 0x40 * (i + offset),
401 &s->busses[i].mr);
402 }
403 }
404
405 static void aspeed_i2c_class_init(ObjectClass *klass, void *data)
406 {
407 DeviceClass *dc = DEVICE_CLASS(klass);
408
409 dc->vmsd = &aspeed_i2c_vmstate;
410 dc->reset = aspeed_i2c_reset;
411 dc->realize = aspeed_i2c_realize;
412 dc->desc = "Aspeed I2C Controller";
413 }
414
415 static const TypeInfo aspeed_i2c_info = {
416 .name = TYPE_ASPEED_I2C,
417 .parent = TYPE_SYS_BUS_DEVICE,
418 .instance_size = sizeof(AspeedI2CState),
419 .class_init = aspeed_i2c_class_init,
420 };
421
422 static void aspeed_i2c_register_types(void)
423 {
424 type_register_static(&aspeed_i2c_info);
425 }
426
427 type_init(aspeed_i2c_register_types)
428
429
430 I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr)
431 {
432 AspeedI2CState *s = ASPEED_I2C(dev);
433 I2CBus *bus = NULL;
434
435 if (busnr >= 0 && busnr < ASPEED_I2C_NR_BUSSES) {
436 bus = s->busses[busnr].bus;
437 }
438
439 return bus;
440 }
AR7 emulation for QEMU