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pc: ACPI BIOS: make GPE.3 handle memory hotplug event on PIIX and Q35 machines
[qemu/ar7.git] / memory.c
blob3e8cd5680bbdd2eccaf9357d5ae0fd10451f58a5
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "exec/memory.h"
17 #include "exec/address-spaces.h"
18 #include "exec/ioport.h"
19 #include "qemu/bitops.h"
20 #include "qom/object.h"
21 #include "trace.h"
22 #include <assert.h>
23
24 #include "exec/memory-internal.h"
25 #include "exec/ram_addr.h"
26
27 //#define DEBUG_UNASSIGNED
28
29 static unsigned memory_region_transaction_depth;
30 static bool memory_region_update_pending;
31 static bool ioeventfd_update_pending;
32 static bool global_dirty_log = false;
33
34 /* flat_view_mutex is taken around reading as->current_map; the critical
35 * section is extremely short, so I'm using a single mutex for every AS.
36 * We could also RCU for the read-side.
37 *
38 * The BQL is taken around transaction commits, hence both locks are taken
39 * while writing to as->current_map (with the BQL taken outside).
40 */
41 static QemuMutex flat_view_mutex;
42
43 static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
44 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
45
46 static QTAILQ_HEAD(, AddressSpace) address_spaces
47 = QTAILQ_HEAD_INITIALIZER(address_spaces);
48
49 static void memory_init(void)
50 {
51 qemu_mutex_init(&flat_view_mutex);
52 }
53
54 typedef struct AddrRange AddrRange;
55
56 /*
57 * Note using signed integers limits us to physical addresses at most
58 * 63 bits wide. They are needed for negative offsetting in aliases
59 * (large MemoryRegion::alias_offset).
60 */
61 struct AddrRange {
62 Int128 start;
63 Int128 size;
64 };
65
66 static AddrRange addrrange_make(Int128 start, Int128 size)
67 {
68 return (AddrRange) { start, size };
69 }
70
71 static bool addrrange_equal(AddrRange r1, AddrRange r2)
72 {
73 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
74 }
75
76 static Int128 addrrange_end(AddrRange r)
77 {
78 return int128_add(r.start, r.size);
79 }
80
81 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
82 {
83 int128_addto(&range.start, delta);
84 return range;
85 }
86
87 static bool addrrange_contains(AddrRange range, Int128 addr)
88 {
89 return int128_ge(addr, range.start)
90 && int128_lt(addr, addrrange_end(range));
91 }
92
93 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
94 {
95 return addrrange_contains(r1, r2.start)
96 || addrrange_contains(r2, r1.start);
97 }
98
99 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
100 {
101 Int128 start = int128_max(r1.start, r2.start);
102 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
103 return addrrange_make(start, int128_sub(end, start));
104 }
105
106 enum ListenerDirection { Forward, Reverse };
107
108 static bool memory_listener_match(MemoryListener *listener,
109 MemoryRegionSection *section)
110 {
111 return !listener->address_space_filter
112 || listener->address_space_filter == section->address_space;
113 }
114
115 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
116 do { \
117 MemoryListener *_listener; \
118 \
119 switch (_direction) { \
120 case Forward: \
121 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
122 if (_listener->_callback) { \
123 _listener->_callback(_listener, ##_args); \
124 } \
125 } \
126 break; \
127 case Reverse: \
128 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
129 memory_listeners, link) { \
130 if (_listener->_callback) { \
131 _listener->_callback(_listener, ##_args); \
132 } \
133 } \
134 break; \
135 default: \
136 abort(); \
137 } \
138 } while (0)
139
140 #define MEMORY_LISTENER_CALL(_callback, _direction, _section, _args...) \
141 do { \
142 MemoryListener *_listener; \
143 \
144 switch (_direction) { \
145 case Forward: \
146 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
147 if (_listener->_callback \
148 && memory_listener_match(_listener, _section)) { \
149 _listener->_callback(_listener, _section, ##_args); \
150 } \
151 } \
152 break; \
153 case Reverse: \
154 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
155 memory_listeners, link) { \
156 if (_listener->_callback \
157 && memory_listener_match(_listener, _section)) { \
158 _listener->_callback(_listener, _section, ##_args); \
159 } \
160 } \
161 break; \
162 default: \
163 abort(); \
164 } \
165 } while (0)
166
167 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
168 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback) \
169 MEMORY_LISTENER_CALL(callback, dir, (&(MemoryRegionSection) { \
170 .mr = (fr)->mr, \
171 .address_space = (as), \
172 .offset_within_region = (fr)->offset_in_region, \
173 .size = (fr)->addr.size, \
174 .offset_within_address_space = int128_get64((fr)->addr.start), \
175 .readonly = (fr)->readonly, \
176 }))
177
178 struct CoalescedMemoryRange {
179 AddrRange addr;
180 QTAILQ_ENTRY(CoalescedMemoryRange) link;
181 };
182
183 struct MemoryRegionIoeventfd {
184 AddrRange addr;
185 bool match_data;
186 uint64_t data;
187 EventNotifier *e;
188 };
189
190 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
191 MemoryRegionIoeventfd b)
192 {
193 if (int128_lt(a.addr.start, b.addr.start)) {
194 return true;
195 } else if (int128_gt(a.addr.start, b.addr.start)) {
196 return false;
197 } else if (int128_lt(a.addr.size, b.addr.size)) {
198 return true;
199 } else if (int128_gt(a.addr.size, b.addr.size)) {
200 return false;
201 } else if (a.match_data < b.match_data) {
202 return true;
203 } else if (a.match_data > b.match_data) {
204 return false;
205 } else if (a.match_data) {
206 if (a.data < b.data) {
207 return true;
208 } else if (a.data > b.data) {
209 return false;
210 }
211 }
212 if (a.e < b.e) {
213 return true;
214 } else if (a.e > b.e) {
215 return false;
216 }
217 return false;
218 }
219
220 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
221 MemoryRegionIoeventfd b)
222 {
223 return !memory_region_ioeventfd_before(a, b)
224 && !memory_region_ioeventfd_before(b, a);
225 }
226
227 typedef struct FlatRange FlatRange;
228 typedef struct FlatView FlatView;
229
230 /* Range of memory in the global map. Addresses are absolute. */
231 struct FlatRange {
232 MemoryRegion *mr;
233 hwaddr offset_in_region;
234 AddrRange addr;
235 uint8_t dirty_log_mask;
236 bool romd_mode;
237 bool readonly;
238 };
239
240 /* Flattened global view of current active memory hierarchy. Kept in sorted
241 * order.
242 */
243 struct FlatView {
244 unsigned ref;
245 FlatRange *ranges;
246 unsigned nr;
247 unsigned nr_allocated;
248 };
249
250 typedef struct AddressSpaceOps AddressSpaceOps;
251
252 #define FOR_EACH_FLAT_RANGE(var, view) \
253 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
254
255 static bool flatrange_equal(FlatRange *a, FlatRange *b)
256 {
257 return a->mr == b->mr
258 && addrrange_equal(a->addr, b->addr)
259 && a->offset_in_region == b->offset_in_region
260 && a->romd_mode == b->romd_mode
261 && a->readonly == b->readonly;
262 }
263
264 static void flatview_init(FlatView *view)
265 {
266 view->ref = 1;
267 view->ranges = NULL;
268 view->nr = 0;
269 view->nr_allocated = 0;
270 }
271
272 /* Insert a range into a given position. Caller is responsible for maintaining
273 * sorting order.
274 */
275 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
276 {
277 if (view->nr == view->nr_allocated) {
278 view->nr_allocated = MAX(2 * view->nr, 10);
279 view->ranges = g_realloc(view->ranges,
280 view->nr_allocated * sizeof(*view->ranges));
281 }
282 memmove(view->ranges + pos + 1, view->ranges + pos,
283 (view->nr - pos) * sizeof(FlatRange));
284 view->ranges[pos] = *range;
285 memory_region_ref(range->mr);
286 ++view->nr;
287 }
288
289 static void flatview_destroy(FlatView *view)
290 {
291 int i;
292
293 for (i = 0; i < view->nr; i++) {
294 memory_region_unref(view->ranges[i].mr);
295 }
296 g_free(view->ranges);
297 g_free(view);
298 }
299
300 static void flatview_ref(FlatView *view)
301 {
302 atomic_inc(&view->ref);
303 }
304
305 static void flatview_unref(FlatView *view)
306 {
307 if (atomic_fetch_dec(&view->ref) == 1) {
308 flatview_destroy(view);
309 }
310 }
311
312 static bool can_merge(FlatRange *r1, FlatRange *r2)
313 {
314 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
315 && r1->mr == r2->mr
316 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
317 r1->addr.size),
318 int128_make64(r2->offset_in_region))
319 && r1->dirty_log_mask == r2->dirty_log_mask
320 && r1->romd_mode == r2->romd_mode
321 && r1->readonly == r2->readonly;
322 }
323
324 /* Attempt to simplify a view by merging adjacent ranges */
325 static void flatview_simplify(FlatView *view)
326 {
327 unsigned i, j;
328
329 i = 0;
330 while (i < view->nr) {
331 j = i + 1;
332 while (j < view->nr
333 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
334 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
335 ++j;
336 }
337 ++i;
338 memmove(&view->ranges[i], &view->ranges[j],
339 (view->nr - j) * sizeof(view->ranges[j]));
340 view->nr -= j - i;
341 }
342 }
343
344 static bool memory_region_big_endian(MemoryRegion *mr)
345 {
346 #ifdef TARGET_WORDS_BIGENDIAN
347 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
348 #else
349 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
350 #endif
351 }
352
353 static bool memory_region_wrong_endianness(MemoryRegion *mr)
354 {
355 #ifdef TARGET_WORDS_BIGENDIAN
356 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
357 #else
358 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
359 #endif
360 }
361
362 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
363 {
364 if (memory_region_wrong_endianness(mr)) {
365 switch (size) {
366 case 1:
367 break;
368 case 2:
369 *data = bswap16(*data);
370 break;
371 case 4:
372 *data = bswap32(*data);
373 break;
374 case 8:
375 *data = bswap64(*data);
376 break;
377 default:
378 abort();
379 }
380 }
381 }
382
383 static void memory_region_oldmmio_read_accessor(MemoryRegion *mr,
384 hwaddr addr,
385 uint64_t *value,
386 unsigned size,
387 unsigned shift,
388 uint64_t mask)
389 {
390 uint64_t tmp;
391
392 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
393 trace_memory_region_ops_read(mr, addr, tmp, size);
394 *value |= (tmp & mask) << shift;
395 }
396
397 static void memory_region_read_accessor(MemoryRegion *mr,
398 hwaddr addr,
399 uint64_t *value,
400 unsigned size,
401 unsigned shift,
402 uint64_t mask)
403 {
404 uint64_t tmp;
405
406 if (mr->flush_coalesced_mmio) {
407 qemu_flush_coalesced_mmio_buffer();
408 }
409 tmp = mr->ops->read(mr->opaque, addr, size);
410 trace_memory_region_ops_read(mr, addr, tmp, size);
411 *value |= (tmp & mask) << shift;
412 }
413
414 static void memory_region_oldmmio_write_accessor(MemoryRegion *mr,
415 hwaddr addr,
416 uint64_t *value,
417 unsigned size,
418 unsigned shift,
419 uint64_t mask)
420 {
421 uint64_t tmp;
422
423 tmp = (*value >> shift) & mask;
424 trace_memory_region_ops_write(mr, addr, tmp, size);
425 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
426 }
427
428 static void memory_region_write_accessor(MemoryRegion *mr,
429 hwaddr addr,
430 uint64_t *value,
431 unsigned size,
432 unsigned shift,
433 uint64_t mask)
434 {
435 uint64_t tmp;
436
437 if (mr->flush_coalesced_mmio) {
438 qemu_flush_coalesced_mmio_buffer();
439 }
440 tmp = (*value >> shift) & mask;
441 trace_memory_region_ops_write(mr, addr, tmp, size);
442 mr->ops->write(mr->opaque, addr, tmp, size);
443 }
444
445 static void access_with_adjusted_size(hwaddr addr,
446 uint64_t *value,
447 unsigned size,
448 unsigned access_size_min,
449 unsigned access_size_max,
450 void (*access)(MemoryRegion *mr,
451 hwaddr addr,
452 uint64_t *value,
453 unsigned size,
454 unsigned shift,
455 uint64_t mask),
456 MemoryRegion *mr)
457 {
458 uint64_t access_mask;
459 unsigned access_size;
460 unsigned i;
461
462 if (!access_size_min) {
463 access_size_min = 1;
464 }
465 if (!access_size_max) {
466 access_size_max = 4;
467 }
468
469 /* FIXME: support unaligned access? */
470 access_size = MAX(MIN(size, access_size_max), access_size_min);
471 access_mask = -1ULL >> (64 - access_size * 8);
472 if (memory_region_big_endian(mr)) {
473 for (i = 0; i < size; i += access_size) {
474 access(mr, addr + i, value, access_size,
475 (size - access_size - i) * 8, access_mask);
476 }
477 } else {
478 for (i = 0; i < size; i += access_size) {
479 access(mr, addr + i, value, access_size, i * 8, access_mask);
480 }
481 }
482 }
483
484 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
485 {
486 AddressSpace *as;
487
488 while (mr->container) {
489 mr = mr->container;
490 }
491 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
492 if (mr == as->root) {
493 return as;
494 }
495 }
496 return NULL;
497 }
498
499 /* Render a memory region into the global view. Ranges in @view obscure
500 * ranges in @mr.
501 */
502 static void render_memory_region(FlatView *view,
503 MemoryRegion *mr,
504 Int128 base,
505 AddrRange clip,
506 bool readonly)
507 {
508 MemoryRegion *subregion;
509 unsigned i;
510 hwaddr offset_in_region;
511 Int128 remain;
512 Int128 now;
513 FlatRange fr;
514 AddrRange tmp;
515
516 if (!mr->enabled) {
517 return;
518 }
519
520 int128_addto(&base, int128_make64(mr->addr));
521 readonly |= mr->readonly;
522
523 tmp = addrrange_make(base, mr->size);
524
525 if (!addrrange_intersects(tmp, clip)) {
526 return;
527 }
528
529 clip = addrrange_intersection(tmp, clip);
530
531 if (mr->alias) {
532 int128_subfrom(&base, int128_make64(mr->alias->addr));
533 int128_subfrom(&base, int128_make64(mr->alias_offset));
534 render_memory_region(view, mr->alias, base, clip, readonly);
535 return;
536 }
537
538 /* Render subregions in priority order. */
539 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
540 render_memory_region(view, subregion, base, clip, readonly);
541 }
542
543 if (!mr->terminates) {
544 return;
545 }
546
547 offset_in_region = int128_get64(int128_sub(clip.start, base));
548 base = clip.start;
549 remain = clip.size;
550
551 fr.mr = mr;
552 fr.dirty_log_mask = mr->dirty_log_mask;
553 fr.romd_mode = mr->romd_mode;
554 fr.readonly = readonly;
555
556 /* Render the region itself into any gaps left by the current view. */
557 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
558 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
559 continue;
560 }
561 if (int128_lt(base, view->ranges[i].addr.start)) {
562 now = int128_min(remain,
563 int128_sub(view->ranges[i].addr.start, base));
564 fr.offset_in_region = offset_in_region;
565 fr.addr = addrrange_make(base, now);
566 flatview_insert(view, i, &fr);
567 ++i;
568 int128_addto(&base, now);
569 offset_in_region += int128_get64(now);
570 int128_subfrom(&remain, now);
571 }
572 now = int128_sub(int128_min(int128_add(base, remain),
573 addrrange_end(view->ranges[i].addr)),
574 base);
575 int128_addto(&base, now);
576 offset_in_region += int128_get64(now);
577 int128_subfrom(&remain, now);
578 }
579 if (int128_nz(remain)) {
580 fr.offset_in_region = offset_in_region;
581 fr.addr = addrrange_make(base, remain);
582 flatview_insert(view, i, &fr);
583 }
584 }
585
586 /* Render a memory topology into a list of disjoint absolute ranges. */
587 static FlatView *generate_memory_topology(MemoryRegion *mr)
588 {
589 FlatView *view;
590
591 view = g_new(FlatView, 1);
592 flatview_init(view);
593
594 if (mr) {
595 render_memory_region(view, mr, int128_zero(),
596 addrrange_make(int128_zero(), int128_2_64()), false);
597 }
598 flatview_simplify(view);
599
600 return view;
601 }
602
603 static void address_space_add_del_ioeventfds(AddressSpace *as,
604 MemoryRegionIoeventfd *fds_new,
605 unsigned fds_new_nb,
606 MemoryRegionIoeventfd *fds_old,
607 unsigned fds_old_nb)
608 {
609 unsigned iold, inew;
610 MemoryRegionIoeventfd *fd;
611 MemoryRegionSection section;
612
613 /* Generate a symmetric difference of the old and new fd sets, adding
614 * and deleting as necessary.
615 */
616
617 iold = inew = 0;
618 while (iold < fds_old_nb || inew < fds_new_nb) {
619 if (iold < fds_old_nb
620 && (inew == fds_new_nb
621 || memory_region_ioeventfd_before(fds_old[iold],
622 fds_new[inew]))) {
623 fd = &fds_old[iold];
624 section = (MemoryRegionSection) {
625 .address_space = as,
626 .offset_within_address_space = int128_get64(fd->addr.start),
627 .size = fd->addr.size,
628 };
629 MEMORY_LISTENER_CALL(eventfd_del, Forward, &section,
630 fd->match_data, fd->data, fd->e);
631 ++iold;
632 } else if (inew < fds_new_nb
633 && (iold == fds_old_nb
634 || memory_region_ioeventfd_before(fds_new[inew],
635 fds_old[iold]))) {
636 fd = &fds_new[inew];
637 section = (MemoryRegionSection) {
638 .address_space = as,
639 .offset_within_address_space = int128_get64(fd->addr.start),
640 .size = fd->addr.size,
641 };
642 MEMORY_LISTENER_CALL(eventfd_add, Reverse, &section,
643 fd->match_data, fd->data, fd->e);
644 ++inew;
645 } else {
646 ++iold;
647 ++inew;
648 }
649 }
650 }
651
652 static FlatView *address_space_get_flatview(AddressSpace *as)
653 {
654 FlatView *view;
655
656 qemu_mutex_lock(&flat_view_mutex);
657 view = as->current_map;
658 flatview_ref(view);
659 qemu_mutex_unlock(&flat_view_mutex);
660 return view;
661 }
662
663 static void address_space_update_ioeventfds(AddressSpace *as)
664 {
665 FlatView *view;
666 FlatRange *fr;
667 unsigned ioeventfd_nb = 0;
668 MemoryRegionIoeventfd *ioeventfds = NULL;
669 AddrRange tmp;
670 unsigned i;
671
672 view = address_space_get_flatview(as);
673 FOR_EACH_FLAT_RANGE(fr, view) {
674 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
675 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
676 int128_sub(fr->addr.start,
677 int128_make64(fr->offset_in_region)));
678 if (addrrange_intersects(fr->addr, tmp)) {
679 ++ioeventfd_nb;
680 ioeventfds = g_realloc(ioeventfds,
681 ioeventfd_nb * sizeof(*ioeventfds));
682 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
683 ioeventfds[ioeventfd_nb-1].addr = tmp;
684 }
685 }
686 }
687
688 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
689 as->ioeventfds, as->ioeventfd_nb);
690
691 g_free(as->ioeventfds);
692 as->ioeventfds = ioeventfds;
693 as->ioeventfd_nb = ioeventfd_nb;
694 flatview_unref(view);
695 }
696
697 static void address_space_update_topology_pass(AddressSpace *as,
698 const FlatView *old_view,
699 const FlatView *new_view,
700 bool adding)
701 {
702 unsigned iold, inew;
703 FlatRange *frold, *frnew;
704
705 /* Generate a symmetric difference of the old and new memory maps.
706 * Kill ranges in the old map, and instantiate ranges in the new map.
707 */
708 iold = inew = 0;
709 while (iold < old_view->nr || inew < new_view->nr) {
710 if (iold < old_view->nr) {
711 frold = &old_view->ranges[iold];
712 } else {
713 frold = NULL;
714 }
715 if (inew < new_view->nr) {
716 frnew = &new_view->ranges[inew];
717 } else {
718 frnew = NULL;
719 }
720
721 if (frold
722 && (!frnew
723 || int128_lt(frold->addr.start, frnew->addr.start)
724 || (int128_eq(frold->addr.start, frnew->addr.start)
725 && !flatrange_equal(frold, frnew)))) {
726 /* In old but not in new, or in both but attributes changed. */
727
728 if (!adding) {
729 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
730 }
731
732 ++iold;
733 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
734 /* In both and unchanged (except logging may have changed) */
735
736 if (adding) {
737 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
738 if (frold->dirty_log_mask && !frnew->dirty_log_mask) {
739 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop);
740 } else if (frnew->dirty_log_mask && !frold->dirty_log_mask) {
741 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start);
742 }
743 }
744
745 ++iold;
746 ++inew;
747 } else {
748 /* In new */
749
750 if (adding) {
751 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
752 }
753
754 ++inew;
755 }
756 }
757 }
758
759
760 static void address_space_update_topology(AddressSpace *as)
761 {
762 FlatView *old_view = address_space_get_flatview(as);
763 FlatView *new_view = generate_memory_topology(as->root);
764
765 address_space_update_topology_pass(as, old_view, new_view, false);
766 address_space_update_topology_pass(as, old_view, new_view, true);
767
768 qemu_mutex_lock(&flat_view_mutex);
769 flatview_unref(as->current_map);
770 as->current_map = new_view;
771 qemu_mutex_unlock(&flat_view_mutex);
772
773 /* Note that all the old MemoryRegions are still alive up to this
774 * point. This relieves most MemoryListeners from the need to
775 * ref/unref the MemoryRegions they get---unless they use them
776 * outside the iothread mutex, in which case precise reference
777 * counting is necessary.
778 */
779 flatview_unref(old_view);
780
781 address_space_update_ioeventfds(as);
782 }
783
784 void memory_region_transaction_begin(void)
785 {
786 qemu_flush_coalesced_mmio_buffer();
787 ++memory_region_transaction_depth;
788 }
789
790 static void memory_region_clear_pending(void)
791 {
792 memory_region_update_pending = false;
793 ioeventfd_update_pending = false;
794 }
795
796 void memory_region_transaction_commit(void)
797 {
798 AddressSpace *as;
799
800 assert(memory_region_transaction_depth);
801 --memory_region_transaction_depth;
802 if (!memory_region_transaction_depth) {
803 if (memory_region_update_pending) {
804 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
805
806 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
807 address_space_update_topology(as);
808 }
809
810 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
811 } else if (ioeventfd_update_pending) {
812 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
813 address_space_update_ioeventfds(as);
814 }
815 }
816 memory_region_clear_pending();
817 }
818 }
819
820 static void memory_region_destructor_none(MemoryRegion *mr)
821 {
822 }
823
824 static void memory_region_destructor_ram(MemoryRegion *mr)
825 {
826 qemu_ram_free(mr->ram_addr);
827 }
828
829 static void memory_region_destructor_alias(MemoryRegion *mr)
830 {
831 memory_region_unref(mr->alias);
832 }
833
834 static void memory_region_destructor_ram_from_ptr(MemoryRegion *mr)
835 {
836 qemu_ram_free_from_ptr(mr->ram_addr);
837 }
838
839 static void memory_region_destructor_rom_device(MemoryRegion *mr)
840 {
841 qemu_ram_free(mr->ram_addr & TARGET_PAGE_MASK);
842 }
843
844 void memory_region_init(MemoryRegion *mr,
845 Object *owner,
846 const char *name,
847 uint64_t size)
848 {
849 mr->ops = &unassigned_mem_ops;
850 mr->opaque = NULL;
851 mr->owner = owner;
852 mr->iommu_ops = NULL;
853 mr->container = NULL;
854 mr->size = int128_make64(size);
855 if (size == UINT64_MAX) {
856 mr->size = int128_2_64();
857 }
858 mr->addr = 0;
859 mr->subpage = false;
860 mr->enabled = true;
861 mr->terminates = false;
862 mr->ram = false;
863 mr->romd_mode = true;
864 mr->readonly = false;
865 mr->rom_device = false;
866 mr->destructor = memory_region_destructor_none;
867 mr->priority = 0;
868 mr->may_overlap = false;
869 mr->alias = NULL;
870 QTAILQ_INIT(&mr->subregions);
871 memset(&mr->subregions_link, 0, sizeof mr->subregions_link);
872 QTAILQ_INIT(&mr->coalesced);
873 mr->name = g_strdup(name);
874 mr->dirty_log_mask = 0;
875 mr->ioeventfd_nb = 0;
876 mr->ioeventfds = NULL;
877 mr->flush_coalesced_mmio = false;
878 }
879
880 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
881 unsigned size)
882 {
883 #ifdef DEBUG_UNASSIGNED
884 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
885 #endif
886 if (current_cpu != NULL) {
887 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
888 }
889 return 0;
890 }
891
892 static void unassigned_mem_write(void *opaque, hwaddr addr,
893 uint64_t val, unsigned size)
894 {
895 #ifdef DEBUG_UNASSIGNED
896 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
897 #endif
898 if (current_cpu != NULL) {
899 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
900 }
901 }
902
903 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
904 unsigned size, bool is_write)
905 {
906 return false;
907 }
908
909 const MemoryRegionOps unassigned_mem_ops = {
910 .valid.accepts = unassigned_mem_accepts,
911 .endianness = DEVICE_NATIVE_ENDIAN,
912 };
913
914 bool memory_region_access_valid(MemoryRegion *mr,
915 hwaddr addr,
916 unsigned size,
917 bool is_write)
918 {
919 int access_size_min, access_size_max;
920 int access_size, i;
921
922 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
923 return false;
924 }
925
926 if (!mr->ops->valid.accepts) {
927 return true;
928 }
929
930 access_size_min = mr->ops->valid.min_access_size;
931 if (!mr->ops->valid.min_access_size) {
932 access_size_min = 1;
933 }
934
935 access_size_max = mr->ops->valid.max_access_size;
936 if (!mr->ops->valid.max_access_size) {
937 access_size_max = 4;
938 }
939
940 access_size = MAX(MIN(size, access_size_max), access_size_min);
941 for (i = 0; i < size; i += access_size) {
942 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
943 is_write)) {
944 return false;
945 }
946 }
947
948 return true;
949 }
950
951 static uint64_t memory_region_dispatch_read1(MemoryRegion *mr,
952 hwaddr addr,
953 unsigned size)
954 {
955 uint64_t data = 0;
956
957 if (mr->ops->read) {
958 access_with_adjusted_size(addr, &data, size,
959 mr->ops->impl.min_access_size,
960 mr->ops->impl.max_access_size,
961 memory_region_read_accessor, mr);
962 } else {
963 access_with_adjusted_size(addr, &data, size, 1, 4,
964 memory_region_oldmmio_read_accessor, mr);
965 }
966
967 return data;
968 }
969
970 static bool memory_region_dispatch_read(MemoryRegion *mr,
971 hwaddr addr,
972 uint64_t *pval,
973 unsigned size)
974 {
975 if (!memory_region_access_valid(mr, addr, size, false)) {
976 *pval = unassigned_mem_read(mr, addr, size);
977 return true;
978 }
979
980 *pval = memory_region_dispatch_read1(mr, addr, size);
981 adjust_endianness(mr, pval, size);
982 return false;
983 }
984
985 static bool memory_region_dispatch_write(MemoryRegion *mr,
986 hwaddr addr,
987 uint64_t data,
988 unsigned size)
989 {
990 if (!memory_region_access_valid(mr, addr, size, true)) {
991 unassigned_mem_write(mr, addr, data, size);
992 return true;
993 }
994
995 adjust_endianness(mr, &data, size);
996
997 if (mr->ops->write) {
998 access_with_adjusted_size(addr, &data, size,
999 mr->ops->impl.min_access_size,
1000 mr->ops->impl.max_access_size,
1001 memory_region_write_accessor, mr);
1002 } else {
1003 access_with_adjusted_size(addr, &data, size, 1, 4,
1004 memory_region_oldmmio_write_accessor, mr);
1005 }
1006 return false;
1007 }
1008
1009 void memory_region_init_io(MemoryRegion *mr,
1010 Object *owner,
1011 const MemoryRegionOps *ops,
1012 void *opaque,
1013 const char *name,
1014 uint64_t size)
1015 {
1016 memory_region_init(mr, owner, name, size);
1017 mr->ops = ops;
1018 mr->opaque = opaque;
1019 mr->terminates = true;
1020 mr->ram_addr = ~(ram_addr_t)0;
1021 }
1022
1023 void memory_region_init_ram(MemoryRegion *mr,
1024 Object *owner,
1025 const char *name,
1026 uint64_t size)
1027 {
1028 memory_region_init(mr, owner, name, size);
1029 mr->ram = true;
1030 mr->terminates = true;
1031 mr->destructor = memory_region_destructor_ram;
1032 mr->ram_addr = qemu_ram_alloc(size, mr);
1033 }
1034
1035 void memory_region_init_ram_ptr(MemoryRegion *mr,
1036 Object *owner,
1037 const char *name,
1038 uint64_t size,
1039 void *ptr)
1040 {
1041 memory_region_init(mr, owner, name, size);
1042 mr->ram = true;
1043 mr->terminates = true;
1044 mr->destructor = memory_region_destructor_ram_from_ptr;
1045 mr->ram_addr = qemu_ram_alloc_from_ptr(size, ptr, mr);
1046 }
1047
1048 void memory_region_init_alias(MemoryRegion *mr,
1049 Object *owner,
1050 const char *name,
1051 MemoryRegion *orig,
1052 hwaddr offset,
1053 uint64_t size)
1054 {
1055 memory_region_init(mr, owner, name, size);
1056 memory_region_ref(orig);
1057 mr->destructor = memory_region_destructor_alias;
1058 mr->alias = orig;
1059 mr->alias_offset = offset;
1060 }
1061
1062 void memory_region_init_rom_device(MemoryRegion *mr,
1063 Object *owner,
1064 const MemoryRegionOps *ops,
1065 void *opaque,
1066 const char *name,
1067 uint64_t size)
1068 {
1069 memory_region_init(mr, owner, name, size);
1070 mr->ops = ops;
1071 mr->opaque = opaque;
1072 mr->terminates = true;
1073 mr->rom_device = true;
1074 mr->destructor = memory_region_destructor_rom_device;
1075 mr->ram_addr = qemu_ram_alloc(size, mr);
1076 }
1077
1078 void memory_region_init_iommu(MemoryRegion *mr,
1079 Object *owner,
1080 const MemoryRegionIOMMUOps *ops,
1081 const char *name,
1082 uint64_t size)
1083 {
1084 memory_region_init(mr, owner, name, size);
1085 mr->iommu_ops = ops,
1086 mr->terminates = true; /* then re-forwards */
1087 notifier_list_init(&mr->iommu_notify);
1088 }
1089
1090 void memory_region_init_reservation(MemoryRegion *mr,
1091 Object *owner,
1092 const char *name,
1093 uint64_t size)
1094 {
1095 memory_region_init_io(mr, owner, &unassigned_mem_ops, mr, name, size);
1096 }
1097
1098 void memory_region_destroy(MemoryRegion *mr)
1099 {
1100 assert(QTAILQ_EMPTY(&mr->subregions));
1101 assert(memory_region_transaction_depth == 0);
1102 mr->destructor(mr);
1103 memory_region_clear_coalescing(mr);
1104 g_free((char *)mr->name);
1105 g_free(mr->ioeventfds);
1106 }
1107
1108 Object *memory_region_owner(MemoryRegion *mr)
1109 {
1110 return mr->owner;
1111 }
1112
1113 void memory_region_ref(MemoryRegion *mr)
1114 {
1115 if (mr && mr->owner) {
1116 object_ref(mr->owner);
1117 }
1118 }
1119
1120 void memory_region_unref(MemoryRegion *mr)
1121 {
1122 if (mr && mr->owner) {
1123 object_unref(mr->owner);
1124 }
1125 }
1126
1127 uint64_t memory_region_size(MemoryRegion *mr)
1128 {
1129 if (int128_eq(mr->size, int128_2_64())) {
1130 return UINT64_MAX;
1131 }
1132 return int128_get64(mr->size);
1133 }
1134
1135 const char *memory_region_name(MemoryRegion *mr)
1136 {
1137 return mr->name;
1138 }
1139
1140 bool memory_region_is_ram(MemoryRegion *mr)
1141 {
1142 return mr->ram;
1143 }
1144
1145 bool memory_region_is_logging(MemoryRegion *mr)
1146 {
1147 return mr->dirty_log_mask;
1148 }
1149
1150 bool memory_region_is_rom(MemoryRegion *mr)
1151 {
1152 return mr->ram && mr->readonly;
1153 }
1154
1155 bool memory_region_is_iommu(MemoryRegion *mr)
1156 {
1157 return mr->iommu_ops;
1158 }
1159
1160 void memory_region_register_iommu_notifier(MemoryRegion *mr, Notifier *n)
1161 {
1162 notifier_list_add(&mr->iommu_notify, n);
1163 }
1164
1165 void memory_region_unregister_iommu_notifier(Notifier *n)
1166 {
1167 notifier_remove(n);
1168 }
1169
1170 void memory_region_notify_iommu(MemoryRegion *mr,
1171 IOMMUTLBEntry entry)
1172 {
1173 assert(memory_region_is_iommu(mr));
1174 notifier_list_notify(&mr->iommu_notify, &entry);
1175 }
1176
1177 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1178 {
1179 uint8_t mask = 1 << client;
1180
1181 memory_region_transaction_begin();
1182 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
1183 memory_region_update_pending |= mr->enabled;
1184 memory_region_transaction_commit();
1185 }
1186
1187 bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1188 hwaddr size, unsigned client)
1189 {
1190 assert(mr->terminates);
1191 return cpu_physical_memory_get_dirty(mr->ram_addr + addr, size, client);
1192 }
1193
1194 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1195 hwaddr size)
1196 {
1197 assert(mr->terminates);
1198 cpu_physical_memory_set_dirty_range(mr->ram_addr + addr, size);
1199 }
1200
1201 bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1202 hwaddr size, unsigned client)
1203 {
1204 bool ret;
1205 assert(mr->terminates);
1206 ret = cpu_physical_memory_get_dirty(mr->ram_addr + addr, size, client);
1207 if (ret) {
1208 cpu_physical_memory_reset_dirty(mr->ram_addr + addr, size, client);
1209 }
1210 return ret;
1211 }
1212
1213
1214 void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1215 {
1216 AddressSpace *as;
1217 FlatRange *fr;
1218
1219 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1220 FlatView *view = address_space_get_flatview(as);
1221 FOR_EACH_FLAT_RANGE(fr, view) {
1222 if (fr->mr == mr) {
1223 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, log_sync);
1224 }
1225 }
1226 flatview_unref(view);
1227 }
1228 }
1229
1230 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1231 {
1232 if (mr->readonly != readonly) {
1233 memory_region_transaction_begin();
1234 mr->readonly = readonly;
1235 memory_region_update_pending |= mr->enabled;
1236 memory_region_transaction_commit();
1237 }
1238 }
1239
1240 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
1241 {
1242 if (mr->romd_mode != romd_mode) {
1243 memory_region_transaction_begin();
1244 mr->romd_mode = romd_mode;
1245 memory_region_update_pending |= mr->enabled;
1246 memory_region_transaction_commit();
1247 }
1248 }
1249
1250 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
1251 hwaddr size, unsigned client)
1252 {
1253 assert(mr->terminates);
1254 cpu_physical_memory_reset_dirty(mr->ram_addr + addr, size, client);
1255 }
1256
1257 void *memory_region_get_ram_ptr(MemoryRegion *mr)
1258 {
1259 if (mr->alias) {
1260 return memory_region_get_ram_ptr(mr->alias) + mr->alias_offset;
1261 }
1262
1263 assert(mr->terminates);
1264
1265 return qemu_get_ram_ptr(mr->ram_addr & TARGET_PAGE_MASK);
1266 }
1267
1268 static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
1269 {
1270 FlatView *view;
1271 FlatRange *fr;
1272 CoalescedMemoryRange *cmr;
1273 AddrRange tmp;
1274 MemoryRegionSection section;
1275
1276 view = address_space_get_flatview(as);
1277 FOR_EACH_FLAT_RANGE(fr, view) {
1278 if (fr->mr == mr) {
1279 section = (MemoryRegionSection) {
1280 .address_space = as,
1281 .offset_within_address_space = int128_get64(fr->addr.start),
1282 .size = fr->addr.size,
1283 };
1284
1285 MEMORY_LISTENER_CALL(coalesced_mmio_del, Reverse, &section,
1286 int128_get64(fr->addr.start),
1287 int128_get64(fr->addr.size));
1288 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
1289 tmp = addrrange_shift(cmr->addr,
1290 int128_sub(fr->addr.start,
1291 int128_make64(fr->offset_in_region)));
1292 if (!addrrange_intersects(tmp, fr->addr)) {
1293 continue;
1294 }
1295 tmp = addrrange_intersection(tmp, fr->addr);
1296 MEMORY_LISTENER_CALL(coalesced_mmio_add, Forward, &section,
1297 int128_get64(tmp.start),
1298 int128_get64(tmp.size));
1299 }
1300 }
1301 }
1302 flatview_unref(view);
1303 }
1304
1305 static void memory_region_update_coalesced_range(MemoryRegion *mr)
1306 {
1307 AddressSpace *as;
1308
1309 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1310 memory_region_update_coalesced_range_as(mr, as);
1311 }
1312 }
1313
1314 void memory_region_set_coalescing(MemoryRegion *mr)
1315 {
1316 memory_region_clear_coalescing(mr);
1317 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
1318 }
1319
1320 void memory_region_add_coalescing(MemoryRegion *mr,
1321 hwaddr offset,
1322 uint64_t size)
1323 {
1324 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
1325
1326 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
1327 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
1328 memory_region_update_coalesced_range(mr);
1329 memory_region_set_flush_coalesced(mr);
1330 }
1331
1332 void memory_region_clear_coalescing(MemoryRegion *mr)
1333 {
1334 CoalescedMemoryRange *cmr;
1335 bool updated = false;
1336
1337 qemu_flush_coalesced_mmio_buffer();
1338 mr->flush_coalesced_mmio = false;
1339
1340 while (!QTAILQ_EMPTY(&mr->coalesced)) {
1341 cmr = QTAILQ_FIRST(&mr->coalesced);
1342 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
1343 g_free(cmr);
1344 updated = true;
1345 }
1346
1347 if (updated) {
1348 memory_region_update_coalesced_range(mr);
1349 }
1350 }
1351
1352 void memory_region_set_flush_coalesced(MemoryRegion *mr)
1353 {
1354 mr->flush_coalesced_mmio = true;
1355 }
1356
1357 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
1358 {
1359 qemu_flush_coalesced_mmio_buffer();
1360 if (QTAILQ_EMPTY(&mr->coalesced)) {
1361 mr->flush_coalesced_mmio = false;
1362 }
1363 }
1364
1365 void memory_region_add_eventfd(MemoryRegion *mr,
1366 hwaddr addr,
1367 unsigned size,
1368 bool match_data,
1369 uint64_t data,
1370 EventNotifier *e)
1371 {
1372 MemoryRegionIoeventfd mrfd = {
1373 .addr.start = int128_make64(addr),
1374 .addr.size = int128_make64(size),
1375 .match_data = match_data,
1376 .data = data,
1377 .e = e,
1378 };
1379 unsigned i;
1380
1381 adjust_endianness(mr, &mrfd.data, size);
1382 memory_region_transaction_begin();
1383 for (i = 0; i < mr->ioeventfd_nb; ++i) {
1384 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
1385 break;
1386 }
1387 }
1388 ++mr->ioeventfd_nb;
1389 mr->ioeventfds = g_realloc(mr->ioeventfds,
1390 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
1391 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
1392 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
1393 mr->ioeventfds[i] = mrfd;
1394 ioeventfd_update_pending |= mr->enabled;
1395 memory_region_transaction_commit();
1396 }
1397
1398 void memory_region_del_eventfd(MemoryRegion *mr,
1399 hwaddr addr,
1400 unsigned size,
1401 bool match_data,
1402 uint64_t data,
1403 EventNotifier *e)
1404 {
1405 MemoryRegionIoeventfd mrfd = {
1406 .addr.start = int128_make64(addr),
1407 .addr.size = int128_make64(size),
1408 .match_data = match_data,
1409 .data = data,
1410 .e = e,
1411 };
1412 unsigned i;
1413
1414 adjust_endianness(mr, &mrfd.data, size);
1415 memory_region_transaction_begin();
1416 for (i = 0; i < mr->ioeventfd_nb; ++i) {
1417 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
1418 break;
1419 }
1420 }
1421 assert(i != mr->ioeventfd_nb);
1422 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
1423 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
1424 --mr->ioeventfd_nb;
1425 mr->ioeventfds = g_realloc(mr->ioeventfds,
1426 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
1427 ioeventfd_update_pending |= mr->enabled;
1428 memory_region_transaction_commit();
1429 }
1430
1431 static void memory_region_update_container_subregions(MemoryRegion *subregion)
1432 {
1433 hwaddr offset = subregion->addr;
1434 MemoryRegion *mr = subregion->container;
1435 MemoryRegion *other;
1436
1437 memory_region_transaction_begin();
1438
1439 memory_region_ref(subregion);
1440 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
1441 if (subregion->may_overlap || other->may_overlap) {
1442 continue;
1443 }
1444 if (int128_ge(int128_make64(offset),
1445 int128_add(int128_make64(other->addr), other->size))
1446 || int128_le(int128_add(int128_make64(offset), subregion->size),
1447 int128_make64(other->addr))) {
1448 continue;
1449 }
1450 #if 0
1451 printf("warning: subregion collision %llx/%llx (%s) "
1452 "vs %llx/%llx (%s)\n",
1453 (unsigned long long)offset,
1454 (unsigned long long)int128_get64(subregion->size),
1455 subregion->name,
1456 (unsigned long long)other->addr,
1457 (unsigned long long)int128_get64(other->size),
1458 other->name);
1459 #endif
1460 }
1461 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
1462 if (subregion->priority >= other->priority) {
1463 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
1464 goto done;
1465 }
1466 }
1467 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
1468 done:
1469 memory_region_update_pending |= mr->enabled && subregion->enabled;
1470 memory_region_transaction_commit();
1471 }
1472
1473 static void memory_region_add_subregion_common(MemoryRegion *mr,
1474 hwaddr offset,
1475 MemoryRegion *subregion)
1476 {
1477 assert(!subregion->container);
1478 subregion->container = mr;
1479 subregion->addr = offset;
1480 memory_region_update_container_subregions(subregion);
1481 }
1482
1483 void memory_region_add_subregion(MemoryRegion *mr,
1484 hwaddr offset,
1485 MemoryRegion *subregion)
1486 {
1487 subregion->may_overlap = false;
1488 subregion->priority = 0;
1489 memory_region_add_subregion_common(mr, offset, subregion);
1490 }
1491
1492 void memory_region_add_subregion_overlap(MemoryRegion *mr,
1493 hwaddr offset,
1494 MemoryRegion *subregion,
1495 int priority)
1496 {
1497 subregion->may_overlap = true;
1498 subregion->priority = priority;
1499 memory_region_add_subregion_common(mr, offset, subregion);
1500 }
1501
1502 void memory_region_del_subregion(MemoryRegion *mr,
1503 MemoryRegion *subregion)
1504 {
1505 memory_region_transaction_begin();
1506 assert(subregion->container == mr);
1507 subregion->container = NULL;
1508 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
1509 memory_region_unref(subregion);
1510 memory_region_update_pending |= mr->enabled && subregion->enabled;
1511 memory_region_transaction_commit();
1512 }
1513
1514 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
1515 {
1516 if (enabled == mr->enabled) {
1517 return;
1518 }
1519 memory_region_transaction_begin();
1520 mr->enabled = enabled;
1521 memory_region_update_pending = true;
1522 memory_region_transaction_commit();
1523 }
1524
1525 static void memory_region_readd_subregion(MemoryRegion *mr)
1526 {
1527 MemoryRegion *container = mr->container;
1528
1529 if (container) {
1530 memory_region_transaction_begin();
1531 memory_region_ref(mr);
1532 memory_region_del_subregion(container, mr);
1533 mr->container = container;
1534 memory_region_update_container_subregions(mr);
1535 memory_region_unref(mr);
1536 memory_region_transaction_commit();
1537 }
1538 }
1539
1540 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
1541 {
1542 if (addr != mr->addr) {
1543 mr->addr = addr;
1544 memory_region_readd_subregion(mr);
1545 }
1546 }
1547
1548 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
1549 {
1550 assert(mr->alias);
1551
1552 if (offset == mr->alias_offset) {
1553 return;
1554 }
1555
1556 memory_region_transaction_begin();
1557 mr->alias_offset = offset;
1558 memory_region_update_pending |= mr->enabled;
1559 memory_region_transaction_commit();
1560 }
1561
1562 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
1563 {
1564 return mr->ram_addr;
1565 }
1566
1567 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
1568 {
1569 const AddrRange *addr = addr_;
1570 const FlatRange *fr = fr_;
1571
1572 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
1573 return -1;
1574 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
1575 return 1;
1576 }
1577 return 0;
1578 }
1579
1580 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
1581 {
1582 return bsearch(&addr, view->ranges, view->nr,
1583 sizeof(FlatRange), cmp_flatrange_addr);
1584 }
1585
1586 bool memory_region_present(MemoryRegion *container, hwaddr addr)
1587 {
1588 MemoryRegion *mr = memory_region_find(container, addr, 1).mr;
1589 if (!mr || (mr == container)) {
1590 return false;
1591 }
1592 memory_region_unref(mr);
1593 return true;
1594 }
1595
1596 bool memory_region_is_mapped(MemoryRegion *mr)
1597 {
1598 return mr->container ? true : false;
1599 }
1600
1601 MemoryRegionSection memory_region_find(MemoryRegion *mr,
1602 hwaddr addr, uint64_t size)
1603 {
1604 MemoryRegionSection ret = { .mr = NULL };
1605 MemoryRegion *root;
1606 AddressSpace *as;
1607 AddrRange range;
1608 FlatView *view;
1609 FlatRange *fr;
1610
1611 addr += mr->addr;
1612 for (root = mr; root->container; ) {
1613 root = root->container;
1614 addr += root->addr;
1615 }
1616
1617 as = memory_region_to_address_space(root);
1618 if (!as) {
1619 return ret;
1620 }
1621 range = addrrange_make(int128_make64(addr), int128_make64(size));
1622
1623 view = address_space_get_flatview(as);
1624 fr = flatview_lookup(view, range);
1625 if (!fr) {
1626 flatview_unref(view);
1627 return ret;
1628 }
1629
1630 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
1631 --fr;
1632 }
1633
1634 ret.mr = fr->mr;
1635 ret.address_space = as;
1636 range = addrrange_intersection(range, fr->addr);
1637 ret.offset_within_region = fr->offset_in_region;
1638 ret.offset_within_region += int128_get64(int128_sub(range.start,
1639 fr->addr.start));
1640 ret.size = range.size;
1641 ret.offset_within_address_space = int128_get64(range.start);
1642 ret.readonly = fr->readonly;
1643 memory_region_ref(ret.mr);
1644
1645 flatview_unref(view);
1646 return ret;
1647 }
1648
1649 void address_space_sync_dirty_bitmap(AddressSpace *as)
1650 {
1651 FlatView *view;
1652 FlatRange *fr;
1653
1654 view = address_space_get_flatview(as);
1655 FOR_EACH_FLAT_RANGE(fr, view) {
1656 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, log_sync);
1657 }
1658 flatview_unref(view);
1659 }
1660
1661 void memory_global_dirty_log_start(void)
1662 {
1663 global_dirty_log = true;
1664 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
1665 }
1666
1667 void memory_global_dirty_log_stop(void)
1668 {
1669 global_dirty_log = false;
1670 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
1671 }
1672
1673 static void listener_add_address_space(MemoryListener *listener,
1674 AddressSpace *as)
1675 {
1676 FlatView *view;
1677 FlatRange *fr;
1678
1679 if (listener->address_space_filter
1680 && listener->address_space_filter != as) {
1681 return;
1682 }
1683
1684 if (global_dirty_log) {
1685 if (listener->log_global_start) {
1686 listener->log_global_start(listener);
1687 }
1688 }
1689
1690 view = address_space_get_flatview(as);
1691 FOR_EACH_FLAT_RANGE(fr, view) {
1692 MemoryRegionSection section = {
1693 .mr = fr->mr,
1694 .address_space = as,
1695 .offset_within_region = fr->offset_in_region,
1696 .size = fr->addr.size,
1697 .offset_within_address_space = int128_get64(fr->addr.start),
1698 .readonly = fr->readonly,
1699 };
1700 if (listener->region_add) {
1701 listener->region_add(listener, &section);
1702 }
1703 }
1704 flatview_unref(view);
1705 }
1706
1707 void memory_listener_register(MemoryListener *listener, AddressSpace *filter)
1708 {
1709 MemoryListener *other = NULL;
1710 AddressSpace *as;
1711
1712 listener->address_space_filter = filter;
1713 if (QTAILQ_EMPTY(&memory_listeners)
1714 || listener->priority >= QTAILQ_LAST(&memory_listeners,
1715 memory_listeners)->priority) {
1716 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
1717 } else {
1718 QTAILQ_FOREACH(other, &memory_listeners, link) {
1719 if (listener->priority < other->priority) {
1720 break;
1721 }
1722 }
1723 QTAILQ_INSERT_BEFORE(other, listener, link);
1724 }
1725
1726 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1727 listener_add_address_space(listener, as);
1728 }
1729 }
1730
1731 void memory_listener_unregister(MemoryListener *listener)
1732 {
1733 QTAILQ_REMOVE(&memory_listeners, listener, link);
1734 }
1735
1736 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
1737 {
1738 if (QTAILQ_EMPTY(&address_spaces)) {
1739 memory_init();
1740 }
1741
1742 memory_region_transaction_begin();
1743 as->root = root;
1744 as->current_map = g_new(FlatView, 1);
1745 flatview_init(as->current_map);
1746 as->ioeventfd_nb = 0;
1747 as->ioeventfds = NULL;
1748 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
1749 as->name = g_strdup(name ? name : "anonymous");
1750 address_space_init_dispatch(as);
1751 memory_region_update_pending |= root->enabled;
1752 memory_region_transaction_commit();
1753 }
1754
1755 void address_space_destroy(AddressSpace *as)
1756 {
1757 MemoryListener *listener;
1758
1759 /* Flush out anything from MemoryListeners listening in on this */
1760 memory_region_transaction_begin();
1761 as->root = NULL;
1762 memory_region_transaction_commit();
1763 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
1764 address_space_destroy_dispatch(as);
1765
1766 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1767 assert(listener->address_space_filter != as);
1768 }
1769
1770 flatview_unref(as->current_map);
1771 g_free(as->name);
1772 g_free(as->ioeventfds);
1773 }
1774
1775 bool io_mem_read(MemoryRegion *mr, hwaddr addr, uint64_t *pval, unsigned size)
1776 {
1777 return memory_region_dispatch_read(mr, addr, pval, size);
1778 }
1779
1780 bool io_mem_write(MemoryRegion *mr, hwaddr addr,
1781 uint64_t val, unsigned size)
1782 {
1783 return memory_region_dispatch_write(mr, addr, val, size);
1784 }
1785
1786 typedef struct MemoryRegionList MemoryRegionList;
1787
1788 struct MemoryRegionList {
1789 const MemoryRegion *mr;
1790 bool printed;
1791 QTAILQ_ENTRY(MemoryRegionList) queue;
1792 };
1793
1794 typedef QTAILQ_HEAD(queue, MemoryRegionList) MemoryRegionListHead;
1795
1796 static void mtree_print_mr(fprintf_function mon_printf, void *f,
1797 const MemoryRegion *mr, unsigned int level,
1798 hwaddr base,
1799 MemoryRegionListHead *alias_print_queue)
1800 {
1801 MemoryRegionList *new_ml, *ml, *next_ml;
1802 MemoryRegionListHead submr_print_queue;
1803 const MemoryRegion *submr;
1804 unsigned int i;
1805
1806 if (!mr || !mr->enabled) {
1807 return;
1808 }
1809
1810 for (i = 0; i < level; i++) {
1811 mon_printf(f, " ");
1812 }
1813
1814 if (mr->alias) {
1815 MemoryRegionList *ml;
1816 bool found = false;
1817
1818 /* check if the alias is already in the queue */
1819 QTAILQ_FOREACH(ml, alias_print_queue, queue) {
1820 if (ml->mr == mr->alias && !ml->printed) {
1821 found = true;
1822 }
1823 }
1824
1825 if (!found) {
1826 ml = g_new(MemoryRegionList, 1);
1827 ml->mr = mr->alias;
1828 ml->printed = false;
1829 QTAILQ_INSERT_TAIL(alias_print_queue, ml, queue);
1830 }
1831 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
1832 " (prio %d, %c%c): alias %s @%s " TARGET_FMT_plx
1833 "-" TARGET_FMT_plx "\n",
1834 base + mr->addr,
1835 base + mr->addr
1836 + (int128_nz(mr->size) ?
1837 (hwaddr)int128_get64(int128_sub(mr->size,
1838 int128_one())) : 0),
1839 mr->priority,
1840 mr->romd_mode ? 'R' : '-',
1841 !mr->readonly && !(mr->rom_device && mr->romd_mode) ? 'W'
1842 : '-',
1843 mr->name,
1844 mr->alias->name,
1845 mr->alias_offset,
1846 mr->alias_offset
1847 + (int128_nz(mr->size) ?
1848 (hwaddr)int128_get64(int128_sub(mr->size,
1849 int128_one())) : 0));
1850 } else {
1851 mon_printf(f,
1852 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %c%c): %s\n",
1853 base + mr->addr,
1854 base + mr->addr
1855 + (int128_nz(mr->size) ?
1856 (hwaddr)int128_get64(int128_sub(mr->size,
1857 int128_one())) : 0),
1858 mr->priority,
1859 mr->romd_mode ? 'R' : '-',
1860 !mr->readonly && !(mr->rom_device && mr->romd_mode) ? 'W'
1861 : '-',
1862 mr->name);
1863 }
1864
1865 QTAILQ_INIT(&submr_print_queue);
1866
1867 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
1868 new_ml = g_new(MemoryRegionList, 1);
1869 new_ml->mr = submr;
1870 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
1871 if (new_ml->mr->addr < ml->mr->addr ||
1872 (new_ml->mr->addr == ml->mr->addr &&
1873 new_ml->mr->priority > ml->mr->priority)) {
1874 QTAILQ_INSERT_BEFORE(ml, new_ml, queue);
1875 new_ml = NULL;
1876 break;
1877 }
1878 }
1879 if (new_ml) {
1880 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, queue);
1881 }
1882 }
1883
1884 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
1885 mtree_print_mr(mon_printf, f, ml->mr, level + 1, base + mr->addr,
1886 alias_print_queue);
1887 }
1888
1889 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, queue, next_ml) {
1890 g_free(ml);
1891 }
1892 }
1893
1894 void mtree_info(fprintf_function mon_printf, void *f)
1895 {
1896 MemoryRegionListHead ml_head;
1897 MemoryRegionList *ml, *ml2;
1898 AddressSpace *as;
1899
1900 QTAILQ_INIT(&ml_head);
1901
1902 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1903 mon_printf(f, "%s\n", as->name);
1904 mtree_print_mr(mon_printf, f, as->root, 0, 0, &ml_head);
1905 }
1906
1907 mon_printf(f, "aliases\n");
1908 /* print aliased regions */
1909 QTAILQ_FOREACH(ml, &ml_head, queue) {
1910 if (!ml->printed) {
1911 mon_printf(f, "%s\n", ml->mr->name);
1912 mtree_print_mr(mon_printf, f, ml->mr, 0, 0, &ml_head);
1913 }
1914 }
1915
1916 QTAILQ_FOREACH_SAFE(ml, &ml_head, queue, ml2) {
1917 g_free(ml);
1918 }
1919 }
AR7 emulation for QEMU