i.MX: implement a more correct version of EPIT timer.
[qemu/ar7.git] / target-xtensa / cpu-qom.h
blobaf0ce2823c94b5ce4343666ce3ea51cc9c95bf18
1 /*
2 * QEMU Xtensa CPU
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 * All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * * Neither the name of the Open Source and Linux Lab nor the
15 * names of its contributors may be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
22 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #ifndef QEMU_XTENSA_CPU_QOM_H
30 #define QEMU_XTENSA_CPU_QOM_H
32 #include "qom/cpu.h"
33 #include "cpu.h"
35 #define TYPE_XTENSA_CPU "xtensa-cpu"
37 #define XTENSA_CPU_CLASS(class) \
38 OBJECT_CLASS_CHECK(XtensaCPUClass, (class), TYPE_XTENSA_CPU)
39 #define XTENSA_CPU(obj) \
40 OBJECT_CHECK(XtensaCPU, (obj), TYPE_XTENSA_CPU)
41 #define XTENSA_CPU_GET_CLASS(obj) \
42 OBJECT_GET_CLASS(XtensaCPUClass, (obj), TYPE_XTENSA_CPU)
44 /**
45 * XtensaCPUClass:
46 * @parent_realize: The parent class' realize handler.
47 * @parent_reset: The parent class' reset handler.
49 * An Xtensa CPU model.
51 typedef struct XtensaCPUClass {
52 /*< private >*/
53 CPUClass parent_class;
54 /*< public >*/
56 DeviceRealize parent_realize;
57 void (*parent_reset)(CPUState *cpu);
58 } XtensaCPUClass;
60 /**
61 * XtensaCPU:
62 * @env: #CPUXtensaState
64 * An Xtensa CPU.
66 typedef struct XtensaCPU {
67 /*< private >*/
68 CPUState parent_obj;
69 /*< public >*/
71 CPUXtensaState env;
72 } XtensaCPU;
74 static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
76 return XTENSA_CPU(container_of(env, XtensaCPU, env));
79 #define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
81 #define ENV_OFFSET offsetof(XtensaCPU, env)
83 void xtensa_cpu_do_interrupt(CPUState *cpu);
85 #endif