target-tilegx/cpu.c

   1 /*
   2  * QEMU TILE-Gx CPU
   3  *
   4  *  Copyright (c) 2015 Chen Gang
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #include "hw/qdev-properties.h"
  24 #include "migration/vmstate.h"
  25
  26 static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
  27                                   fprintf_function cpu_fprintf, int flags)
  28 {
  29     static const char * const reg_names[TILEGX_R_COUNT] = {
  30          "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
  31          "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  32         "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  33         "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
  34         "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  35         "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
  36         "r48", "r49", "r50", "r51",  "bp",  "tp",  "sp",  "lr"
  37     };
  38
  39     TileGXCPU *cpu = TILEGX_CPU(cs);
  40     CPUTLGState *env = &cpu->env;
  41     int i;
  42
  43     for (i = 0; i < TILEGX_R_COUNT; i++) {
  44         cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s",
  45                     reg_names[i], env->regs[i],
  46                     (i % 4) == 3 ? "\n" : " ");
  47     }
  48     cpu_fprintf(f, "PC  " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n",
  49                 env->pc, env->spregs[TILEGX_SPR_CMPEXCH]);
  50 }
  51
  52 TileGXCPU *cpu_tilegx_init(const char *cpu_model)
  53 {
  54     TileGXCPU *cpu;
  55
  56     cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU));
  57
  58     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
  59
  60     return cpu;
  61 }
  62
  63 static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
  64 {
  65     TileGXCPU *cpu = TILEGX_CPU(cs);
  66
  67     cpu->env.pc = value;
  68 }
  69
  70 static bool tilegx_cpu_has_work(CPUState *cs)
  71 {
  72     return true;
  73 }
  74
  75 static void tilegx_cpu_reset(CPUState *s)
  76 {
  77     TileGXCPU *cpu = TILEGX_CPU(s);
  78     TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
  79     CPUTLGState *env = &cpu->env;
  80
  81     tcc->parent_reset(s);
  82
  83     memset(env, 0, sizeof(CPUTLGState));
  84     tlb_flush(s, 1);
  85 }
  86
  87 static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
  88 {
  89     CPUState *cs = CPU(dev);
  90     TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
  91
  92     cpu_reset(cs);
  93     qemu_init_vcpu(cs);
  94
  95     tcc->parent_realize(dev, errp);
  96 }
  97
  98 static void tilegx_cpu_initfn(Object *obj)
  99 {
 100     CPUState *cs = CPU(obj);
 101     TileGXCPU *cpu = TILEGX_CPU(obj);
 102     CPUTLGState *env = &cpu->env;
 103     static bool tcg_initialized;
 104
 105     cs->env_ptr = env;
 106     cpu_exec_init(cs, &error_abort);
 107
 108     if (tcg_enabled() && !tcg_initialized) {
 109         tcg_initialized = true;
 110         tilegx_tcg_init();
 111     }
 112 }
 113
 114 static void tilegx_cpu_do_interrupt(CPUState *cs)
 115 {
 116     cs->exception_index = -1;
 117 }
 118
 119 static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 120                                        int mmu_idx)
 121 {
 122     TileGXCPU *cpu = TILEGX_CPU(cs);
 123
 124     cs->exception_index = TILEGX_EXCP_SEGV;
 125     cpu->env.excaddr = address;
 126     return 1;
 127 }
 128
 129 static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 130 {
 131     if (interrupt_request & CPU_INTERRUPT_HARD) {
 132         tilegx_cpu_do_interrupt(cs);
 133         return true;
 134     }
 135     return false;
 136 }
 137
 138 static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
 139 {
 140     DeviceClass *dc = DEVICE_CLASS(oc);
 141     CPUClass *cc = CPU_CLASS(oc);
 142     TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
 143
 144     tcc->parent_realize = dc->realize;
 145     dc->realize = tilegx_cpu_realizefn;
 146
 147     tcc->parent_reset = cc->reset;
 148     cc->reset = tilegx_cpu_reset;
 149
 150     cc->has_work = tilegx_cpu_has_work;
 151     cc->do_interrupt = tilegx_cpu_do_interrupt;
 152     cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
 153     cc->dump_state = tilegx_cpu_dump_state;
 154     cc->set_pc = tilegx_cpu_set_pc;
 155     cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
 156     cc->gdb_num_core_regs = 0;
 157 }
 158
 159 static const TypeInfo tilegx_cpu_type_info = {
 160     .name = TYPE_TILEGX_CPU,
 161     .parent = TYPE_CPU,
 162     .instance_size = sizeof(TileGXCPU),
 163     .instance_init = tilegx_cpu_initfn,
 164     .class_size = sizeof(TileGXCPUClass),
 165     .class_init = tilegx_cpu_class_init,
 166 };
 167
 168 static void tilegx_cpu_register_types(void)
 169 {
 170     type_register_static(&tilegx_cpu_type_info);
 171 }
 172
 173 type_init(tilegx_cpu_register_types)