2 * Allwinner (sun4i and above) SD Host Controller emulation
4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "qemu/module.h"
23 #include "qemu/units.h"
24 #include "sysemu/blockdev.h"
26 #include "hw/sd/allwinner-sdhost.h"
27 #include "migration/vmstate.h"
30 #define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus"
31 #define AW_SDHOST_BUS(obj) \
32 OBJECT_CHECK(SDBus, (obj), TYPE_AW_SDHOST_BUS)
34 /* SD Host register offsets */
36 REG_SD_GCTL
= 0x00, /* Global Control */
37 REG_SD_CKCR
= 0x04, /* Clock Control */
38 REG_SD_TMOR
= 0x08, /* Timeout */
39 REG_SD_BWDR
= 0x0C, /* Bus Width */
40 REG_SD_BKSR
= 0x10, /* Block Size */
41 REG_SD_BYCR
= 0x14, /* Byte Count */
42 REG_SD_CMDR
= 0x18, /* Command */
43 REG_SD_CAGR
= 0x1C, /* Command Argument */
44 REG_SD_RESP0
= 0x20, /* Response Zero */
45 REG_SD_RESP1
= 0x24, /* Response One */
46 REG_SD_RESP2
= 0x28, /* Response Two */
47 REG_SD_RESP3
= 0x2C, /* Response Three */
48 REG_SD_IMKR
= 0x30, /* Interrupt Mask */
49 REG_SD_MISR
= 0x34, /* Masked Interrupt Status */
50 REG_SD_RISR
= 0x38, /* Raw Interrupt Status */
51 REG_SD_STAR
= 0x3C, /* Status */
52 REG_SD_FWLR
= 0x40, /* FIFO Water Level */
53 REG_SD_FUNS
= 0x44, /* FIFO Function Select */
54 REG_SD_DBGC
= 0x50, /* Debug Enable */
55 REG_SD_A12A
= 0x58, /* Auto command 12 argument */
56 REG_SD_NTSR
= 0x5C, /* SD NewTiming Set */
57 REG_SD_SDBG
= 0x60, /* SD newTiming Set Debug */
58 REG_SD_HWRST
= 0x78, /* Hardware Reset Register */
59 REG_SD_DMAC
= 0x80, /* Internal DMA Controller Control */
60 REG_SD_DLBA
= 0x84, /* Descriptor List Base Address */
61 REG_SD_IDST
= 0x88, /* Internal DMA Controller Status */
62 REG_SD_IDIE
= 0x8C, /* Internal DMA Controller IRQ Enable */
63 REG_SD_THLDC
= 0x100, /* Card Threshold Control */
64 REG_SD_DSBD
= 0x10C, /* eMMC DDR Start Bit Detection Control */
65 REG_SD_RES_CRC
= 0x110, /* Response CRC from card/eMMC */
66 REG_SD_DATA7_CRC
= 0x114, /* CRC Data 7 from card/eMMC */
67 REG_SD_DATA6_CRC
= 0x118, /* CRC Data 6 from card/eMMC */
68 REG_SD_DATA5_CRC
= 0x11C, /* CRC Data 5 from card/eMMC */
69 REG_SD_DATA4_CRC
= 0x120, /* CRC Data 4 from card/eMMC */
70 REG_SD_DATA3_CRC
= 0x124, /* CRC Data 3 from card/eMMC */
71 REG_SD_DATA2_CRC
= 0x128, /* CRC Data 2 from card/eMMC */
72 REG_SD_DATA1_CRC
= 0x12C, /* CRC Data 1 from card/eMMC */
73 REG_SD_DATA0_CRC
= 0x130, /* CRC Data 0 from card/eMMC */
74 REG_SD_CRC_STA
= 0x134, /* CRC status from card/eMMC during write */
75 REG_SD_FIFO
= 0x200, /* Read/Write FIFO */
78 /* SD Host register flags */
80 SD_GCTL_FIFO_AC_MOD
= (1 << 31),
81 SD_GCTL_DDR_MOD_SEL
= (1 << 10),
82 SD_GCTL_CD_DBC_ENB
= (1 << 8),
83 SD_GCTL_DMA_ENB
= (1 << 5),
84 SD_GCTL_INT_ENB
= (1 << 4),
85 SD_GCTL_DMA_RST
= (1 << 2),
86 SD_GCTL_FIFO_RST
= (1 << 1),
87 SD_GCTL_SOFT_RST
= (1 << 0),
91 SD_CMDR_LOAD
= (1 << 31),
92 SD_CMDR_CLKCHANGE
= (1 << 21),
93 SD_CMDR_WRITE
= (1 << 10),
94 SD_CMDR_AUTOSTOP
= (1 << 12),
95 SD_CMDR_DATA
= (1 << 9),
96 SD_CMDR_RESPONSE_LONG
= (1 << 7),
97 SD_CMDR_RESPONSE
= (1 << 6),
98 SD_CMDR_CMDID_MASK
= (0x3f),
102 SD_RISR_CARD_REMOVE
= (1 << 31),
103 SD_RISR_CARD_INSERT
= (1 << 30),
104 SD_RISR_SDIO_INTR
= (1 << 16),
105 SD_RISR_AUTOCMD_DONE
= (1 << 14),
106 SD_RISR_DATA_COMPLETE
= (1 << 3),
107 SD_RISR_CMD_COMPLETE
= (1 << 2),
108 SD_RISR_NO_RESPONSE
= (1 << 1),
112 SD_STAR_CARD_PRESENT
= (1 << 8),
116 SD_IDST_INT_SUMMARY
= (1 << 8),
117 SD_IDST_RECEIVE_IRQ
= (1 << 1),
118 SD_IDST_TRANSMIT_IRQ
= (1 << 0),
119 SD_IDST_IRQ_MASK
= (1 << 1) | (1 << 0) | (1 << 8),
120 SD_IDST_WR_MASK
= (0x3ff),
123 /* SD Host register reset values */
125 REG_SD_GCTL_RST
= 0x00000300,
126 REG_SD_CKCR_RST
= 0x0,
127 REG_SD_TMOR_RST
= 0xFFFFFF40,
128 REG_SD_BWDR_RST
= 0x0,
129 REG_SD_BKSR_RST
= 0x00000200,
130 REG_SD_BYCR_RST
= 0x00000200,
131 REG_SD_CMDR_RST
= 0x0,
132 REG_SD_CAGR_RST
= 0x0,
133 REG_SD_RESP_RST
= 0x0,
134 REG_SD_IMKR_RST
= 0x0,
135 REG_SD_MISR_RST
= 0x0,
136 REG_SD_RISR_RST
= 0x0,
137 REG_SD_STAR_RST
= 0x00000100,
138 REG_SD_FWLR_RST
= 0x000F0000,
139 REG_SD_FUNS_RST
= 0x0,
140 REG_SD_DBGC_RST
= 0x0,
141 REG_SD_A12A_RST
= 0x0000FFFF,
142 REG_SD_NTSR_RST
= 0x00000001,
143 REG_SD_SDBG_RST
= 0x0,
144 REG_SD_HWRST_RST
= 0x00000001,
145 REG_SD_DMAC_RST
= 0x0,
146 REG_SD_DLBA_RST
= 0x0,
147 REG_SD_IDST_RST
= 0x0,
148 REG_SD_IDIE_RST
= 0x0,
149 REG_SD_THLDC_RST
= 0x0,
150 REG_SD_DSBD_RST
= 0x0,
151 REG_SD_RES_CRC_RST
= 0x0,
152 REG_SD_DATA_CRC_RST
= 0x0,
153 REG_SD_CRC_STA_RST
= 0x0,
154 REG_SD_FIFO_RST
= 0x0,
157 /* Data transfer descriptor for DMA */
158 typedef struct TransferDescriptor
{
159 uint32_t status
; /* Status flags */
160 uint32_t size
; /* Data buffer size */
161 uint32_t addr
; /* Data buffer address */
162 uint32_t next
; /* Physical address of next descriptor */
163 } TransferDescriptor
;
165 /* Data transfer descriptor flags */
167 DESC_STATUS_HOLD
= (1 << 31), /* Set when descriptor is in use by DMA */
168 DESC_STATUS_ERROR
= (1 << 30), /* Set when DMA transfer error occurred */
169 DESC_STATUS_CHAIN
= (1 << 4), /* Indicates chained descriptor. */
170 DESC_STATUS_FIRST
= (1 << 3), /* Set on the first descriptor */
171 DESC_STATUS_LAST
= (1 << 2), /* Set on the last descriptor */
172 DESC_STATUS_NOIRQ
= (1 << 1), /* Skip raising interrupt after transfer */
173 DESC_SIZE_MASK
= (0xfffffffc)
176 static void allwinner_sdhost_update_irq(AwSdHostState
*s
)
180 if (s
->global_ctl
& SD_GCTL_INT_ENB
) {
181 irq
= s
->irq_status
& s
->irq_mask
;
186 trace_allwinner_sdhost_update_irq(irq
);
187 qemu_set_irq(s
->irq
, irq
);
190 static void allwinner_sdhost_update_transfer_cnt(AwSdHostState
*s
,
193 if (s
->transfer_cnt
> bytes
) {
194 s
->transfer_cnt
-= bytes
;
199 if (!s
->transfer_cnt
) {
200 s
->irq_status
|= SD_RISR_DATA_COMPLETE
;
204 static void allwinner_sdhost_set_inserted(DeviceState
*dev
, bool inserted
)
206 AwSdHostState
*s
= AW_SDHOST(dev
);
208 trace_allwinner_sdhost_set_inserted(inserted
);
211 s
->irq_status
|= SD_RISR_CARD_INSERT
;
212 s
->irq_status
&= ~SD_RISR_CARD_REMOVE
;
213 s
->status
|= SD_STAR_CARD_PRESENT
;
215 s
->irq_status
&= ~SD_RISR_CARD_INSERT
;
216 s
->irq_status
|= SD_RISR_CARD_REMOVE
;
217 s
->status
&= ~SD_STAR_CARD_PRESENT
;
220 allwinner_sdhost_update_irq(s
);
223 static void allwinner_sdhost_send_command(AwSdHostState
*s
)
229 /* Auto clear load flag */
230 s
->command
&= ~SD_CMDR_LOAD
;
232 /* Clock change does not actually interact with the SD bus */
233 if (!(s
->command
& SD_CMDR_CLKCHANGE
)) {
235 /* Prepare request */
236 request
.cmd
= s
->command
& SD_CMDR_CMDID_MASK
;
237 request
.arg
= s
->command_arg
;
239 /* Send request to SD bus */
240 rlen
= sdbus_do_command(&s
->sdbus
, &request
, resp
);
245 /* If the command has a response, store it in the response registers */
246 if ((s
->command
& SD_CMDR_RESPONSE
)) {
247 if (rlen
== 4 && !(s
->command
& SD_CMDR_RESPONSE_LONG
)) {
248 s
->response
[0] = ldl_be_p(&resp
[0]);
249 s
->response
[1] = s
->response
[2] = s
->response
[3] = 0;
251 } else if (rlen
== 16 && (s
->command
& SD_CMDR_RESPONSE_LONG
)) {
252 s
->response
[0] = ldl_be_p(&resp
[12]);
253 s
->response
[1] = ldl_be_p(&resp
[8]);
254 s
->response
[2] = ldl_be_p(&resp
[4]);
255 s
->response
[3] = ldl_be_p(&resp
[0]);
262 /* Set interrupt status bits */
263 s
->irq_status
|= SD_RISR_CMD_COMPLETE
;
267 s
->irq_status
|= SD_RISR_NO_RESPONSE
;
270 static void allwinner_sdhost_auto_stop(AwSdHostState
*s
)
273 * The stop command (CMD12) ensures the SD bus
274 * returns to the transfer state.
276 if ((s
->command
& SD_CMDR_AUTOSTOP
) && (s
->transfer_cnt
== 0)) {
277 /* First save current command registers */
278 uint32_t saved_cmd
= s
->command
;
279 uint32_t saved_arg
= s
->command_arg
;
281 /* Prepare stop command (CMD12) */
282 s
->command
&= ~SD_CMDR_CMDID_MASK
;
283 s
->command
|= 12; /* CMD12 */
286 /* Put the command on SD bus */
287 allwinner_sdhost_send_command(s
);
289 /* Restore command values */
290 s
->command
= saved_cmd
;
291 s
->command_arg
= saved_arg
;
293 /* Set IRQ status bit for automatic stop done */
294 s
->irq_status
|= SD_RISR_AUTOCMD_DONE
;
298 static uint32_t allwinner_sdhost_process_desc(AwSdHostState
*s
,
300 TransferDescriptor
*desc
,
301 bool is_write
, uint32_t max_bytes
)
303 AwSdHostClass
*klass
= AW_SDHOST_GET_CLASS(s
);
304 uint32_t num_done
= 0;
305 uint32_t num_bytes
= max_bytes
;
308 /* Read descriptor */
309 cpu_physical_memory_read(desc_addr
, desc
, sizeof(*desc
));
310 if (desc
->size
== 0) {
311 desc
->size
= klass
->max_desc_size
;
312 } else if (desc
->size
> klass
->max_desc_size
) {
313 qemu_log_mask(LOG_GUEST_ERROR
, "%s: DMA descriptor buffer size "
314 " is out-of-bounds: %" PRIu32
" > %zu",
315 __func__
, desc
->size
, klass
->max_desc_size
);
316 desc
->size
= klass
->max_desc_size
;
318 if (desc
->size
< num_bytes
) {
319 num_bytes
= desc
->size
;
322 trace_allwinner_sdhost_process_desc(desc_addr
, desc
->size
,
323 is_write
, max_bytes
);
325 while (num_done
< num_bytes
) {
326 /* Try to completely fill the local buffer */
327 uint32_t buf_bytes
= num_bytes
- num_done
;
328 if (buf_bytes
> sizeof(buf
)) {
329 buf_bytes
= sizeof(buf
);
332 /* Write to SD bus */
334 cpu_physical_memory_read((desc
->addr
& DESC_SIZE_MASK
) + num_done
,
336 sdbus_write_data(&s
->sdbus
, buf
, buf_bytes
);
338 /* Read from SD bus */
340 sdbus_read_data(&s
->sdbus
, buf
, buf_bytes
);
341 cpu_physical_memory_write((desc
->addr
& DESC_SIZE_MASK
) + num_done
,
344 num_done
+= buf_bytes
;
347 /* Clear hold flag and flush descriptor */
348 desc
->status
&= ~DESC_STATUS_HOLD
;
349 cpu_physical_memory_write(desc_addr
, desc
, sizeof(*desc
));
354 static void allwinner_sdhost_dma(AwSdHostState
*s
)
356 TransferDescriptor desc
;
357 hwaddr desc_addr
= s
->desc_base
;
358 bool is_write
= (s
->command
& SD_CMDR_WRITE
);
359 uint32_t bytes_done
= 0;
361 /* Check if DMA can be performed */
362 if (s
->byte_count
== 0 || s
->block_size
== 0 ||
363 !(s
->global_ctl
& SD_GCTL_DMA_ENB
)) {
368 * For read operations, data must be available on the SD bus
369 * If not, it is an error and we should not act at all
371 if (!is_write
&& !sdbus_data_ready(&s
->sdbus
)) {
375 /* Process the DMA descriptors until all data is copied */
376 while (s
->byte_count
> 0) {
377 bytes_done
= allwinner_sdhost_process_desc(s
, desc_addr
, &desc
,
378 is_write
, s
->byte_count
);
379 allwinner_sdhost_update_transfer_cnt(s
, bytes_done
);
381 if (bytes_done
<= s
->byte_count
) {
382 s
->byte_count
-= bytes_done
;
387 if (desc
.status
& DESC_STATUS_LAST
) {
390 desc_addr
= desc
.next
;
394 /* Raise IRQ to signal DMA is completed */
395 s
->irq_status
|= SD_RISR_DATA_COMPLETE
| SD_RISR_SDIO_INTR
;
397 /* Update DMAC bits */
398 s
->dmac_status
|= SD_IDST_INT_SUMMARY
;
401 s
->dmac_status
|= SD_IDST_TRANSMIT_IRQ
;
403 s
->dmac_status
|= SD_IDST_RECEIVE_IRQ
;
407 static uint64_t allwinner_sdhost_read(void *opaque
, hwaddr offset
,
410 AwSdHostState
*s
= AW_SDHOST(opaque
);
414 case REG_SD_GCTL
: /* Global Control */
417 case REG_SD_CKCR
: /* Clock Control */
420 case REG_SD_TMOR
: /* Timeout */
423 case REG_SD_BWDR
: /* Bus Width */
426 case REG_SD_BKSR
: /* Block Size */
429 case REG_SD_BYCR
: /* Byte Count */
432 case REG_SD_CMDR
: /* Command */
435 case REG_SD_CAGR
: /* Command Argument */
436 res
= s
->command_arg
;
438 case REG_SD_RESP0
: /* Response Zero */
439 res
= s
->response
[0];
441 case REG_SD_RESP1
: /* Response One */
442 res
= s
->response
[1];
444 case REG_SD_RESP2
: /* Response Two */
445 res
= s
->response
[2];
447 case REG_SD_RESP3
: /* Response Three */
448 res
= s
->response
[3];
450 case REG_SD_IMKR
: /* Interrupt Mask */
453 case REG_SD_MISR
: /* Masked Interrupt Status */
454 res
= s
->irq_status
& s
->irq_mask
;
456 case REG_SD_RISR
: /* Raw Interrupt Status */
459 case REG_SD_STAR
: /* Status */
462 case REG_SD_FWLR
: /* FIFO Water Level */
463 res
= s
->fifo_wlevel
;
465 case REG_SD_FUNS
: /* FIFO Function Select */
466 res
= s
->fifo_func_sel
;
468 case REG_SD_DBGC
: /* Debug Enable */
469 res
= s
->debug_enable
;
471 case REG_SD_A12A
: /* Auto command 12 argument */
474 case REG_SD_NTSR
: /* SD NewTiming Set */
475 res
= s
->newtiming_set
;
477 case REG_SD_SDBG
: /* SD newTiming Set Debug */
478 res
= s
->newtiming_debug
;
480 case REG_SD_HWRST
: /* Hardware Reset Register */
481 res
= s
->hardware_rst
;
483 case REG_SD_DMAC
: /* Internal DMA Controller Control */
486 case REG_SD_DLBA
: /* Descriptor List Base Address */
489 case REG_SD_IDST
: /* Internal DMA Controller Status */
490 res
= s
->dmac_status
;
492 case REG_SD_IDIE
: /* Internal DMA Controller Interrupt Enable */
495 case REG_SD_THLDC
: /* Card Threshold Control */
496 res
= s
->card_threshold
;
498 case REG_SD_DSBD
: /* eMMC DDR Start Bit Detection Control */
499 res
= s
->startbit_detect
;
501 case REG_SD_RES_CRC
: /* Response CRC from card/eMMC */
502 res
= s
->response_crc
;
504 case REG_SD_DATA7_CRC
: /* CRC Data 7 from card/eMMC */
505 case REG_SD_DATA6_CRC
: /* CRC Data 6 from card/eMMC */
506 case REG_SD_DATA5_CRC
: /* CRC Data 5 from card/eMMC */
507 case REG_SD_DATA4_CRC
: /* CRC Data 4 from card/eMMC */
508 case REG_SD_DATA3_CRC
: /* CRC Data 3 from card/eMMC */
509 case REG_SD_DATA2_CRC
: /* CRC Data 2 from card/eMMC */
510 case REG_SD_DATA1_CRC
: /* CRC Data 1 from card/eMMC */
511 case REG_SD_DATA0_CRC
: /* CRC Data 0 from card/eMMC */
512 res
= s
->data_crc
[((offset
- REG_SD_DATA7_CRC
) / sizeof(uint32_t))];
514 case REG_SD_CRC_STA
: /* CRC status from card/eMMC in write operation */
517 case REG_SD_FIFO
: /* Read/Write FIFO */
518 if (sdbus_data_ready(&s
->sdbus
)) {
519 sdbus_read_data(&s
->sdbus
, &res
, sizeof(uint32_t));
521 allwinner_sdhost_update_transfer_cnt(s
, sizeof(uint32_t));
522 allwinner_sdhost_auto_stop(s
);
523 allwinner_sdhost_update_irq(s
);
525 qemu_log_mask(LOG_GUEST_ERROR
, "%s: no data ready on SD bus\n",
530 qemu_log_mask(LOG_GUEST_ERROR
, "%s: out-of-bounds offset %"
531 HWADDR_PRIx
"\n", __func__
, offset
);
536 trace_allwinner_sdhost_read(offset
, res
, size
);
540 static void allwinner_sdhost_write(void *opaque
, hwaddr offset
,
541 uint64_t value
, unsigned size
)
543 AwSdHostState
*s
= AW_SDHOST(opaque
);
546 trace_allwinner_sdhost_write(offset
, value
, size
);
549 case REG_SD_GCTL
: /* Global Control */
550 s
->global_ctl
= value
;
551 s
->global_ctl
&= ~(SD_GCTL_DMA_RST
| SD_GCTL_FIFO_RST
|
553 allwinner_sdhost_update_irq(s
);
555 case REG_SD_CKCR
: /* Clock Control */
556 s
->clock_ctl
= value
;
558 case REG_SD_TMOR
: /* Timeout */
561 case REG_SD_BWDR
: /* Bus Width */
562 s
->bus_width
= value
;
564 case REG_SD_BKSR
: /* Block Size */
565 s
->block_size
= value
;
567 case REG_SD_BYCR
: /* Byte Count */
568 s
->byte_count
= value
;
569 s
->transfer_cnt
= value
;
571 case REG_SD_CMDR
: /* Command */
573 if (value
& SD_CMDR_LOAD
) {
574 allwinner_sdhost_send_command(s
);
575 allwinner_sdhost_dma(s
);
576 allwinner_sdhost_auto_stop(s
);
578 allwinner_sdhost_update_irq(s
);
580 case REG_SD_CAGR
: /* Command Argument */
581 s
->command_arg
= value
;
583 case REG_SD_RESP0
: /* Response Zero */
584 s
->response
[0] = value
;
586 case REG_SD_RESP1
: /* Response One */
587 s
->response
[1] = value
;
589 case REG_SD_RESP2
: /* Response Two */
590 s
->response
[2] = value
;
592 case REG_SD_RESP3
: /* Response Three */
593 s
->response
[3] = value
;
595 case REG_SD_IMKR
: /* Interrupt Mask */
597 allwinner_sdhost_update_irq(s
);
599 case REG_SD_MISR
: /* Masked Interrupt Status */
600 case REG_SD_RISR
: /* Raw Interrupt Status */
601 s
->irq_status
&= ~value
;
602 allwinner_sdhost_update_irq(s
);
604 case REG_SD_STAR
: /* Status */
606 allwinner_sdhost_update_irq(s
);
608 case REG_SD_FWLR
: /* FIFO Water Level */
609 s
->fifo_wlevel
= value
;
611 case REG_SD_FUNS
: /* FIFO Function Select */
612 s
->fifo_func_sel
= value
;
614 case REG_SD_DBGC
: /* Debug Enable */
615 s
->debug_enable
= value
;
617 case REG_SD_A12A
: /* Auto command 12 argument */
618 s
->auto12_arg
= value
;
620 case REG_SD_NTSR
: /* SD NewTiming Set */
621 s
->newtiming_set
= value
;
623 case REG_SD_SDBG
: /* SD newTiming Set Debug */
624 s
->newtiming_debug
= value
;
626 case REG_SD_HWRST
: /* Hardware Reset Register */
627 s
->hardware_rst
= value
;
629 case REG_SD_DMAC
: /* Internal DMA Controller Control */
631 allwinner_sdhost_update_irq(s
);
633 case REG_SD_DLBA
: /* Descriptor List Base Address */
634 s
->desc_base
= value
;
636 case REG_SD_IDST
: /* Internal DMA Controller Status */
637 s
->dmac_status
&= (~SD_IDST_WR_MASK
) | (~value
& SD_IDST_WR_MASK
);
638 allwinner_sdhost_update_irq(s
);
640 case REG_SD_IDIE
: /* Internal DMA Controller Interrupt Enable */
642 allwinner_sdhost_update_irq(s
);
644 case REG_SD_THLDC
: /* Card Threshold Control */
645 s
->card_threshold
= value
;
647 case REG_SD_DSBD
: /* eMMC DDR Start Bit Detection Control */
648 s
->startbit_detect
= value
;
650 case REG_SD_FIFO
: /* Read/Write FIFO */
651 u32
= cpu_to_le32(value
);
652 sdbus_write_data(&s
->sdbus
, &u32
, sizeof(u32
));
653 allwinner_sdhost_update_transfer_cnt(s
, sizeof(u32
));
654 allwinner_sdhost_auto_stop(s
);
655 allwinner_sdhost_update_irq(s
);
657 case REG_SD_RES_CRC
: /* Response CRC from card/eMMC */
658 case REG_SD_DATA7_CRC
: /* CRC Data 7 from card/eMMC */
659 case REG_SD_DATA6_CRC
: /* CRC Data 6 from card/eMMC */
660 case REG_SD_DATA5_CRC
: /* CRC Data 5 from card/eMMC */
661 case REG_SD_DATA4_CRC
: /* CRC Data 4 from card/eMMC */
662 case REG_SD_DATA3_CRC
: /* CRC Data 3 from card/eMMC */
663 case REG_SD_DATA2_CRC
: /* CRC Data 2 from card/eMMC */
664 case REG_SD_DATA1_CRC
: /* CRC Data 1 from card/eMMC */
665 case REG_SD_DATA0_CRC
: /* CRC Data 0 from card/eMMC */
666 case REG_SD_CRC_STA
: /* CRC status from card/eMMC in write operation */
669 qemu_log_mask(LOG_GUEST_ERROR
, "%s: out-of-bounds offset %"
670 HWADDR_PRIx
"\n", __func__
, offset
);
675 static const MemoryRegionOps allwinner_sdhost_ops
= {
676 .read
= allwinner_sdhost_read
,
677 .write
= allwinner_sdhost_write
,
678 .endianness
= DEVICE_NATIVE_ENDIAN
,
680 .min_access_size
= 4,
681 .max_access_size
= 4,
683 .impl
.min_access_size
= 4,
686 static const VMStateDescription vmstate_allwinner_sdhost
= {
687 .name
= "allwinner-sdhost",
689 .minimum_version_id
= 1,
690 .fields
= (VMStateField
[]) {
691 VMSTATE_UINT32(global_ctl
, AwSdHostState
),
692 VMSTATE_UINT32(clock_ctl
, AwSdHostState
),
693 VMSTATE_UINT32(timeout
, AwSdHostState
),
694 VMSTATE_UINT32(bus_width
, AwSdHostState
),
695 VMSTATE_UINT32(block_size
, AwSdHostState
),
696 VMSTATE_UINT32(byte_count
, AwSdHostState
),
697 VMSTATE_UINT32(transfer_cnt
, AwSdHostState
),
698 VMSTATE_UINT32(command
, AwSdHostState
),
699 VMSTATE_UINT32(command_arg
, AwSdHostState
),
700 VMSTATE_UINT32_ARRAY(response
, AwSdHostState
, 4),
701 VMSTATE_UINT32(irq_mask
, AwSdHostState
),
702 VMSTATE_UINT32(irq_status
, AwSdHostState
),
703 VMSTATE_UINT32(status
, AwSdHostState
),
704 VMSTATE_UINT32(fifo_wlevel
, AwSdHostState
),
705 VMSTATE_UINT32(fifo_func_sel
, AwSdHostState
),
706 VMSTATE_UINT32(debug_enable
, AwSdHostState
),
707 VMSTATE_UINT32(auto12_arg
, AwSdHostState
),
708 VMSTATE_UINT32(newtiming_set
, AwSdHostState
),
709 VMSTATE_UINT32(newtiming_debug
, AwSdHostState
),
710 VMSTATE_UINT32(hardware_rst
, AwSdHostState
),
711 VMSTATE_UINT32(dmac
, AwSdHostState
),
712 VMSTATE_UINT32(desc_base
, AwSdHostState
),
713 VMSTATE_UINT32(dmac_status
, AwSdHostState
),
714 VMSTATE_UINT32(dmac_irq
, AwSdHostState
),
715 VMSTATE_UINT32(card_threshold
, AwSdHostState
),
716 VMSTATE_UINT32(startbit_detect
, AwSdHostState
),
717 VMSTATE_UINT32(response_crc
, AwSdHostState
),
718 VMSTATE_UINT32_ARRAY(data_crc
, AwSdHostState
, 8),
719 VMSTATE_UINT32(status_crc
, AwSdHostState
),
720 VMSTATE_END_OF_LIST()
724 static void allwinner_sdhost_init(Object
*obj
)
726 AwSdHostState
*s
= AW_SDHOST(obj
);
728 qbus_create_inplace(&s
->sdbus
, sizeof(s
->sdbus
),
729 TYPE_AW_SDHOST_BUS
, DEVICE(s
), "sd-bus");
731 memory_region_init_io(&s
->iomem
, obj
, &allwinner_sdhost_ops
, s
,
732 TYPE_AW_SDHOST
, 4 * KiB
);
733 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->iomem
);
734 sysbus_init_irq(SYS_BUS_DEVICE(s
), &s
->irq
);
737 static void allwinner_sdhost_reset(DeviceState
*dev
)
739 AwSdHostState
*s
= AW_SDHOST(dev
);
741 s
->global_ctl
= REG_SD_GCTL_RST
;
742 s
->clock_ctl
= REG_SD_CKCR_RST
;
743 s
->timeout
= REG_SD_TMOR_RST
;
744 s
->bus_width
= REG_SD_BWDR_RST
;
745 s
->block_size
= REG_SD_BKSR_RST
;
746 s
->byte_count
= REG_SD_BYCR_RST
;
749 s
->command
= REG_SD_CMDR_RST
;
750 s
->command_arg
= REG_SD_CAGR_RST
;
752 for (int i
= 0; i
< ARRAY_SIZE(s
->response
); i
++) {
753 s
->response
[i
] = REG_SD_RESP_RST
;
756 s
->irq_mask
= REG_SD_IMKR_RST
;
757 s
->irq_status
= REG_SD_RISR_RST
;
758 s
->status
= REG_SD_STAR_RST
;
760 s
->fifo_wlevel
= REG_SD_FWLR_RST
;
761 s
->fifo_func_sel
= REG_SD_FUNS_RST
;
762 s
->debug_enable
= REG_SD_DBGC_RST
;
763 s
->auto12_arg
= REG_SD_A12A_RST
;
764 s
->newtiming_set
= REG_SD_NTSR_RST
;
765 s
->newtiming_debug
= REG_SD_SDBG_RST
;
766 s
->hardware_rst
= REG_SD_HWRST_RST
;
767 s
->dmac
= REG_SD_DMAC_RST
;
768 s
->desc_base
= REG_SD_DLBA_RST
;
769 s
->dmac_status
= REG_SD_IDST_RST
;
770 s
->dmac_irq
= REG_SD_IDIE_RST
;
771 s
->card_threshold
= REG_SD_THLDC_RST
;
772 s
->startbit_detect
= REG_SD_DSBD_RST
;
773 s
->response_crc
= REG_SD_RES_CRC_RST
;
775 for (int i
= 0; i
< ARRAY_SIZE(s
->data_crc
); i
++) {
776 s
->data_crc
[i
] = REG_SD_DATA_CRC_RST
;
779 s
->status_crc
= REG_SD_CRC_STA_RST
;
782 static void allwinner_sdhost_bus_class_init(ObjectClass
*klass
, void *data
)
784 SDBusClass
*sbc
= SD_BUS_CLASS(klass
);
786 sbc
->set_inserted
= allwinner_sdhost_set_inserted
;
789 static void allwinner_sdhost_class_init(ObjectClass
*klass
, void *data
)
791 DeviceClass
*dc
= DEVICE_CLASS(klass
);
793 dc
->reset
= allwinner_sdhost_reset
;
794 dc
->vmsd
= &vmstate_allwinner_sdhost
;
797 static void allwinner_sdhost_sun4i_class_init(ObjectClass
*klass
, void *data
)
799 AwSdHostClass
*sc
= AW_SDHOST_CLASS(klass
);
800 sc
->max_desc_size
= 8 * KiB
;
803 static void allwinner_sdhost_sun5i_class_init(ObjectClass
*klass
, void *data
)
805 AwSdHostClass
*sc
= AW_SDHOST_CLASS(klass
);
806 sc
->max_desc_size
= 64 * KiB
;
809 static TypeInfo allwinner_sdhost_info
= {
810 .name
= TYPE_AW_SDHOST
,
811 .parent
= TYPE_SYS_BUS_DEVICE
,
812 .instance_init
= allwinner_sdhost_init
,
813 .instance_size
= sizeof(AwSdHostState
),
814 .class_init
= allwinner_sdhost_class_init
,
815 .class_size
= sizeof(AwSdHostClass
),
819 static const TypeInfo allwinner_sdhost_sun4i_info
= {
820 .name
= TYPE_AW_SDHOST_SUN4I
,
821 .parent
= TYPE_AW_SDHOST
,
822 .class_init
= allwinner_sdhost_sun4i_class_init
,
825 static const TypeInfo allwinner_sdhost_sun5i_info
= {
826 .name
= TYPE_AW_SDHOST_SUN5I
,
827 .parent
= TYPE_AW_SDHOST
,
828 .class_init
= allwinner_sdhost_sun5i_class_init
,
831 static const TypeInfo allwinner_sdhost_bus_info
= {
832 .name
= TYPE_AW_SDHOST_BUS
,
833 .parent
= TYPE_SD_BUS
,
834 .instance_size
= sizeof(SDBus
),
835 .class_init
= allwinner_sdhost_bus_class_init
,
838 static void allwinner_sdhost_register_types(void)
840 type_register_static(&allwinner_sdhost_info
);
841 type_register_static(&allwinner_sdhost_sun4i_info
);
842 type_register_static(&allwinner_sdhost_sun5i_info
);
843 type_register_static(&allwinner_sdhost_bus_info
);
846 type_init(allwinner_sdhost_register_types
)