2 * QEMU PowerPC sPAPR XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "qemu/error-report.h"
15 #include "target/ppc/cpu.h"
16 #include "sysemu/cpus.h"
17 #include "sysemu/reset.h"
18 #include "migration/vmstate.h"
19 #include "monitor/monitor.h"
20 #include "hw/ppc/fdt.h"
21 #include "hw/ppc/spapr.h"
22 #include "hw/ppc/spapr_cpu_core.h"
23 #include "hw/ppc/spapr_xive.h"
24 #include "hw/ppc/xive.h"
25 #include "hw/ppc/xive_regs.h"
26 #include "hw/qdev-properties.h"
29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we
30 * use for the ESB pages and the TIMA pages
32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull
33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull
36 * The allocation of VP blocks is a complex operation in OPAL and the
37 * VP identifiers have a relation with the number of HW chips, the
38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE
39 * controller model does not have the same constraints and can use a
40 * simple mapping scheme of the CPU vcpu_id
42 * These identifiers are never returned to the OS.
45 #define SPAPR_XIVE_NVT_BASE 0x400
48 * sPAPR NVT and END indexing helpers
50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk
, uint32_t nvt_idx
)
52 return nvt_idx
- SPAPR_XIVE_NVT_BASE
;
55 static void spapr_xive_cpu_to_nvt(PowerPCCPU
*cpu
,
56 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
61 *out_nvt_blk
= SPAPR_XIVE_BLOCK_ID
;
65 *out_nvt_idx
= SPAPR_XIVE_NVT_BASE
+ cpu
->vcpu_id
;
69 static int spapr_xive_target_to_nvt(uint32_t target
,
70 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
72 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
78 spapr_xive_cpu_to_nvt(cpu
, out_nvt_blk
, out_nvt_idx
);
83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8
86 int spapr_xive_end_to_target(uint8_t end_blk
, uint32_t end_idx
,
87 uint32_t *out_server
, uint8_t *out_prio
)
90 assert(end_blk
== SPAPR_XIVE_BLOCK_ID
);
93 *out_server
= end_idx
>> 3;
97 *out_prio
= end_idx
& 0x7;
102 static void spapr_xive_cpu_to_end(PowerPCCPU
*cpu
, uint8_t prio
,
103 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
108 *out_end_blk
= SPAPR_XIVE_BLOCK_ID
;
112 *out_end_idx
= (cpu
->vcpu_id
<< 3) + prio
;
116 static int spapr_xive_target_to_end(uint32_t target
, uint8_t prio
,
117 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
119 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
125 spapr_xive_cpu_to_end(cpu
, prio
, out_end_blk
, out_end_idx
);
130 * On sPAPR machines, use a simplified output for the XIVE END
131 * structure dumping only the information related to the OS EQ.
133 static void spapr_xive_end_pic_print_info(SpaprXive
*xive
, XiveEND
*end
,
136 uint64_t qaddr_base
= xive_end_qaddr(end
);
137 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
138 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
139 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
140 uint32_t qentries
= 1 << (qsize
+ 10);
141 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
142 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
144 monitor_printf(mon
, "%3d/%d % 6d/%5d @%"PRIx64
" ^%d",
145 spapr_xive_nvt_to_target(0, nvt
),
146 priority
, qindex
, qentries
, qaddr_base
, qgen
);
148 xive_end_queue_pic_print_info(end
, 6, mon
);
152 * kvm_irqchip_in_kernel() will cause the compiler to turn this
153 * info a nop if CONFIG_KVM isn't defined.
155 #define spapr_xive_in_kernel(xive) \
156 (kvm_irqchip_in_kernel() && (xive)->fd != -1)
158 void spapr_xive_pic_print_info(SpaprXive
*xive
, Monitor
*mon
)
160 XiveSource
*xsrc
= &xive
->source
;
163 if (spapr_xive_in_kernel(xive
)) {
164 Error
*local_err
= NULL
;
166 kvmppc_xive_synchronize_state(xive
, &local_err
);
168 error_report_err(local_err
);
173 monitor_printf(mon
, " LISN PQ EISN CPU/PRIO EQ\n");
175 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
176 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
177 XiveEAS
*eas
= &xive
->eat
[i
];
179 if (!xive_eas_is_valid(eas
)) {
183 monitor_printf(mon
, " %08x %s %c%c%c %s %08x ", i
,
184 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
185 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
186 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
187 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ',
188 xive_eas_is_masked(eas
) ? "M" : " ",
189 (int) xive_get_field64(EAS_END_DATA
, eas
->w
));
191 if (!xive_eas_is_masked(eas
)) {
192 uint32_t end_idx
= xive_get_field64(EAS_END_INDEX
, eas
->w
);
195 assert(end_idx
< xive
->nr_ends
);
196 end
= &xive
->endt
[end_idx
];
198 if (xive_end_is_valid(end
)) {
199 spapr_xive_end_pic_print_info(xive
, end
, mon
);
202 monitor_printf(mon
, "\n");
206 void spapr_xive_mmio_set_enabled(SpaprXive
*xive
, bool enable
)
208 memory_region_set_enabled(&xive
->source
.esb_mmio
, enable
);
209 memory_region_set_enabled(&xive
->tm_mmio
, enable
);
211 /* Disable the END ESBs until a guest OS makes use of them */
212 memory_region_set_enabled(&xive
->end_source
.esb_mmio
, false);
215 static void spapr_xive_tm_write(void *opaque
, hwaddr offset
,
216 uint64_t value
, unsigned size
)
218 XiveTCTX
*tctx
= spapr_cpu_state(POWERPC_CPU(current_cpu
))->tctx
;
220 xive_tctx_tm_write(XIVE_PRESENTER(opaque
), tctx
, offset
, value
, size
);
223 static uint64_t spapr_xive_tm_read(void *opaque
, hwaddr offset
, unsigned size
)
225 XiveTCTX
*tctx
= spapr_cpu_state(POWERPC_CPU(current_cpu
))->tctx
;
227 return xive_tctx_tm_read(XIVE_PRESENTER(opaque
), tctx
, offset
, size
);
230 const MemoryRegionOps spapr_xive_tm_ops
= {
231 .read
= spapr_xive_tm_read
,
232 .write
= spapr_xive_tm_write
,
233 .endianness
= DEVICE_BIG_ENDIAN
,
235 .min_access_size
= 1,
236 .max_access_size
= 8,
239 .min_access_size
= 1,
240 .max_access_size
= 8,
244 static void spapr_xive_end_reset(XiveEND
*end
)
246 memset(end
, 0, sizeof(*end
));
248 /* switch off the escalation and notification ESBs */
249 end
->w1
= cpu_to_be32(END_W1_ESe_Q
| END_W1_ESn_Q
);
252 static void spapr_xive_reset(void *dev
)
254 SpaprXive
*xive
= SPAPR_XIVE(dev
);
258 * The XiveSource has its own reset handler, which mask off all
262 /* Mask all valid EASs in the IRQ number space. */
263 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
264 XiveEAS
*eas
= &xive
->eat
[i
];
265 if (xive_eas_is_valid(eas
)) {
266 eas
->w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
273 for (i
= 0; i
< xive
->nr_ends
; i
++) {
274 spapr_xive_end_reset(&xive
->endt
[i
]);
278 static void spapr_xive_instance_init(Object
*obj
)
280 SpaprXive
*xive
= SPAPR_XIVE(obj
);
282 object_initialize_child(obj
, "source", &xive
->source
, TYPE_XIVE_SOURCE
);
284 object_initialize_child(obj
, "end_source", &xive
->end_source
,
285 TYPE_XIVE_END_SOURCE
);
287 /* Not connected to the KVM XIVE device */
291 static void spapr_xive_realize(DeviceState
*dev
, Error
**errp
)
293 SpaprXive
*xive
= SPAPR_XIVE(dev
);
294 SpaprXiveClass
*sxc
= SPAPR_XIVE_GET_CLASS(xive
);
295 XiveSource
*xsrc
= &xive
->source
;
296 XiveENDSource
*end_xsrc
= &xive
->end_source
;
297 Error
*local_err
= NULL
;
299 sxc
->parent_realize(dev
, &local_err
);
301 error_propagate(errp
, local_err
);
305 if (!xive
->nr_irqs
) {
306 error_setg(errp
, "Number of interrupt needs to be greater 0");
310 if (!xive
->nr_ends
) {
311 error_setg(errp
, "Number of interrupt needs to be greater 0");
316 * Initialize the internal sources, for IPIs and virtual devices.
318 object_property_set_int(OBJECT(xsrc
), "nr-irqs", xive
->nr_irqs
,
320 object_property_set_link(OBJECT(xsrc
), "xive", OBJECT(xive
), &error_abort
);
321 if (!qdev_realize(DEVICE(xsrc
), NULL
, errp
)) {
324 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xsrc
->esb_mmio
);
327 * Initialize the END ESB source
329 object_property_set_int(OBJECT(end_xsrc
), "nr-ends", xive
->nr_irqs
,
331 object_property_set_link(OBJECT(end_xsrc
), "xive", OBJECT(xive
),
333 if (!qdev_realize(DEVICE(end_xsrc
), NULL
, errp
)) {
336 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &end_xsrc
->esb_mmio
);
338 /* Set the mapping address of the END ESB pages after the source ESBs */
339 xive
->end_base
= xive
->vc_base
+ xive_source_esb_len(xsrc
);
342 * Allocate the routing tables
344 xive
->eat
= g_new0(XiveEAS
, xive
->nr_irqs
);
345 xive
->endt
= g_new0(XiveEND
, xive
->nr_ends
);
347 xive
->nodename
= g_strdup_printf("interrupt-controller@%" PRIx64
,
348 xive
->tm_base
+ XIVE_TM_USER_PAGE
* (1 << TM_SHIFT
));
350 qemu_register_reset(spapr_xive_reset
, dev
);
352 /* TIMA initialization */
353 memory_region_init_io(&xive
->tm_mmio
, OBJECT(xive
), &spapr_xive_tm_ops
,
354 xive
, "xive.tima", 4ull << TM_SHIFT
);
355 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xive
->tm_mmio
);
358 * Map all regions. These will be enabled or disabled at reset and
359 * can also be overridden by KVM memory regions if active
361 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 0, xive
->vc_base
);
362 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 1, xive
->end_base
);
363 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 2, xive
->tm_base
);
366 static int spapr_xive_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
,
367 uint32_t eas_idx
, XiveEAS
*eas
)
369 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
371 if (eas_idx
>= xive
->nr_irqs
) {
375 *eas
= xive
->eat
[eas_idx
];
379 static int spapr_xive_get_end(XiveRouter
*xrtr
,
380 uint8_t end_blk
, uint32_t end_idx
, XiveEND
*end
)
382 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
384 if (end_idx
>= xive
->nr_ends
) {
388 memcpy(end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
392 static int spapr_xive_write_end(XiveRouter
*xrtr
, uint8_t end_blk
,
393 uint32_t end_idx
, XiveEND
*end
,
396 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
398 if (end_idx
>= xive
->nr_ends
) {
402 memcpy(&xive
->endt
[end_idx
], end
, sizeof(XiveEND
));
406 static int spapr_xive_get_nvt(XiveRouter
*xrtr
,
407 uint8_t nvt_blk
, uint32_t nvt_idx
, XiveNVT
*nvt
)
409 uint32_t vcpu_id
= spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
410 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
413 /* TODO: should we assert() if we can find a NVT ? */
418 * sPAPR does not maintain a NVT table. Return that the NVT is
419 * valid if we have found a matching CPU
421 nvt
->w0
= cpu_to_be32(NVT_W0_VALID
);
425 static int spapr_xive_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
,
426 uint32_t nvt_idx
, XiveNVT
*nvt
,
430 * We don't need to write back to the NVTs because the sPAPR
431 * machine should never hit a non-scheduled NVT. It should never
434 g_assert_not_reached();
437 static int spapr_xive_match_nvt(XivePresenter
*xptr
, uint8_t format
,
438 uint8_t nvt_blk
, uint32_t nvt_idx
,
439 bool cam_ignore
, uint8_t priority
,
440 uint32_t logic_serv
, XiveTCTXMatch
*match
)
446 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
447 XiveTCTX
*tctx
= spapr_cpu_state(cpu
)->tctx
;
451 * Skip partially initialized vCPUs. This can happen when
452 * vCPUs are hotplugged.
459 * Check the thread context CAM lines and record matches.
461 ring
= xive_presenter_tctx_match(xptr
, tctx
, format
, nvt_blk
, nvt_idx
,
462 cam_ignore
, logic_serv
);
464 * Save the matching thread interrupt context and follow on to
465 * check for duplicates which are invalid.
469 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: already found a thread "
470 "context NVT %x/%x\n", nvt_blk
, nvt_idx
);
483 static uint8_t spapr_xive_get_block_id(XiveRouter
*xrtr
)
485 return SPAPR_XIVE_BLOCK_ID
;
488 static const VMStateDescription vmstate_spapr_xive_end
= {
489 .name
= TYPE_SPAPR_XIVE
"/end",
491 .minimum_version_id
= 1,
492 .fields
= (VMStateField
[]) {
493 VMSTATE_UINT32(w0
, XiveEND
),
494 VMSTATE_UINT32(w1
, XiveEND
),
495 VMSTATE_UINT32(w2
, XiveEND
),
496 VMSTATE_UINT32(w3
, XiveEND
),
497 VMSTATE_UINT32(w4
, XiveEND
),
498 VMSTATE_UINT32(w5
, XiveEND
),
499 VMSTATE_UINT32(w6
, XiveEND
),
500 VMSTATE_UINT32(w7
, XiveEND
),
501 VMSTATE_END_OF_LIST()
505 static const VMStateDescription vmstate_spapr_xive_eas
= {
506 .name
= TYPE_SPAPR_XIVE
"/eas",
508 .minimum_version_id
= 1,
509 .fields
= (VMStateField
[]) {
510 VMSTATE_UINT64(w
, XiveEAS
),
511 VMSTATE_END_OF_LIST()
515 static int vmstate_spapr_xive_pre_save(void *opaque
)
517 SpaprXive
*xive
= SPAPR_XIVE(opaque
);
519 if (spapr_xive_in_kernel(xive
)) {
520 return kvmppc_xive_pre_save(xive
);
527 * Called by the sPAPR IRQ backend 'post_load' method at the machine
530 static int spapr_xive_post_load(SpaprInterruptController
*intc
, int version_id
)
532 SpaprXive
*xive
= SPAPR_XIVE(intc
);
534 if (spapr_xive_in_kernel(xive
)) {
535 return kvmppc_xive_post_load(xive
, version_id
);
541 static const VMStateDescription vmstate_spapr_xive
= {
542 .name
= TYPE_SPAPR_XIVE
,
544 .minimum_version_id
= 1,
545 .pre_save
= vmstate_spapr_xive_pre_save
,
546 .post_load
= NULL
, /* handled at the machine level */
547 .fields
= (VMStateField
[]) {
548 VMSTATE_UINT32_EQUAL(nr_irqs
, SpaprXive
, NULL
),
549 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat
, SpaprXive
, nr_irqs
,
550 vmstate_spapr_xive_eas
, XiveEAS
),
551 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt
, SpaprXive
, nr_ends
,
552 vmstate_spapr_xive_end
, XiveEND
),
553 VMSTATE_END_OF_LIST()
557 static int spapr_xive_claim_irq(SpaprInterruptController
*intc
, int lisn
,
558 bool lsi
, Error
**errp
)
560 SpaprXive
*xive
= SPAPR_XIVE(intc
);
561 XiveSource
*xsrc
= &xive
->source
;
563 assert(lisn
< xive
->nr_irqs
);
565 if (xive_eas_is_valid(&xive
->eat
[lisn
])) {
566 error_setg(errp
, "IRQ %d is not free", lisn
);
571 * Set default values when allocating an IRQ number
573 xive
->eat
[lisn
].w
|= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
575 xive_source_irq_set_lsi(xsrc
, lisn
);
578 if (spapr_xive_in_kernel(xive
)) {
579 return kvmppc_xive_source_reset_one(xsrc
, lisn
, errp
);
585 static void spapr_xive_free_irq(SpaprInterruptController
*intc
, int lisn
)
587 SpaprXive
*xive
= SPAPR_XIVE(intc
);
588 assert(lisn
< xive
->nr_irqs
);
590 xive
->eat
[lisn
].w
&= cpu_to_be64(~EAS_VALID
);
593 static Property spapr_xive_properties
[] = {
594 DEFINE_PROP_UINT32("nr-irqs", SpaprXive
, nr_irqs
, 0),
595 DEFINE_PROP_UINT32("nr-ends", SpaprXive
, nr_ends
, 0),
596 DEFINE_PROP_UINT64("vc-base", SpaprXive
, vc_base
, SPAPR_XIVE_VC_BASE
),
597 DEFINE_PROP_UINT64("tm-base", SpaprXive
, tm_base
, SPAPR_XIVE_TM_BASE
),
598 DEFINE_PROP_END_OF_LIST(),
601 static int spapr_xive_cpu_intc_create(SpaprInterruptController
*intc
,
602 PowerPCCPU
*cpu
, Error
**errp
)
604 SpaprXive
*xive
= SPAPR_XIVE(intc
);
606 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
608 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_PRESENTER(xive
), errp
);
613 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
617 static void xive_tctx_set_os_cam(XiveTCTX
*tctx
, uint32_t os_cam
)
619 uint32_t qw1w2
= cpu_to_be32(TM_QW1W2_VO
| os_cam
);
620 memcpy(&tctx
->regs
[TM_QW1_OS
+ TM_WORD2
], &qw1w2
, 4);
623 static void spapr_xive_cpu_intc_reset(SpaprInterruptController
*intc
,
626 XiveTCTX
*tctx
= spapr_cpu_state(cpu
)->tctx
;
630 xive_tctx_reset(tctx
);
633 * When a Virtual Processor is scheduled to run on a HW thread,
634 * the hypervisor pushes its identifier in the OS CAM line.
635 * Emulate the same behavior under QEMU.
637 spapr_xive_cpu_to_nvt(cpu
, &nvt_blk
, &nvt_idx
);
639 xive_tctx_set_os_cam(tctx
, xive_nvt_cam_line(nvt_blk
, nvt_idx
));
642 static void spapr_xive_cpu_intc_destroy(SpaprInterruptController
*intc
,
645 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
647 xive_tctx_destroy(spapr_cpu
->tctx
);
648 spapr_cpu
->tctx
= NULL
;
651 static void spapr_xive_set_irq(SpaprInterruptController
*intc
, int irq
, int val
)
653 SpaprXive
*xive
= SPAPR_XIVE(intc
);
655 if (spapr_xive_in_kernel(xive
)) {
656 kvmppc_xive_source_set_irq(&xive
->source
, irq
, val
);
658 xive_source_set_irq(&xive
->source
, irq
, val
);
662 static void spapr_xive_print_info(SpaprInterruptController
*intc
, Monitor
*mon
)
664 SpaprXive
*xive
= SPAPR_XIVE(intc
);
668 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
670 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
673 spapr_xive_pic_print_info(xive
, mon
);
676 static void spapr_xive_dt(SpaprInterruptController
*intc
, uint32_t nr_servers
,
677 void *fdt
, uint32_t phandle
)
679 SpaprXive
*xive
= SPAPR_XIVE(intc
);
681 uint64_t timas
[2 * 2];
682 /* Interrupt number ranges for the IPIs */
683 uint32_t lisn_ranges
[] = {
684 cpu_to_be32(SPAPR_IRQ_IPI
),
685 cpu_to_be32(SPAPR_IRQ_IPI
+ nr_servers
),
688 * EQ size - the sizes of pages supported by the system 4K, 64K,
689 * 2M, 16M. We only advertise 64K for the moment.
691 uint32_t eq_sizes
[] = {
692 cpu_to_be32(16), /* 64K */
695 * The following array is in sync with the reserved priorities
696 * defined by the 'spapr_xive_priority_is_reserved' routine.
698 uint32_t plat_res_int_priorities
[] = {
699 cpu_to_be32(7), /* start */
700 cpu_to_be32(0xf8), /* count */
703 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */
704 timas
[0] = cpu_to_be64(xive
->tm_base
+
705 XIVE_TM_USER_PAGE
* (1ull << TM_SHIFT
));
706 timas
[1] = cpu_to_be64(1ull << TM_SHIFT
);
707 timas
[2] = cpu_to_be64(xive
->tm_base
+
708 XIVE_TM_OS_PAGE
* (1ull << TM_SHIFT
));
709 timas
[3] = cpu_to_be64(1ull << TM_SHIFT
);
711 _FDT(node
= fdt_add_subnode(fdt
, 0, xive
->nodename
));
713 _FDT(fdt_setprop_string(fdt
, node
, "device_type", "power-ivpe"));
714 _FDT(fdt_setprop(fdt
, node
, "reg", timas
, sizeof(timas
)));
716 _FDT(fdt_setprop_string(fdt
, node
, "compatible", "ibm,power-ivpe"));
717 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-eq-sizes", eq_sizes
,
719 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-lisn-ranges", lisn_ranges
,
720 sizeof(lisn_ranges
)));
722 /* For Linux to link the LSIs to the interrupt controller. */
723 _FDT(fdt_setprop(fdt
, node
, "interrupt-controller", NULL
, 0));
724 _FDT(fdt_setprop_cell(fdt
, node
, "#interrupt-cells", 2));
727 _FDT(fdt_setprop_cell(fdt
, node
, "linux,phandle", phandle
));
728 _FDT(fdt_setprop_cell(fdt
, node
, "phandle", phandle
));
731 * The "ibm,plat-res-int-priorities" property defines the priority
732 * ranges reserved by the hypervisor
734 _FDT(fdt_setprop(fdt
, 0, "ibm,plat-res-int-priorities",
735 plat_res_int_priorities
, sizeof(plat_res_int_priorities
)));
738 static int spapr_xive_activate(SpaprInterruptController
*intc
,
739 uint32_t nr_servers
, Error
**errp
)
741 SpaprXive
*xive
= SPAPR_XIVE(intc
);
744 int rc
= spapr_irq_init_kvm(kvmppc_xive_connect
, intc
, nr_servers
,
751 /* Activate the XIVE MMIOs */
752 spapr_xive_mmio_set_enabled(xive
, true);
757 static void spapr_xive_deactivate(SpaprInterruptController
*intc
)
759 SpaprXive
*xive
= SPAPR_XIVE(intc
);
761 spapr_xive_mmio_set_enabled(xive
, false);
763 if (spapr_xive_in_kernel(xive
)) {
764 kvmppc_xive_disconnect(intc
);
768 static bool spapr_xive_in_kernel_xptr(const XivePresenter
*xptr
)
770 return spapr_xive_in_kernel(SPAPR_XIVE(xptr
));
773 static void spapr_xive_class_init(ObjectClass
*klass
, void *data
)
775 DeviceClass
*dc
= DEVICE_CLASS(klass
);
776 XiveRouterClass
*xrc
= XIVE_ROUTER_CLASS(klass
);
777 SpaprInterruptControllerClass
*sicc
= SPAPR_INTC_CLASS(klass
);
778 XivePresenterClass
*xpc
= XIVE_PRESENTER_CLASS(klass
);
779 SpaprXiveClass
*sxc
= SPAPR_XIVE_CLASS(klass
);
781 dc
->desc
= "sPAPR XIVE Interrupt Controller";
782 device_class_set_props(dc
, spapr_xive_properties
);
783 device_class_set_parent_realize(dc
, spapr_xive_realize
,
784 &sxc
->parent_realize
);
785 dc
->vmsd
= &vmstate_spapr_xive
;
787 xrc
->get_eas
= spapr_xive_get_eas
;
788 xrc
->get_end
= spapr_xive_get_end
;
789 xrc
->write_end
= spapr_xive_write_end
;
790 xrc
->get_nvt
= spapr_xive_get_nvt
;
791 xrc
->write_nvt
= spapr_xive_write_nvt
;
792 xrc
->get_block_id
= spapr_xive_get_block_id
;
794 sicc
->activate
= spapr_xive_activate
;
795 sicc
->deactivate
= spapr_xive_deactivate
;
796 sicc
->cpu_intc_create
= spapr_xive_cpu_intc_create
;
797 sicc
->cpu_intc_reset
= spapr_xive_cpu_intc_reset
;
798 sicc
->cpu_intc_destroy
= spapr_xive_cpu_intc_destroy
;
799 sicc
->claim_irq
= spapr_xive_claim_irq
;
800 sicc
->free_irq
= spapr_xive_free_irq
;
801 sicc
->set_irq
= spapr_xive_set_irq
;
802 sicc
->print_info
= spapr_xive_print_info
;
803 sicc
->dt
= spapr_xive_dt
;
804 sicc
->post_load
= spapr_xive_post_load
;
806 xpc
->match_nvt
= spapr_xive_match_nvt
;
807 xpc
->in_kernel
= spapr_xive_in_kernel_xptr
;
810 static const TypeInfo spapr_xive_info
= {
811 .name
= TYPE_SPAPR_XIVE
,
812 .parent
= TYPE_XIVE_ROUTER
,
813 .instance_init
= spapr_xive_instance_init
,
814 .instance_size
= sizeof(SpaprXive
),
815 .class_init
= spapr_xive_class_init
,
816 .class_size
= sizeof(SpaprXiveClass
),
817 .interfaces
= (InterfaceInfo
[]) {
823 static void spapr_xive_register_types(void)
825 type_register_static(&spapr_xive_info
);
828 type_init(spapr_xive_register_types
)
833 * The terminology used by the XIVE hcalls is the following :
836 * EQ Event Queue assigned by OS to receive event data
837 * ESB page for source interrupt management
838 * LISN Logical Interrupt Source Number identifying a source in the
840 * EISN Effective Interrupt Source Number used by guest OS to
841 * identify source in the guest
843 * The EAS, END, NVT structures are not exposed.
847 * Linux hosts under OPAL reserve priority 7 for their own escalation
848 * interrupts (DD2.X POWER9). So we only allow the guest to use
851 static bool spapr_xive_priority_is_reserved(uint8_t priority
)
856 case 7: /* OPAL escalation queue */
863 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical
864 * real address of the MMIO page through which the Event State Buffer
865 * entry associated with the value of the "lisn" parameter is managed.
871 * - R5: "lisn" is per "interrupts", "interrupt-map", or
872 * "ibm,xive-lisn-ranges" properties, or as returned by the
873 * ibm,query-interrupt-source-number RTAS call, or as returned
874 * by the H_ALLOCATE_VAS_WINDOW hcall
878 * Bits 0-59: Reserved
879 * Bit 60: H_INT_ESB must be used for Event State Buffer
881 * Bit 61: 1 == LSI 0 == MSI
882 * Bit 62: the full function page supports trigger
883 * Bit 63: Store EOI Supported
884 * - R5: Logical Real address of full function Event State Buffer
885 * management page, -1 if H_INT_ESB hcall flag is set to 1.
886 * - R6: Logical Real Address of trigger only Event State Buffer
887 * management page or -1.
888 * - R7: Power of 2 page size for the ESB management pages returned in
892 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */
893 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */
894 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
896 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */
898 static target_ulong
h_int_get_source_info(PowerPCCPU
*cpu
,
899 SpaprMachineState
*spapr
,
903 SpaprXive
*xive
= spapr
->xive
;
904 XiveSource
*xsrc
= &xive
->source
;
905 target_ulong flags
= args
[0];
906 target_ulong lisn
= args
[1];
908 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
916 if (lisn
>= xive
->nr_irqs
) {
917 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
922 if (!xive_eas_is_valid(&xive
->eat
[lisn
])) {
923 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
929 * All sources are emulated under the main XIVE object and share
930 * the same characteristics.
933 if (!xive_source_esb_has_2page(xsrc
)) {
934 args
[0] |= SPAPR_XIVE_SRC_TRIGGER
;
936 if (xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
) {
937 args
[0] |= SPAPR_XIVE_SRC_STORE_EOI
;
941 * Force the use of the H_INT_ESB hcall in case of an LSI
942 * interrupt. This is necessary under KVM to re-trigger the
943 * interrupt if the level is still asserted
945 if (xive_source_irq_is_lsi(xsrc
, lisn
)) {
946 args
[0] |= SPAPR_XIVE_SRC_H_INT_ESB
| SPAPR_XIVE_SRC_LSI
;
949 if (!(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
950 args
[1] = xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
);
955 if (xive_source_esb_has_2page(xsrc
) &&
956 !(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
957 args
[2] = xive
->vc_base
+ xive_source_esb_page(xsrc
, lisn
);
962 if (xive_source_esb_has_2page(xsrc
)) {
963 args
[3] = xsrc
->esb_shift
- 1;
965 args
[3] = xsrc
->esb_shift
;
972 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical
973 * Interrupt Source to a target. The Logical Interrupt Source is
974 * designated with the "lisn" parameter and the target is designated
975 * with the "target" and "priority" parameters. Upon return from the
976 * hcall(), no additional interrupts will be directed to the old EQ.
981 * Bits 0-61: Reserved
982 * Bit 62: set the "eisn" in the EAS
983 * Bit 63: masks the interrupt source in the hardware interrupt
984 * control structure. An interrupt masked by this mechanism will
985 * be dropped, but it's source state bits will still be
986 * set. There is no race-free way of unmasking and restoring the
987 * source. Thus this should only be used in interrupts that are
988 * also masked at the source, and only in cases where the
989 * interrupt is not meant to be used for a large amount of time
990 * because no valid target exists for it for example
991 * - R5: "lisn" is per "interrupts", "interrupt-map", or
992 * "ibm,xive-lisn-ranges" properties, or as returned by the
993 * ibm,query-interrupt-source-number RTAS call, or as returned by
994 * the H_ALLOCATE_VAS_WINDOW hcall
995 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or
996 * "ibm,ppc-interrupt-gserver#s"
997 * - R7: "priority" is a valid priority not in
998 * "ibm,plat-res-int-priorities"
999 * - R8: "eisn" is the guest EISN associated with the "lisn"
1005 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62)
1006 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63)
1008 static target_ulong
h_int_set_source_config(PowerPCCPU
*cpu
,
1009 SpaprMachineState
*spapr
,
1010 target_ulong opcode
,
1013 SpaprXive
*xive
= spapr
->xive
;
1014 XiveEAS eas
, new_eas
;
1015 target_ulong flags
= args
[0];
1016 target_ulong lisn
= args
[1];
1017 target_ulong target
= args
[2];
1018 target_ulong priority
= args
[3];
1019 target_ulong eisn
= args
[4];
1023 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1027 if (flags
& ~(SPAPR_XIVE_SRC_SET_EISN
| SPAPR_XIVE_SRC_MASK
)) {
1031 if (lisn
>= xive
->nr_irqs
) {
1032 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1037 eas
= xive
->eat
[lisn
];
1038 if (!xive_eas_is_valid(&eas
)) {
1039 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1044 /* priority 0xff is used to reset the EAS */
1045 if (priority
== 0xff) {
1046 new_eas
.w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
1050 if (flags
& SPAPR_XIVE_SRC_MASK
) {
1051 new_eas
.w
= eas
.w
| cpu_to_be64(EAS_MASKED
);
1053 new_eas
.w
= eas
.w
& cpu_to_be64(~EAS_MASKED
);
1056 if (spapr_xive_priority_is_reserved(priority
)) {
1057 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1058 " is reserved\n", priority
);
1063 * Validate that "target" is part of the list of threads allocated
1064 * to the partition. For that, find the END corresponding to the
1067 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1071 new_eas
.w
= xive_set_field64(EAS_END_BLOCK
, new_eas
.w
, end_blk
);
1072 new_eas
.w
= xive_set_field64(EAS_END_INDEX
, new_eas
.w
, end_idx
);
1074 if (flags
& SPAPR_XIVE_SRC_SET_EISN
) {
1075 new_eas
.w
= xive_set_field64(EAS_END_DATA
, new_eas
.w
, eisn
);
1078 if (spapr_xive_in_kernel(xive
)) {
1079 Error
*local_err
= NULL
;
1081 kvmppc_xive_set_source_config(xive
, lisn
, &new_eas
, &local_err
);
1083 error_report_err(local_err
);
1089 xive
->eat
[lisn
] = new_eas
;
1094 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which
1095 * target/priority pair is assigned to the specified Logical Interrupt
1101 * Bits 0-63 Reserved
1102 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1103 * "ibm,xive-lisn-ranges" properties, or as returned by the
1104 * ibm,query-interrupt-source-number RTAS call, or as
1105 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1108 * - R4: Target to which the specified Logical Interrupt Source is
1110 * - R5: Priority to which the specified Logical Interrupt Source is
1112 * - R6: EISN for the specified Logical Interrupt Source (this will be
1113 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG)
1115 static target_ulong
h_int_get_source_config(PowerPCCPU
*cpu
,
1116 SpaprMachineState
*spapr
,
1117 target_ulong opcode
,
1120 SpaprXive
*xive
= spapr
->xive
;
1121 target_ulong flags
= args
[0];
1122 target_ulong lisn
= args
[1];
1126 uint32_t end_idx
, nvt_idx
;
1128 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1136 if (lisn
>= xive
->nr_irqs
) {
1137 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1142 eas
= xive
->eat
[lisn
];
1143 if (!xive_eas_is_valid(&eas
)) {
1144 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1149 /* EAS_END_BLOCK is unused on sPAPR */
1150 end_idx
= xive_get_field64(EAS_END_INDEX
, eas
.w
);
1152 assert(end_idx
< xive
->nr_ends
);
1153 end
= &xive
->endt
[end_idx
];
1155 nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
->w6
);
1156 nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
1157 args
[0] = spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
1159 if (xive_eas_is_masked(&eas
)) {
1162 args
[1] = xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
1165 args
[2] = xive_get_field64(EAS_END_DATA
, eas
.w
);
1171 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real
1172 * address of the notification management page associated with the
1173 * specified target and priority.
1178 * Bits 0-63 Reserved
1179 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1180 * "ibm,ppc-interrupt-gserver#s"
1181 * - R6: "priority" is a valid priority not in
1182 * "ibm,plat-res-int-priorities"
1185 * - R4: Logical real address of notification page
1186 * - R5: Power of 2 page size of the notification page
1188 static target_ulong
h_int_get_queue_info(PowerPCCPU
*cpu
,
1189 SpaprMachineState
*spapr
,
1190 target_ulong opcode
,
1193 SpaprXive
*xive
= spapr
->xive
;
1194 XiveENDSource
*end_xsrc
= &xive
->end_source
;
1195 target_ulong flags
= args
[0];
1196 target_ulong target
= args
[1];
1197 target_ulong priority
= args
[2];
1202 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1211 * H_STATE should be returned if a H_INT_RESET is in progress.
1212 * This is not needed when running the emulation under QEMU
1215 if (spapr_xive_priority_is_reserved(priority
)) {
1216 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1217 " is reserved\n", priority
);
1222 * Validate that "target" is part of the list of threads allocated
1223 * to the partition. For that, find the END corresponding to the
1226 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1230 assert(end_idx
< xive
->nr_ends
);
1231 end
= &xive
->endt
[end_idx
];
1233 args
[0] = xive
->end_base
+ (1ull << (end_xsrc
->esb_shift
+ 1)) * end_idx
;
1234 if (xive_end_is_enqueue(end
)) {
1235 args
[1] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1244 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for
1245 * a given "target" and "priority". It is also used to set the
1246 * notification config associated with the EQ. An EQ size of 0 is
1247 * used to reset the EQ config for a given target and priority. If
1248 * resetting the EQ config, the END associated with the given "target"
1249 * and "priority" will be changed to disable queueing.
1251 * Upon return from the hcall(), no additional interrupts will be
1252 * directed to the old EQ (if one was set). The old EQ (if one was
1253 * set) should be investigated for interrupts that occurred prior to
1254 * or during the hcall().
1259 * Bits 0-62: Reserved
1260 * Bit 63: Unconditional Notify (n) per the XIVE spec
1261 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1262 * "ibm,ppc-interrupt-gserver#s"
1263 * - R6: "priority" is a valid priority not in
1264 * "ibm,plat-res-int-priorities"
1265 * - R7: "eventQueue": The logical real address of the start of the EQ
1266 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes"
1272 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63)
1274 static target_ulong
h_int_set_queue_config(PowerPCCPU
*cpu
,
1275 SpaprMachineState
*spapr
,
1276 target_ulong opcode
,
1279 SpaprXive
*xive
= spapr
->xive
;
1280 target_ulong flags
= args
[0];
1281 target_ulong target
= args
[1];
1282 target_ulong priority
= args
[2];
1283 target_ulong qpage
= args
[3];
1284 target_ulong qsize
= args
[4];
1286 uint8_t end_blk
, nvt_blk
;
1287 uint32_t end_idx
, nvt_idx
;
1289 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1293 if (flags
& ~SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1298 * H_STATE should be returned if a H_INT_RESET is in progress.
1299 * This is not needed when running the emulation under QEMU
1302 if (spapr_xive_priority_is_reserved(priority
)) {
1303 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1304 " is reserved\n", priority
);
1309 * Validate that "target" is part of the list of threads allocated
1310 * to the partition. For that, find the END corresponding to the
1314 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1318 assert(end_idx
< xive
->nr_ends
);
1319 memcpy(&end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
1326 if (!QEMU_IS_ALIGNED(qpage
, 1ul << qsize
)) {
1327 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: EQ @0x%" HWADDR_PRIx
1328 " is not naturally aligned with %" HWADDR_PRIx
"\n",
1329 qpage
, (hwaddr
)1 << qsize
);
1332 end
.w2
= cpu_to_be32((qpage
>> 32) & 0x0fffffff);
1333 end
.w3
= cpu_to_be32(qpage
& 0xffffffff);
1334 end
.w0
|= cpu_to_be32(END_W0_ENQUEUE
);
1335 end
.w0
= xive_set_field32(END_W0_QSIZE
, end
.w0
, qsize
- 12);
1338 /* reset queue and disable queueing */
1339 spapr_xive_end_reset(&end
);
1343 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid EQ size %"PRIx64
"\n",
1349 hwaddr plen
= 1 << qsize
;
1353 * Validate the guest EQ. We should also check that the queue
1354 * has been zeroed by the OS.
1356 eq
= address_space_map(CPU(cpu
)->as
, qpage
, &plen
, true,
1357 MEMTXATTRS_UNSPECIFIED
);
1358 if (plen
!= 1 << qsize
) {
1359 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to map EQ @0x%"
1360 HWADDR_PRIx
"\n", qpage
);
1363 address_space_unmap(CPU(cpu
)->as
, eq
, plen
, true, plen
);
1366 /* "target" should have been validated above */
1367 if (spapr_xive_target_to_nvt(target
, &nvt_blk
, &nvt_idx
)) {
1368 g_assert_not_reached();
1372 * Ensure the priority and target are correctly set (they will not
1373 * be right after allocation)
1375 end
.w6
= xive_set_field32(END_W6_NVT_BLOCK
, 0ul, nvt_blk
) |
1376 xive_set_field32(END_W6_NVT_INDEX
, 0ul, nvt_idx
);
1377 end
.w7
= xive_set_field32(END_W7_F0_PRIORITY
, 0ul, priority
);
1379 if (flags
& SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1380 end
.w0
|= cpu_to_be32(END_W0_UCOND_NOTIFY
);
1382 end
.w0
&= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY
);
1386 * The generation bit for the END starts at 1 and The END page
1387 * offset counter starts at 0.
1389 end
.w1
= cpu_to_be32(END_W1_GENERATION
) |
1390 xive_set_field32(END_W1_PAGE_OFF
, 0ul, 0ul);
1391 end
.w0
|= cpu_to_be32(END_W0_VALID
);
1394 * TODO: issue syncs required to ensure all in-flight interrupts
1395 * are complete on the old END
1399 if (spapr_xive_in_kernel(xive
)) {
1400 Error
*local_err
= NULL
;
1402 kvmppc_xive_set_queue_config(xive
, end_blk
, end_idx
, &end
, &local_err
);
1404 error_report_err(local_err
);
1410 memcpy(&xive
->endt
[end_idx
], &end
, sizeof(XiveEND
));
1415 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given
1416 * target and priority.
1421 * Bits 0-62: Reserved
1422 * Bit 63: Debug: Return debug data
1423 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1424 * "ibm,ppc-interrupt-gserver#s"
1425 * - R6: "priority" is a valid priority not in
1426 * "ibm,plat-res-int-priorities"
1430 * Bits 0-61: Reserved
1431 * Bit 62: The value of Event Queue Generation Number (g) per
1432 * the XIVE spec if "Debug" = 1
1433 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec
1434 * - R5: The logical real address of the start of the EQ
1435 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes"
1436 * - R7: The value of Event Queue Offset Counter per XIVE spec
1437 * if "Debug" = 1, else 0
1441 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63)
1443 static target_ulong
h_int_get_queue_config(PowerPCCPU
*cpu
,
1444 SpaprMachineState
*spapr
,
1445 target_ulong opcode
,
1448 SpaprXive
*xive
= spapr
->xive
;
1449 target_ulong flags
= args
[0];
1450 target_ulong target
= args
[1];
1451 target_ulong priority
= args
[2];
1456 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1460 if (flags
& ~SPAPR_XIVE_END_DEBUG
) {
1465 * H_STATE should be returned if a H_INT_RESET is in progress.
1466 * This is not needed when running the emulation under QEMU
1469 if (spapr_xive_priority_is_reserved(priority
)) {
1470 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1471 " is reserved\n", priority
);
1476 * Validate that "target" is part of the list of threads allocated
1477 * to the partition. For that, find the END corresponding to the
1480 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1484 assert(end_idx
< xive
->nr_ends
);
1485 end
= &xive
->endt
[end_idx
];
1488 if (xive_end_is_notify(end
)) {
1489 args
[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY
;
1492 if (xive_end_is_enqueue(end
)) {
1493 args
[1] = xive_end_qaddr(end
);
1494 args
[2] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1500 if (spapr_xive_in_kernel(xive
)) {
1501 Error
*local_err
= NULL
;
1503 kvmppc_xive_get_queue_config(xive
, end_blk
, end_idx
, end
, &local_err
);
1505 error_report_err(local_err
);
1510 /* TODO: do we need any locking on the END ? */
1511 if (flags
& SPAPR_XIVE_END_DEBUG
) {
1512 /* Load the event queue generation number into the return flags */
1513 args
[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION
, end
->w1
) << 62;
1515 /* Load R7 with the event queue offset counter */
1516 args
[3] = xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1525 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the
1526 * reporting cache line pair for the calling thread. The reporting
1527 * cache lines will contain the OS interrupt context when the OS
1528 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS
1529 * interrupt. The reporting cache lines can be reset by inputting -1
1530 * in "reportingLine". Issuing the CI store byte without reporting
1531 * cache lines registered will result in the data not being accessible
1537 * Bits 0-63: Reserved
1538 * - R5: "reportingLine": The logical real address of the reporting cache
1544 static target_ulong
h_int_set_os_reporting_line(PowerPCCPU
*cpu
,
1545 SpaprMachineState
*spapr
,
1546 target_ulong opcode
,
1549 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1554 * H_STATE should be returned if a H_INT_RESET is in progress.
1555 * This is not needed when running the emulation under QEMU
1558 /* TODO: H_INT_SET_OS_REPORTING_LINE */
1563 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical
1564 * real address of the reporting cache line pair set for the input
1565 * "target". If no reporting cache line pair has been set, -1 is
1571 * Bits 0-63: Reserved
1572 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1573 * "ibm,ppc-interrupt-gserver#s"
1574 * - R6: "reportingLine": The logical real address of the reporting
1578 * - R4: The logical real address of the reporting line if set, else -1
1580 static target_ulong
h_int_get_os_reporting_line(PowerPCCPU
*cpu
,
1581 SpaprMachineState
*spapr
,
1582 target_ulong opcode
,
1585 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1590 * H_STATE should be returned if a H_INT_RESET is in progress.
1591 * This is not needed when running the emulation under QEMU
1594 /* TODO: H_INT_GET_OS_REPORTING_LINE */
1599 * The H_INT_ESB hcall() is used to issue a load or store to the ESB
1600 * page for the input "lisn". This hcall is only supported for LISNs
1601 * that have the ESB hcall flag set to 1 when returned from hcall()
1602 * H_INT_GET_SOURCE_INFO.
1607 * Bits 0-62: Reserved
1608 * bit 63: Store: Store=1, store operation, else load operation
1609 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1610 * "ibm,xive-lisn-ranges" properties, or as returned by the
1611 * ibm,query-interrupt-source-number RTAS call, or as
1612 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1613 * - R6: "esbOffset" is the offset into the ESB page for the load or
1615 * - R7: "storeData" is the data to write for a store operation
1618 * - R4: The value of the load if load operation, else -1
1621 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63)
1623 static target_ulong
h_int_esb(PowerPCCPU
*cpu
,
1624 SpaprMachineState
*spapr
,
1625 target_ulong opcode
,
1628 SpaprXive
*xive
= spapr
->xive
;
1630 target_ulong flags
= args
[0];
1631 target_ulong lisn
= args
[1];
1632 target_ulong offset
= args
[2];
1633 target_ulong data
= args
[3];
1635 XiveSource
*xsrc
= &xive
->source
;
1637 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1641 if (flags
& ~SPAPR_XIVE_ESB_STORE
) {
1645 if (lisn
>= xive
->nr_irqs
) {
1646 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1651 eas
= xive
->eat
[lisn
];
1652 if (!xive_eas_is_valid(&eas
)) {
1653 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1658 if (offset
> (1ull << xsrc
->esb_shift
)) {
1662 if (spapr_xive_in_kernel(xive
)) {
1663 args
[0] = kvmppc_xive_esb_rw(xsrc
, lisn
, offset
, data
,
1664 flags
& SPAPR_XIVE_ESB_STORE
);
1666 mmio_addr
= xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
) + offset
;
1668 if (dma_memory_rw(&address_space_memory
, mmio_addr
, &data
, 8,
1669 (flags
& SPAPR_XIVE_ESB_STORE
))) {
1670 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to access ESB @0x%"
1671 HWADDR_PRIx
"\n", mmio_addr
);
1674 args
[0] = (flags
& SPAPR_XIVE_ESB_STORE
) ? -1 : data
;
1680 * The H_INT_SYNC hcall() is used to issue hardware syncs that will
1681 * ensure any in flight events for the input lisn are in the event
1687 * Bits 0-63: Reserved
1688 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1689 * "ibm,xive-lisn-ranges" properties, or as returned by the
1690 * ibm,query-interrupt-source-number RTAS call, or as
1691 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1696 static target_ulong
h_int_sync(PowerPCCPU
*cpu
,
1697 SpaprMachineState
*spapr
,
1698 target_ulong opcode
,
1701 SpaprXive
*xive
= spapr
->xive
;
1703 target_ulong flags
= args
[0];
1704 target_ulong lisn
= args
[1];
1706 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1714 if (lisn
>= xive
->nr_irqs
) {
1715 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1720 eas
= xive
->eat
[lisn
];
1721 if (!xive_eas_is_valid(&eas
)) {
1722 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1728 * H_STATE should be returned if a H_INT_RESET is in progress.
1729 * This is not needed when running the emulation under QEMU
1733 * This is not real hardware. Nothing to be done unless when
1737 if (spapr_xive_in_kernel(xive
)) {
1738 Error
*local_err
= NULL
;
1740 kvmppc_xive_sync_source(xive
, lisn
, &local_err
);
1742 error_report_err(local_err
);
1750 * The H_INT_RESET hcall() is used to reset all of the partition's
1751 * interrupt exploitation structures to their initial state. This
1752 * means losing all previously set interrupt state set via
1753 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG.
1758 * Bits 0-63: Reserved
1763 static target_ulong
h_int_reset(PowerPCCPU
*cpu
,
1764 SpaprMachineState
*spapr
,
1765 target_ulong opcode
,
1768 SpaprXive
*xive
= spapr
->xive
;
1769 target_ulong flags
= args
[0];
1771 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1779 device_legacy_reset(DEVICE(xive
));
1781 if (spapr_xive_in_kernel(xive
)) {
1782 Error
*local_err
= NULL
;
1784 kvmppc_xive_reset(xive
, &local_err
);
1786 error_report_err(local_err
);
1793 void spapr_xive_hcall_init(SpaprMachineState
*spapr
)
1795 spapr_register_hypercall(H_INT_GET_SOURCE_INFO
, h_int_get_source_info
);
1796 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG
, h_int_set_source_config
);
1797 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG
, h_int_get_source_config
);
1798 spapr_register_hypercall(H_INT_GET_QUEUE_INFO
, h_int_get_queue_info
);
1799 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG
, h_int_set_queue_config
);
1800 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG
, h_int_get_queue_config
);
1801 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE
,
1802 h_int_set_os_reporting_line
);
1803 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE
,
1804 h_int_get_os_reporting_line
);
1805 spapr_register_hypercall(H_INT_ESB
, h_int_esb
);
1806 spapr_register_hypercall(H_INT_SYNC
, h_int_sync
);
1807 spapr_register_hypercall(H_INT_RESET
, h_int_reset
);