hw/intc/ibex_plic.c

   1 /*
   2  * QEMU RISC-V lowRISC Ibex PLIC
   3  *
   4  * Copyright (c) 2020 Western Digital
   5  *
   6  * Documentation avaliable: https://docs.opentitan.org/hw/ip/rv_plic/doc/
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/log.h"
  23 #include "hw/qdev-properties.h"
  24 #include "hw/core/cpu.h"
  25 #include "hw/boards.h"
  26 #include "hw/pci/msi.h"
  27 #include "target/riscv/cpu_bits.h"
  28 #include "target/riscv/cpu.h"
  29 #include "hw/intc/ibex_plic.h"
  30
  31 static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
  32 {
  33     uint32_t end = base + (num * 0x04);
  34
  35     if (addr >= base && addr < end) {
  36         return true;
  37     }
  38
  39     return false;
  40 }
  41
  42 static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
  43 {
  44     int pending_num = irq / 32;
  45
  46     if (s->claimed[pending_num] & 1 << (irq % 32)) {
  47         /*
  48          * The interrupt has been claimed, but not compelted.
  49          * The pending bit can't be set.
  50          */
  51         return;
  52     }
  53
  54     s->pending[pending_num] |= level << (irq % 32);
  55 }
  56
  57 static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
  58 {
  59     int i;
  60     uint32_t max_irq = 0;
  61     uint32_t max_prio = s->threshold;
  62
  63     for (i = 0; i < s->pending_num; i++) {
  64         uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
  65
  66         if (!(s->pending[i] & s->enable[i])) {
  67             /* No pending and enabled IRQ */
  68             continue;
  69         }
  70
  71         if (s->priority[irq_num] > max_prio) {
  72             max_irq = irq_num;
  73             max_prio = s->priority[irq_num];
  74         }
  75     }
  76
  77     if (max_irq) {
  78         s->claim = max_irq;
  79         return true;
  80     }
  81
  82     return false;
  83 }
  84
  85 static void ibex_plic_update(IbexPlicState *s)
  86 {
  87     CPUState *cpu;
  88     int level, i;
  89
  90     for (i = 0; i < s->num_cpus; i++) {
  91         cpu = qemu_get_cpu(i);
  92
  93         if (!cpu) {
  94             continue;
  95         }
  96
  97         level = ibex_plic_irqs_pending(s, 0);
  98
  99         riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
 100     }
 101 }
 102
 103 static void ibex_plic_reset(DeviceState *dev)
 104 {
 105     IbexPlicState *s = IBEX_PLIC(dev);
 106
 107     s->threshold = 0x00000000;
 108     s->claim = 0x00000000;
 109 }
 110
 111 static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
 112                                unsigned int size)
 113 {
 114     IbexPlicState *s = opaque;
 115     int offset;
 116     uint32_t ret = 0;
 117
 118     if (addr_between(addr, s->pending_base, s->pending_num)) {
 119         offset = (addr - s->pending_base) / 4;
 120         ret = s->pending[offset];
 121     } else if (addr_between(addr, s->source_base, s->source_num)) {
 122         qemu_log_mask(LOG_UNIMP,
 123                       "%s: Interrupt source mode not supported\n", __func__);
 124     } else if (addr_between(addr, s->priority_base, s->priority_num)) {
 125         offset = (addr - s->priority_base) / 4;
 126         ret = s->priority[offset];
 127     } else if (addr_between(addr, s->enable_base, s->enable_num)) {
 128         offset = (addr - s->enable_base) / 4;
 129         ret = s->enable[offset];
 130     } else if (addr_between(addr, s->threshold_base, 1)) {
 131         ret = s->threshold;
 132     } else if (addr_between(addr, s->claim_base, 1)) {
 133         int pending_num = s->claim / 32;
 134         s->pending[pending_num] &= ~(1 << (s->claim % 32));
 135
 136         /* Set the interrupt as claimed, but not compelted */
 137         s->claimed[pending_num] |= 1 << (s->claim % 32);
 138
 139         /* Return the current claimed interrupt */
 140         ret = s->claim;
 141
 142         /* Update the interrupt status after the claim */
 143         ibex_plic_update(s);
 144     }
 145
 146     return ret;
 147 }
 148
 149 static void ibex_plic_write(void *opaque, hwaddr addr,
 150                             uint64_t value, unsigned int size)
 151 {
 152     IbexPlicState *s = opaque;
 153
 154     if (addr_between(addr, s->pending_base, s->pending_num)) {
 155         qemu_log_mask(LOG_GUEST_ERROR,
 156                       "%s: Pending registers are read only\n", __func__);
 157     } else if (addr_between(addr, s->source_base, s->source_num)) {
 158         qemu_log_mask(LOG_UNIMP,
 159                       "%s: Interrupt source mode not supported\n", __func__);
 160     } else if (addr_between(addr, s->priority_base, s->priority_num)) {
 161         uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
 162         s->priority[irq] = value & 7;
 163         ibex_plic_update(s);
 164     } else if (addr_between(addr, s->enable_base, s->enable_num)) {
 165         uint32_t enable_reg = (addr - s->enable_base) / 4;
 166
 167         s->enable[enable_reg] = value;
 168     } else if (addr_between(addr, s->threshold_base, 1)) {
 169         s->threshold = value & 3;
 170     } else if (addr_between(addr, s->claim_base, 1)) {
 171         if (s->claim == value) {
 172             /* Interrupt was completed */
 173             s->claim = 0;
 174         }
 175         if (s->claimed[value / 32] & 1 << (value % 32)) {
 176             /* This value was already claimed, clear it. */
 177             s->claimed[value / 32] &= ~(1 << (value % 32));
 178         }
 179     }
 180
 181     ibex_plic_update(s);
 182 }
 183
 184 static const MemoryRegionOps ibex_plic_ops = {
 185     .read = ibex_plic_read,
 186     .write = ibex_plic_write,
 187     .endianness = DEVICE_NATIVE_ENDIAN,
 188     .valid = {
 189         .min_access_size = 4,
 190         .max_access_size = 4
 191     }
 192 };
 193
 194 static void ibex_plic_irq_request(void *opaque, int irq, int level)
 195 {
 196     IbexPlicState *s = opaque;
 197
 198     ibex_plic_irqs_set_pending(s, irq, level > 0);
 199     ibex_plic_update(s);
 200 }
 201
 202 static Property ibex_plic_properties[] = {
 203     DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
 204     DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80),
 205
 206     DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
 207     DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3),
 208
 209     DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c),
 210     DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3),
 211
 212     DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18),
 213     DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80),
 214
 215     DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200),
 216     DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3),
 217
 218     DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x20c),
 219
 220     DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210),
 221     DEFINE_PROP_END_OF_LIST(),
 222 };
 223
 224 static void ibex_plic_init(Object *obj)
 225 {
 226     IbexPlicState *s = IBEX_PLIC(obj);
 227
 228     memory_region_init_io(&s->mmio, obj, &ibex_plic_ops, s,
 229                           TYPE_IBEX_PLIC, 0x400);
 230     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 231 }
 232
 233 static void ibex_plic_realize(DeviceState *dev, Error **errp)
 234 {
 235     IbexPlicState *s = IBEX_PLIC(dev);
 236     int i;
 237
 238     s->pending = g_new0(uint32_t, s->pending_num);
 239     s->claimed = g_new0(uint32_t, s->pending_num);
 240     s->source = g_new0(uint32_t, s->source_num);
 241     s->priority = g_new0(uint32_t, s->priority_num);
 242     s->enable = g_new0(uint32_t, s->enable_num);
 243
 244     qdev_init_gpio_in(dev, ibex_plic_irq_request, s->num_sources);
 245
 246     /*
 247      * We can't allow the supervisor to control SEIP as this would allow the
 248      * supervisor to clear a pending external interrupt which will result in
 249      * a lost interrupt in the case a PLIC is attached. The SEIP bit must be
 250      * hardware controlled when a PLIC is attached.
 251      */
 252     MachineState *ms = MACHINE(qdev_get_machine());
 253     unsigned int smp_cpus = ms->smp.cpus;
 254     for (i = 0; i < smp_cpus; i++) {
 255         RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
 256         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
 257             error_report("SEIP already claimed");
 258             exit(1);
 259         }
 260     }
 261
 262     msi_nonbroken = true;
 263 }
 264
 265 static void ibex_plic_class_init(ObjectClass *klass, void *data)
 266 {
 267     DeviceClass *dc = DEVICE_CLASS(klass);
 268
 269     dc->reset = ibex_plic_reset;
 270     device_class_set_props(dc, ibex_plic_properties);
 271     dc->realize = ibex_plic_realize;
 272 }
 273
 274 static const TypeInfo ibex_plic_info = {
 275     .name          = TYPE_IBEX_PLIC,
 276     .parent        = TYPE_SYS_BUS_DEVICE,
 277     .instance_size = sizeof(IbexPlicState),
 278     .instance_init = ibex_plic_init,
 279     .class_init    = ibex_plic_class_init,
 280 };
 281
 282 static void ibex_plic_register_types(void)
 283 {
 284     type_register_static(&ibex_plic_info);
 285 }
 286
 287 type_init(ibex_plic_register_types)