tests/tco-test.c

   1 /*
   2  * QEMU ICH9 TCO emulation tests
   3  *
   4  * Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9 #include <glib.h>
  10 #include <string.h>
  11 #include <stdio.h>
  12 #include <stdlib.h>
  13
  14 #include "libqtest.h"
  15 #include "libqos/pci.h"
  16 #include "libqos/pci-pc.h"
  17 #include "hw/pci/pci_regs.h"
  18 #include "hw/i386/ich9.h"
  19 #include "hw/acpi/ich9.h"
  20 #include "hw/acpi/tco.h"
  21
  22 #define RCBA_BASE_ADDR    0xfed1c000
  23 #define PM_IO_BASE_ADDR   0xb000
  24
  25 enum {
  26     TCO_RLD_DEFAULT         = 0x0000,
  27     TCO_DAT_IN_DEFAULT      = 0x00,
  28     TCO_DAT_OUT_DEFAULT     = 0x00,
  29     TCO1_STS_DEFAULT        = 0x0000,
  30     TCO2_STS_DEFAULT        = 0x0000,
  31     TCO1_CNT_DEFAULT        = 0x0000,
  32     TCO2_CNT_DEFAULT        = 0x0008,
  33     TCO_MESSAGE1_DEFAULT    = 0x00,
  34     TCO_MESSAGE2_DEFAULT    = 0x00,
  35     TCO_WDCNT_DEFAULT       = 0x00,
  36     TCO_TMR_DEFAULT         = 0x0004,
  37     SW_IRQ_GEN_DEFAULT      = 0x03,
  38 };
  39
  40 #define TCO_SECS_TO_TICKS(secs)     (((secs) * 10) / 6)
  41 #define TCO_TICKS_TO_SECS(ticks)    (((ticks) * 6) / 10)
  42
  43 typedef struct {
  44     const char *args;
  45     QPCIDevice *dev;
  46     void *lpc_base;
  47     void *tco_io_base;
  48 } TestData;
  49
  50 static void test_init(TestData *d)
  51 {
  52     QPCIBus *bus;
  53     QTestState *qs;
  54     char *s;
  55
  56     s = g_strdup_printf("-machine q35 %s", !d->args ? "" : d->args);
  57     qs = qtest_start(s);
  58     qtest_irq_intercept_in(qs, "ioapic");
  59     g_free(s);
  60
  61     bus = qpci_init_pc();
  62     d->dev = qpci_device_find(bus, QPCI_DEVFN(0x1f, 0x00));
  63     g_assert(d->dev != NULL);
  64
  65     /* map PCI-to-LPC bridge interface BAR */
  66     d->lpc_base = qpci_iomap(d->dev, 0, NULL);
  67
  68     qpci_device_enable(d->dev);
  69
  70     g_assert(d->lpc_base != NULL);
  71
  72     /* set ACPI PM I/O space base address */
  73     qpci_config_writel(d->dev, (uintptr_t)d->lpc_base + ICH9_LPC_PMBASE,
  74                        PM_IO_BASE_ADDR | 0x1);
  75     /* enable ACPI I/O */
  76     qpci_config_writeb(d->dev, (uintptr_t)d->lpc_base + ICH9_LPC_ACPI_CTRL,
  77                        0x80);
  78     /* set Root Complex BAR */
  79     qpci_config_writel(d->dev, (uintptr_t)d->lpc_base + ICH9_LPC_RCBA,
  80                        RCBA_BASE_ADDR | 0x1);
  81
  82     d->tco_io_base = (void *)((uintptr_t)PM_IO_BASE_ADDR + 0x60);
  83 }
  84
  85 static void stop_tco(const TestData *d)
  86 {
  87     uint32_t val;
  88
  89     val = qpci_io_readw(d->dev, d->tco_io_base + TCO1_CNT);
  90     val |= TCO_TMR_HLT;
  91     qpci_io_writew(d->dev, d->tco_io_base + TCO1_CNT, val);
  92 }
  93
  94 static void start_tco(const TestData *d)
  95 {
  96     uint32_t val;
  97
  98     val = qpci_io_readw(d->dev, d->tco_io_base + TCO1_CNT);
  99     val &= ~TCO_TMR_HLT;
 100     qpci_io_writew(d->dev, d->tco_io_base + TCO1_CNT, val);
 101 }
 102
 103 static void load_tco(const TestData *d)
 104 {
 105     qpci_io_writew(d->dev, d->tco_io_base + TCO_RLD, 4);
 106 }
 107
 108 static void set_tco_timeout(const TestData *d, uint16_t ticks)
 109 {
 110     qpci_io_writew(d->dev, d->tco_io_base + TCO_TMR, ticks);
 111 }
 112
 113 static void clear_tco_status(const TestData *d)
 114 {
 115     qpci_io_writew(d->dev, d->tco_io_base + TCO1_STS, 0x0008);
 116     qpci_io_writew(d->dev, d->tco_io_base + TCO2_STS, 0x0002);
 117     qpci_io_writew(d->dev, d->tco_io_base + TCO2_STS, 0x0004);
 118 }
 119
 120 static void reset_on_second_timeout(bool enable)
 121 {
 122     uint32_t val;
 123
 124     val = readl(RCBA_BASE_ADDR + ICH9_CC_GCS);
 125     if (enable) {
 126         val &= ~ICH9_CC_GCS_NO_REBOOT;
 127     } else {
 128         val |= ICH9_CC_GCS_NO_REBOOT;
 129     }
 130     writel(RCBA_BASE_ADDR + ICH9_CC_GCS, val);
 131 }
 132
 133 static void test_tco_defaults(void)
 134 {
 135     TestData d;
 136
 137     d.args = NULL;
 138     test_init(&d);
 139     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_RLD), ==,
 140                     TCO_RLD_DEFAULT);
 141     /* TCO_DAT_IN & TCO_DAT_OUT */
 142     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_DAT_IN), ==,
 143                     (TCO_DAT_OUT_DEFAULT << 8) | TCO_DAT_IN_DEFAULT);
 144     /* TCO1_STS & TCO2_STS */
 145     g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_base + TCO1_STS), ==,
 146                     (TCO2_STS_DEFAULT << 16) | TCO1_STS_DEFAULT);
 147     /* TCO1_CNT & TCO2_CNT */
 148     g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_base + TCO1_CNT), ==,
 149                     (TCO2_CNT_DEFAULT << 16) | TCO1_CNT_DEFAULT);
 150     /* TCO_MESSAGE1 & TCO_MESSAGE2 */
 151     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_MESSAGE1), ==,
 152                     (TCO_MESSAGE2_DEFAULT << 8) | TCO_MESSAGE1_DEFAULT);
 153     g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_base + TCO_WDCNT), ==,
 154                     TCO_WDCNT_DEFAULT);
 155     g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_base + SW_IRQ_GEN), ==,
 156                     SW_IRQ_GEN_DEFAULT);
 157     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_TMR), ==,
 158                     TCO_TMR_DEFAULT);
 159     qtest_end();
 160 }
 161
 162 static void test_tco_timeout(void)
 163 {
 164     TestData d;
 165     const uint16_t ticks = TCO_SECS_TO_TICKS(4);
 166     uint32_t val;
 167     int ret;
 168
 169     d.args = NULL;
 170     test_init(&d);
 171
 172     stop_tco(&d);
 173     clear_tco_status(&d);
 174     reset_on_second_timeout(false);
 175     set_tco_timeout(&d, ticks);
 176     load_tco(&d);
 177     start_tco(&d);
 178     clock_step(ticks * TCO_TICK_NSEC);
 179
 180     /* test first timeout */
 181     val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
 182     ret = val & TCO_TIMEOUT ? 1 : 0;
 183     g_assert(ret == 1);
 184
 185     /* test clearing timeout bit */
 186     val |= TCO_TIMEOUT;
 187     qpci_io_writew(d.dev, d.tco_io_base + TCO1_STS, val);
 188     val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
 189     ret = val & TCO_TIMEOUT ? 1 : 0;
 190     g_assert(ret == 0);
 191
 192     /* test second timeout */
 193     clock_step(ticks * TCO_TICK_NSEC);
 194     val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
 195     ret = val & TCO_TIMEOUT ? 1 : 0;
 196     g_assert(ret == 1);
 197     val = qpci_io_readw(d.dev, d.tco_io_base + TCO2_STS);
 198     ret = val & TCO_SECOND_TO_STS ? 1 : 0;
 199     g_assert(ret == 1);
 200
 201     stop_tco(&d);
 202     qtest_end();
 203 }
 204
 205 static void test_tco_max_timeout(void)
 206 {
 207     TestData d;
 208     const uint16_t ticks = 0xffff;
 209     uint32_t val;
 210     int ret;
 211
 212     d.args = NULL;
 213     test_init(&d);
 214
 215     stop_tco(&d);
 216     clear_tco_status(&d);
 217     reset_on_second_timeout(false);
 218     set_tco_timeout(&d, ticks);
 219     load_tco(&d);
 220     start_tco(&d);
 221     clock_step(((ticks & TCO_TMR_MASK) - 1) * TCO_TICK_NSEC);
 222
 223     val = qpci_io_readw(d.dev, d.tco_io_base + TCO_RLD);
 224     g_assert_cmpint(val & TCO_RLD_MASK, ==, 1);
 225     val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
 226     ret = val & TCO_TIMEOUT ? 1 : 0;
 227     g_assert(ret == 0);
 228     clock_step(TCO_TICK_NSEC);
 229     val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
 230     ret = val & TCO_TIMEOUT ? 1 : 0;
 231     g_assert(ret == 1);
 232
 233     stop_tco(&d);
 234     qtest_end();
 235 }
 236
 237 static QDict *get_watchdog_action(void)
 238 {
 239     QDict *ev = qmp("");
 240     QDict *data;
 241     g_assert(!strcmp(qdict_get_str(ev, "event"), "WATCHDOG"));
 242
 243     data = qdict_get_qdict(ev, "data");
 244     QINCREF(data);
 245     QDECREF(ev);
 246     return data;
 247 }
 248
 249 static void test_tco_second_timeout_pause(void)
 250 {
 251     TestData td;
 252     const uint16_t ticks = TCO_SECS_TO_TICKS(32);
 253     QDict *ad;
 254
 255     td.args = "-watchdog-action pause";
 256     test_init(&td);
 257
 258     stop_tco(&td);
 259     clear_tco_status(&td);
 260     reset_on_second_timeout(true);
 261     set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
 262     load_tco(&td);
 263     start_tco(&td);
 264     clock_step(ticks * TCO_TICK_NSEC * 2);
 265     ad = get_watchdog_action();
 266     g_assert(!strcmp(qdict_get_str(ad, "action"), "pause"));
 267     QDECREF(ad);
 268
 269     stop_tco(&td);
 270     qtest_end();
 271 }
 272
 273 static void test_tco_second_timeout_reset(void)
 274 {
 275     TestData td;
 276     const uint16_t ticks = TCO_SECS_TO_TICKS(16);
 277     QDict *ad;
 278
 279     td.args = "-watchdog-action reset";
 280     test_init(&td);
 281
 282     stop_tco(&td);
 283     clear_tco_status(&td);
 284     reset_on_second_timeout(true);
 285     set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
 286     load_tco(&td);
 287     start_tco(&td);
 288     clock_step(ticks * TCO_TICK_NSEC * 2);
 289     ad = get_watchdog_action();
 290     g_assert(!strcmp(qdict_get_str(ad, "action"), "reset"));
 291     QDECREF(ad);
 292
 293     stop_tco(&td);
 294     qtest_end();
 295 }
 296
 297 static void test_tco_second_timeout_shutdown(void)
 298 {
 299     TestData td;
 300     const uint16_t ticks = TCO_SECS_TO_TICKS(128);
 301     QDict *ad;
 302
 303     td.args = "-watchdog-action shutdown";
 304     test_init(&td);
 305
 306     stop_tco(&td);
 307     clear_tco_status(&td);
 308     reset_on_second_timeout(true);
 309     set_tco_timeout(&td, ticks);
 310     load_tco(&td);
 311     start_tco(&td);
 312     clock_step(ticks * TCO_TICK_NSEC * 2);
 313     ad = get_watchdog_action();
 314     g_assert(!strcmp(qdict_get_str(ad, "action"), "shutdown"));
 315     QDECREF(ad);
 316
 317     stop_tco(&td);
 318     qtest_end();
 319 }
 320
 321 static void test_tco_second_timeout_none(void)
 322 {
 323     TestData td;
 324     const uint16_t ticks = TCO_SECS_TO_TICKS(256);
 325     QDict *ad;
 326
 327     td.args = "-watchdog-action none";
 328     test_init(&td);
 329
 330     stop_tco(&td);
 331     clear_tco_status(&td);
 332     reset_on_second_timeout(true);
 333     set_tco_timeout(&td, ticks);
 334     load_tco(&td);
 335     start_tco(&td);
 336     clock_step(ticks * TCO_TICK_NSEC * 2);
 337     ad = get_watchdog_action();
 338     g_assert(!strcmp(qdict_get_str(ad, "action"), "none"));
 339     QDECREF(ad);
 340
 341     stop_tco(&td);
 342     qtest_end();
 343 }
 344
 345 static void test_tco_ticks_counter(void)
 346 {
 347     TestData d;
 348     uint16_t ticks = TCO_SECS_TO_TICKS(8);
 349     uint16_t rld;
 350
 351     d.args = NULL;
 352     test_init(&d);
 353
 354     stop_tco(&d);
 355     clear_tco_status(&d);
 356     reset_on_second_timeout(false);
 357     set_tco_timeout(&d, ticks);
 358     load_tco(&d);
 359     start_tco(&d);
 360
 361     do {
 362         rld = qpci_io_readw(d.dev, d.tco_io_base + TCO_RLD) & TCO_RLD_MASK;
 363         g_assert_cmpint(rld, ==, ticks);
 364         clock_step(TCO_TICK_NSEC);
 365         ticks--;
 366     } while (!(qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS) & TCO_TIMEOUT));
 367
 368     stop_tco(&d);
 369     qtest_end();
 370 }
 371
 372 static void test_tco1_control_bits(void)
 373 {
 374     TestData d;
 375     uint16_t val;
 376
 377     d.args = NULL;
 378     test_init(&d);
 379
 380     val = TCO_LOCK;
 381     qpci_io_writew(d.dev, d.tco_io_base + TCO1_CNT, val);
 382     val &= ~TCO_LOCK;
 383     qpci_io_writew(d.dev, d.tco_io_base + TCO1_CNT, val);
 384     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO1_CNT), ==,
 385                     TCO_LOCK);
 386     qtest_end();
 387 }
 388
 389 static void test_tco1_status_bits(void)
 390 {
 391     TestData d;
 392     uint16_t ticks = 8;
 393     uint16_t val;
 394     int ret;
 395
 396     d.args = NULL;
 397     test_init(&d);
 398
 399     stop_tco(&d);
 400     clear_tco_status(&d);
 401     reset_on_second_timeout(false);
 402     set_tco_timeout(&d, ticks);
 403     load_tco(&d);
 404     start_tco(&d);
 405     clock_step(ticks * TCO_TICK_NSEC);
 406
 407     qpci_io_writeb(d.dev, d.tco_io_base + TCO_DAT_IN, 0);
 408     qpci_io_writeb(d.dev, d.tco_io_base + TCO_DAT_OUT, 0);
 409     val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
 410     ret = val & (TCO_TIMEOUT | SW_TCO_SMI | TCO_INT_STS) ? 1 : 0;
 411     g_assert(ret == 1);
 412     qpci_io_writew(d.dev, d.tco_io_base + TCO1_STS, val);
 413     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS), ==, 0);
 414     qtest_end();
 415 }
 416
 417 static void test_tco2_status_bits(void)
 418 {
 419     TestData d;
 420     uint16_t ticks = 8;
 421     uint16_t val;
 422     int ret;
 423
 424     d.args = "-watchdog-action none";
 425     test_init(&d);
 426
 427     stop_tco(&d);
 428     clear_tco_status(&d);
 429     reset_on_second_timeout(true);
 430     set_tco_timeout(&d, ticks);
 431     load_tco(&d);
 432     start_tco(&d);
 433     clock_step(ticks * TCO_TICK_NSEC * 2);
 434
 435     val = qpci_io_readw(d.dev, d.tco_io_base + TCO2_STS);
 436     ret = val & (TCO_SECOND_TO_STS | TCO_BOOT_STS) ? 1 : 0;
 437     g_assert(ret == 1);
 438     qpci_io_writew(d.dev, d.tco_io_base + TCO2_STS, val);
 439     g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO2_STS), ==, 0);
 440     qtest_end();
 441 }
 442
 443 int main(int argc, char **argv)
 444 {
 445     g_test_init(&argc, &argv, NULL);
 446
 447     qtest_add_func("tco/defaults", test_tco_defaults);
 448     qtest_add_func("tco/timeout/no_action", test_tco_timeout);
 449     qtest_add_func("tco/timeout/no_action/max", test_tco_max_timeout);
 450     qtest_add_func("tco/second_timeout/pause", test_tco_second_timeout_pause);
 451     qtest_add_func("tco/second_timeout/reset", test_tco_second_timeout_reset);
 452     qtest_add_func("tco/second_timeout/shutdown",
 453                    test_tco_second_timeout_shutdown);
 454     qtest_add_func("tco/second_timeout/none", test_tco_second_timeout_none);
 455     qtest_add_func("tco/counter", test_tco_ticks_counter);
 456     qtest_add_func("tco/tco1_control/bits", test_tco1_control_bits);
 457     qtest_add_func("tco/tco1_status/bits", test_tco1_status_bits);
 458     qtest_add_func("tco/tco2_status/bits", test_tco2_status_bits);
 459     return g_test_run();
 460 }