2 * SD Association Host Standard Specification v2.0 controller emulation
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Mitsyanko Igor <i.mitsyanko@samsung.com>
6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
9 * by Alexey Merkulov and Vladimir Monakhov.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 #include "qemu/osdep.h"
27 #include "sysemu/block-backend.h"
28 #include "sysemu/blockdev.h"
29 #include "sysemu/dma.h"
30 #include "qemu/timer.h"
31 #include "qemu/bitops.h"
32 #include "sdhci-internal.h"
35 /* host controller debug messages */
40 #define DPRINT_L1(fmt, args...) \
43 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
46 #define DPRINT_L2(fmt, args...) \
48 if (SDHC_DEBUG > 1) { \
49 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
52 #define ERRPRINT(fmt, args...) \
55 fprintf(stderr, "QEMU SDHC ERROR: " fmt, ## args); \
59 #define TYPE_SDHCI_BUS "sdhci-bus"
60 #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
62 /* Default SD/MMC host controller features information, which will be
63 * presented in CAPABILITIES register of generic SD host controller at reset.
64 * If not stated otherwise:
65 * 0 - not supported, 1 - supported, other - prohibited.
67 #define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */
68 #define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */
69 #define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */
70 #define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */
71 #define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */
72 #define SDHC_CAPAB_SDMA 1ul /* SDMA support */
73 #define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */
74 #define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */
75 #define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */
76 /* Maximum host controller R/W buffers size
77 * Possible values: 512, 1024, 2048 bytes */
78 #define SDHC_CAPAB_MAXBLOCKLENGTH 512ul
79 /* Maximum clock frequency for SDclock in MHz
80 * value in range 10-63 MHz, 0 - not defined */
81 #define SDHC_CAPAB_BASECLKFREQ 52ul
82 #define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */
83 /* Timeout clock frequency 1-63, 0 - not defined */
84 #define SDHC_CAPAB_TOCLKFREQ 52ul
86 /* Now check all parameters and calculate CAPABILITIES REGISTER value */
87 #if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \
88 SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \
89 SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\
91 #error Capabilities features can have value 0 or 1 only!
94 #if SDHC_CAPAB_MAXBLOCKLENGTH == 512
95 #define MAX_BLOCK_LENGTH 0ul
96 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024
97 #define MAX_BLOCK_LENGTH 1ul
98 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048
99 #define MAX_BLOCK_LENGTH 2ul
101 #error Max host controller block size can have value 512, 1024 or 2048 only!
104 #if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \
105 SDHC_CAPAB_BASECLKFREQ > 63
106 #error SDclock frequency can have value in range 0, 10-63 only!
109 #if SDHC_CAPAB_TOCLKFREQ > 63
110 #error Timeout clock frequency can have value in range 0-63 only!
113 #define SDHC_CAPAB_REG_DEFAULT \
114 ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \
115 (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \
116 (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \
117 (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \
118 (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \
119 (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
120 (SDHC_CAPAB_TOCLKFREQ))
122 #define MASK_TRNMOD 0x0037
123 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
125 static uint8_t sdhci_slotint(SDHCIState
*s
)
127 return (s
->norintsts
& s
->norintsigen
) || (s
->errintsts
& s
->errintsigen
) ||
128 ((s
->norintsts
& SDHC_NIS_INSERT
) && (s
->wakcon
& SDHC_WKUP_ON_INS
)) ||
129 ((s
->norintsts
& SDHC_NIS_REMOVE
) && (s
->wakcon
& SDHC_WKUP_ON_RMV
));
132 static inline void sdhci_update_irq(SDHCIState
*s
)
134 qemu_set_irq(s
->irq
, sdhci_slotint(s
));
137 static void sdhci_raise_insertion_irq(void *opaque
)
139 SDHCIState
*s
= (SDHCIState
*)opaque
;
141 if (s
->norintsts
& SDHC_NIS_REMOVE
) {
142 timer_mod(s
->insert_timer
,
143 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
145 s
->prnsts
= 0x1ff0000;
146 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
147 s
->norintsts
|= SDHC_NIS_INSERT
;
153 static void sdhci_set_inserted(DeviceState
*dev
, bool level
)
155 SDHCIState
*s
= (SDHCIState
*)dev
;
156 DPRINT_L1("Card state changed: %s!\n", level
? "insert" : "eject");
158 if ((s
->norintsts
& SDHC_NIS_REMOVE
) && level
) {
159 /* Give target some time to notice card ejection */
160 timer_mod(s
->insert_timer
,
161 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
164 s
->prnsts
= 0x1ff0000;
165 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
166 s
->norintsts
|= SDHC_NIS_INSERT
;
169 s
->prnsts
= 0x1fa0000;
170 s
->pwrcon
&= ~SDHC_POWER_ON
;
171 s
->clkcon
&= ~SDHC_CLOCK_SDCLK_EN
;
172 if (s
->norintstsen
& SDHC_NISEN_REMOVE
) {
173 s
->norintsts
|= SDHC_NIS_REMOVE
;
180 static void sdhci_set_readonly(DeviceState
*dev
, bool level
)
182 SDHCIState
*s
= (SDHCIState
*)dev
;
185 s
->prnsts
&= ~SDHC_WRITE_PROTECT
;
188 s
->prnsts
|= SDHC_WRITE_PROTECT
;
192 static void sdhci_reset(SDHCIState
*s
)
194 DeviceState
*dev
= DEVICE(s
);
196 timer_del(s
->insert_timer
);
197 timer_del(s
->transfer_timer
);
198 /* Set all registers to 0. Capabilities registers are not cleared
199 * and assumed to always preserve their value, given to them during
201 memset(&s
->sdmasysad
, 0, (uintptr_t)&s
->capareg
- (uintptr_t)&s
->sdmasysad
);
203 /* Reset other state based on current card insertion/readonly status */
204 sdhci_set_inserted(dev
, sdbus_get_inserted(&s
->sdbus
));
205 sdhci_set_readonly(dev
, sdbus_get_readonly(&s
->sdbus
));
208 s
->stopped_state
= sdhc_not_stopped
;
209 s
->pending_insert_state
= false;
212 static void sdhci_poweron_reset(DeviceState
*dev
)
214 /* QOM (ie power-on) reset. This is identical to reset
215 * commanded via device register apart from handling of the
216 * 'pending insert on powerup' quirk.
218 SDHCIState
*s
= (SDHCIState
*)dev
;
222 if (s
->pending_insert_quirk
) {
223 s
->pending_insert_state
= true;
227 static void sdhci_data_transfer(void *opaque
);
229 static void sdhci_send_command(SDHCIState
*s
)
232 uint8_t response
[16];
237 request
.cmd
= s
->cmdreg
>> 8;
238 request
.arg
= s
->argument
;
239 DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request
.cmd
, request
.arg
);
240 rlen
= sdbus_do_command(&s
->sdbus
, &request
, response
);
242 if (s
->cmdreg
& SDHC_CMD_RESPONSE
) {
244 s
->rspreg
[0] = (response
[0] << 24) | (response
[1] << 16) |
245 (response
[2] << 8) | response
[3];
246 s
->rspreg
[1] = s
->rspreg
[2] = s
->rspreg
[3] = 0;
247 DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s
->rspreg
[0]);
248 } else if (rlen
== 16) {
249 s
->rspreg
[0] = (response
[11] << 24) | (response
[12] << 16) |
250 (response
[13] << 8) | response
[14];
251 s
->rspreg
[1] = (response
[7] << 24) | (response
[8] << 16) |
252 (response
[9] << 8) | response
[10];
253 s
->rspreg
[2] = (response
[3] << 24) | (response
[4] << 16) |
254 (response
[5] << 8) | response
[6];
255 s
->rspreg
[3] = (response
[0] << 16) | (response
[1] << 8) |
257 DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.."
258 "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n",
259 s
->rspreg
[3], s
->rspreg
[2], s
->rspreg
[1], s
->rspreg
[0]);
261 ERRPRINT("Timeout waiting for command response\n");
262 if (s
->errintstsen
& SDHC_EISEN_CMDTIMEOUT
) {
263 s
->errintsts
|= SDHC_EIS_CMDTIMEOUT
;
264 s
->norintsts
|= SDHC_NIS_ERR
;
268 if ((s
->norintstsen
& SDHC_NISEN_TRSCMP
) &&
269 (s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
) {
270 s
->norintsts
|= SDHC_NIS_TRSCMP
;
274 if (s
->norintstsen
& SDHC_NISEN_CMDCMP
) {
275 s
->norintsts
|= SDHC_NIS_CMDCMP
;
280 if (s
->blksize
&& (s
->cmdreg
& SDHC_CMD_DATA_PRESENT
)) {
282 sdhci_data_transfer(s
);
286 static void sdhci_end_transfer(SDHCIState
*s
)
288 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
289 if ((s
->trnmod
& SDHC_TRNS_ACMD12
) != 0) {
291 uint8_t response
[16];
295 DPRINT_L1("Automatically issue CMD%d %08x\n", request
.cmd
, request
.arg
);
296 sdbus_do_command(&s
->sdbus
, &request
, response
);
297 /* Auto CMD12 response goes to the upper Response register */
298 s
->rspreg
[3] = (response
[0] << 24) | (response
[1] << 16) |
299 (response
[2] << 8) | response
[3];
302 s
->prnsts
&= ~(SDHC_DOING_READ
| SDHC_DOING_WRITE
|
303 SDHC_DAT_LINE_ACTIVE
| SDHC_DATA_INHIBIT
|
304 SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
);
306 if (s
->norintstsen
& SDHC_NISEN_TRSCMP
) {
307 s
->norintsts
|= SDHC_NIS_TRSCMP
;
314 * Programmed i/o data transfer
317 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */
318 static void sdhci_read_block_from_card(SDHCIState
*s
)
322 if ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
323 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) {
327 for (index
= 0; index
< (s
->blksize
& 0x0fff); index
++) {
328 s
->fifo_buffer
[index
] = sdbus_read_data(&s
->sdbus
);
331 /* New data now available for READ through Buffer Port Register */
332 s
->prnsts
|= SDHC_DATA_AVAILABLE
;
333 if (s
->norintstsen
& SDHC_NISEN_RBUFRDY
) {
334 s
->norintsts
|= SDHC_NIS_RBUFRDY
;
337 /* Clear DAT line active status if that was the last block */
338 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
339 ((s
->trnmod
& SDHC_TRNS_MULTI
) && s
->blkcnt
== 1)) {
340 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
343 /* If stop at block gap request was set and it's not the last block of
344 * data - generate Block Event interrupt */
345 if (s
->stopped_state
== sdhc_gap_read
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
347 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
348 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
349 s
->norintsts
|= SDHC_EIS_BLKGAP
;
356 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */
357 static uint32_t sdhci_read_dataport(SDHCIState
*s
, unsigned size
)
362 /* first check that a valid data exists in host controller input buffer */
363 if ((s
->prnsts
& SDHC_DATA_AVAILABLE
) == 0) {
364 ERRPRINT("Trying to read from empty buffer\n");
368 for (i
= 0; i
< size
; i
++) {
369 value
|= s
->fifo_buffer
[s
->data_count
] << i
* 8;
371 /* check if we've read all valid data (blksize bytes) from buffer */
372 if ((s
->data_count
) >= (s
->blksize
& 0x0fff)) {
373 DPRINT_L2("All %u bytes of data have been read from input buffer\n",
375 s
->prnsts
&= ~SDHC_DATA_AVAILABLE
; /* no more data in a buffer */
376 s
->data_count
= 0; /* next buff read must start at position [0] */
378 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
382 /* if that was the last block of data */
383 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
384 ((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) ||
385 /* stop at gap request */
386 (s
->stopped_state
== sdhc_gap_read
&&
387 !(s
->prnsts
& SDHC_DAT_LINE_ACTIVE
))) {
388 sdhci_end_transfer(s
);
389 } else { /* if there are more data, read next block from card */
390 sdhci_read_block_from_card(s
);
399 /* Write data from host controller FIFO to card */
400 static void sdhci_write_block_to_card(SDHCIState
*s
)
404 if (s
->prnsts
& SDHC_SPACE_AVAILABLE
) {
405 if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
406 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
412 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
413 if (s
->blkcnt
== 0) {
420 for (index
= 0; index
< (s
->blksize
& 0x0fff); index
++) {
421 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[index
]);
424 /* Next data can be written through BUFFER DATORT register */
425 s
->prnsts
|= SDHC_SPACE_AVAILABLE
;
427 /* Finish transfer if that was the last block of data */
428 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
429 ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
430 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0))) {
431 sdhci_end_transfer(s
);
432 } else if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
433 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
436 /* Generate Block Gap Event if requested and if not the last block */
437 if (s
->stopped_state
== sdhc_gap_write
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
439 s
->prnsts
&= ~SDHC_DOING_WRITE
;
440 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
441 s
->norintsts
|= SDHC_EIS_BLKGAP
;
443 sdhci_end_transfer(s
);
449 /* Write @size bytes of @value data to host controller @s Buffer Data Port
451 static void sdhci_write_dataport(SDHCIState
*s
, uint32_t value
, unsigned size
)
455 /* Check that there is free space left in a buffer */
456 if (!(s
->prnsts
& SDHC_SPACE_AVAILABLE
)) {
457 ERRPRINT("Can't write to data buffer: buffer full\n");
461 for (i
= 0; i
< size
; i
++) {
462 s
->fifo_buffer
[s
->data_count
] = value
& 0xFF;
465 if (s
->data_count
>= (s
->blksize
& 0x0fff)) {
466 DPRINT_L2("write buffer filled with %u bytes of data\n",
469 s
->prnsts
&= ~SDHC_SPACE_AVAILABLE
;
470 if (s
->prnsts
& SDHC_DOING_WRITE
) {
471 sdhci_write_block_to_card(s
);
478 * Single DMA data transfer
481 /* Multi block SDMA transfer */
482 static void sdhci_sdma_transfer_multi_blocks(SDHCIState
*s
)
484 bool page_aligned
= false;
485 unsigned int n
, begin
;
486 const uint16_t block_size
= s
->blksize
& 0x0fff;
487 uint32_t boundary_chk
= 1 << (((s
->blksize
& 0xf000) >> 12) + 12);
488 uint32_t boundary_count
= boundary_chk
- (s
->sdmasysad
% boundary_chk
);
490 if (!(s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) || !s
->blkcnt
) {
491 qemu_log_mask(LOG_UNIMP
, "infinite transfer is not supported\n");
495 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
496 * possible stop at page boundary if initial address is not page aligned,
497 * allow them to work properly */
498 if ((s
->sdmasysad
% boundary_chk
) == 0) {
502 if (s
->trnmod
& SDHC_TRNS_READ
) {
503 s
->prnsts
|= SDHC_DOING_READ
| SDHC_DATA_INHIBIT
|
504 SDHC_DAT_LINE_ACTIVE
;
506 if (s
->data_count
== 0) {
507 for (n
= 0; n
< block_size
; n
++) {
508 s
->fifo_buffer
[n
] = sdbus_read_data(&s
->sdbus
);
511 begin
= s
->data_count
;
512 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
513 s
->data_count
= boundary_count
+ begin
;
516 s
->data_count
= block_size
;
517 boundary_count
-= block_size
- begin
;
518 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
522 dma_memory_write(&address_space_memory
, s
->sdmasysad
,
523 &s
->fifo_buffer
[begin
], s
->data_count
- begin
);
524 s
->sdmasysad
+= s
->data_count
- begin
;
525 if (s
->data_count
== block_size
) {
528 if (page_aligned
&& boundary_count
== 0) {
533 s
->prnsts
|= SDHC_DOING_WRITE
| SDHC_DATA_INHIBIT
|
534 SDHC_DAT_LINE_ACTIVE
;
536 begin
= s
->data_count
;
537 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
538 s
->data_count
= boundary_count
+ begin
;
541 s
->data_count
= block_size
;
542 boundary_count
-= block_size
- begin
;
544 dma_memory_read(&address_space_memory
, s
->sdmasysad
,
545 &s
->fifo_buffer
[begin
], s
->data_count
- begin
);
546 s
->sdmasysad
+= s
->data_count
- begin
;
547 if (s
->data_count
== block_size
) {
548 for (n
= 0; n
< block_size
; n
++) {
549 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[n
]);
552 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
556 if (page_aligned
&& boundary_count
== 0) {
562 if (s
->blkcnt
== 0) {
563 sdhci_end_transfer(s
);
565 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
566 s
->norintsts
|= SDHC_NIS_DMA
;
572 /* single block SDMA transfer */
574 static void sdhci_sdma_transfer_single_block(SDHCIState
*s
)
577 uint32_t datacnt
= s
->blksize
& 0x0fff;
579 if (s
->trnmod
& SDHC_TRNS_READ
) {
580 for (n
= 0; n
< datacnt
; n
++) {
581 s
->fifo_buffer
[n
] = sdbus_read_data(&s
->sdbus
);
583 dma_memory_write(&address_space_memory
, s
->sdmasysad
, s
->fifo_buffer
,
586 dma_memory_read(&address_space_memory
, s
->sdmasysad
, s
->fifo_buffer
,
588 for (n
= 0; n
< datacnt
; n
++) {
589 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[n
]);
593 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
597 sdhci_end_transfer(s
);
600 typedef struct ADMADescr
{
607 static void get_adma_description(SDHCIState
*s
, ADMADescr
*dscr
)
611 hwaddr entry_addr
= (hwaddr
)s
->admasysaddr
;
612 switch (SDHC_DMA_TYPE(s
->hostctl
)) {
613 case SDHC_CTRL_ADMA2_32
:
614 dma_memory_read(&address_space_memory
, entry_addr
, (uint8_t *)&adma2
,
616 adma2
= le64_to_cpu(adma2
);
617 /* The spec does not specify endianness of descriptor table.
618 * We currently assume that it is LE.
620 dscr
->addr
= (hwaddr
)extract64(adma2
, 32, 32) & ~0x3ull
;
621 dscr
->length
= (uint16_t)extract64(adma2
, 16, 16);
622 dscr
->attr
= (uint8_t)extract64(adma2
, 0, 7);
625 case SDHC_CTRL_ADMA1_32
:
626 dma_memory_read(&address_space_memory
, entry_addr
, (uint8_t *)&adma1
,
628 adma1
= le32_to_cpu(adma1
);
629 dscr
->addr
= (hwaddr
)(adma1
& 0xFFFFF000);
630 dscr
->attr
= (uint8_t)extract32(adma1
, 0, 7);
632 if ((dscr
->attr
& SDHC_ADMA_ATTR_ACT_MASK
) == SDHC_ADMA_ATTR_SET_LEN
) {
633 dscr
->length
= (uint16_t)extract32(adma1
, 12, 16);
638 case SDHC_CTRL_ADMA2_64
:
639 dma_memory_read(&address_space_memory
, entry_addr
,
640 (uint8_t *)(&dscr
->attr
), 1);
641 dma_memory_read(&address_space_memory
, entry_addr
+ 2,
642 (uint8_t *)(&dscr
->length
), 2);
643 dscr
->length
= le16_to_cpu(dscr
->length
);
644 dma_memory_read(&address_space_memory
, entry_addr
+ 4,
645 (uint8_t *)(&dscr
->addr
), 8);
646 dscr
->attr
= le64_to_cpu(dscr
->attr
);
647 dscr
->attr
&= 0xfffffff8;
653 /* Advanced DMA data transfer */
655 static void sdhci_do_adma(SDHCIState
*s
)
657 unsigned int n
, begin
, length
;
658 const uint16_t block_size
= s
->blksize
& 0x0fff;
662 for (i
= 0; i
< SDHC_ADMA_DESCS_PER_DELAY
; ++i
) {
663 s
->admaerr
&= ~SDHC_ADMAERR_LENGTH_MISMATCH
;
665 get_adma_description(s
, &dscr
);
666 DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx
", len=%d, attr=%x\n",
667 dscr
.addr
, dscr
.length
, dscr
.attr
);
669 if ((dscr
.attr
& SDHC_ADMA_ATTR_VALID
) == 0) {
670 /* Indicate that error occurred in ST_FDS state */
671 s
->admaerr
&= ~SDHC_ADMAERR_STATE_MASK
;
672 s
->admaerr
|= SDHC_ADMAERR_STATE_ST_FDS
;
674 /* Generate ADMA error interrupt */
675 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
676 s
->errintsts
|= SDHC_EIS_ADMAERR
;
677 s
->norintsts
|= SDHC_NIS_ERR
;
684 length
= dscr
.length
? dscr
.length
: 65536;
686 switch (dscr
.attr
& SDHC_ADMA_ATTR_ACT_MASK
) {
687 case SDHC_ADMA_ATTR_ACT_TRAN
: /* data transfer */
689 if (s
->trnmod
& SDHC_TRNS_READ
) {
691 if (s
->data_count
== 0) {
692 for (n
= 0; n
< block_size
; n
++) {
693 s
->fifo_buffer
[n
] = sdbus_read_data(&s
->sdbus
);
696 begin
= s
->data_count
;
697 if ((length
+ begin
) < block_size
) {
698 s
->data_count
= length
+ begin
;
701 s
->data_count
= block_size
;
702 length
-= block_size
- begin
;
704 dma_memory_write(&address_space_memory
, dscr
.addr
,
705 &s
->fifo_buffer
[begin
],
706 s
->data_count
- begin
);
707 dscr
.addr
+= s
->data_count
- begin
;
708 if (s
->data_count
== block_size
) {
710 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
712 if (s
->blkcnt
== 0) {
720 begin
= s
->data_count
;
721 if ((length
+ begin
) < block_size
) {
722 s
->data_count
= length
+ begin
;
725 s
->data_count
= block_size
;
726 length
-= block_size
- begin
;
728 dma_memory_read(&address_space_memory
, dscr
.addr
,
729 &s
->fifo_buffer
[begin
],
730 s
->data_count
- begin
);
731 dscr
.addr
+= s
->data_count
- begin
;
732 if (s
->data_count
== block_size
) {
733 for (n
= 0; n
< block_size
; n
++) {
734 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[n
]);
737 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
739 if (s
->blkcnt
== 0) {
746 s
->admasysaddr
+= dscr
.incr
;
748 case SDHC_ADMA_ATTR_ACT_LINK
: /* link to next descriptor table */
749 s
->admasysaddr
= dscr
.addr
;
750 DPRINT_L1("ADMA link: admasysaddr=0x%" PRIx64
"\n",
754 s
->admasysaddr
+= dscr
.incr
;
758 if (dscr
.attr
& SDHC_ADMA_ATTR_INT
) {
759 DPRINT_L1("ADMA interrupt: admasysaddr=0x%" PRIx64
"\n",
761 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
762 s
->norintsts
|= SDHC_NIS_DMA
;
768 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
769 if (((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
770 (s
->blkcnt
== 0)) || (dscr
.attr
& SDHC_ADMA_ATTR_END
)) {
771 DPRINT_L2("ADMA transfer completed\n");
772 if (length
|| ((dscr
.attr
& SDHC_ADMA_ATTR_END
) &&
773 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
775 ERRPRINT("SD/MMC host ADMA length mismatch\n");
776 s
->admaerr
|= SDHC_ADMAERR_LENGTH_MISMATCH
|
777 SDHC_ADMAERR_STATE_ST_TFR
;
778 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
779 ERRPRINT("Set ADMA error flag\n");
780 s
->errintsts
|= SDHC_EIS_ADMAERR
;
781 s
->norintsts
|= SDHC_NIS_ERR
;
786 sdhci_end_transfer(s
);
792 /* we have unfinished business - reschedule to continue ADMA */
793 timer_mod(s
->transfer_timer
,
794 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_TRANSFER_DELAY
);
797 /* Perform data transfer according to controller configuration */
799 static void sdhci_data_transfer(void *opaque
)
801 SDHCIState
*s
= (SDHCIState
*)opaque
;
803 if (s
->trnmod
& SDHC_TRNS_DMA
) {
804 switch (SDHC_DMA_TYPE(s
->hostctl
)) {
806 if ((s
->blkcnt
== 1) || !(s
->trnmod
& SDHC_TRNS_MULTI
)) {
807 sdhci_sdma_transfer_single_block(s
);
809 sdhci_sdma_transfer_multi_blocks(s
);
813 case SDHC_CTRL_ADMA1_32
:
814 if (!(s
->capareg
& SDHC_CAN_DO_ADMA1
)) {
815 ERRPRINT("ADMA1 not supported\n");
821 case SDHC_CTRL_ADMA2_32
:
822 if (!(s
->capareg
& SDHC_CAN_DO_ADMA2
)) {
823 ERRPRINT("ADMA2 not supported\n");
829 case SDHC_CTRL_ADMA2_64
:
830 if (!(s
->capareg
& SDHC_CAN_DO_ADMA2
) ||
831 !(s
->capareg
& SDHC_64_BIT_BUS_SUPPORT
)) {
832 ERRPRINT("64 bit ADMA not supported\n");
839 ERRPRINT("Unsupported DMA type\n");
843 if ((s
->trnmod
& SDHC_TRNS_READ
) && sdbus_data_ready(&s
->sdbus
)) {
844 s
->prnsts
|= SDHC_DOING_READ
| SDHC_DATA_INHIBIT
|
845 SDHC_DAT_LINE_ACTIVE
;
846 sdhci_read_block_from_card(s
);
848 s
->prnsts
|= SDHC_DOING_WRITE
| SDHC_DAT_LINE_ACTIVE
|
849 SDHC_SPACE_AVAILABLE
| SDHC_DATA_INHIBIT
;
850 sdhci_write_block_to_card(s
);
855 static bool sdhci_can_issue_command(SDHCIState
*s
)
857 if (!SDHC_CLOCK_IS_ON(s
->clkcon
) ||
858 (((s
->prnsts
& SDHC_DATA_INHIBIT
) || s
->stopped_state
) &&
859 ((s
->cmdreg
& SDHC_CMD_DATA_PRESENT
) ||
860 ((s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
&&
861 !(SDHC_COMMAND_TYPE(s
->cmdreg
) == SDHC_CMD_ABORT
))))) {
868 /* The Buffer Data Port register must be accessed in sequential and
869 * continuous manner */
871 sdhci_buff_access_is_sequential(SDHCIState
*s
, unsigned byte_num
)
873 if ((s
->data_count
& 0x3) != byte_num
) {
874 ERRPRINT("Non-sequential access to Buffer Data Port register"
881 static uint64_t sdhci_read(void *opaque
, hwaddr offset
, unsigned size
)
883 SDHCIState
*s
= (SDHCIState
*)opaque
;
886 switch (offset
& ~0x3) {
891 ret
= s
->blksize
| (s
->blkcnt
<< 16);
897 ret
= s
->trnmod
| (s
->cmdreg
<< 16);
899 case SDHC_RSPREG0
... SDHC_RSPREG3
:
900 ret
= s
->rspreg
[((offset
& ~0x3) - SDHC_RSPREG0
) >> 2];
903 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
904 ret
= sdhci_read_dataport(s
, size
);
905 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size
, (int)offset
,
914 ret
= s
->hostctl
| (s
->pwrcon
<< 8) | (s
->blkgap
<< 16) |
918 ret
= s
->clkcon
| (s
->timeoutcon
<< 16);
921 ret
= s
->norintsts
| (s
->errintsts
<< 16);
923 case SDHC_NORINTSTSEN
:
924 ret
= s
->norintstsen
| (s
->errintstsen
<< 16);
926 case SDHC_NORINTSIGEN
:
927 ret
= s
->norintsigen
| (s
->errintsigen
<< 16);
929 case SDHC_ACMD12ERRSTS
:
930 ret
= s
->acmd12errsts
;
941 case SDHC_ADMASYSADDR
:
942 ret
= (uint32_t)s
->admasysaddr
;
944 case SDHC_ADMASYSADDR
+ 4:
945 ret
= (uint32_t)(s
->admasysaddr
>> 32);
947 case SDHC_SLOT_INT_STATUS
:
948 ret
= (SD_HOST_SPECv2_VERS
<< 16) | sdhci_slotint(s
);
951 ERRPRINT("bad %ub read: addr[0x%04x]\n", size
, (int)offset
);
955 ret
>>= (offset
& 0x3) * 8;
956 ret
&= (1ULL << (size
* 8)) - 1;
957 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size
, (int)offset
, ret
, ret
);
961 static inline void sdhci_blkgap_write(SDHCIState
*s
, uint8_t value
)
963 if ((value
& SDHC_STOP_AT_GAP_REQ
) && (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
)) {
966 s
->blkgap
= value
& SDHC_STOP_AT_GAP_REQ
;
968 if ((value
& SDHC_CONTINUE_REQ
) && s
->stopped_state
&&
969 (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
) == 0) {
970 if (s
->stopped_state
== sdhc_gap_read
) {
971 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_READ
;
972 sdhci_read_block_from_card(s
);
974 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_WRITE
;
975 sdhci_write_block_to_card(s
);
977 s
->stopped_state
= sdhc_not_stopped
;
978 } else if (!s
->stopped_state
&& (value
& SDHC_STOP_AT_GAP_REQ
)) {
979 if (s
->prnsts
& SDHC_DOING_READ
) {
980 s
->stopped_state
= sdhc_gap_read
;
981 } else if (s
->prnsts
& SDHC_DOING_WRITE
) {
982 s
->stopped_state
= sdhc_gap_write
;
987 static inline void sdhci_reset_write(SDHCIState
*s
, uint8_t value
)
994 s
->prnsts
&= ~SDHC_CMD_INHIBIT
;
995 s
->norintsts
&= ~SDHC_NIS_CMDCMP
;
997 case SDHC_RESET_DATA
:
999 s
->prnsts
&= ~(SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
|
1000 SDHC_DOING_READ
| SDHC_DOING_WRITE
|
1001 SDHC_DATA_INHIBIT
| SDHC_DAT_LINE_ACTIVE
);
1002 s
->blkgap
&= ~(SDHC_STOP_AT_GAP_REQ
| SDHC_CONTINUE_REQ
);
1003 s
->stopped_state
= sdhc_not_stopped
;
1004 s
->norintsts
&= ~(SDHC_NIS_WBUFRDY
| SDHC_NIS_RBUFRDY
|
1005 SDHC_NIS_DMA
| SDHC_NIS_TRSCMP
| SDHC_NIS_BLKGAP
);
1011 sdhci_write(void *opaque
, hwaddr offset
, uint64_t val
, unsigned size
)
1013 SDHCIState
*s
= (SDHCIState
*)opaque
;
1014 unsigned shift
= 8 * (offset
& 0x3);
1015 uint32_t mask
= ~(((1ULL << (size
* 8)) - 1) << shift
);
1016 uint32_t value
= val
;
1019 switch (offset
& ~0x3) {
1021 s
->sdmasysad
= (s
->sdmasysad
& mask
) | value
;
1022 MASKED_WRITE(s
->sdmasysad
, mask
, value
);
1023 /* Writing to last byte of sdmasysad might trigger transfer */
1024 if (!(mask
& 0xFF000000) && TRANSFERRING_DATA(s
->prnsts
) && s
->blkcnt
&&
1025 s
->blksize
&& SDHC_DMA_TYPE(s
->hostctl
) == SDHC_CTRL_SDMA
) {
1026 if (s
->trnmod
& SDHC_TRNS_MULTI
) {
1027 sdhci_sdma_transfer_multi_blocks(s
);
1029 sdhci_sdma_transfer_single_block(s
);
1034 if (!TRANSFERRING_DATA(s
->prnsts
)) {
1035 MASKED_WRITE(s
->blksize
, mask
, value
);
1036 MASKED_WRITE(s
->blkcnt
, mask
>> 16, value
>> 16);
1039 /* Limit block size to the maximum buffer size */
1040 if (extract32(s
->blksize
, 0, 12) > s
->buf_maxsz
) {
1041 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Size 0x%x is larger than " \
1042 "the maximum buffer 0x%x", __func__
, s
->blksize
,
1045 s
->blksize
= deposit32(s
->blksize
, 0, 12, s
->buf_maxsz
);
1050 MASKED_WRITE(s
->argument
, mask
, value
);
1053 /* DMA can be enabled only if it is supported as indicated by
1054 * capabilities register */
1055 if (!(s
->capareg
& SDHC_CAN_DO_DMA
)) {
1056 value
&= ~SDHC_TRNS_DMA
;
1058 MASKED_WRITE(s
->trnmod
, mask
, value
& MASK_TRNMOD
);
1059 MASKED_WRITE(s
->cmdreg
, mask
>> 16, value
>> 16);
1061 /* Writing to the upper byte of CMDREG triggers SD command generation */
1062 if ((mask
& 0xFF000000) || !sdhci_can_issue_command(s
)) {
1066 sdhci_send_command(s
);
1069 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
1070 sdhci_write_dataport(s
, value
>> shift
, size
);
1074 if (!(mask
& 0xFF0000)) {
1075 sdhci_blkgap_write(s
, value
>> 16);
1077 MASKED_WRITE(s
->hostctl
, mask
, value
);
1078 MASKED_WRITE(s
->pwrcon
, mask
>> 8, value
>> 8);
1079 MASKED_WRITE(s
->wakcon
, mask
>> 24, value
>> 24);
1080 if (!(s
->prnsts
& SDHC_CARD_PRESENT
) || ((s
->pwrcon
>> 1) & 0x7) < 5 ||
1081 !(s
->capareg
& (1 << (31 - ((s
->pwrcon
>> 1) & 0x7))))) {
1082 s
->pwrcon
&= ~SDHC_POWER_ON
;
1086 if (!(mask
& 0xFF000000)) {
1087 sdhci_reset_write(s
, value
>> 24);
1089 MASKED_WRITE(s
->clkcon
, mask
, value
);
1090 MASKED_WRITE(s
->timeoutcon
, mask
>> 16, value
>> 16);
1091 if (s
->clkcon
& SDHC_CLOCK_INT_EN
) {
1092 s
->clkcon
|= SDHC_CLOCK_INT_STABLE
;
1094 s
->clkcon
&= ~SDHC_CLOCK_INT_STABLE
;
1097 case SDHC_NORINTSTS
:
1098 if (s
->norintstsen
& SDHC_NISEN_CARDINT
) {
1099 value
&= ~SDHC_NIS_CARDINT
;
1101 s
->norintsts
&= mask
| ~value
;
1102 s
->errintsts
&= (mask
>> 16) | ~(value
>> 16);
1104 s
->norintsts
|= SDHC_NIS_ERR
;
1106 s
->norintsts
&= ~SDHC_NIS_ERR
;
1108 sdhci_update_irq(s
);
1110 case SDHC_NORINTSTSEN
:
1111 MASKED_WRITE(s
->norintstsen
, mask
, value
);
1112 MASKED_WRITE(s
->errintstsen
, mask
>> 16, value
>> 16);
1113 s
->norintsts
&= s
->norintstsen
;
1114 s
->errintsts
&= s
->errintstsen
;
1116 s
->norintsts
|= SDHC_NIS_ERR
;
1118 s
->norintsts
&= ~SDHC_NIS_ERR
;
1120 /* Quirk for Raspberry Pi: pending card insert interrupt
1121 * appears when first enabled after power on */
1122 if ((s
->norintstsen
& SDHC_NISEN_INSERT
) && s
->pending_insert_state
) {
1123 assert(s
->pending_insert_quirk
);
1124 s
->norintsts
|= SDHC_NIS_INSERT
;
1125 s
->pending_insert_state
= false;
1127 sdhci_update_irq(s
);
1129 case SDHC_NORINTSIGEN
:
1130 MASKED_WRITE(s
->norintsigen
, mask
, value
);
1131 MASKED_WRITE(s
->errintsigen
, mask
>> 16, value
>> 16);
1132 sdhci_update_irq(s
);
1135 MASKED_WRITE(s
->admaerr
, mask
, value
);
1137 case SDHC_ADMASYSADDR
:
1138 s
->admasysaddr
= (s
->admasysaddr
& (0xFFFFFFFF00000000ULL
|
1139 (uint64_t)mask
)) | (uint64_t)value
;
1141 case SDHC_ADMASYSADDR
+ 4:
1142 s
->admasysaddr
= (s
->admasysaddr
& (0x00000000FFFFFFFFULL
|
1143 ((uint64_t)mask
<< 32))) | ((uint64_t)value
<< 32);
1146 s
->acmd12errsts
|= value
;
1147 s
->errintsts
|= (value
>> 16) & s
->errintstsen
;
1148 if (s
->acmd12errsts
) {
1149 s
->errintsts
|= SDHC_EIS_CMD12ERR
;
1152 s
->norintsts
|= SDHC_NIS_ERR
;
1154 sdhci_update_irq(s
);
1157 ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n",
1158 size
, (int)offset
, value
>> shift
, value
>> shift
);
1161 DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n",
1162 size
, (int)offset
, value
>> shift
, value
>> shift
);
1165 static const MemoryRegionOps sdhci_mmio_ops
= {
1167 .write
= sdhci_write
,
1169 .min_access_size
= 1,
1170 .max_access_size
= 4,
1173 .endianness
= DEVICE_LITTLE_ENDIAN
,
1176 static inline unsigned int sdhci_get_fifolen(SDHCIState
*s
)
1178 switch (SDHC_CAPAB_BLOCKSIZE(s
->capareg
)) {
1186 hw_error("SDHC: unsupported value for maximum block size\n");
1191 static void sdhci_initfn(SDHCIState
*s
)
1193 qbus_create_inplace(&s
->sdbus
, sizeof(s
->sdbus
),
1194 TYPE_SDHCI_BUS
, DEVICE(s
), "sd-bus");
1196 s
->insert_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_raise_insertion_irq
, s
);
1197 s
->transfer_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_data_transfer
, s
);
1200 static void sdhci_uninitfn(SDHCIState
*s
)
1202 timer_del(s
->insert_timer
);
1203 timer_free(s
->insert_timer
);
1204 timer_del(s
->transfer_timer
);
1205 timer_free(s
->transfer_timer
);
1206 qemu_free_irq(s
->eject_cb
);
1207 qemu_free_irq(s
->ro_cb
);
1209 g_free(s
->fifo_buffer
);
1210 s
->fifo_buffer
= NULL
;
1213 static bool sdhci_pending_insert_vmstate_needed(void *opaque
)
1215 SDHCIState
*s
= opaque
;
1217 return s
->pending_insert_state
;
1220 static const VMStateDescription sdhci_pending_insert_vmstate
= {
1221 .name
= "sdhci/pending-insert",
1223 .minimum_version_id
= 1,
1224 .needed
= sdhci_pending_insert_vmstate_needed
,
1225 .fields
= (VMStateField
[]) {
1226 VMSTATE_BOOL(pending_insert_state
, SDHCIState
),
1227 VMSTATE_END_OF_LIST()
1231 const VMStateDescription sdhci_vmstate
= {
1234 .minimum_version_id
= 1,
1235 .fields
= (VMStateField
[]) {
1236 VMSTATE_UINT32(sdmasysad
, SDHCIState
),
1237 VMSTATE_UINT16(blksize
, SDHCIState
),
1238 VMSTATE_UINT16(blkcnt
, SDHCIState
),
1239 VMSTATE_UINT32(argument
, SDHCIState
),
1240 VMSTATE_UINT16(trnmod
, SDHCIState
),
1241 VMSTATE_UINT16(cmdreg
, SDHCIState
),
1242 VMSTATE_UINT32_ARRAY(rspreg
, SDHCIState
, 4),
1243 VMSTATE_UINT32(prnsts
, SDHCIState
),
1244 VMSTATE_UINT8(hostctl
, SDHCIState
),
1245 VMSTATE_UINT8(pwrcon
, SDHCIState
),
1246 VMSTATE_UINT8(blkgap
, SDHCIState
),
1247 VMSTATE_UINT8(wakcon
, SDHCIState
),
1248 VMSTATE_UINT16(clkcon
, SDHCIState
),
1249 VMSTATE_UINT8(timeoutcon
, SDHCIState
),
1250 VMSTATE_UINT8(admaerr
, SDHCIState
),
1251 VMSTATE_UINT16(norintsts
, SDHCIState
),
1252 VMSTATE_UINT16(errintsts
, SDHCIState
),
1253 VMSTATE_UINT16(norintstsen
, SDHCIState
),
1254 VMSTATE_UINT16(errintstsen
, SDHCIState
),
1255 VMSTATE_UINT16(norintsigen
, SDHCIState
),
1256 VMSTATE_UINT16(errintsigen
, SDHCIState
),
1257 VMSTATE_UINT16(acmd12errsts
, SDHCIState
),
1258 VMSTATE_UINT16(data_count
, SDHCIState
),
1259 VMSTATE_UINT64(admasysaddr
, SDHCIState
),
1260 VMSTATE_UINT8(stopped_state
, SDHCIState
),
1261 VMSTATE_VBUFFER_UINT32(fifo_buffer
, SDHCIState
, 1, NULL
, buf_maxsz
),
1262 VMSTATE_TIMER_PTR(insert_timer
, SDHCIState
),
1263 VMSTATE_TIMER_PTR(transfer_timer
, SDHCIState
),
1264 VMSTATE_END_OF_LIST()
1266 .subsections
= (const VMStateDescription
*[]) {
1267 &sdhci_pending_insert_vmstate
,
1272 /* Capabilities registers provide information on supported features of this
1273 * specific host controller implementation */
1274 static Property sdhci_pci_properties
[] = {
1275 DEFINE_PROP_UINT32("capareg", SDHCIState
, capareg
,
1276 SDHC_CAPAB_REG_DEFAULT
),
1277 DEFINE_PROP_UINT32("maxcurr", SDHCIState
, maxcurr
, 0),
1278 DEFINE_PROP_END_OF_LIST(),
1281 static void sdhci_pci_realize(PCIDevice
*dev
, Error
**errp
)
1283 SDHCIState
*s
= PCI_SDHCI(dev
);
1284 dev
->config
[PCI_CLASS_PROG
] = 0x01; /* Standard Host supported DMA */
1285 dev
->config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin A */
1287 s
->buf_maxsz
= sdhci_get_fifolen(s
);
1288 s
->fifo_buffer
= g_malloc0(s
->buf_maxsz
);
1289 s
->irq
= pci_allocate_irq(dev
);
1290 memory_region_init_io(&s
->iomem
, OBJECT(s
), &sdhci_mmio_ops
, s
, "sdhci",
1291 SDHC_REGISTERS_MAP_SIZE
);
1292 pci_register_bar(dev
, 0, 0, &s
->iomem
);
1295 static void sdhci_pci_exit(PCIDevice
*dev
)
1297 SDHCIState
*s
= PCI_SDHCI(dev
);
1301 static void sdhci_pci_class_init(ObjectClass
*klass
, void *data
)
1303 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1304 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1306 k
->realize
= sdhci_pci_realize
;
1307 k
->exit
= sdhci_pci_exit
;
1308 k
->vendor_id
= PCI_VENDOR_ID_REDHAT
;
1309 k
->device_id
= PCI_DEVICE_ID_REDHAT_SDHCI
;
1310 k
->class_id
= PCI_CLASS_SYSTEM_SDHCI
;
1311 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1312 dc
->vmsd
= &sdhci_vmstate
;
1313 dc
->props
= sdhci_pci_properties
;
1314 dc
->reset
= sdhci_poweron_reset
;
1317 static const TypeInfo sdhci_pci_info
= {
1318 .name
= TYPE_PCI_SDHCI
,
1319 .parent
= TYPE_PCI_DEVICE
,
1320 .instance_size
= sizeof(SDHCIState
),
1321 .class_init
= sdhci_pci_class_init
,
1324 static Property sdhci_sysbus_properties
[] = {
1325 DEFINE_PROP_UINT32("capareg", SDHCIState
, capareg
,
1326 SDHC_CAPAB_REG_DEFAULT
),
1327 DEFINE_PROP_UINT32("maxcurr", SDHCIState
, maxcurr
, 0),
1328 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState
, pending_insert_quirk
,
1330 DEFINE_PROP_END_OF_LIST(),
1333 static void sdhci_sysbus_init(Object
*obj
)
1335 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1340 static void sdhci_sysbus_finalize(Object
*obj
)
1342 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1346 static void sdhci_sysbus_realize(DeviceState
*dev
, Error
** errp
)
1348 SDHCIState
*s
= SYSBUS_SDHCI(dev
);
1349 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1351 s
->buf_maxsz
= sdhci_get_fifolen(s
);
1352 s
->fifo_buffer
= g_malloc0(s
->buf_maxsz
);
1353 sysbus_init_irq(sbd
, &s
->irq
);
1354 memory_region_init_io(&s
->iomem
, OBJECT(s
), &sdhci_mmio_ops
, s
, "sdhci",
1355 SDHC_REGISTERS_MAP_SIZE
);
1356 sysbus_init_mmio(sbd
, &s
->iomem
);
1359 static void sdhci_sysbus_class_init(ObjectClass
*klass
, void *data
)
1361 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1363 dc
->vmsd
= &sdhci_vmstate
;
1364 dc
->props
= sdhci_sysbus_properties
;
1365 dc
->realize
= sdhci_sysbus_realize
;
1366 dc
->reset
= sdhci_poweron_reset
;
1369 static const TypeInfo sdhci_sysbus_info
= {
1370 .name
= TYPE_SYSBUS_SDHCI
,
1371 .parent
= TYPE_SYS_BUS_DEVICE
,
1372 .instance_size
= sizeof(SDHCIState
),
1373 .instance_init
= sdhci_sysbus_init
,
1374 .instance_finalize
= sdhci_sysbus_finalize
,
1375 .class_init
= sdhci_sysbus_class_init
,
1378 static void sdhci_bus_class_init(ObjectClass
*klass
, void *data
)
1380 SDBusClass
*sbc
= SD_BUS_CLASS(klass
);
1382 sbc
->set_inserted
= sdhci_set_inserted
;
1383 sbc
->set_readonly
= sdhci_set_readonly
;
1386 static const TypeInfo sdhci_bus_info
= {
1387 .name
= TYPE_SDHCI_BUS
,
1388 .parent
= TYPE_SD_BUS
,
1389 .instance_size
= sizeof(SDBus
),
1390 .class_init
= sdhci_bus_class_init
,
1393 static void sdhci_register_types(void)
1395 type_register_static(&sdhci_pci_info
);
1396 type_register_static(&sdhci_sysbus_info
);
1397 type_register_static(&sdhci_bus_info
);
1400 type_init(sdhci_register_types
)