hw/i386/intel_iommu: Fix struct VTDInvDescIEC on big endian hosts
[qemu/ar7.git] / tcg / mips / tcg-target-con-set.h
blob864034f4687827fb57c5a3583282fea99264a48f
1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Define MIPS target-specific constraint sets.
4 * Copyright (c) 2021 Linaro
5 */
7 /*
8 * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
9 * Each operand should be a sequence of constraint letters as defined by
10 * tcg-target-con-str.h; the constraint combination is inclusive or.
12 C_O0_I1(r)
13 C_O0_I2(rZ, r)
14 C_O0_I2(rZ, rZ)
15 C_O0_I3(rZ, r, r)
16 C_O0_I3(rZ, rZ, r)
17 C_O0_I4(rZ, rZ, rZ, rZ)
18 C_O0_I4(rZ, rZ, r, r)
19 C_O1_I1(r, r)
20 C_O1_I2(r, 0, rZ)
21 C_O1_I2(r, r, r)
22 C_O1_I2(r, r, ri)
23 C_O1_I2(r, r, rI)
24 C_O1_I2(r, r, rIK)
25 C_O1_I2(r, r, rJ)
26 C_O1_I2(r, r, rWZ)
27 C_O1_I2(r, rZ, rN)
28 C_O1_I2(r, rZ, rZ)
29 C_O1_I4(r, rZ, rZ, rZ, 0)
30 C_O1_I4(r, rZ, rZ, rZ, rZ)
31 C_O2_I1(r, r, r)
32 C_O2_I2(r, r, r, r)
33 C_O2_I4(r, r, rZ, rZ, rN, rN)