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target/m68k: introduce gen_singlestep_exception() function
[qemu/ar7.git] / target / m68k / translate.c
blob10e8aba42e421be279cb6910979065a5d2dadafd
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
26 #include "qemu/log.h"
27 #include "qemu/qemu-print.h"
28 #include "exec/cpu_ldst.h"
29 #include "exec/translator.h"
30
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
33
34 #include "trace-tcg.h"
35 #include "exec/log.h"
36 #include "fpu/softfloat.h"
37
38
39 //#define DEBUG_DISPATCH 1
40
41 #define DEFO32(name, offset) static TCGv QREG_##name;
42 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
43 #include "qregs.def"
44 #undef DEFO32
45 #undef DEFO64
46
47 static TCGv_i32 cpu_halted;
48 static TCGv_i32 cpu_exception_index;
49
50 static char cpu_reg_names[2 * 8 * 3 + 5 * 4];
51 static TCGv cpu_dregs[8];
52 static TCGv cpu_aregs[8];
53 static TCGv_i64 cpu_macc[4];
54
55 #define REG(insn, pos) (((insn) >> (pos)) & 7)
56 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
57 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
58 #define MACREG(acc) cpu_macc[acc]
59 #define QREG_SP get_areg(s, 7)
60
61 static TCGv NULL_QREG;
62 #define IS_NULL_QREG(t) (t == NULL_QREG)
63 /* Used to distinguish stores from bad addressing modes. */
64 static TCGv store_dummy;
65
66 #include "exec/gen-icount.h"
67
68 void m68k_tcg_init(void)
69 {
70 char *p;
71 int i;
72
73 #define DEFO32(name, offset) \
74 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
75 offsetof(CPUM68KState, offset), #name);
76 #define DEFO64(name, offset) \
77 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
78 offsetof(CPUM68KState, offset), #name);
79 #include "qregs.def"
80 #undef DEFO32
81 #undef DEFO64
82
83 cpu_halted = tcg_global_mem_new_i32(cpu_env,
84 -offsetof(M68kCPU, env) +
85 offsetof(CPUState, halted), "HALTED");
86 cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
87 -offsetof(M68kCPU, env) +
88 offsetof(CPUState, exception_index),
89 "EXCEPTION");
90
91 p = cpu_reg_names;
92 for (i = 0; i < 8; i++) {
93 sprintf(p, "D%d", i);
94 cpu_dregs[i] = tcg_global_mem_new(cpu_env,
95 offsetof(CPUM68KState, dregs[i]), p);
96 p += 3;
97 sprintf(p, "A%d", i);
98 cpu_aregs[i] = tcg_global_mem_new(cpu_env,
99 offsetof(CPUM68KState, aregs[i]), p);
100 p += 3;
101 }
102 for (i = 0; i < 4; i++) {
103 sprintf(p, "ACC%d", i);
104 cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
105 offsetof(CPUM68KState, macc[i]), p);
106 p += 5;
107 }
108
109 NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
110 store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
111 }
112
113 /* internal defines */
114 typedef struct DisasContext {
115 DisasContextBase base;
116 CPUM68KState *env;
117 target_ulong pc;
118 CCOp cc_op; /* Current CC operation */
119 int cc_op_synced;
120 TCGv_i64 mactmp;
121 int done_mac;
122 int writeback_mask;
123 TCGv writeback[8];
124 #define MAX_TO_RELEASE 8
125 int release_count;
126 TCGv release[MAX_TO_RELEASE];
127 } DisasContext;
128
129 static void init_release_array(DisasContext *s)
130 {
131 #ifdef CONFIG_DEBUG_TCG
132 memset(s->release, 0, sizeof(s->release));
133 #endif
134 s->release_count = 0;
135 }
136
137 static void do_release(DisasContext *s)
138 {
139 int i;
140 for (i = 0; i < s->release_count; i++) {
141 tcg_temp_free(s->release[i]);
142 }
143 init_release_array(s);
144 }
145
146 static TCGv mark_to_release(DisasContext *s, TCGv tmp)
147 {
148 g_assert(s->release_count < MAX_TO_RELEASE);
149 return s->release[s->release_count++] = tmp;
150 }
151
152 static TCGv get_areg(DisasContext *s, unsigned regno)
153 {
154 if (s->writeback_mask & (1 << regno)) {
155 return s->writeback[regno];
156 } else {
157 return cpu_aregs[regno];
158 }
159 }
160
161 static void delay_set_areg(DisasContext *s, unsigned regno,
162 TCGv val, bool give_temp)
163 {
164 if (s->writeback_mask & (1 << regno)) {
165 if (give_temp) {
166 tcg_temp_free(s->writeback[regno]);
167 s->writeback[regno] = val;
168 } else {
169 tcg_gen_mov_i32(s->writeback[regno], val);
170 }
171 } else {
172 s->writeback_mask |= 1 << regno;
173 if (give_temp) {
174 s->writeback[regno] = val;
175 } else {
176 TCGv tmp = tcg_temp_new();
177 s->writeback[regno] = tmp;
178 tcg_gen_mov_i32(tmp, val);
179 }
180 }
181 }
182
183 static void do_writebacks(DisasContext *s)
184 {
185 unsigned mask = s->writeback_mask;
186 if (mask) {
187 s->writeback_mask = 0;
188 do {
189 unsigned regno = ctz32(mask);
190 tcg_gen_mov_i32(cpu_aregs[regno], s->writeback[regno]);
191 tcg_temp_free(s->writeback[regno]);
192 mask &= mask - 1;
193 } while (mask);
194 }
195 }
196
197 static bool is_singlestepping(DisasContext *s)
198 {
199 /*
200 * Return true if we are singlestepping either because of QEMU gdbstub
201 * singlestep. This does not include the command line '-singlestep' mode
202 * which is rather misnamed as it only means "one instruction per TB" and
203 * doesn't affect the code we generate.
204 */
205 return s->base.singlestep_enabled;
206 }
207
208 /* is_jmp field values */
209 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
210 #define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
211
212 #if defined(CONFIG_USER_ONLY)
213 #define IS_USER(s) 1
214 #else
215 #define IS_USER(s) (!(s->base.tb->flags & TB_FLAGS_MSR_S))
216 #define SFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_SFC_S) ? \
217 MMU_KERNEL_IDX : MMU_USER_IDX)
218 #define DFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_DFC_S) ? \
219 MMU_KERNEL_IDX : MMU_USER_IDX)
220 #endif
221
222 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
223
224 #ifdef DEBUG_DISPATCH
225 #define DISAS_INSN(name) \
226 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
227 uint16_t insn); \
228 static void disas_##name(CPUM68KState *env, DisasContext *s, \
229 uint16_t insn) \
230 { \
231 qemu_log("Dispatch " #name "\n"); \
232 real_disas_##name(env, s, insn); \
233 } \
234 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
235 uint16_t insn)
236 #else
237 #define DISAS_INSN(name) \
238 static void disas_##name(CPUM68KState *env, DisasContext *s, \
239 uint16_t insn)
240 #endif
241
242 static const uint8_t cc_op_live[CC_OP_NB] = {
243 [CC_OP_DYNAMIC] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
244 [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
245 [CC_OP_ADDB ... CC_OP_ADDL] = CCF_X | CCF_N | CCF_V,
246 [CC_OP_SUBB ... CC_OP_SUBL] = CCF_X | CCF_N | CCF_V,
247 [CC_OP_CMPB ... CC_OP_CMPL] = CCF_X | CCF_N | CCF_V,
248 [CC_OP_LOGIC] = CCF_X | CCF_N
249 };
250
251 static void set_cc_op(DisasContext *s, CCOp op)
252 {
253 CCOp old_op = s->cc_op;
254 int dead;
255
256 if (old_op == op) {
257 return;
258 }
259 s->cc_op = op;
260 s->cc_op_synced = 0;
261
262 /*
263 * Discard CC computation that will no longer be used.
264 * Note that X and N are never dead.
265 */
266 dead = cc_op_live[old_op] & ~cc_op_live[op];
267 if (dead & CCF_C) {
268 tcg_gen_discard_i32(QREG_CC_C);
269 }
270 if (dead & CCF_Z) {
271 tcg_gen_discard_i32(QREG_CC_Z);
272 }
273 if (dead & CCF_V) {
274 tcg_gen_discard_i32(QREG_CC_V);
275 }
276 }
277
278 /* Update the CPU env CC_OP state. */
279 static void update_cc_op(DisasContext *s)
280 {
281 if (!s->cc_op_synced) {
282 s->cc_op_synced = 1;
283 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
284 }
285 }
286
287 /* Generate a jump to an immediate address. */
288 static void gen_jmp_im(DisasContext *s, uint32_t dest)
289 {
290 update_cc_op(s);
291 tcg_gen_movi_i32(QREG_PC, dest);
292 s->base.is_jmp = DISAS_JUMP;
293 }
294
295 /* Generate a jump to the address in qreg DEST. */
296 static void gen_jmp(DisasContext *s, TCGv dest)
297 {
298 update_cc_op(s);
299 tcg_gen_mov_i32(QREG_PC, dest);
300 s->base.is_jmp = DISAS_JUMP;
301 }
302
303 static void gen_raise_exception(int nr)
304 {
305 TCGv_i32 tmp;
306
307 tmp = tcg_const_i32(nr);
308 gen_helper_raise_exception(cpu_env, tmp);
309 tcg_temp_free_i32(tmp);
310 }
311
312 static void gen_exception(DisasContext *s, uint32_t dest, int nr)
313 {
314 update_cc_op(s);
315 tcg_gen_movi_i32(QREG_PC, dest);
316
317 gen_raise_exception(nr);
318
319 s->base.is_jmp = DISAS_NORETURN;
320 }
321
322 static void gen_singlestep_exception(DisasContext *s)
323 {
324 /*
325 * Generate the right kind of exception for singlestep, which is
326 * EXCP_DEBUG for QEMU's gdb singlestepping.
327 */
328 gen_raise_exception(EXCP_DEBUG);
329 }
330
331 static inline void gen_addr_fault(DisasContext *s)
332 {
333 gen_exception(s, s->base.pc_next, EXCP_ADDRESS);
334 }
335
336 /*
337 * Generate a load from the specified address. Narrow values are
338 * sign extended to full register width.
339 */
340 static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr,
341 int sign, int index)
342 {
343 TCGv tmp;
344 tmp = tcg_temp_new_i32();
345 switch(opsize) {
346 case OS_BYTE:
347 if (sign)
348 tcg_gen_qemu_ld8s(tmp, addr, index);
349 else
350 tcg_gen_qemu_ld8u(tmp, addr, index);
351 break;
352 case OS_WORD:
353 if (sign)
354 tcg_gen_qemu_ld16s(tmp, addr, index);
355 else
356 tcg_gen_qemu_ld16u(tmp, addr, index);
357 break;
358 case OS_LONG:
359 tcg_gen_qemu_ld32u(tmp, addr, index);
360 break;
361 default:
362 g_assert_not_reached();
363 }
364 return tmp;
365 }
366
367 /* Generate a store. */
368 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val,
369 int index)
370 {
371 switch(opsize) {
372 case OS_BYTE:
373 tcg_gen_qemu_st8(val, addr, index);
374 break;
375 case OS_WORD:
376 tcg_gen_qemu_st16(val, addr, index);
377 break;
378 case OS_LONG:
379 tcg_gen_qemu_st32(val, addr, index);
380 break;
381 default:
382 g_assert_not_reached();
383 }
384 }
385
386 typedef enum {
387 EA_STORE,
388 EA_LOADU,
389 EA_LOADS
390 } ea_what;
391
392 /*
393 * Generate an unsigned load if VAL is 0 a signed load if val is -1,
394 * otherwise generate a store.
395 */
396 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
397 ea_what what, int index)
398 {
399 if (what == EA_STORE) {
400 gen_store(s, opsize, addr, val, index);
401 return store_dummy;
402 } else {
403 return mark_to_release(s, gen_load(s, opsize, addr,
404 what == EA_LOADS, index));
405 }
406 }
407
408 /* Read a 16-bit immediate constant */
409 static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
410 {
411 uint16_t im;
412 im = translator_lduw(env, s->pc);
413 s->pc += 2;
414 return im;
415 }
416
417 /* Read an 8-bit immediate constant */
418 static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s)
419 {
420 return read_im16(env, s);
421 }
422
423 /* Read a 32-bit immediate constant. */
424 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
425 {
426 uint32_t im;
427 im = read_im16(env, s) << 16;
428 im |= 0xffff & read_im16(env, s);
429 return im;
430 }
431
432 /* Read a 64-bit immediate constant. */
433 static inline uint64_t read_im64(CPUM68KState *env, DisasContext *s)
434 {
435 uint64_t im;
436 im = (uint64_t)read_im32(env, s) << 32;
437 im |= (uint64_t)read_im32(env, s);
438 return im;
439 }
440
441 /* Calculate and address index. */
442 static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
443 {
444 TCGv add;
445 int scale;
446
447 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
448 if ((ext & 0x800) == 0) {
449 tcg_gen_ext16s_i32(tmp, add);
450 add = tmp;
451 }
452 scale = (ext >> 9) & 3;
453 if (scale != 0) {
454 tcg_gen_shli_i32(tmp, add, scale);
455 add = tmp;
456 }
457 return add;
458 }
459
460 /*
461 * Handle a base + index + displacement effective address.
462 * A NULL_QREG base means pc-relative.
463 */
464 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
465 {
466 uint32_t offset;
467 uint16_t ext;
468 TCGv add;
469 TCGv tmp;
470 uint32_t bd, od;
471
472 offset = s->pc;
473 ext = read_im16(env, s);
474
475 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
476 return NULL_QREG;
477
478 if (m68k_feature(s->env, M68K_FEATURE_M68000) &&
479 !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) {
480 ext &= ~(3 << 9);
481 }
482
483 if (ext & 0x100) {
484 /* full extension word format */
485 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
486 return NULL_QREG;
487
488 if ((ext & 0x30) > 0x10) {
489 /* base displacement */
490 if ((ext & 0x30) == 0x20) {
491 bd = (int16_t)read_im16(env, s);
492 } else {
493 bd = read_im32(env, s);
494 }
495 } else {
496 bd = 0;
497 }
498 tmp = mark_to_release(s, tcg_temp_new());
499 if ((ext & 0x44) == 0) {
500 /* pre-index */
501 add = gen_addr_index(s, ext, tmp);
502 } else {
503 add = NULL_QREG;
504 }
505 if ((ext & 0x80) == 0) {
506 /* base not suppressed */
507 if (IS_NULL_QREG(base)) {
508 base = mark_to_release(s, tcg_const_i32(offset + bd));
509 bd = 0;
510 }
511 if (!IS_NULL_QREG(add)) {
512 tcg_gen_add_i32(tmp, add, base);
513 add = tmp;
514 } else {
515 add = base;
516 }
517 }
518 if (!IS_NULL_QREG(add)) {
519 if (bd != 0) {
520 tcg_gen_addi_i32(tmp, add, bd);
521 add = tmp;
522 }
523 } else {
524 add = mark_to_release(s, tcg_const_i32(bd));
525 }
526 if ((ext & 3) != 0) {
527 /* memory indirect */
528 base = mark_to_release(s, gen_load(s, OS_LONG, add, 0, IS_USER(s)));
529 if ((ext & 0x44) == 4) {
530 add = gen_addr_index(s, ext, tmp);
531 tcg_gen_add_i32(tmp, add, base);
532 add = tmp;
533 } else {
534 add = base;
535 }
536 if ((ext & 3) > 1) {
537 /* outer displacement */
538 if ((ext & 3) == 2) {
539 od = (int16_t)read_im16(env, s);
540 } else {
541 od = read_im32(env, s);
542 }
543 } else {
544 od = 0;
545 }
546 if (od != 0) {
547 tcg_gen_addi_i32(tmp, add, od);
548 add = tmp;
549 }
550 }
551 } else {
552 /* brief extension word format */
553 tmp = mark_to_release(s, tcg_temp_new());
554 add = gen_addr_index(s, ext, tmp);
555 if (!IS_NULL_QREG(base)) {
556 tcg_gen_add_i32(tmp, add, base);
557 if ((int8_t)ext)
558 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
559 } else {
560 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
561 }
562 add = tmp;
563 }
564 return add;
565 }
566
567 /* Sign or zero extend a value. */
568
569 static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign)
570 {
571 switch (opsize) {
572 case OS_BYTE:
573 if (sign) {
574 tcg_gen_ext8s_i32(res, val);
575 } else {
576 tcg_gen_ext8u_i32(res, val);
577 }
578 break;
579 case OS_WORD:
580 if (sign) {
581 tcg_gen_ext16s_i32(res, val);
582 } else {
583 tcg_gen_ext16u_i32(res, val);
584 }
585 break;
586 case OS_LONG:
587 tcg_gen_mov_i32(res, val);
588 break;
589 default:
590 g_assert_not_reached();
591 }
592 }
593
594 /* Evaluate all the CC flags. */
595
596 static void gen_flush_flags(DisasContext *s)
597 {
598 TCGv t0, t1;
599
600 switch (s->cc_op) {
601 case CC_OP_FLAGS:
602 return;
603
604 case CC_OP_ADDB:
605 case CC_OP_ADDW:
606 case CC_OP_ADDL:
607 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
608 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
609 /* Compute signed overflow for addition. */
610 t0 = tcg_temp_new();
611 t1 = tcg_temp_new();
612 tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V);
613 gen_ext(t0, t0, s->cc_op - CC_OP_ADDB, 1);
614 tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
615 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
616 tcg_temp_free(t0);
617 tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V);
618 tcg_temp_free(t1);
619 break;
620
621 case CC_OP_SUBB:
622 case CC_OP_SUBW:
623 case CC_OP_SUBL:
624 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
625 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
626 /* Compute signed overflow for subtraction. */
627 t0 = tcg_temp_new();
628 t1 = tcg_temp_new();
629 tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V);
630 gen_ext(t0, t0, s->cc_op - CC_OP_SUBB, 1);
631 tcg_gen_xor_i32(t1, QREG_CC_N, t0);
632 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
633 tcg_temp_free(t0);
634 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1);
635 tcg_temp_free(t1);
636 break;
637
638 case CC_OP_CMPB:
639 case CC_OP_CMPW:
640 case CC_OP_CMPL:
641 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V);
642 tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V);
643 gen_ext(QREG_CC_Z, QREG_CC_Z, s->cc_op - CC_OP_CMPB, 1);
644 /* Compute signed overflow for subtraction. */
645 t0 = tcg_temp_new();
646 tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N);
647 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N);
648 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0);
649 tcg_temp_free(t0);
650 tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z);
651 break;
652
653 case CC_OP_LOGIC:
654 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
655 tcg_gen_movi_i32(QREG_CC_C, 0);
656 tcg_gen_movi_i32(QREG_CC_V, 0);
657 break;
658
659 case CC_OP_DYNAMIC:
660 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
661 s->cc_op_synced = 1;
662 break;
663
664 default:
665 t0 = tcg_const_i32(s->cc_op);
666 gen_helper_flush_flags(cpu_env, t0);
667 tcg_temp_free(t0);
668 s->cc_op_synced = 1;
669 break;
670 }
671
672 /* Note that flush_flags also assigned to env->cc_op. */
673 s->cc_op = CC_OP_FLAGS;
674 }
675
676 static inline TCGv gen_extend(DisasContext *s, TCGv val, int opsize, int sign)
677 {
678 TCGv tmp;
679
680 if (opsize == OS_LONG) {
681 tmp = val;
682 } else {
683 tmp = mark_to_release(s, tcg_temp_new());
684 gen_ext(tmp, val, opsize, sign);
685 }
686
687 return tmp;
688 }
689
690 static void gen_logic_cc(DisasContext *s, TCGv val, int opsize)
691 {
692 gen_ext(QREG_CC_N, val, opsize, 1);
693 set_cc_op(s, CC_OP_LOGIC);
694 }
695
696 static void gen_update_cc_cmp(DisasContext *s, TCGv dest, TCGv src, int opsize)
697 {
698 tcg_gen_mov_i32(QREG_CC_N, dest);
699 tcg_gen_mov_i32(QREG_CC_V, src);
700 set_cc_op(s, CC_OP_CMPB + opsize);
701 }
702
703 static void gen_update_cc_add(TCGv dest, TCGv src, int opsize)
704 {
705 gen_ext(QREG_CC_N, dest, opsize, 1);
706 tcg_gen_mov_i32(QREG_CC_V, src);
707 }
708
709 static inline int opsize_bytes(int opsize)
710 {
711 switch (opsize) {
712 case OS_BYTE: return 1;
713 case OS_WORD: return 2;
714 case OS_LONG: return 4;
715 case OS_SINGLE: return 4;
716 case OS_DOUBLE: return 8;
717 case OS_EXTENDED: return 12;
718 case OS_PACKED: return 12;
719 default:
720 g_assert_not_reached();
721 }
722 }
723
724 static inline int insn_opsize(int insn)
725 {
726 switch ((insn >> 6) & 3) {
727 case 0: return OS_BYTE;
728 case 1: return OS_WORD;
729 case 2: return OS_LONG;
730 default:
731 g_assert_not_reached();
732 }
733 }
734
735 static inline int ext_opsize(int ext, int pos)
736 {
737 switch ((ext >> pos) & 7) {
738 case 0: return OS_LONG;
739 case 1: return OS_SINGLE;
740 case 2: return OS_EXTENDED;
741 case 3: return OS_PACKED;
742 case 4: return OS_WORD;
743 case 5: return OS_DOUBLE;
744 case 6: return OS_BYTE;
745 default:
746 g_assert_not_reached();
747 }
748 }
749
750 /*
751 * Assign value to a register. If the width is less than the register width
752 * only the low part of the register is set.
753 */
754 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
755 {
756 TCGv tmp;
757 switch (opsize) {
758 case OS_BYTE:
759 tcg_gen_andi_i32(reg, reg, 0xffffff00);
760 tmp = tcg_temp_new();
761 tcg_gen_ext8u_i32(tmp, val);
762 tcg_gen_or_i32(reg, reg, tmp);
763 tcg_temp_free(tmp);
764 break;
765 case OS_WORD:
766 tcg_gen_andi_i32(reg, reg, 0xffff0000);
767 tmp = tcg_temp_new();
768 tcg_gen_ext16u_i32(tmp, val);
769 tcg_gen_or_i32(reg, reg, tmp);
770 tcg_temp_free(tmp);
771 break;
772 case OS_LONG:
773 case OS_SINGLE:
774 tcg_gen_mov_i32(reg, val);
775 break;
776 default:
777 g_assert_not_reached();
778 }
779 }
780
781 /*
782 * Generate code for an "effective address". Does not adjust the base
783 * register for autoincrement addressing modes.
784 */
785 static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
786 int mode, int reg0, int opsize)
787 {
788 TCGv reg;
789 TCGv tmp;
790 uint16_t ext;
791 uint32_t offset;
792
793 switch (mode) {
794 case 0: /* Data register direct. */
795 case 1: /* Address register direct. */
796 return NULL_QREG;
797 case 3: /* Indirect postincrement. */
798 if (opsize == OS_UNSIZED) {
799 return NULL_QREG;
800 }
801 /* fallthru */
802 case 2: /* Indirect register */
803 return get_areg(s, reg0);
804 case 4: /* Indirect predecrememnt. */
805 if (opsize == OS_UNSIZED) {
806 return NULL_QREG;
807 }
808 reg = get_areg(s, reg0);
809 tmp = mark_to_release(s, tcg_temp_new());
810 if (reg0 == 7 && opsize == OS_BYTE &&
811 m68k_feature(s->env, M68K_FEATURE_M68000)) {
812 tcg_gen_subi_i32(tmp, reg, 2);
813 } else {
814 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
815 }
816 return tmp;
817 case 5: /* Indirect displacement. */
818 reg = get_areg(s, reg0);
819 tmp = mark_to_release(s, tcg_temp_new());
820 ext = read_im16(env, s);
821 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
822 return tmp;
823 case 6: /* Indirect index + displacement. */
824 reg = get_areg(s, reg0);
825 return gen_lea_indexed(env, s, reg);
826 case 7: /* Other */
827 switch (reg0) {
828 case 0: /* Absolute short. */
829 offset = (int16_t)read_im16(env, s);
830 return mark_to_release(s, tcg_const_i32(offset));
831 case 1: /* Absolute long. */
832 offset = read_im32(env, s);
833 return mark_to_release(s, tcg_const_i32(offset));
834 case 2: /* pc displacement */
835 offset = s->pc;
836 offset += (int16_t)read_im16(env, s);
837 return mark_to_release(s, tcg_const_i32(offset));
838 case 3: /* pc index+displacement. */
839 return gen_lea_indexed(env, s, NULL_QREG);
840 case 4: /* Immediate. */
841 default:
842 return NULL_QREG;
843 }
844 }
845 /* Should never happen. */
846 return NULL_QREG;
847 }
848
849 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
850 int opsize)
851 {
852 int mode = extract32(insn, 3, 3);
853 int reg0 = REG(insn, 0);
854 return gen_lea_mode(env, s, mode, reg0, opsize);
855 }
856
857 /*
858 * Generate code to load/store a value from/into an EA. If WHAT > 0 this is
859 * a write otherwise it is a read (0 == sign extend, -1 == zero extend).
860 * ADDRP is non-null for readwrite operands.
861 */
862 static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
863 int opsize, TCGv val, TCGv *addrp, ea_what what,
864 int index)
865 {
866 TCGv reg, tmp, result;
867 int32_t offset;
868
869 switch (mode) {
870 case 0: /* Data register direct. */
871 reg = cpu_dregs[reg0];
872 if (what == EA_STORE) {
873 gen_partset_reg(opsize, reg, val);
874 return store_dummy;
875 } else {
876 return gen_extend(s, reg, opsize, what == EA_LOADS);
877 }
878 case 1: /* Address register direct. */
879 reg = get_areg(s, reg0);
880 if (what == EA_STORE) {
881 tcg_gen_mov_i32(reg, val);
882 return store_dummy;
883 } else {
884 return gen_extend(s, reg, opsize, what == EA_LOADS);
885 }
886 case 2: /* Indirect register */
887 reg = get_areg(s, reg0);
888 return gen_ldst(s, opsize, reg, val, what, index);
889 case 3: /* Indirect postincrement. */
890 reg = get_areg(s, reg0);
891 result = gen_ldst(s, opsize, reg, val, what, index);
892 if (what == EA_STORE || !addrp) {
893 TCGv tmp = tcg_temp_new();
894 if (reg0 == 7 && opsize == OS_BYTE &&
895 m68k_feature(s->env, M68K_FEATURE_M68000)) {
896 tcg_gen_addi_i32(tmp, reg, 2);
897 } else {
898 tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
899 }
900 delay_set_areg(s, reg0, tmp, true);
901 }
902 return result;
903 case 4: /* Indirect predecrememnt. */
904 if (addrp && what == EA_STORE) {
905 tmp = *addrp;
906 } else {
907 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
908 if (IS_NULL_QREG(tmp)) {
909 return tmp;
910 }
911 if (addrp) {
912 *addrp = tmp;
913 }
914 }
915 result = gen_ldst(s, opsize, tmp, val, what, index);
916 if (what == EA_STORE || !addrp) {
917 delay_set_areg(s, reg0, tmp, false);
918 }
919 return result;
920 case 5: /* Indirect displacement. */
921 case 6: /* Indirect index + displacement. */
922 do_indirect:
923 if (addrp && what == EA_STORE) {
924 tmp = *addrp;
925 } else {
926 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
927 if (IS_NULL_QREG(tmp)) {
928 return tmp;
929 }
930 if (addrp) {
931 *addrp = tmp;
932 }
933 }
934 return gen_ldst(s, opsize, tmp, val, what, index);
935 case 7: /* Other */
936 switch (reg0) {
937 case 0: /* Absolute short. */
938 case 1: /* Absolute long. */
939 case 2: /* pc displacement */
940 case 3: /* pc index+displacement. */
941 goto do_indirect;
942 case 4: /* Immediate. */
943 /* Sign extend values for consistency. */
944 switch (opsize) {
945 case OS_BYTE:
946 if (what == EA_LOADS) {
947 offset = (int8_t)read_im8(env, s);
948 } else {
949 offset = read_im8(env, s);
950 }
951 break;
952 case OS_WORD:
953 if (what == EA_LOADS) {
954 offset = (int16_t)read_im16(env, s);
955 } else {
956 offset = read_im16(env, s);
957 }
958 break;
959 case OS_LONG:
960 offset = read_im32(env, s);
961 break;
962 default:
963 g_assert_not_reached();
964 }
965 return mark_to_release(s, tcg_const_i32(offset));
966 default:
967 return NULL_QREG;
968 }
969 }
970 /* Should never happen. */
971 return NULL_QREG;
972 }
973
974 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
975 int opsize, TCGv val, TCGv *addrp, ea_what what, int index)
976 {
977 int mode = extract32(insn, 3, 3);
978 int reg0 = REG(insn, 0);
979 return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what, index);
980 }
981
982 static TCGv_ptr gen_fp_ptr(int freg)
983 {
984 TCGv_ptr fp = tcg_temp_new_ptr();
985 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fregs[freg]));
986 return fp;
987 }
988
989 static TCGv_ptr gen_fp_result_ptr(void)
990 {
991 TCGv_ptr fp = tcg_temp_new_ptr();
992 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fp_result));
993 return fp;
994 }
995
996 static void gen_fp_move(TCGv_ptr dest, TCGv_ptr src)
997 {
998 TCGv t32;
999 TCGv_i64 t64;
1000
1001 t32 = tcg_temp_new();
1002 tcg_gen_ld16u_i32(t32, src, offsetof(FPReg, l.upper));
1003 tcg_gen_st16_i32(t32, dest, offsetof(FPReg, l.upper));
1004 tcg_temp_free(t32);
1005
1006 t64 = tcg_temp_new_i64();
1007 tcg_gen_ld_i64(t64, src, offsetof(FPReg, l.lower));
1008 tcg_gen_st_i64(t64, dest, offsetof(FPReg, l.lower));
1009 tcg_temp_free_i64(t64);
1010 }
1011
1012 static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
1013 int index)
1014 {
1015 TCGv tmp;
1016 TCGv_i64 t64;
1017
1018 t64 = tcg_temp_new_i64();
1019 tmp = tcg_temp_new();
1020 switch (opsize) {
1021 case OS_BYTE:
1022 tcg_gen_qemu_ld8s(tmp, addr, index);
1023 gen_helper_exts32(cpu_env, fp, tmp);
1024 break;
1025 case OS_WORD:
1026 tcg_gen_qemu_ld16s(tmp, addr, index);
1027 gen_helper_exts32(cpu_env, fp, tmp);
1028 break;
1029 case OS_LONG:
1030 tcg_gen_qemu_ld32u(tmp, addr, index);
1031 gen_helper_exts32(cpu_env, fp, tmp);
1032 break;
1033 case OS_SINGLE:
1034 tcg_gen_qemu_ld32u(tmp, addr, index);
1035 gen_helper_extf32(cpu_env, fp, tmp);
1036 break;
1037 case OS_DOUBLE:
1038 tcg_gen_qemu_ld64(t64, addr, index);
1039 gen_helper_extf64(cpu_env, fp, t64);
1040 break;
1041 case OS_EXTENDED:
1042 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1043 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1044 break;
1045 }
1046 tcg_gen_qemu_ld32u(tmp, addr, index);
1047 tcg_gen_shri_i32(tmp, tmp, 16);
1048 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
1049 tcg_gen_addi_i32(tmp, addr, 4);
1050 tcg_gen_qemu_ld64(t64, tmp, index);
1051 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
1052 break;
1053 case OS_PACKED:
1054 /*
1055 * unimplemented data type on 68040/ColdFire
1056 * FIXME if needed for another FPU
1057 */
1058 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1059 break;
1060 default:
1061 g_assert_not_reached();
1062 }
1063 tcg_temp_free(tmp);
1064 tcg_temp_free_i64(t64);
1065 }
1066
1067 static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
1068 int index)
1069 {
1070 TCGv tmp;
1071 TCGv_i64 t64;
1072
1073 t64 = tcg_temp_new_i64();
1074 tmp = tcg_temp_new();
1075 switch (opsize) {
1076 case OS_BYTE:
1077 gen_helper_reds32(tmp, cpu_env, fp);
1078 tcg_gen_qemu_st8(tmp, addr, index);
1079 break;
1080 case OS_WORD:
1081 gen_helper_reds32(tmp, cpu_env, fp);
1082 tcg_gen_qemu_st16(tmp, addr, index);
1083 break;
1084 case OS_LONG:
1085 gen_helper_reds32(tmp, cpu_env, fp);
1086 tcg_gen_qemu_st32(tmp, addr, index);
1087 break;
1088 case OS_SINGLE:
1089 gen_helper_redf32(tmp, cpu_env, fp);
1090 tcg_gen_qemu_st32(tmp, addr, index);
1091 break;
1092 case OS_DOUBLE:
1093 gen_helper_redf64(t64, cpu_env, fp);
1094 tcg_gen_qemu_st64(t64, addr, index);
1095 break;
1096 case OS_EXTENDED:
1097 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1098 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1099 break;
1100 }
1101 tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
1102 tcg_gen_shli_i32(tmp, tmp, 16);
1103 tcg_gen_qemu_st32(tmp, addr, index);
1104 tcg_gen_addi_i32(tmp, addr, 4);
1105 tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
1106 tcg_gen_qemu_st64(t64, tmp, index);
1107 break;
1108 case OS_PACKED:
1109 /*
1110 * unimplemented data type on 68040/ColdFire
1111 * FIXME if needed for another FPU
1112 */
1113 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1114 break;
1115 default:
1116 g_assert_not_reached();
1117 }
1118 tcg_temp_free(tmp);
1119 tcg_temp_free_i64(t64);
1120 }
1121
1122 static void gen_ldst_fp(DisasContext *s, int opsize, TCGv addr,
1123 TCGv_ptr fp, ea_what what, int index)
1124 {
1125 if (what == EA_STORE) {
1126 gen_store_fp(s, opsize, addr, fp, index);
1127 } else {
1128 gen_load_fp(s, opsize, addr, fp, index);
1129 }
1130 }
1131
1132 static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
1133 int reg0, int opsize, TCGv_ptr fp, ea_what what,
1134 int index)
1135 {
1136 TCGv reg, addr, tmp;
1137 TCGv_i64 t64;
1138
1139 switch (mode) {
1140 case 0: /* Data register direct. */
1141 reg = cpu_dregs[reg0];
1142 if (what == EA_STORE) {
1143 switch (opsize) {
1144 case OS_BYTE:
1145 case OS_WORD:
1146 case OS_LONG:
1147 gen_helper_reds32(reg, cpu_env, fp);
1148 break;
1149 case OS_SINGLE:
1150 gen_helper_redf32(reg, cpu_env, fp);
1151 break;
1152 default:
1153 g_assert_not_reached();
1154 }
1155 } else {
1156 tmp = tcg_temp_new();
1157 switch (opsize) {
1158 case OS_BYTE:
1159 tcg_gen_ext8s_i32(tmp, reg);
1160 gen_helper_exts32(cpu_env, fp, tmp);
1161 break;
1162 case OS_WORD:
1163 tcg_gen_ext16s_i32(tmp, reg);
1164 gen_helper_exts32(cpu_env, fp, tmp);
1165 break;
1166 case OS_LONG:
1167 gen_helper_exts32(cpu_env, fp, reg);
1168 break;
1169 case OS_SINGLE:
1170 gen_helper_extf32(cpu_env, fp, reg);
1171 break;
1172 default:
1173 g_assert_not_reached();
1174 }
1175 tcg_temp_free(tmp);
1176 }
1177 return 0;
1178 case 1: /* Address register direct. */
1179 return -1;
1180 case 2: /* Indirect register */
1181 addr = get_areg(s, reg0);
1182 gen_ldst_fp(s, opsize, addr, fp, what, index);
1183 return 0;
1184 case 3: /* Indirect postincrement. */
1185 addr = cpu_aregs[reg0];
1186 gen_ldst_fp(s, opsize, addr, fp, what, index);
1187 tcg_gen_addi_i32(addr, addr, opsize_bytes(opsize));
1188 return 0;
1189 case 4: /* Indirect predecrememnt. */
1190 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1191 if (IS_NULL_QREG(addr)) {
1192 return -1;
1193 }
1194 gen_ldst_fp(s, opsize, addr, fp, what, index);
1195 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
1196 return 0;
1197 case 5: /* Indirect displacement. */
1198 case 6: /* Indirect index + displacement. */
1199 do_indirect:
1200 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1201 if (IS_NULL_QREG(addr)) {
1202 return -1;
1203 }
1204 gen_ldst_fp(s, opsize, addr, fp, what, index);
1205 return 0;
1206 case 7: /* Other */
1207 switch (reg0) {
1208 case 0: /* Absolute short. */
1209 case 1: /* Absolute long. */
1210 case 2: /* pc displacement */
1211 case 3: /* pc index+displacement. */
1212 goto do_indirect;
1213 case 4: /* Immediate. */
1214 if (what == EA_STORE) {
1215 return -1;
1216 }
1217 switch (opsize) {
1218 case OS_BYTE:
1219 tmp = tcg_const_i32((int8_t)read_im8(env, s));
1220 gen_helper_exts32(cpu_env, fp, tmp);
1221 tcg_temp_free(tmp);
1222 break;
1223 case OS_WORD:
1224 tmp = tcg_const_i32((int16_t)read_im16(env, s));
1225 gen_helper_exts32(cpu_env, fp, tmp);
1226 tcg_temp_free(tmp);
1227 break;
1228 case OS_LONG:
1229 tmp = tcg_const_i32(read_im32(env, s));
1230 gen_helper_exts32(cpu_env, fp, tmp);
1231 tcg_temp_free(tmp);
1232 break;
1233 case OS_SINGLE:
1234 tmp = tcg_const_i32(read_im32(env, s));
1235 gen_helper_extf32(cpu_env, fp, tmp);
1236 tcg_temp_free(tmp);
1237 break;
1238 case OS_DOUBLE:
1239 t64 = tcg_const_i64(read_im64(env, s));
1240 gen_helper_extf64(cpu_env, fp, t64);
1241 tcg_temp_free_i64(t64);
1242 break;
1243 case OS_EXTENDED:
1244 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1245 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1246 break;
1247 }
1248 tmp = tcg_const_i32(read_im32(env, s) >> 16);
1249 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
1250 tcg_temp_free(tmp);
1251 t64 = tcg_const_i64(read_im64(env, s));
1252 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
1253 tcg_temp_free_i64(t64);
1254 break;
1255 case OS_PACKED:
1256 /*
1257 * unimplemented data type on 68040/ColdFire
1258 * FIXME if needed for another FPU
1259 */
1260 gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
1261 break;
1262 default:
1263 g_assert_not_reached();
1264 }
1265 return 0;
1266 default:
1267 return -1;
1268 }
1269 }
1270 return -1;
1271 }
1272
1273 static int gen_ea_fp(CPUM68KState *env, DisasContext *s, uint16_t insn,
1274 int opsize, TCGv_ptr fp, ea_what what, int index)
1275 {
1276 int mode = extract32(insn, 3, 3);
1277 int reg0 = REG(insn, 0);
1278 return gen_ea_mode_fp(env, s, mode, reg0, opsize, fp, what, index);
1279 }
1280
1281 typedef struct {
1282 TCGCond tcond;
1283 bool g1;
1284 bool g2;
1285 TCGv v1;
1286 TCGv v2;
1287 } DisasCompare;
1288
1289 static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
1290 {
1291 TCGv tmp, tmp2;
1292 TCGCond tcond;
1293 CCOp op = s->cc_op;
1294
1295 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1296 if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) {
1297 c->g1 = c->g2 = 1;
1298 c->v1 = QREG_CC_N;
1299 c->v2 = QREG_CC_V;
1300 switch (cond) {
1301 case 2: /* HI */
1302 case 3: /* LS */
1303 tcond = TCG_COND_LEU;
1304 goto done;
1305 case 4: /* CC */
1306 case 5: /* CS */
1307 tcond = TCG_COND_LTU;
1308 goto done;
1309 case 6: /* NE */
1310 case 7: /* EQ */
1311 tcond = TCG_COND_EQ;
1312 goto done;
1313 case 10: /* PL */
1314 case 11: /* MI */
1315 c->g1 = c->g2 = 0;
1316 c->v2 = tcg_const_i32(0);
1317 c->v1 = tmp = tcg_temp_new();
1318 tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
1319 gen_ext(tmp, tmp, op - CC_OP_CMPB, 1);
1320 /* fallthru */
1321 case 12: /* GE */
1322 case 13: /* LT */
1323 tcond = TCG_COND_LT;
1324 goto done;
1325 case 14: /* GT */
1326 case 15: /* LE */
1327 tcond = TCG_COND_LE;
1328 goto done;
1329 }
1330 }
1331
1332 c->g1 = 1;
1333 c->g2 = 0;
1334 c->v2 = tcg_const_i32(0);
1335
1336 switch (cond) {
1337 case 0: /* T */
1338 case 1: /* F */
1339 c->v1 = c->v2;
1340 tcond = TCG_COND_NEVER;
1341 goto done;
1342 case 14: /* GT (!(Z || (N ^ V))) */
1343 case 15: /* LE (Z || (N ^ V)) */
1344 /*
1345 * Logic operations clear V, which simplifies LE to (Z || N),
1346 * and since Z and N are co-located, this becomes a normal
1347 * comparison vs N.
1348 */
1349 if (op == CC_OP_LOGIC) {
1350 c->v1 = QREG_CC_N;
1351 tcond = TCG_COND_LE;
1352 goto done;
1353 }
1354 break;
1355 case 12: /* GE (!(N ^ V)) */
1356 case 13: /* LT (N ^ V) */
1357 /* Logic operations clear V, which simplifies this to N. */
1358 if (op != CC_OP_LOGIC) {
1359 break;
1360 }
1361 /* fallthru */
1362 case 10: /* PL (!N) */
1363 case 11: /* MI (N) */
1364 /* Several cases represent N normally. */
1365 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1366 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1367 op == CC_OP_LOGIC) {
1368 c->v1 = QREG_CC_N;
1369 tcond = TCG_COND_LT;
1370 goto done;
1371 }
1372 break;
1373 case 6: /* NE (!Z) */
1374 case 7: /* EQ (Z) */
1375 /* Some cases fold Z into N. */
1376 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1377 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1378 op == CC_OP_LOGIC) {
1379 tcond = TCG_COND_EQ;
1380 c->v1 = QREG_CC_N;
1381 goto done;
1382 }
1383 break;
1384 case 4: /* CC (!C) */
1385 case 5: /* CS (C) */
1386 /* Some cases fold C into X. */
1387 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1388 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL) {
1389 tcond = TCG_COND_NE;
1390 c->v1 = QREG_CC_X;
1391 goto done;
1392 }
1393 /* fallthru */
1394 case 8: /* VC (!V) */
1395 case 9: /* VS (V) */
1396 /* Logic operations clear V and C. */
1397 if (op == CC_OP_LOGIC) {
1398 tcond = TCG_COND_NEVER;
1399 c->v1 = c->v2;
1400 goto done;
1401 }
1402 break;
1403 }
1404
1405 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1406 gen_flush_flags(s);
1407
1408 switch (cond) {
1409 case 0: /* T */
1410 case 1: /* F */
1411 default:
1412 /* Invalid, or handled above. */
1413 abort();
1414 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1415 case 3: /* LS (C || Z) */
1416 c->v1 = tmp = tcg_temp_new();
1417 c->g1 = 0;
1418 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1419 tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
1420 tcond = TCG_COND_NE;
1421 break;
1422 case 4: /* CC (!C) */
1423 case 5: /* CS (C) */
1424 c->v1 = QREG_CC_C;
1425 tcond = TCG_COND_NE;
1426 break;
1427 case 6: /* NE (!Z) */
1428 case 7: /* EQ (Z) */
1429 c->v1 = QREG_CC_Z;
1430 tcond = TCG_COND_EQ;
1431 break;
1432 case 8: /* VC (!V) */
1433 case 9: /* VS (V) */
1434 c->v1 = QREG_CC_V;
1435 tcond = TCG_COND_LT;
1436 break;
1437 case 10: /* PL (!N) */
1438 case 11: /* MI (N) */
1439 c->v1 = QREG_CC_N;
1440 tcond = TCG_COND_LT;
1441 break;
1442 case 12: /* GE (!(N ^ V)) */
1443 case 13: /* LT (N ^ V) */
1444 c->v1 = tmp = tcg_temp_new();
1445 c->g1 = 0;
1446 tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
1447 tcond = TCG_COND_LT;
1448 break;
1449 case 14: /* GT (!(Z || (N ^ V))) */
1450 case 15: /* LE (Z || (N ^ V)) */
1451 c->v1 = tmp = tcg_temp_new();
1452 c->g1 = 0;
1453 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1454 tcg_gen_neg_i32(tmp, tmp);
1455 tmp2 = tcg_temp_new();
1456 tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
1457 tcg_gen_or_i32(tmp, tmp, tmp2);
1458 tcg_temp_free(tmp2);
1459 tcond = TCG_COND_LT;
1460 break;
1461 }
1462
1463 done:
1464 if ((cond & 1) == 0) {
1465 tcond = tcg_invert_cond(tcond);
1466 }
1467 c->tcond = tcond;
1468 }
1469
1470 static void free_cond(DisasCompare *c)
1471 {
1472 if (!c->g1) {
1473 tcg_temp_free(c->v1);
1474 }
1475 if (!c->g2) {
1476 tcg_temp_free(c->v2);
1477 }
1478 }
1479
1480 static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
1481 {
1482 DisasCompare c;
1483
1484 gen_cc_cond(&c, s, cond);
1485 update_cc_op(s);
1486 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
1487 free_cond(&c);
1488 }
1489
1490 /* Force a TB lookup after an instruction that changes the CPU state. */
1491 static void gen_exit_tb(DisasContext *s)
1492 {
1493 update_cc_op(s);
1494 tcg_gen_movi_i32(QREG_PC, s->pc);
1495 s->base.is_jmp = DISAS_EXIT;
1496 }
1497
1498 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1499 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1500 op_sign ? EA_LOADS : EA_LOADU, IS_USER(s)); \
1501 if (IS_NULL_QREG(result)) { \
1502 gen_addr_fault(s); \
1503 return; \
1504 } \
1505 } while (0)
1506
1507 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1508 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, \
1509 EA_STORE, IS_USER(s)); \
1510 if (IS_NULL_QREG(ea_result)) { \
1511 gen_addr_fault(s); \
1512 return; \
1513 } \
1514 } while (0)
1515
1516 static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
1517 {
1518 #ifndef CONFIG_USER_ONLY
1519 return (s->base.pc_first & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)
1520 || (s->base.pc_next & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
1521 #else
1522 return true;
1523 #endif
1524 }
1525
1526 /* Generate a jump to an immediate address. */
1527 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
1528 {
1529 if (unlikely(is_singlestepping(s))) {
1530 update_cc_op(s);
1531 tcg_gen_movi_i32(QREG_PC, dest);
1532 gen_singlestep_exception(s);
1533 } else if (use_goto_tb(s, dest)) {
1534 tcg_gen_goto_tb(n);
1535 tcg_gen_movi_i32(QREG_PC, dest);
1536 tcg_gen_exit_tb(s->base.tb, n);
1537 } else {
1538 gen_jmp_im(s, dest);
1539 tcg_gen_exit_tb(NULL, 0);
1540 }
1541 s->base.is_jmp = DISAS_NORETURN;
1542 }
1543
1544 DISAS_INSN(scc)
1545 {
1546 DisasCompare c;
1547 int cond;
1548 TCGv tmp;
1549
1550 cond = (insn >> 8) & 0xf;
1551 gen_cc_cond(&c, s, cond);
1552
1553 tmp = tcg_temp_new();
1554 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
1555 free_cond(&c);
1556
1557 tcg_gen_neg_i32(tmp, tmp);
1558 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
1559 tcg_temp_free(tmp);
1560 }
1561
1562 DISAS_INSN(dbcc)
1563 {
1564 TCGLabel *l1;
1565 TCGv reg;
1566 TCGv tmp;
1567 int16_t offset;
1568 uint32_t base;
1569
1570 reg = DREG(insn, 0);
1571 base = s->pc;
1572 offset = (int16_t)read_im16(env, s);
1573 l1 = gen_new_label();
1574 gen_jmpcc(s, (insn >> 8) & 0xf, l1);
1575
1576 tmp = tcg_temp_new();
1577 tcg_gen_ext16s_i32(tmp, reg);
1578 tcg_gen_addi_i32(tmp, tmp, -1);
1579 gen_partset_reg(OS_WORD, reg, tmp);
1580 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1);
1581 gen_jmp_tb(s, 1, base + offset);
1582 gen_set_label(l1);
1583 gen_jmp_tb(s, 0, s->pc);
1584 }
1585
1586 DISAS_INSN(undef_mac)
1587 {
1588 gen_exception(s, s->base.pc_next, EXCP_LINEA);
1589 }
1590
1591 DISAS_INSN(undef_fpu)
1592 {
1593 gen_exception(s, s->base.pc_next, EXCP_LINEF);
1594 }
1595
1596 DISAS_INSN(undef)
1597 {
1598 /*
1599 * ??? This is both instructions that are as yet unimplemented
1600 * for the 680x0 series, as well as those that are implemented
1601 * but actually illegal for CPU32 or pre-68020.
1602 */
1603 qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n",
1604 insn, s->base.pc_next);
1605 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
1606 }
1607
1608 DISAS_INSN(mulw)
1609 {
1610 TCGv reg;
1611 TCGv tmp;
1612 TCGv src;
1613 int sign;
1614
1615 sign = (insn & 0x100) != 0;
1616 reg = DREG(insn, 9);
1617 tmp = tcg_temp_new();
1618 if (sign)
1619 tcg_gen_ext16s_i32(tmp, reg);
1620 else
1621 tcg_gen_ext16u_i32(tmp, reg);
1622 SRC_EA(env, src, OS_WORD, sign, NULL);
1623 tcg_gen_mul_i32(tmp, tmp, src);
1624 tcg_gen_mov_i32(reg, tmp);
1625 gen_logic_cc(s, tmp, OS_LONG);
1626 tcg_temp_free(tmp);
1627 }
1628
1629 DISAS_INSN(divw)
1630 {
1631 int sign;
1632 TCGv src;
1633 TCGv destr;
1634
1635 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1636
1637 sign = (insn & 0x100) != 0;
1638
1639 /* dest.l / src.w */
1640
1641 SRC_EA(env, src, OS_WORD, sign, NULL);
1642 destr = tcg_const_i32(REG(insn, 9));
1643 if (sign) {
1644 gen_helper_divsw(cpu_env, destr, src);
1645 } else {
1646 gen_helper_divuw(cpu_env, destr, src);
1647 }
1648 tcg_temp_free(destr);
1649
1650 set_cc_op(s, CC_OP_FLAGS);
1651 }
1652
1653 DISAS_INSN(divl)
1654 {
1655 TCGv num, reg, den;
1656 int sign;
1657 uint16_t ext;
1658
1659 ext = read_im16(env, s);
1660
1661 sign = (ext & 0x0800) != 0;
1662
1663 if (ext & 0x400) {
1664 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
1665 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
1666 return;
1667 }
1668
1669 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1670
1671 SRC_EA(env, den, OS_LONG, 0, NULL);
1672 num = tcg_const_i32(REG(ext, 12));
1673 reg = tcg_const_i32(REG(ext, 0));
1674 if (sign) {
1675 gen_helper_divsll(cpu_env, num, reg, den);
1676 } else {
1677 gen_helper_divull(cpu_env, num, reg, den);
1678 }
1679 tcg_temp_free(reg);
1680 tcg_temp_free(num);
1681 set_cc_op(s, CC_OP_FLAGS);
1682 return;
1683 }
1684
1685 /* divX.l <EA>, Dq 32/32 -> 32q */
1686 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1687
1688 SRC_EA(env, den, OS_LONG, 0, NULL);
1689 num = tcg_const_i32(REG(ext, 12));
1690 reg = tcg_const_i32(REG(ext, 0));
1691 if (sign) {
1692 gen_helper_divsl(cpu_env, num, reg, den);
1693 } else {
1694 gen_helper_divul(cpu_env, num, reg, den);
1695 }
1696 tcg_temp_free(reg);
1697 tcg_temp_free(num);
1698
1699 set_cc_op(s, CC_OP_FLAGS);
1700 }
1701
1702 static void bcd_add(TCGv dest, TCGv src)
1703 {
1704 TCGv t0, t1;
1705
1706 /*
1707 * dest10 = dest10 + src10 + X
1708 *
1709 * t1 = src
1710 * t2 = t1 + 0x066
1711 * t3 = t2 + dest + X
1712 * t4 = t2 ^ dest
1713 * t5 = t3 ^ t4
1714 * t6 = ~t5 & 0x110
1715 * t7 = (t6 >> 2) | (t6 >> 3)
1716 * return t3 - t7
1717 */
1718
1719 /*
1720 * t1 = (src + 0x066) + dest + X
1721 * = result with some possible exceeding 0x6
1722 */
1723
1724 t0 = tcg_const_i32(0x066);
1725 tcg_gen_add_i32(t0, t0, src);
1726
1727 t1 = tcg_temp_new();
1728 tcg_gen_add_i32(t1, t0, dest);
1729 tcg_gen_add_i32(t1, t1, QREG_CC_X);
1730
1731 /* we will remove exceeding 0x6 where there is no carry */
1732
1733 /*
1734 * t0 = (src + 0x0066) ^ dest
1735 * = t1 without carries
1736 */
1737
1738 tcg_gen_xor_i32(t0, t0, dest);
1739
1740 /*
1741 * extract the carries
1742 * t0 = t0 ^ t1
1743 * = only the carries
1744 */
1745
1746 tcg_gen_xor_i32(t0, t0, t1);
1747
1748 /*
1749 * generate 0x1 where there is no carry
1750 * and for each 0x10, generate a 0x6
1751 */
1752
1753 tcg_gen_shri_i32(t0, t0, 3);
1754 tcg_gen_not_i32(t0, t0);
1755 tcg_gen_andi_i32(t0, t0, 0x22);
1756 tcg_gen_add_i32(dest, t0, t0);
1757 tcg_gen_add_i32(dest, dest, t0);
1758 tcg_temp_free(t0);
1759
1760 /*
1761 * remove the exceeding 0x6
1762 * for digits that have not generated a carry
1763 */
1764
1765 tcg_gen_sub_i32(dest, t1, dest);
1766 tcg_temp_free(t1);
1767 }
1768
1769 static void bcd_sub(TCGv dest, TCGv src)
1770 {
1771 TCGv t0, t1, t2;
1772
1773 /*
1774 * dest10 = dest10 - src10 - X
1775 * = bcd_add(dest + 1 - X, 0x199 - src)
1776 */
1777
1778 /* t0 = 0x066 + (0x199 - src) */
1779
1780 t0 = tcg_temp_new();
1781 tcg_gen_subfi_i32(t0, 0x1ff, src);
1782
1783 /* t1 = t0 + dest + 1 - X*/
1784
1785 t1 = tcg_temp_new();
1786 tcg_gen_add_i32(t1, t0, dest);
1787 tcg_gen_addi_i32(t1, t1, 1);
1788 tcg_gen_sub_i32(t1, t1, QREG_CC_X);
1789
1790 /* t2 = t0 ^ dest */
1791
1792 t2 = tcg_temp_new();
1793 tcg_gen_xor_i32(t2, t0, dest);
1794
1795 /* t0 = t1 ^ t2 */
1796
1797 tcg_gen_xor_i32(t0, t1, t2);
1798
1799 /*
1800 * t2 = ~t0 & 0x110
1801 * t0 = (t2 >> 2) | (t2 >> 3)
1802 *
1803 * to fit on 8bit operands, changed in:
1804 *
1805 * t2 = ~(t0 >> 3) & 0x22
1806 * t0 = t2 + t2
1807 * t0 = t0 + t2
1808 */
1809
1810 tcg_gen_shri_i32(t2, t0, 3);
1811 tcg_gen_not_i32(t2, t2);
1812 tcg_gen_andi_i32(t2, t2, 0x22);
1813 tcg_gen_add_i32(t0, t2, t2);
1814 tcg_gen_add_i32(t0, t0, t2);
1815 tcg_temp_free(t2);
1816
1817 /* return t1 - t0 */
1818
1819 tcg_gen_sub_i32(dest, t1, t0);
1820 tcg_temp_free(t0);
1821 tcg_temp_free(t1);
1822 }
1823
1824 static void bcd_flags(TCGv val)
1825 {
1826 tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff);
1827 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C);
1828
1829 tcg_gen_extract_i32(QREG_CC_C, val, 8, 1);
1830
1831 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
1832 }
1833
1834 DISAS_INSN(abcd_reg)
1835 {
1836 TCGv src;
1837 TCGv dest;
1838
1839 gen_flush_flags(s); /* !Z is sticky */
1840
1841 src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
1842 dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
1843 bcd_add(dest, src);
1844 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1845
1846 bcd_flags(dest);
1847 }
1848
1849 DISAS_INSN(abcd_mem)
1850 {
1851 TCGv src, dest, addr;
1852
1853 gen_flush_flags(s); /* !Z is sticky */
1854
1855 /* Indirect pre-decrement load (mode 4) */
1856
1857 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1858 NULL_QREG, NULL, EA_LOADU, IS_USER(s));
1859 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1860 NULL_QREG, &addr, EA_LOADU, IS_USER(s));
1861
1862 bcd_add(dest, src);
1863
1864 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr,
1865 EA_STORE, IS_USER(s));
1866
1867 bcd_flags(dest);
1868 }
1869
1870 DISAS_INSN(sbcd_reg)
1871 {
1872 TCGv src, dest;
1873
1874 gen_flush_flags(s); /* !Z is sticky */
1875
1876 src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
1877 dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
1878
1879 bcd_sub(dest, src);
1880
1881 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1882
1883 bcd_flags(dest);
1884 }
1885
1886 DISAS_INSN(sbcd_mem)
1887 {
1888 TCGv src, dest, addr;
1889
1890 gen_flush_flags(s); /* !Z is sticky */
1891
1892 /* Indirect pre-decrement load (mode 4) */
1893
1894 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1895 NULL_QREG, NULL, EA_LOADU, IS_USER(s));
1896 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1897 NULL_QREG, &addr, EA_LOADU, IS_USER(s));
1898
1899 bcd_sub(dest, src);
1900
1901 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr,
1902 EA_STORE, IS_USER(s));
1903
1904 bcd_flags(dest);
1905 }
1906
1907 DISAS_INSN(nbcd)
1908 {
1909 TCGv src, dest;
1910 TCGv addr;
1911
1912 gen_flush_flags(s); /* !Z is sticky */
1913
1914 SRC_EA(env, src, OS_BYTE, 0, &addr);
1915
1916 dest = tcg_const_i32(0);
1917 bcd_sub(dest, src);
1918
1919 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1920
1921 bcd_flags(dest);
1922
1923 tcg_temp_free(dest);
1924 }
1925
1926 DISAS_INSN(addsub)
1927 {
1928 TCGv reg;
1929 TCGv dest;
1930 TCGv src;
1931 TCGv tmp;
1932 TCGv addr;
1933 int add;
1934 int opsize;
1935
1936 add = (insn & 0x4000) != 0;
1937 opsize = insn_opsize(insn);
1938 reg = gen_extend(s, DREG(insn, 9), opsize, 1);
1939 dest = tcg_temp_new();
1940 if (insn & 0x100) {
1941 SRC_EA(env, tmp, opsize, 1, &addr);
1942 src = reg;
1943 } else {
1944 tmp = reg;
1945 SRC_EA(env, src, opsize, 1, NULL);
1946 }
1947 if (add) {
1948 tcg_gen_add_i32(dest, tmp, src);
1949 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src);
1950 set_cc_op(s, CC_OP_ADDB + opsize);
1951 } else {
1952 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src);
1953 tcg_gen_sub_i32(dest, tmp, src);
1954 set_cc_op(s, CC_OP_SUBB + opsize);
1955 }
1956 gen_update_cc_add(dest, src, opsize);
1957 if (insn & 0x100) {
1958 DEST_EA(env, insn, opsize, dest, &addr);
1959 } else {
1960 gen_partset_reg(opsize, DREG(insn, 9), dest);
1961 }
1962 tcg_temp_free(dest);
1963 }
1964
1965 /* Reverse the order of the bits in REG. */
1966 DISAS_INSN(bitrev)
1967 {
1968 TCGv reg;
1969 reg = DREG(insn, 0);
1970 gen_helper_bitrev(reg, reg);
1971 }
1972
1973 DISAS_INSN(bitop_reg)
1974 {
1975 int opsize;
1976 int op;
1977 TCGv src1;
1978 TCGv src2;
1979 TCGv tmp;
1980 TCGv addr;
1981 TCGv dest;
1982
1983 if ((insn & 0x38) != 0)
1984 opsize = OS_BYTE;
1985 else
1986 opsize = OS_LONG;
1987 op = (insn >> 6) & 3;
1988 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1989
1990 gen_flush_flags(s);
1991 src2 = tcg_temp_new();
1992 if (opsize == OS_BYTE)
1993 tcg_gen_andi_i32(src2, DREG(insn, 9), 7);
1994 else
1995 tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
1996
1997 tmp = tcg_const_i32(1);
1998 tcg_gen_shl_i32(tmp, tmp, src2);
1999 tcg_temp_free(src2);
2000
2001 tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
2002
2003 dest = tcg_temp_new();
2004 switch (op) {
2005 case 1: /* bchg */
2006 tcg_gen_xor_i32(dest, src1, tmp);
2007 break;
2008 case 2: /* bclr */
2009 tcg_gen_andc_i32(dest, src1, tmp);
2010 break;
2011 case 3: /* bset */
2012 tcg_gen_or_i32(dest, src1, tmp);
2013 break;
2014 default: /* btst */
2015 break;
2016 }
2017 tcg_temp_free(tmp);
2018 if (op) {
2019 DEST_EA(env, insn, opsize, dest, &addr);
2020 }
2021 tcg_temp_free(dest);
2022 }
2023
2024 DISAS_INSN(sats)
2025 {
2026 TCGv reg;
2027 reg = DREG(insn, 0);
2028 gen_flush_flags(s);
2029 gen_helper_sats(reg, reg, QREG_CC_V);
2030 gen_logic_cc(s, reg, OS_LONG);
2031 }
2032
2033 static void gen_push(DisasContext *s, TCGv val)
2034 {
2035 TCGv tmp;
2036
2037 tmp = tcg_temp_new();
2038 tcg_gen_subi_i32(tmp, QREG_SP, 4);
2039 gen_store(s, OS_LONG, tmp, val, IS_USER(s));
2040 tcg_gen_mov_i32(QREG_SP, tmp);
2041 tcg_temp_free(tmp);
2042 }
2043
2044 static TCGv mreg(int reg)
2045 {
2046 if (reg < 8) {
2047 /* Dx */
2048 return cpu_dregs[reg];
2049 }
2050 /* Ax */
2051 return cpu_aregs[reg & 7];
2052 }
2053
2054 DISAS_INSN(movem)
2055 {
2056 TCGv addr, incr, tmp, r[16];
2057 int is_load = (insn & 0x0400) != 0;
2058 int opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD;
2059 uint16_t mask = read_im16(env, s);
2060 int mode = extract32(insn, 3, 3);
2061 int reg0 = REG(insn, 0);
2062 int i;
2063
2064 tmp = cpu_aregs[reg0];
2065
2066 switch (mode) {
2067 case 0: /* data register direct */
2068 case 1: /* addr register direct */
2069 do_addr_fault:
2070 gen_addr_fault(s);
2071 return;
2072
2073 case 2: /* indirect */
2074 break;
2075
2076 case 3: /* indirect post-increment */
2077 if (!is_load) {
2078 /* post-increment is not allowed */
2079 goto do_addr_fault;
2080 }
2081 break;
2082
2083 case 4: /* indirect pre-decrement */
2084 if (is_load) {
2085 /* pre-decrement is not allowed */
2086 goto do_addr_fault;
2087 }
2088 /*
2089 * We want a bare copy of the address reg, without any pre-decrement
2090 * adjustment, as gen_lea would provide.
2091 */
2092 break;
2093
2094 default:
2095 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
2096 if (IS_NULL_QREG(tmp)) {
2097 goto do_addr_fault;
2098 }
2099 break;
2100 }
2101
2102 addr = tcg_temp_new();
2103 tcg_gen_mov_i32(addr, tmp);
2104 incr = tcg_const_i32(opsize_bytes(opsize));
2105
2106 if (is_load) {
2107 /* memory to register */
2108 for (i = 0; i < 16; i++) {
2109 if (mask & (1 << i)) {
2110 r[i] = gen_load(s, opsize, addr, 1, IS_USER(s));
2111 tcg_gen_add_i32(addr, addr, incr);
2112 }
2113 }
2114 for (i = 0; i < 16; i++) {
2115 if (mask & (1 << i)) {
2116 tcg_gen_mov_i32(mreg(i), r[i]);
2117 tcg_temp_free(r[i]);
2118 }
2119 }
2120 if (mode == 3) {
2121 /* post-increment: movem (An)+,X */
2122 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2123 }
2124 } else {
2125 /* register to memory */
2126 if (mode == 4) {
2127 /* pre-decrement: movem X,-(An) */
2128 for (i = 15; i >= 0; i--) {
2129 if ((mask << i) & 0x8000) {
2130 tcg_gen_sub_i32(addr, addr, incr);
2131 if (reg0 + 8 == i &&
2132 m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) {
2133 /*
2134 * M68020+: if the addressing register is the
2135 * register moved to memory, the value written
2136 * is the initial value decremented by the size of
2137 * the operation, regardless of how many actual
2138 * stores have been performed until this point.
2139 * M68000/M68010: the value is the initial value.
2140 */
2141 tmp = tcg_temp_new();
2142 tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr);
2143 gen_store(s, opsize, addr, tmp, IS_USER(s));
2144 tcg_temp_free(tmp);
2145 } else {
2146 gen_store(s, opsize, addr, mreg(i), IS_USER(s));
2147 }
2148 }
2149 }
2150 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2151 } else {
2152 for (i = 0; i < 16; i++) {
2153 if (mask & (1 << i)) {
2154 gen_store(s, opsize, addr, mreg(i), IS_USER(s));
2155 tcg_gen_add_i32(addr, addr, incr);
2156 }
2157 }
2158 }
2159 }
2160
2161 tcg_temp_free(incr);
2162 tcg_temp_free(addr);
2163 }
2164
2165 DISAS_INSN(movep)
2166 {
2167 uint8_t i;
2168 int16_t displ;
2169 TCGv reg;
2170 TCGv addr;
2171 TCGv abuf;
2172 TCGv dbuf;
2173
2174 displ = read_im16(env, s);
2175
2176 addr = AREG(insn, 0);
2177 reg = DREG(insn, 9);
2178
2179 abuf = tcg_temp_new();
2180 tcg_gen_addi_i32(abuf, addr, displ);
2181 dbuf = tcg_temp_new();
2182
2183 if (insn & 0x40) {
2184 i = 4;
2185 } else {
2186 i = 2;
2187 }
2188
2189 if (insn & 0x80) {
2190 for ( ; i > 0 ; i--) {
2191 tcg_gen_shri_i32(dbuf, reg, (i - 1) * 8);
2192 tcg_gen_qemu_st8(dbuf, abuf, IS_USER(s));
2193 if (i > 1) {
2194 tcg_gen_addi_i32(abuf, abuf, 2);
2195 }
2196 }
2197 } else {
2198 for ( ; i > 0 ; i--) {
2199 tcg_gen_qemu_ld8u(dbuf, abuf, IS_USER(s));
2200 tcg_gen_deposit_i32(reg, reg, dbuf, (i - 1) * 8, 8);
2201 if (i > 1) {
2202 tcg_gen_addi_i32(abuf, abuf, 2);
2203 }
2204 }
2205 }
2206 tcg_temp_free(abuf);
2207 tcg_temp_free(dbuf);
2208 }
2209
2210 DISAS_INSN(bitop_im)
2211 {
2212 int opsize;
2213 int op;
2214 TCGv src1;
2215 uint32_t mask;
2216 int bitnum;
2217 TCGv tmp;
2218 TCGv addr;
2219
2220 if ((insn & 0x38) != 0)
2221 opsize = OS_BYTE;
2222 else
2223 opsize = OS_LONG;
2224 op = (insn >> 6) & 3;
2225
2226 bitnum = read_im16(env, s);
2227 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2228 if (bitnum & 0xfe00) {
2229 disas_undef(env, s, insn);
2230 return;
2231 }
2232 } else {
2233 if (bitnum & 0xff00) {
2234 disas_undef(env, s, insn);
2235 return;
2236 }
2237 }
2238
2239 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
2240
2241 gen_flush_flags(s);
2242 if (opsize == OS_BYTE)
2243 bitnum &= 7;
2244 else
2245 bitnum &= 31;
2246 mask = 1 << bitnum;
2247
2248 tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
2249
2250 if (op) {
2251 tmp = tcg_temp_new();
2252 switch (op) {
2253 case 1: /* bchg */
2254 tcg_gen_xori_i32(tmp, src1, mask);
2255 break;
2256 case 2: /* bclr */
2257 tcg_gen_andi_i32(tmp, src1, ~mask);
2258 break;
2259 case 3: /* bset */
2260 tcg_gen_ori_i32(tmp, src1, mask);
2261 break;
2262 default: /* btst */
2263 break;
2264 }
2265 DEST_EA(env, insn, opsize, tmp, &addr);
2266 tcg_temp_free(tmp);
2267 }
2268 }
2269
2270 static TCGv gen_get_ccr(DisasContext *s)
2271 {
2272 TCGv dest;
2273
2274 update_cc_op(s);
2275 dest = tcg_temp_new();
2276 gen_helper_get_ccr(dest, cpu_env);
2277 return dest;
2278 }
2279
2280 static TCGv gen_get_sr(DisasContext *s)
2281 {
2282 TCGv ccr;
2283 TCGv sr;
2284
2285 ccr = gen_get_ccr(s);
2286 sr = tcg_temp_new();
2287 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
2288 tcg_gen_or_i32(sr, sr, ccr);
2289 tcg_temp_free(ccr);
2290 return sr;
2291 }
2292
2293 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
2294 {
2295 if (ccr_only) {
2296 tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0);
2297 tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0);
2298 tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1);
2299 tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
2300 tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
2301 } else {
2302 TCGv sr = tcg_const_i32(val);
2303 gen_helper_set_sr(cpu_env, sr);
2304 tcg_temp_free(sr);
2305 }
2306 set_cc_op(s, CC_OP_FLAGS);
2307 }
2308
2309 static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
2310 {
2311 if (ccr_only) {
2312 gen_helper_set_ccr(cpu_env, val);
2313 } else {
2314 gen_helper_set_sr(cpu_env, val);
2315 }
2316 set_cc_op(s, CC_OP_FLAGS);
2317 }
2318
2319 static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
2320 bool ccr_only)
2321 {
2322 if ((insn & 0x3f) == 0x3c) {
2323 uint16_t val;
2324 val = read_im16(env, s);
2325 gen_set_sr_im(s, val, ccr_only);
2326 } else {
2327 TCGv src;
2328 SRC_EA(env, src, OS_WORD, 0, NULL);
2329 gen_set_sr(s, src, ccr_only);
2330 }
2331 }
2332
2333 DISAS_INSN(arith_im)
2334 {
2335 int op;
2336 TCGv im;
2337 TCGv src1;
2338 TCGv dest;
2339 TCGv addr;
2340 int opsize;
2341 bool with_SR = ((insn & 0x3f) == 0x3c);
2342
2343 op = (insn >> 9) & 7;
2344 opsize = insn_opsize(insn);
2345 switch (opsize) {
2346 case OS_BYTE:
2347 im = tcg_const_i32((int8_t)read_im8(env, s));
2348 break;
2349 case OS_WORD:
2350 im = tcg_const_i32((int16_t)read_im16(env, s));
2351 break;
2352 case OS_LONG:
2353 im = tcg_const_i32(read_im32(env, s));
2354 break;
2355 default:
2356 g_assert_not_reached();
2357 }
2358
2359 if (with_SR) {
2360 /* SR/CCR can only be used with andi/eori/ori */
2361 if (op == 2 || op == 3 || op == 6) {
2362 disas_undef(env, s, insn);
2363 return;
2364 }
2365 switch (opsize) {
2366 case OS_BYTE:
2367 src1 = gen_get_ccr(s);
2368 break;
2369 case OS_WORD:
2370 if (IS_USER(s)) {
2371 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
2372 return;
2373 }
2374 src1 = gen_get_sr(s);
2375 break;
2376 default:
2377 /* OS_LONG; others already g_assert_not_reached. */
2378 disas_undef(env, s, insn);
2379 return;
2380 }
2381 } else {
2382 SRC_EA(env, src1, opsize, 1, (op == 6) ? NULL : &addr);
2383 }
2384 dest = tcg_temp_new();
2385 switch (op) {
2386 case 0: /* ori */
2387 tcg_gen_or_i32(dest, src1, im);
2388 if (with_SR) {
2389 gen_set_sr(s, dest, opsize == OS_BYTE);
2390 } else {
2391 DEST_EA(env, insn, opsize, dest, &addr);
2392 gen_logic_cc(s, dest, opsize);
2393 }
2394 break;
2395 case 1: /* andi */
2396 tcg_gen_and_i32(dest, src1, im);
2397 if (with_SR) {
2398 gen_set_sr(s, dest, opsize == OS_BYTE);
2399 } else {
2400 DEST_EA(env, insn, opsize, dest, &addr);
2401 gen_logic_cc(s, dest, opsize);
2402 }
2403 break;
2404 case 2: /* subi */
2405 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im);
2406 tcg_gen_sub_i32(dest, src1, im);
2407 gen_update_cc_add(dest, im, opsize);
2408 set_cc_op(s, CC_OP_SUBB + opsize);
2409 DEST_EA(env, insn, opsize, dest, &addr);
2410 break;
2411 case 3: /* addi */
2412 tcg_gen_add_i32(dest, src1, im);
2413 gen_update_cc_add(dest, im, opsize);
2414 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im);
2415 set_cc_op(s, CC_OP_ADDB + opsize);
2416 DEST_EA(env, insn, opsize, dest, &addr);
2417 break;
2418 case 5: /* eori */
2419 tcg_gen_xor_i32(dest, src1, im);
2420 if (with_SR) {
2421 gen_set_sr(s, dest, opsize == OS_BYTE);
2422 } else {
2423 DEST_EA(env, insn, opsize, dest, &addr);
2424 gen_logic_cc(s, dest, opsize);
2425 }
2426 break;
2427 case 6: /* cmpi */
2428 gen_update_cc_cmp(s, src1, im, opsize);
2429 break;
2430 default:
2431 abort();
2432 }
2433 tcg_temp_free(im);
2434 tcg_temp_free(dest);
2435 }
2436
2437 DISAS_INSN(cas)
2438 {
2439 int opsize;
2440 TCGv addr;
2441 uint16_t ext;
2442 TCGv load;
2443 TCGv cmp;
2444 MemOp opc;
2445
2446 switch ((insn >> 9) & 3) {
2447 case 1:
2448 opsize = OS_BYTE;
2449 opc = MO_SB;
2450 break;
2451 case 2:
2452 opsize = OS_WORD;
2453 opc = MO_TESW;
2454 break;
2455 case 3:
2456 opsize = OS_LONG;
2457 opc = MO_TESL;
2458 break;
2459 default:
2460 g_assert_not_reached();
2461 }
2462
2463 ext = read_im16(env, s);
2464
2465 /* cas Dc,Du,<EA> */
2466
2467 addr = gen_lea(env, s, insn, opsize);
2468 if (IS_NULL_QREG(addr)) {
2469 gen_addr_fault(s);
2470 return;
2471 }
2472
2473 cmp = gen_extend(s, DREG(ext, 0), opsize, 1);
2474
2475 /*
2476 * if <EA> == Dc then
2477 * <EA> = Du
2478 * Dc = <EA> (because <EA> == Dc)
2479 * else
2480 * Dc = <EA>
2481 */
2482
2483 load = tcg_temp_new();
2484 tcg_gen_atomic_cmpxchg_i32(load, addr, cmp, DREG(ext, 6),
2485 IS_USER(s), opc);
2486 /* update flags before setting cmp to load */
2487 gen_update_cc_cmp(s, load, cmp, opsize);
2488 gen_partset_reg(opsize, DREG(ext, 0), load);
2489
2490 tcg_temp_free(load);
2491
2492 switch (extract32(insn, 3, 3)) {
2493 case 3: /* Indirect postincrement. */
2494 tcg_gen_addi_i32(AREG(insn, 0), addr, opsize_bytes(opsize));
2495 break;
2496 case 4: /* Indirect predecrememnt. */
2497 tcg_gen_mov_i32(AREG(insn, 0), addr);
2498 break;
2499 }
2500 }
2501
2502 DISAS_INSN(cas2w)
2503 {
2504 uint16_t ext1, ext2;
2505 TCGv addr1, addr2;
2506 TCGv regs;
2507
2508 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2509
2510 ext1 = read_im16(env, s);
2511
2512 if (ext1 & 0x8000) {
2513 /* Address Register */
2514 addr1 = AREG(ext1, 12);
2515 } else {
2516 /* Data Register */
2517 addr1 = DREG(ext1, 12);
2518 }
2519
2520 ext2 = read_im16(env, s);
2521 if (ext2 & 0x8000) {
2522 /* Address Register */
2523 addr2 = AREG(ext2, 12);
2524 } else {
2525 /* Data Register */
2526 addr2 = DREG(ext2, 12);
2527 }
2528
2529 /*
2530 * if (R1) == Dc1 && (R2) == Dc2 then
2531 * (R1) = Du1
2532 * (R2) = Du2
2533 * else
2534 * Dc1 = (R1)
2535 * Dc2 = (R2)
2536 */
2537
2538 regs = tcg_const_i32(REG(ext2, 6) |
2539 (REG(ext1, 6) << 3) |
2540 (REG(ext2, 0) << 6) |
2541 (REG(ext1, 0) << 9));
2542 if (tb_cflags(s->base.tb) & CF_PARALLEL) {
2543 gen_helper_exit_atomic(cpu_env);
2544 } else {
2545 gen_helper_cas2w(cpu_env, regs, addr1, addr2);
2546 }
2547 tcg_temp_free(regs);
2548
2549 /* Note that cas2w also assigned to env->cc_op. */
2550 s->cc_op = CC_OP_CMPW;
2551 s->cc_op_synced = 1;
2552 }
2553
2554 DISAS_INSN(cas2l)
2555 {
2556 uint16_t ext1, ext2;
2557 TCGv addr1, addr2, regs;
2558
2559 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2560
2561 ext1 = read_im16(env, s);
2562
2563 if (ext1 & 0x8000) {
2564 /* Address Register */
2565 addr1 = AREG(ext1, 12);
2566 } else {
2567 /* Data Register */
2568 addr1 = DREG(ext1, 12);
2569 }
2570
2571 ext2 = read_im16(env, s);
2572 if (ext2 & 0x8000) {
2573 /* Address Register */
2574 addr2 = AREG(ext2, 12);
2575 } else {
2576 /* Data Register */
2577 addr2 = DREG(ext2, 12);
2578 }
2579
2580 /*
2581 * if (R1) == Dc1 && (R2) == Dc2 then
2582 * (R1) = Du1
2583 * (R2) = Du2
2584 * else
2585 * Dc1 = (R1)
2586 * Dc2 = (R2)
2587 */
2588
2589 regs = tcg_const_i32(REG(ext2, 6) |
2590 (REG(ext1, 6) << 3) |
2591 (REG(ext2, 0) << 6) |
2592 (REG(ext1, 0) << 9));
2593 if (tb_cflags(s->base.tb) & CF_PARALLEL) {
2594 gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2);
2595 } else {
2596 gen_helper_cas2l(cpu_env, regs, addr1, addr2);
2597 }
2598 tcg_temp_free(regs);
2599
2600 /* Note that cas2l also assigned to env->cc_op. */
2601 s->cc_op = CC_OP_CMPL;
2602 s->cc_op_synced = 1;
2603 }
2604
2605 DISAS_INSN(byterev)
2606 {
2607 TCGv reg;
2608
2609 reg = DREG(insn, 0);
2610 tcg_gen_bswap32_i32(reg, reg);
2611 }
2612
2613 DISAS_INSN(move)
2614 {
2615 TCGv src;
2616 TCGv dest;
2617 int op;
2618 int opsize;
2619
2620 switch (insn >> 12) {
2621 case 1: /* move.b */
2622 opsize = OS_BYTE;
2623 break;
2624 case 2: /* move.l */
2625 opsize = OS_LONG;
2626 break;
2627 case 3: /* move.w */
2628 opsize = OS_WORD;
2629 break;
2630 default:
2631 abort();
2632 }
2633 SRC_EA(env, src, opsize, 1, NULL);
2634 op = (insn >> 6) & 7;
2635 if (op == 1) {
2636 /* movea */
2637 /* The value will already have been sign extended. */
2638 dest = AREG(insn, 9);
2639 tcg_gen_mov_i32(dest, src);
2640 } else {
2641 /* normal move */
2642 uint16_t dest_ea;
2643 dest_ea = ((insn >> 9) & 7) | (op << 3);
2644 DEST_EA(env, dest_ea, opsize, src, NULL);
2645 /* This will be correct because loads sign extend. */
2646 gen_logic_cc(s, src, opsize);
2647 }
2648 }
2649
2650 DISAS_INSN(negx)
2651 {
2652 TCGv z;
2653 TCGv src;
2654 TCGv addr;
2655 int opsize;
2656
2657 opsize = insn_opsize(insn);
2658 SRC_EA(env, src, opsize, 1, &addr);
2659
2660 gen_flush_flags(s); /* compute old Z */
2661
2662 /*
2663 * Perform subtract with borrow.
2664 * (X, N) = -(src + X);
2665 */
2666
2667 z = tcg_const_i32(0);
2668 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z);
2669 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X);
2670 tcg_temp_free(z);
2671 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
2672
2673 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
2674
2675 /*
2676 * Compute signed-overflow for negation. The normal formula for
2677 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2678 * this simplifies to res & src.
2679 */
2680
2681 tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src);
2682
2683 /* Copy the rest of the results into place. */
2684 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
2685 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
2686
2687 set_cc_op(s, CC_OP_FLAGS);
2688
2689 /* result is in QREG_CC_N */
2690
2691 DEST_EA(env, insn, opsize, QREG_CC_N, &addr);
2692 }
2693
2694 DISAS_INSN(lea)
2695 {
2696 TCGv reg;
2697 TCGv tmp;
2698
2699 reg = AREG(insn, 9);
2700 tmp = gen_lea(env, s, insn, OS_LONG);
2701 if (IS_NULL_QREG(tmp)) {
2702 gen_addr_fault(s);
2703 return;
2704 }
2705 tcg_gen_mov_i32(reg, tmp);
2706 }
2707
2708 DISAS_INSN(clr)
2709 {
2710 int opsize;
2711 TCGv zero;
2712
2713 zero = tcg_const_i32(0);
2714
2715 opsize = insn_opsize(insn);
2716 DEST_EA(env, insn, opsize, zero, NULL);
2717 gen_logic_cc(s, zero, opsize);
2718 tcg_temp_free(zero);
2719 }
2720
2721 DISAS_INSN(move_from_ccr)
2722 {
2723 TCGv ccr;
2724
2725 ccr = gen_get_ccr(s);
2726 DEST_EA(env, insn, OS_WORD, ccr, NULL);
2727 }
2728
2729 DISAS_INSN(neg)
2730 {
2731 TCGv src1;
2732 TCGv dest;
2733 TCGv addr;
2734 int opsize;
2735
2736 opsize = insn_opsize(insn);
2737 SRC_EA(env, src1, opsize, 1, &addr);
2738 dest = tcg_temp_new();
2739 tcg_gen_neg_i32(dest, src1);
2740 set_cc_op(s, CC_OP_SUBB + opsize);
2741 gen_update_cc_add(dest, src1, opsize);
2742 tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0);
2743 DEST_EA(env, insn, opsize, dest, &addr);
2744 tcg_temp_free(dest);
2745 }
2746
2747 DISAS_INSN(move_to_ccr)
2748 {
2749 gen_move_to_sr(env, s, insn, true);
2750 }
2751
2752 DISAS_INSN(not)
2753 {
2754 TCGv src1;
2755 TCGv dest;
2756 TCGv addr;
2757 int opsize;
2758
2759 opsize = insn_opsize(insn);
2760 SRC_EA(env, src1, opsize, 1, &addr);
2761 dest = tcg_temp_new();
2762 tcg_gen_not_i32(dest, src1);
2763 DEST_EA(env, insn, opsize, dest, &addr);
2764 gen_logic_cc(s, dest, opsize);
2765 }
2766
2767 DISAS_INSN(swap)
2768 {
2769 TCGv src1;
2770 TCGv src2;
2771 TCGv reg;
2772
2773 src1 = tcg_temp_new();
2774 src2 = tcg_temp_new();
2775 reg = DREG(insn, 0);
2776 tcg_gen_shli_i32(src1, reg, 16);
2777 tcg_gen_shri_i32(src2, reg, 16);
2778 tcg_gen_or_i32(reg, src1, src2);
2779 tcg_temp_free(src2);
2780 tcg_temp_free(src1);
2781 gen_logic_cc(s, reg, OS_LONG);
2782 }
2783
2784 DISAS_INSN(bkpt)
2785 {
2786 gen_exception(s, s->base.pc_next, EXCP_DEBUG);
2787 }
2788
2789 DISAS_INSN(pea)
2790 {
2791 TCGv tmp;
2792
2793 tmp = gen_lea(env, s, insn, OS_LONG);
2794 if (IS_NULL_QREG(tmp)) {
2795 gen_addr_fault(s);
2796 return;
2797 }
2798 gen_push(s, tmp);
2799 }
2800
2801 DISAS_INSN(ext)
2802 {
2803 int op;
2804 TCGv reg;
2805 TCGv tmp;
2806
2807 reg = DREG(insn, 0);
2808 op = (insn >> 6) & 7;
2809 tmp = tcg_temp_new();
2810 if (op == 3)
2811 tcg_gen_ext16s_i32(tmp, reg);
2812 else
2813 tcg_gen_ext8s_i32(tmp, reg);
2814 if (op == 2)
2815 gen_partset_reg(OS_WORD, reg, tmp);
2816 else
2817 tcg_gen_mov_i32(reg, tmp);
2818 gen_logic_cc(s, tmp, OS_LONG);
2819 tcg_temp_free(tmp);
2820 }
2821
2822 DISAS_INSN(tst)
2823 {
2824 int opsize;
2825 TCGv tmp;
2826
2827 opsize = insn_opsize(insn);
2828 SRC_EA(env, tmp, opsize, 1, NULL);
2829 gen_logic_cc(s, tmp, opsize);
2830 }
2831
2832 DISAS_INSN(pulse)
2833 {
2834 /* Implemented as a NOP. */
2835 }
2836
2837 DISAS_INSN(illegal)
2838 {
2839 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
2840 }
2841
2842 /* ??? This should be atomic. */
2843 DISAS_INSN(tas)
2844 {
2845 TCGv dest;
2846 TCGv src1;
2847 TCGv addr;
2848
2849 dest = tcg_temp_new();
2850 SRC_EA(env, src1, OS_BYTE, 1, &addr);
2851 gen_logic_cc(s, src1, OS_BYTE);
2852 tcg_gen_ori_i32(dest, src1, 0x80);
2853 DEST_EA(env, insn, OS_BYTE, dest, &addr);
2854 tcg_temp_free(dest);
2855 }
2856
2857 DISAS_INSN(mull)
2858 {
2859 uint16_t ext;
2860 TCGv src1;
2861 int sign;
2862
2863 ext = read_im16(env, s);
2864
2865 sign = ext & 0x800;
2866
2867 if (ext & 0x400) {
2868 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
2869 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
2870 return;
2871 }
2872
2873 SRC_EA(env, src1, OS_LONG, 0, NULL);
2874
2875 if (sign) {
2876 tcg_gen_muls2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2877 } else {
2878 tcg_gen_mulu2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2879 }
2880 /* if Dl == Dh, 68040 returns low word */
2881 tcg_gen_mov_i32(DREG(ext, 0), QREG_CC_N);
2882 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_Z);
2883 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N);
2884
2885 tcg_gen_movi_i32(QREG_CC_V, 0);
2886 tcg_gen_movi_i32(QREG_CC_C, 0);
2887
2888 set_cc_op(s, CC_OP_FLAGS);
2889 return;
2890 }
2891 SRC_EA(env, src1, OS_LONG, 0, NULL);
2892 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2893 tcg_gen_movi_i32(QREG_CC_C, 0);
2894 if (sign) {
2895 tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2896 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2897 tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31);
2898 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z);
2899 } else {
2900 tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2901 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2902 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C);
2903 }
2904 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
2905 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N);
2906
2907 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
2908
2909 set_cc_op(s, CC_OP_FLAGS);
2910 } else {
2911 /*
2912 * The upper 32 bits of the product are discarded, so
2913 * muls.l and mulu.l are functionally equivalent.
2914 */
2915 tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12));
2916 gen_logic_cc(s, DREG(ext, 12), OS_LONG);
2917 }
2918 }
2919
2920 static void gen_link(DisasContext *s, uint16_t insn, int32_t offset)
2921 {
2922 TCGv reg;
2923 TCGv tmp;
2924
2925 reg = AREG(insn, 0);
2926 tmp = tcg_temp_new();
2927 tcg_gen_subi_i32(tmp, QREG_SP, 4);
2928 gen_store(s, OS_LONG, tmp, reg, IS_USER(s));
2929 if ((insn & 7) != 7) {
2930 tcg_gen_mov_i32(reg, tmp);
2931 }
2932 tcg_gen_addi_i32(QREG_SP, tmp, offset);
2933 tcg_temp_free(tmp);
2934 }
2935
2936 DISAS_INSN(link)
2937 {
2938 int16_t offset;
2939
2940 offset = read_im16(env, s);
2941 gen_link(s, insn, offset);
2942 }
2943
2944 DISAS_INSN(linkl)
2945 {
2946 int32_t offset;
2947
2948 offset = read_im32(env, s);
2949 gen_link(s, insn, offset);
2950 }
2951
2952 DISAS_INSN(unlk)
2953 {
2954 TCGv src;
2955 TCGv reg;
2956 TCGv tmp;
2957
2958 src = tcg_temp_new();
2959 reg = AREG(insn, 0);
2960 tcg_gen_mov_i32(src, reg);
2961 tmp = gen_load(s, OS_LONG, src, 0, IS_USER(s));
2962 tcg_gen_mov_i32(reg, tmp);
2963 tcg_gen_addi_i32(QREG_SP, src, 4);
2964 tcg_temp_free(src);
2965 tcg_temp_free(tmp);
2966 }
2967
2968 #if defined(CONFIG_SOFTMMU)
2969 DISAS_INSN(reset)
2970 {
2971 if (IS_USER(s)) {
2972 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
2973 return;
2974 }
2975
2976 gen_helper_reset(cpu_env);
2977 }
2978 #endif
2979
2980 DISAS_INSN(nop)
2981 {
2982 }
2983
2984 DISAS_INSN(rtd)
2985 {
2986 TCGv tmp;
2987 int16_t offset = read_im16(env, s);
2988
2989 tmp = gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s));
2990 tcg_gen_addi_i32(QREG_SP, QREG_SP, offset + 4);
2991 gen_jmp(s, tmp);
2992 }
2993
2994 DISAS_INSN(rtr)
2995 {
2996 TCGv tmp;
2997 TCGv ccr;
2998 TCGv sp;
2999
3000 sp = tcg_temp_new();
3001 ccr = gen_load(s, OS_WORD, QREG_SP, 0, IS_USER(s));
3002 tcg_gen_addi_i32(sp, QREG_SP, 2);
3003 tmp = gen_load(s, OS_LONG, sp, 0, IS_USER(s));
3004 tcg_gen_addi_i32(QREG_SP, sp, 4);
3005 tcg_temp_free(sp);
3006
3007 gen_set_sr(s, ccr, true);
3008 tcg_temp_free(ccr);
3009
3010 gen_jmp(s, tmp);
3011 }
3012
3013 DISAS_INSN(rts)
3014 {
3015 TCGv tmp;
3016
3017 tmp = gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s));
3018 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
3019 gen_jmp(s, tmp);
3020 }
3021
3022 DISAS_INSN(jump)
3023 {
3024 TCGv tmp;
3025
3026 /*
3027 * Load the target address first to ensure correct exception
3028 * behavior.
3029 */
3030 tmp = gen_lea(env, s, insn, OS_LONG);
3031 if (IS_NULL_QREG(tmp)) {
3032 gen_addr_fault(s);
3033 return;
3034 }
3035 if ((insn & 0x40) == 0) {
3036 /* jsr */
3037 gen_push(s, tcg_const_i32(s->pc));
3038 }
3039 gen_jmp(s, tmp);
3040 }
3041
3042 DISAS_INSN(addsubq)
3043 {
3044 TCGv src;
3045 TCGv dest;
3046 TCGv val;
3047 int imm;
3048 TCGv addr;
3049 int opsize;
3050
3051 if ((insn & 070) == 010) {
3052 /* Operation on address register is always long. */
3053 opsize = OS_LONG;
3054 } else {
3055 opsize = insn_opsize(insn);
3056 }
3057 SRC_EA(env, src, opsize, 1, &addr);
3058 imm = (insn >> 9) & 7;
3059 if (imm == 0) {
3060 imm = 8;
3061 }
3062 val = tcg_const_i32(imm);
3063 dest = tcg_temp_new();
3064 tcg_gen_mov_i32(dest, src);
3065 if ((insn & 0x38) == 0x08) {
3066 /*
3067 * Don't update condition codes if the destination is an
3068 * address register.
3069 */
3070 if (insn & 0x0100) {
3071 tcg_gen_sub_i32(dest, dest, val);
3072 } else {
3073 tcg_gen_add_i32(dest, dest, val);
3074 }
3075 } else {
3076 if (insn & 0x0100) {
3077 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
3078 tcg_gen_sub_i32(dest, dest, val);
3079 set_cc_op(s, CC_OP_SUBB + opsize);
3080 } else {
3081 tcg_gen_add_i32(dest, dest, val);
3082 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
3083 set_cc_op(s, CC_OP_ADDB + opsize);
3084 }
3085 gen_update_cc_add(dest, val, opsize);
3086 }
3087 tcg_temp_free(val);
3088 DEST_EA(env, insn, opsize, dest, &addr);
3089 tcg_temp_free(dest);
3090 }
3091
3092 DISAS_INSN(tpf)
3093 {
3094 switch (insn & 7) {
3095 case 2: /* One extension word. */
3096 s->pc += 2;
3097 break;
3098 case 3: /* Two extension words. */
3099 s->pc += 4;
3100 break;
3101 case 4: /* No extension words. */
3102 break;
3103 default:
3104 disas_undef(env, s, insn);
3105 }
3106 }
3107
3108 DISAS_INSN(branch)
3109 {
3110 int32_t offset;
3111 uint32_t base;
3112 int op;
3113
3114 base = s->pc;
3115 op = (insn >> 8) & 0xf;
3116 offset = (int8_t)insn;
3117 if (offset == 0) {
3118 offset = (int16_t)read_im16(env, s);
3119 } else if (offset == -1) {
3120 offset = read_im32(env, s);
3121 }
3122 if (op == 1) {
3123 /* bsr */
3124 gen_push(s, tcg_const_i32(s->pc));
3125 }
3126 if (op > 1) {
3127 /* Bcc */
3128 TCGLabel *l1 = gen_new_label();
3129 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
3130 gen_jmp_tb(s, 1, base + offset);
3131 gen_set_label(l1);
3132 gen_jmp_tb(s, 0, s->pc);
3133 } else {
3134 /* Unconditional branch. */
3135 update_cc_op(s);
3136 gen_jmp_tb(s, 0, base + offset);
3137 }
3138 }
3139
3140 DISAS_INSN(moveq)
3141 {
3142 tcg_gen_movi_i32(DREG(insn, 9), (int8_t)insn);
3143 gen_logic_cc(s, DREG(insn, 9), OS_LONG);
3144 }
3145
3146 DISAS_INSN(mvzs)
3147 {
3148 int opsize;
3149 TCGv src;
3150 TCGv reg;
3151
3152 if (insn & 0x40)
3153 opsize = OS_WORD;
3154 else
3155 opsize = OS_BYTE;
3156 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
3157 reg = DREG(insn, 9);
3158 tcg_gen_mov_i32(reg, src);
3159 gen_logic_cc(s, src, opsize);
3160 }
3161
3162 DISAS_INSN(or)
3163 {
3164 TCGv reg;
3165 TCGv dest;
3166 TCGv src;
3167 TCGv addr;
3168 int opsize;
3169
3170 opsize = insn_opsize(insn);
3171 reg = gen_extend(s, DREG(insn, 9), opsize, 0);
3172 dest = tcg_temp_new();
3173 if (insn & 0x100) {
3174 SRC_EA(env, src, opsize, 0, &addr);
3175 tcg_gen_or_i32(dest, src, reg);
3176 DEST_EA(env, insn, opsize, dest, &addr);
3177 } else {
3178 SRC_EA(env, src, opsize, 0, NULL);
3179 tcg_gen_or_i32(dest, src, reg);
3180 gen_partset_reg(opsize, DREG(insn, 9), dest);
3181 }
3182 gen_logic_cc(s, dest, opsize);
3183 tcg_temp_free(dest);
3184 }
3185
3186 DISAS_INSN(suba)
3187 {
3188 TCGv src;
3189 TCGv reg;
3190
3191 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
3192 reg = AREG(insn, 9);
3193 tcg_gen_sub_i32(reg, reg, src);
3194 }
3195
3196 static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
3197 {
3198 TCGv tmp;
3199
3200 gen_flush_flags(s); /* compute old Z */
3201
3202 /*
3203 * Perform subtract with borrow.
3204 * (X, N) = dest - (src + X);
3205 */
3206
3207 tmp = tcg_const_i32(0);
3208 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp);
3209 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X);
3210 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3211 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
3212
3213 /* Compute signed-overflow for subtract. */
3214
3215 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
3216 tcg_gen_xor_i32(tmp, dest, src);
3217 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp);
3218 tcg_temp_free(tmp);
3219
3220 /* Copy the rest of the results into place. */
3221 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
3222 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
3223
3224 set_cc_op(s, CC_OP_FLAGS);
3225
3226 /* result is in QREG_CC_N */
3227 }
3228
3229 DISAS_INSN(subx_reg)
3230 {
3231 TCGv dest;
3232 TCGv src;
3233 int opsize;
3234
3235 opsize = insn_opsize(insn);
3236
3237 src = gen_extend(s, DREG(insn, 0), opsize, 1);
3238 dest = gen_extend(s, DREG(insn, 9), opsize, 1);
3239
3240 gen_subx(s, src, dest, opsize);
3241
3242 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3243 }
3244
3245 DISAS_INSN(subx_mem)
3246 {
3247 TCGv src;
3248 TCGv addr_src;
3249 TCGv dest;
3250 TCGv addr_dest;
3251 int opsize;
3252
3253 opsize = insn_opsize(insn);
3254
3255 addr_src = AREG(insn, 0);
3256 tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize));
3257 src = gen_load(s, opsize, addr_src, 1, IS_USER(s));
3258
3259 addr_dest = AREG(insn, 9);
3260 tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize));
3261 dest = gen_load(s, opsize, addr_dest, 1, IS_USER(s));
3262
3263 gen_subx(s, src, dest, opsize);
3264
3265 gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s));
3266
3267 tcg_temp_free(dest);
3268 tcg_temp_free(src);
3269 }
3270
3271 DISAS_INSN(mov3q)
3272 {
3273 TCGv src;
3274 int val;
3275
3276 val = (insn >> 9) & 7;
3277 if (val == 0)
3278 val = -1;
3279 src = tcg_const_i32(val);
3280 gen_logic_cc(s, src, OS_LONG);
3281 DEST_EA(env, insn, OS_LONG, src, NULL);
3282 tcg_temp_free(src);
3283 }
3284
3285 DISAS_INSN(cmp)
3286 {
3287 TCGv src;
3288 TCGv reg;
3289 int opsize;
3290
3291 opsize = insn_opsize(insn);
3292 SRC_EA(env, src, opsize, 1, NULL);
3293 reg = gen_extend(s, DREG(insn, 9), opsize, 1);
3294 gen_update_cc_cmp(s, reg, src, opsize);
3295 }
3296
3297 DISAS_INSN(cmpa)
3298 {
3299 int opsize;
3300 TCGv src;
3301 TCGv reg;
3302
3303 if (insn & 0x100) {
3304 opsize = OS_LONG;
3305 } else {
3306 opsize = OS_WORD;
3307 }
3308 SRC_EA(env, src, opsize, 1, NULL);
3309 reg = AREG(insn, 9);
3310 gen_update_cc_cmp(s, reg, src, OS_LONG);
3311 }
3312
3313 DISAS_INSN(cmpm)
3314 {
3315 int opsize = insn_opsize(insn);
3316 TCGv src, dst;
3317
3318 /* Post-increment load (mode 3) from Ay. */
3319 src = gen_ea_mode(env, s, 3, REG(insn, 0), opsize,
3320 NULL_QREG, NULL, EA_LOADS, IS_USER(s));
3321 /* Post-increment load (mode 3) from Ax. */
3322 dst = gen_ea_mode(env, s, 3, REG(insn, 9), opsize,
3323 NULL_QREG, NULL, EA_LOADS, IS_USER(s));
3324
3325 gen_update_cc_cmp(s, dst, src, opsize);
3326 }
3327
3328 DISAS_INSN(eor)
3329 {
3330 TCGv src;
3331 TCGv dest;
3332 TCGv addr;
3333 int opsize;
3334
3335 opsize = insn_opsize(insn);
3336
3337 SRC_EA(env, src, opsize, 0, &addr);
3338 dest = tcg_temp_new();
3339 tcg_gen_xor_i32(dest, src, DREG(insn, 9));
3340 gen_logic_cc(s, dest, opsize);
3341 DEST_EA(env, insn, opsize, dest, &addr);
3342 tcg_temp_free(dest);
3343 }
3344
3345 static void do_exg(TCGv reg1, TCGv reg2)
3346 {
3347 TCGv temp = tcg_temp_new();
3348 tcg_gen_mov_i32(temp, reg1);
3349 tcg_gen_mov_i32(reg1, reg2);
3350 tcg_gen_mov_i32(reg2, temp);
3351 tcg_temp_free(temp);
3352 }
3353
3354 DISAS_INSN(exg_dd)
3355 {
3356 /* exchange Dx and Dy */
3357 do_exg(DREG(insn, 9), DREG(insn, 0));
3358 }
3359
3360 DISAS_INSN(exg_aa)
3361 {
3362 /* exchange Ax and Ay */
3363 do_exg(AREG(insn, 9), AREG(insn, 0));
3364 }
3365
3366 DISAS_INSN(exg_da)
3367 {
3368 /* exchange Dx and Ay */
3369 do_exg(DREG(insn, 9), AREG(insn, 0));
3370 }
3371
3372 DISAS_INSN(and)
3373 {
3374 TCGv src;
3375 TCGv reg;
3376 TCGv dest;
3377 TCGv addr;
3378 int opsize;
3379
3380 dest = tcg_temp_new();
3381
3382 opsize = insn_opsize(insn);
3383 reg = DREG(insn, 9);
3384 if (insn & 0x100) {
3385 SRC_EA(env, src, opsize, 0, &addr);
3386 tcg_gen_and_i32(dest, src, reg);
3387 DEST_EA(env, insn, opsize, dest, &addr);
3388 } else {
3389 SRC_EA(env, src, opsize, 0, NULL);
3390 tcg_gen_and_i32(dest, src, reg);
3391 gen_partset_reg(opsize, reg, dest);
3392 }
3393 gen_logic_cc(s, dest, opsize);
3394 tcg_temp_free(dest);
3395 }
3396
3397 DISAS_INSN(adda)
3398 {
3399 TCGv src;
3400 TCGv reg;
3401
3402 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
3403 reg = AREG(insn, 9);
3404 tcg_gen_add_i32(reg, reg, src);
3405 }
3406
3407 static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
3408 {
3409 TCGv tmp;
3410
3411 gen_flush_flags(s); /* compute old Z */
3412
3413 /*
3414 * Perform addition with carry.
3415 * (X, N) = src + dest + X;
3416 */
3417
3418 tmp = tcg_const_i32(0);
3419 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp);
3420 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp);
3421 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3422
3423 /* Compute signed-overflow for addition. */
3424
3425 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3426 tcg_gen_xor_i32(tmp, dest, src);
3427 tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp);
3428 tcg_temp_free(tmp);
3429
3430 /* Copy the rest of the results into place. */
3431 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
3432 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
3433
3434 set_cc_op(s, CC_OP_FLAGS);
3435
3436 /* result is in QREG_CC_N */
3437 }
3438
3439 DISAS_INSN(addx_reg)
3440 {
3441 TCGv dest;
3442 TCGv src;
3443 int opsize;
3444
3445 opsize = insn_opsize(insn);
3446
3447 dest = gen_extend(s, DREG(insn, 9), opsize, 1);
3448 src = gen_extend(s, DREG(insn, 0), opsize, 1);
3449
3450 gen_addx(s, src, dest, opsize);
3451
3452 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3453 }
3454
3455 DISAS_INSN(addx_mem)
3456 {
3457 TCGv src;
3458 TCGv addr_src;
3459 TCGv dest;
3460 TCGv addr_dest;
3461 int opsize;
3462
3463 opsize = insn_opsize(insn);
3464
3465 addr_src = AREG(insn, 0);
3466 tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize));
3467 src = gen_load(s, opsize, addr_src, 1, IS_USER(s));
3468
3469 addr_dest = AREG(insn, 9);
3470 tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize));
3471 dest = gen_load(s, opsize, addr_dest, 1, IS_USER(s));
3472
3473 gen_addx(s, src, dest, opsize);
3474
3475 gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s));
3476
3477 tcg_temp_free(dest);
3478 tcg_temp_free(src);
3479 }
3480
3481 static inline void shift_im(DisasContext *s, uint16_t insn, int opsize)
3482 {
3483 int count = (insn >> 9) & 7;
3484 int logical = insn & 8;
3485 int left = insn & 0x100;
3486 int bits = opsize_bytes(opsize) * 8;
3487 TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
3488
3489 if (count == 0) {
3490 count = 8;
3491 }
3492
3493 tcg_gen_movi_i32(QREG_CC_V, 0);
3494 if (left) {
3495 tcg_gen_shri_i32(QREG_CC_C, reg, bits - count);
3496 tcg_gen_shli_i32(QREG_CC_N, reg, count);
3497
3498 /*
3499 * Note that ColdFire always clears V (done above),
3500 * while M68000 sets if the most significant bit is changed at
3501 * any time during the shift operation.
3502 */
3503 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3504 /* if shift count >= bits, V is (reg != 0) */
3505 if (count >= bits) {
3506 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V);
3507 } else {
3508 TCGv t0 = tcg_temp_new();
3509 tcg_gen_sari_i32(QREG_CC_V, reg, bits - 1);
3510 tcg_gen_sari_i32(t0, reg, bits - count - 1);
3511 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0);
3512 tcg_temp_free(t0);
3513 }
3514 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3515 }
3516 } else {
3517 tcg_gen_shri_i32(QREG_CC_C, reg, count - 1);
3518 if (logical) {
3519 tcg_gen_shri_i32(QREG_CC_N, reg, count);
3520 } else {
3521 tcg_gen_sari_i32(QREG_CC_N, reg, count);
3522 }
3523 }
3524
3525 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3526 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3527 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3528 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3529
3530 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3531 set_cc_op(s, CC_OP_FLAGS);
3532 }
3533
3534 static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
3535 {
3536 int logical = insn & 8;
3537 int left = insn & 0x100;
3538 int bits = opsize_bytes(opsize) * 8;
3539 TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
3540 TCGv s32;
3541 TCGv_i64 t64, s64;
3542
3543 t64 = tcg_temp_new_i64();
3544 s64 = tcg_temp_new_i64();
3545 s32 = tcg_temp_new();
3546
3547 /*
3548 * Note that m68k truncates the shift count modulo 64, not 32.
3549 * In addition, a 64-bit shift makes it easy to find "the last
3550 * bit shifted out", for the carry flag.
3551 */
3552 tcg_gen_andi_i32(s32, DREG(insn, 9), 63);
3553 tcg_gen_extu_i32_i64(s64, s32);
3554 tcg_gen_extu_i32_i64(t64, reg);
3555
3556 /* Optimistically set V=0. Also used as a zero source below. */
3557 tcg_gen_movi_i32(QREG_CC_V, 0);
3558 if (left) {
3559 tcg_gen_shl_i64(t64, t64, s64);
3560
3561 if (opsize == OS_LONG) {
3562 tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
3563 /* Note that C=0 if shift count is 0, and we get that for free. */
3564 } else {
3565 TCGv zero = tcg_const_i32(0);
3566 tcg_gen_extrl_i64_i32(QREG_CC_N, t64);
3567 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits);
3568 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3569 s32, zero, zero, QREG_CC_C);
3570 tcg_temp_free(zero);
3571 }
3572 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3573
3574 /* X = C, but only if the shift count was non-zero. */
3575 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3576 QREG_CC_C, QREG_CC_X);
3577
3578 /*
3579 * M68000 sets V if the most significant bit is changed at
3580 * any time during the shift operation. Do this via creating
3581 * an extension of the sign bit, comparing, and discarding
3582 * the bits below the sign bit. I.e.
3583 * int64_t s = (intN_t)reg;
3584 * int64_t t = (int64_t)(intN_t)reg << count;
3585 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3586 */
3587 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3588 TCGv_i64 tt = tcg_const_i64(32);
3589 /* if shift is greater than 32, use 32 */
3590 tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64);
3591 tcg_temp_free_i64(tt);
3592 /* Sign extend the input to 64 bits; re-do the shift. */
3593 tcg_gen_ext_i32_i64(t64, reg);
3594 tcg_gen_shl_i64(s64, t64, s64);
3595 /* Clear all bits that are unchanged. */
3596 tcg_gen_xor_i64(t64, t64, s64);
3597 /* Ignore the bits below the sign bit. */
3598 tcg_gen_andi_i64(t64, t64, -1ULL << (bits - 1));
3599 /* If any bits remain set, we have overflow. */
3600 tcg_gen_setcondi_i64(TCG_COND_NE, t64, t64, 0);
3601 tcg_gen_extrl_i64_i32(QREG_CC_V, t64);
3602 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3603 }
3604 } else {
3605 tcg_gen_shli_i64(t64, t64, 32);
3606 if (logical) {
3607 tcg_gen_shr_i64(t64, t64, s64);
3608 } else {
3609 tcg_gen_sar_i64(t64, t64, s64);
3610 }
3611 tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64);
3612
3613 /* Note that C=0 if shift count is 0, and we get that for free. */
3614 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31);
3615
3616 /* X = C, but only if the shift count was non-zero. */
3617 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3618 QREG_CC_C, QREG_CC_X);
3619 }
3620 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3621 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3622
3623 tcg_temp_free(s32);
3624 tcg_temp_free_i64(s64);
3625 tcg_temp_free_i64(t64);
3626
3627 /* Write back the result. */
3628 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3629 set_cc_op(s, CC_OP_FLAGS);
3630 }
3631
3632 DISAS_INSN(shift8_im)
3633 {
3634 shift_im(s, insn, OS_BYTE);
3635 }
3636
3637 DISAS_INSN(shift16_im)
3638 {
3639 shift_im(s, insn, OS_WORD);
3640 }
3641
3642 DISAS_INSN(shift_im)
3643 {
3644 shift_im(s, insn, OS_LONG);
3645 }
3646
3647 DISAS_INSN(shift8_reg)
3648 {
3649 shift_reg(s, insn, OS_BYTE);
3650 }
3651
3652 DISAS_INSN(shift16_reg)
3653 {
3654 shift_reg(s, insn, OS_WORD);
3655 }
3656
3657 DISAS_INSN(shift_reg)
3658 {
3659 shift_reg(s, insn, OS_LONG);
3660 }
3661
3662 DISAS_INSN(shift_mem)
3663 {
3664 int logical = insn & 8;
3665 int left = insn & 0x100;
3666 TCGv src;
3667 TCGv addr;
3668
3669 SRC_EA(env, src, OS_WORD, !logical, &addr);
3670 tcg_gen_movi_i32(QREG_CC_V, 0);
3671 if (left) {
3672 tcg_gen_shri_i32(QREG_CC_C, src, 15);
3673 tcg_gen_shli_i32(QREG_CC_N, src, 1);
3674
3675 /*
3676 * Note that ColdFire always clears V,
3677 * while M68000 sets if the most significant bit is changed at
3678 * any time during the shift operation
3679 */
3680 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3681 src = gen_extend(s, src, OS_WORD, 1);
3682 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3683 }
3684 } else {
3685 tcg_gen_mov_i32(QREG_CC_C, src);
3686 if (logical) {
3687 tcg_gen_shri_i32(QREG_CC_N, src, 1);
3688 } else {
3689 tcg_gen_sari_i32(QREG_CC_N, src, 1);
3690 }
3691 }
3692
3693 gen_ext(QREG_CC_N, QREG_CC_N, OS_WORD, 1);
3694 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3695 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3696 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3697
3698 DEST_EA(env, insn, OS_WORD, QREG_CC_N, &addr);
3699 set_cc_op(s, CC_OP_FLAGS);
3700 }
3701
3702 static void rotate(TCGv reg, TCGv shift, int left, int size)
3703 {
3704 switch (size) {
3705 case 8:
3706 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3707 tcg_gen_ext8u_i32(reg, reg);
3708 tcg_gen_muli_i32(reg, reg, 0x01010101);
3709 goto do_long;
3710 case 16:
3711 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3712 tcg_gen_deposit_i32(reg, reg, reg, 16, 16);
3713 goto do_long;
3714 do_long:
3715 default:
3716 if (left) {
3717 tcg_gen_rotl_i32(reg, reg, shift);
3718 } else {
3719 tcg_gen_rotr_i32(reg, reg, shift);
3720 }
3721 }
3722
3723 /* compute flags */
3724
3725 switch (size) {
3726 case 8:
3727 tcg_gen_ext8s_i32(reg, reg);
3728 break;
3729 case 16:
3730 tcg_gen_ext16s_i32(reg, reg);
3731 break;
3732 default:
3733 break;
3734 }
3735
3736 /* QREG_CC_X is not affected */
3737
3738 tcg_gen_mov_i32(QREG_CC_N, reg);
3739 tcg_gen_mov_i32(QREG_CC_Z, reg);
3740
3741 if (left) {
3742 tcg_gen_andi_i32(QREG_CC_C, reg, 1);
3743 } else {
3744 tcg_gen_shri_i32(QREG_CC_C, reg, 31);
3745 }
3746
3747 tcg_gen_movi_i32(QREG_CC_V, 0); /* always cleared */
3748 }
3749
3750 static void rotate_x_flags(TCGv reg, TCGv X, int size)
3751 {
3752 switch (size) {
3753 case 8:
3754 tcg_gen_ext8s_i32(reg, reg);
3755 break;
3756 case 16:
3757 tcg_gen_ext16s_i32(reg, reg);
3758 break;
3759 default:
3760 break;
3761 }
3762 tcg_gen_mov_i32(QREG_CC_N, reg);
3763 tcg_gen_mov_i32(QREG_CC_Z, reg);
3764 tcg_gen_mov_i32(QREG_CC_X, X);
3765 tcg_gen_mov_i32(QREG_CC_C, X);
3766 tcg_gen_movi_i32(QREG_CC_V, 0);
3767 }
3768
3769 /* Result of rotate_x() is valid if 0 <= shift <= size */
3770 static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size)
3771 {
3772 TCGv X, shl, shr, shx, sz, zero;
3773
3774 sz = tcg_const_i32(size);
3775
3776 shr = tcg_temp_new();
3777 shl = tcg_temp_new();
3778 shx = tcg_temp_new();
3779 if (left) {
3780 tcg_gen_mov_i32(shl, shift); /* shl = shift */
3781 tcg_gen_movi_i32(shr, size + 1);
3782 tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */
3783 tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */
3784 /* shx = shx < 0 ? size : shx; */
3785 zero = tcg_const_i32(0);
3786 tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx);
3787 tcg_temp_free(zero);
3788 } else {
3789 tcg_gen_mov_i32(shr, shift); /* shr = shift */
3790 tcg_gen_movi_i32(shl, size + 1);
3791 tcg_gen_sub_i32(shl, shl, shift); /* shl = size + 1 - shift */
3792 tcg_gen_sub_i32(shx, sz, shift); /* shx = size - shift */
3793 }
3794 tcg_temp_free_i32(sz);
3795
3796 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3797
3798 tcg_gen_shl_i32(shl, reg, shl);
3799 tcg_gen_shr_i32(shr, reg, shr);
3800 tcg_gen_or_i32(reg, shl, shr);
3801 tcg_temp_free(shl);
3802 tcg_temp_free(shr);
3803 tcg_gen_shl_i32(shx, QREG_CC_X, shx);
3804 tcg_gen_or_i32(reg, reg, shx);
3805 tcg_temp_free(shx);
3806
3807 /* X = (reg >> size) & 1 */
3808
3809 X = tcg_temp_new();
3810 tcg_gen_extract_i32(X, reg, size, 1);
3811
3812 return X;
3813 }
3814
3815 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3816 static TCGv rotate32_x(TCGv reg, TCGv shift, int left)
3817 {
3818 TCGv_i64 t0, shift64;
3819 TCGv X, lo, hi, zero;
3820
3821 shift64 = tcg_temp_new_i64();
3822 tcg_gen_extu_i32_i64(shift64, shift);
3823
3824 t0 = tcg_temp_new_i64();
3825
3826 X = tcg_temp_new();
3827 lo = tcg_temp_new();
3828 hi = tcg_temp_new();
3829
3830 if (left) {
3831 /* create [reg:X:..] */
3832
3833 tcg_gen_shli_i32(lo, QREG_CC_X, 31);
3834 tcg_gen_concat_i32_i64(t0, lo, reg);
3835
3836 /* rotate */
3837
3838 tcg_gen_rotl_i64(t0, t0, shift64);
3839 tcg_temp_free_i64(shift64);
3840
3841 /* result is [reg:..:reg:X] */
3842
3843 tcg_gen_extr_i64_i32(lo, hi, t0);
3844 tcg_gen_andi_i32(X, lo, 1);
3845
3846 tcg_gen_shri_i32(lo, lo, 1);
3847 } else {
3848 /* create [..:X:reg] */
3849
3850 tcg_gen_concat_i32_i64(t0, reg, QREG_CC_X);
3851
3852 tcg_gen_rotr_i64(t0, t0, shift64);
3853 tcg_temp_free_i64(shift64);
3854
3855 /* result is value: [X:reg:..:reg] */
3856
3857 tcg_gen_extr_i64_i32(lo, hi, t0);
3858
3859 /* extract X */
3860
3861 tcg_gen_shri_i32(X, hi, 31);
3862
3863 /* extract result */
3864
3865 tcg_gen_shli_i32(hi, hi, 1);
3866 }
3867 tcg_temp_free_i64(t0);
3868 tcg_gen_or_i32(lo, lo, hi);
3869 tcg_temp_free(hi);
3870
3871 /* if shift == 0, register and X are not affected */
3872
3873 zero = tcg_const_i32(0);
3874 tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X);
3875 tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo);
3876 tcg_temp_free(zero);
3877 tcg_temp_free(lo);
3878
3879 return X;
3880 }
3881
3882 DISAS_INSN(rotate_im)
3883 {
3884 TCGv shift;
3885 int tmp;
3886 int left = (insn & 0x100);
3887
3888 tmp = (insn >> 9) & 7;
3889 if (tmp == 0) {
3890 tmp = 8;
3891 }
3892
3893 shift = tcg_const_i32(tmp);
3894 if (insn & 8) {
3895 rotate(DREG(insn, 0), shift, left, 32);
3896 } else {
3897 TCGv X = rotate32_x(DREG(insn, 0), shift, left);
3898 rotate_x_flags(DREG(insn, 0), X, 32);
3899 tcg_temp_free(X);
3900 }
3901 tcg_temp_free(shift);
3902
3903 set_cc_op(s, CC_OP_FLAGS);
3904 }
3905
3906 DISAS_INSN(rotate8_im)
3907 {
3908 int left = (insn & 0x100);
3909 TCGv reg;
3910 TCGv shift;
3911 int tmp;
3912
3913 reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
3914
3915 tmp = (insn >> 9) & 7;
3916 if (tmp == 0) {
3917 tmp = 8;
3918 }
3919
3920 shift = tcg_const_i32(tmp);
3921 if (insn & 8) {
3922 rotate(reg, shift, left, 8);
3923 } else {
3924 TCGv X = rotate_x(reg, shift, left, 8);
3925 rotate_x_flags(reg, X, 8);
3926 tcg_temp_free(X);
3927 }
3928 tcg_temp_free(shift);
3929 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
3930 set_cc_op(s, CC_OP_FLAGS);
3931 }
3932
3933 DISAS_INSN(rotate16_im)
3934 {
3935 int left = (insn & 0x100);
3936 TCGv reg;
3937 TCGv shift;
3938 int tmp;
3939
3940 reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
3941 tmp = (insn >> 9) & 7;
3942 if (tmp == 0) {
3943 tmp = 8;
3944 }
3945
3946 shift = tcg_const_i32(tmp);
3947 if (insn & 8) {
3948 rotate(reg, shift, left, 16);
3949 } else {
3950 TCGv X = rotate_x(reg, shift, left, 16);
3951 rotate_x_flags(reg, X, 16);
3952 tcg_temp_free(X);
3953 }
3954 tcg_temp_free(shift);
3955 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
3956 set_cc_op(s, CC_OP_FLAGS);
3957 }
3958
3959 DISAS_INSN(rotate_reg)
3960 {
3961 TCGv reg;
3962 TCGv src;
3963 TCGv t0, t1;
3964 int left = (insn & 0x100);
3965
3966 reg = DREG(insn, 0);
3967 src = DREG(insn, 9);
3968 /* shift in [0..63] */
3969 t0 = tcg_temp_new();
3970 tcg_gen_andi_i32(t0, src, 63);
3971 t1 = tcg_temp_new_i32();
3972 if (insn & 8) {
3973 tcg_gen_andi_i32(t1, src, 31);
3974 rotate(reg, t1, left, 32);
3975 /* if shift == 0, clear C */
3976 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3977 t0, QREG_CC_V /* 0 */,
3978 QREG_CC_V /* 0 */, QREG_CC_C);
3979 } else {
3980 TCGv X;
3981 /* modulo 33 */
3982 tcg_gen_movi_i32(t1, 33);
3983 tcg_gen_remu_i32(t1, t0, t1);
3984 X = rotate32_x(DREG(insn, 0), t1, left);
3985 rotate_x_flags(DREG(insn, 0), X, 32);
3986 tcg_temp_free(X);
3987 }
3988 tcg_temp_free(t1);
3989 tcg_temp_free(t0);
3990 set_cc_op(s, CC_OP_FLAGS);
3991 }
3992
3993 DISAS_INSN(rotate8_reg)
3994 {
3995 TCGv reg;
3996 TCGv src;
3997 TCGv t0, t1;
3998 int left = (insn & 0x100);
3999
4000 reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
4001 src = DREG(insn, 9);
4002 /* shift in [0..63] */
4003 t0 = tcg_temp_new_i32();
4004 tcg_gen_andi_i32(t0, src, 63);
4005 t1 = tcg_temp_new_i32();
4006 if (insn & 8) {
4007 tcg_gen_andi_i32(t1, src, 7);
4008 rotate(reg, t1, left, 8);
4009 /* if shift == 0, clear C */
4010 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
4011 t0, QREG_CC_V /* 0 */,
4012 QREG_CC_V /* 0 */, QREG_CC_C);
4013 } else {
4014 TCGv X;
4015 /* modulo 9 */
4016 tcg_gen_movi_i32(t1, 9);
4017 tcg_gen_remu_i32(t1, t0, t1);
4018 X = rotate_x(reg, t1, left, 8);
4019 rotate_x_flags(reg, X, 8);
4020 tcg_temp_free(X);
4021 }
4022 tcg_temp_free(t1);
4023 tcg_temp_free(t0);
4024 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
4025 set_cc_op(s, CC_OP_FLAGS);
4026 }
4027
4028 DISAS_INSN(rotate16_reg)
4029 {
4030 TCGv reg;
4031 TCGv src;
4032 TCGv t0, t1;
4033 int left = (insn & 0x100);
4034
4035 reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
4036 src = DREG(insn, 9);
4037 /* shift in [0..63] */
4038 t0 = tcg_temp_new_i32();
4039 tcg_gen_andi_i32(t0, src, 63);
4040 t1 = tcg_temp_new_i32();
4041 if (insn & 8) {
4042 tcg_gen_andi_i32(t1, src, 15);
4043 rotate(reg, t1, left, 16);
4044 /* if shift == 0, clear C */
4045 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
4046 t0, QREG_CC_V /* 0 */,
4047 QREG_CC_V /* 0 */, QREG_CC_C);
4048 } else {
4049 TCGv X;
4050 /* modulo 17 */
4051 tcg_gen_movi_i32(t1, 17);
4052 tcg_gen_remu_i32(t1, t0, t1);
4053 X = rotate_x(reg, t1, left, 16);
4054 rotate_x_flags(reg, X, 16);
4055 tcg_temp_free(X);
4056 }
4057 tcg_temp_free(t1);
4058 tcg_temp_free(t0);
4059 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
4060 set_cc_op(s, CC_OP_FLAGS);
4061 }
4062
4063 DISAS_INSN(rotate_mem)
4064 {
4065 TCGv src;
4066 TCGv addr;
4067 TCGv shift;
4068 int left = (insn & 0x100);
4069
4070 SRC_EA(env, src, OS_WORD, 0, &addr);
4071
4072 shift = tcg_const_i32(1);
4073 if (insn & 0x0200) {
4074 rotate(src, shift, left, 16);
4075 } else {
4076 TCGv X = rotate_x(src, shift, left, 16);
4077 rotate_x_flags(src, X, 16);
4078 tcg_temp_free(X);
4079 }
4080 tcg_temp_free(shift);
4081 DEST_EA(env, insn, OS_WORD, src, &addr);
4082 set_cc_op(s, CC_OP_FLAGS);
4083 }
4084
4085 DISAS_INSN(bfext_reg)
4086 {
4087 int ext = read_im16(env, s);
4088 int is_sign = insn & 0x200;
4089 TCGv src = DREG(insn, 0);
4090 TCGv dst = DREG(ext, 12);
4091 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4092 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4093 int pos = 32 - ofs - len; /* little bit-endian */
4094 TCGv tmp = tcg_temp_new();
4095 TCGv shift;
4096
4097 /*
4098 * In general, we're going to rotate the field so that it's at the
4099 * top of the word and then right-shift by the complement of the
4100 * width to extend the field.
4101 */
4102 if (ext & 0x20) {
4103 /* Variable width. */
4104 if (ext & 0x800) {
4105 /* Variable offset. */
4106 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
4107 tcg_gen_rotl_i32(tmp, src, tmp);
4108 } else {
4109 tcg_gen_rotli_i32(tmp, src, ofs);
4110 }
4111
4112 shift = tcg_temp_new();
4113 tcg_gen_neg_i32(shift, DREG(ext, 0));
4114 tcg_gen_andi_i32(shift, shift, 31);
4115 tcg_gen_sar_i32(QREG_CC_N, tmp, shift);
4116 if (is_sign) {
4117 tcg_gen_mov_i32(dst, QREG_CC_N);
4118 } else {
4119 tcg_gen_shr_i32(dst, tmp, shift);
4120 }
4121 tcg_temp_free(shift);
4122 } else {
4123 /* Immediate width. */
4124 if (ext & 0x800) {
4125 /* Variable offset */
4126 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
4127 tcg_gen_rotl_i32(tmp, src, tmp);
4128 src = tmp;
4129 pos = 32 - len;
4130 } else {
4131 /*
4132 * Immediate offset. If the field doesn't wrap around the
4133 * end of the word, rely on (s)extract completely.
4134 */
4135 if (pos < 0) {
4136 tcg_gen_rotli_i32(tmp, src, ofs);
4137 src = tmp;
4138 pos = 32 - len;
4139 }
4140 }
4141
4142 tcg_gen_sextract_i32(QREG_CC_N, src, pos, len);
4143 if (is_sign) {
4144 tcg_gen_mov_i32(dst, QREG_CC_N);
4145 } else {
4146 tcg_gen_extract_i32(dst, src, pos, len);
4147 }
4148 }
4149
4150 tcg_temp_free(tmp);
4151 set_cc_op(s, CC_OP_LOGIC);
4152 }
4153
4154 DISAS_INSN(bfext_mem)
4155 {
4156 int ext = read_im16(env, s);
4157 int is_sign = insn & 0x200;
4158 TCGv dest = DREG(ext, 12);
4159 TCGv addr, len, ofs;
4160
4161 addr = gen_lea(env, s, insn, OS_UNSIZED);
4162 if (IS_NULL_QREG(addr)) {
4163 gen_addr_fault(s);
4164 return;
4165 }
4166
4167 if (ext & 0x20) {
4168 len = DREG(ext, 0);
4169 } else {
4170 len = tcg_const_i32(extract32(ext, 0, 5));
4171 }
4172 if (ext & 0x800) {
4173 ofs = DREG(ext, 6);
4174 } else {
4175 ofs = tcg_const_i32(extract32(ext, 6, 5));
4176 }
4177
4178 if (is_sign) {
4179 gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len);
4180 tcg_gen_mov_i32(QREG_CC_N, dest);
4181 } else {
4182 TCGv_i64 tmp = tcg_temp_new_i64();
4183 gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len);
4184 tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp);
4185 tcg_temp_free_i64(tmp);
4186 }
4187 set_cc_op(s, CC_OP_LOGIC);
4188
4189 if (!(ext & 0x20)) {
4190 tcg_temp_free(len);
4191 }
4192 if (!(ext & 0x800)) {
4193 tcg_temp_free(ofs);
4194 }
4195 }
4196
4197 DISAS_INSN(bfop_reg)
4198 {
4199 int ext = read_im16(env, s);
4200 TCGv src = DREG(insn, 0);
4201 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4202 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4203 TCGv mask, tofs, tlen;
4204
4205 tofs = NULL;
4206 tlen = NULL;
4207 if ((insn & 0x0f00) == 0x0d00) { /* bfffo */
4208 tofs = tcg_temp_new();
4209 tlen = tcg_temp_new();
4210 }
4211
4212 if ((ext & 0x820) == 0) {
4213 /* Immediate width and offset. */
4214 uint32_t maski = 0x7fffffffu >> (len - 1);
4215 if (ofs + len <= 32) {
4216 tcg_gen_shli_i32(QREG_CC_N, src, ofs);
4217 } else {
4218 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
4219 }
4220 tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski);
4221 mask = tcg_const_i32(ror32(maski, ofs));
4222 if (tofs) {
4223 tcg_gen_movi_i32(tofs, ofs);
4224 tcg_gen_movi_i32(tlen, len);
4225 }
4226 } else {
4227 TCGv tmp = tcg_temp_new();
4228 if (ext & 0x20) {
4229 /* Variable width */
4230 tcg_gen_subi_i32(tmp, DREG(ext, 0), 1);
4231 tcg_gen_andi_i32(tmp, tmp, 31);
4232 mask = tcg_const_i32(0x7fffffffu);
4233 tcg_gen_shr_i32(mask, mask, tmp);
4234 if (tlen) {
4235 tcg_gen_addi_i32(tlen, tmp, 1);
4236 }
4237 } else {
4238 /* Immediate width */
4239 mask = tcg_const_i32(0x7fffffffu >> (len - 1));
4240 if (tlen) {
4241 tcg_gen_movi_i32(tlen, len);
4242 }
4243 }
4244 if (ext & 0x800) {
4245 /* Variable offset */
4246 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
4247 tcg_gen_rotl_i32(QREG_CC_N, src, tmp);
4248 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
4249 tcg_gen_rotr_i32(mask, mask, tmp);
4250 if (tofs) {
4251 tcg_gen_mov_i32(tofs, tmp);
4252 }
4253 } else {
4254 /* Immediate offset (and variable width) */
4255 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
4256 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
4257 tcg_gen_rotri_i32(mask, mask, ofs);
4258 if (tofs) {
4259 tcg_gen_movi_i32(tofs, ofs);
4260 }
4261 }
4262 tcg_temp_free(tmp);
4263 }
4264 set_cc_op(s, CC_OP_LOGIC);
4265
4266 switch (insn & 0x0f00) {
4267 case 0x0a00: /* bfchg */
4268 tcg_gen_eqv_i32(src, src, mask);
4269 break;
4270 case 0x0c00: /* bfclr */
4271 tcg_gen_and_i32(src, src, mask);
4272 break;
4273 case 0x0d00: /* bfffo */
4274 gen_helper_bfffo_reg(DREG(ext, 12), QREG_CC_N, tofs, tlen);
4275 tcg_temp_free(tlen);
4276 tcg_temp_free(tofs);
4277 break;
4278 case 0x0e00: /* bfset */
4279 tcg_gen_orc_i32(src, src, mask);
4280 break;
4281 case 0x0800: /* bftst */
4282 /* flags already set; no other work to do. */
4283 break;
4284 default:
4285 g_assert_not_reached();
4286 }
4287 tcg_temp_free(mask);
4288 }
4289
4290 DISAS_INSN(bfop_mem)
4291 {
4292 int ext = read_im16(env, s);
4293 TCGv addr, len, ofs;
4294 TCGv_i64 t64;
4295
4296 addr = gen_lea(env, s, insn, OS_UNSIZED);
4297 if (IS_NULL_QREG(addr)) {
4298 gen_addr_fault(s);
4299 return;
4300 }
4301
4302 if (ext & 0x20) {
4303 len = DREG(ext, 0);
4304 } else {
4305 len = tcg_const_i32(extract32(ext, 0, 5));
4306 }
4307 if (ext & 0x800) {
4308 ofs = DREG(ext, 6);
4309 } else {
4310 ofs = tcg_const_i32(extract32(ext, 6, 5));
4311 }
4312
4313 switch (insn & 0x0f00) {
4314 case 0x0a00: /* bfchg */
4315 gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4316 break;
4317 case 0x0c00: /* bfclr */
4318 gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4319 break;
4320 case 0x0d00: /* bfffo */
4321 t64 = tcg_temp_new_i64();
4322 gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len);
4323 tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64);
4324 tcg_temp_free_i64(t64);
4325 break;
4326 case 0x0e00: /* bfset */
4327 gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4328 break;
4329 case 0x0800: /* bftst */
4330 gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4331 break;
4332 default:
4333 g_assert_not_reached();
4334 }
4335 set_cc_op(s, CC_OP_LOGIC);
4336
4337 if (!(ext & 0x20)) {
4338 tcg_temp_free(len);
4339 }
4340 if (!(ext & 0x800)) {
4341 tcg_temp_free(ofs);
4342 }
4343 }
4344
4345 DISAS_INSN(bfins_reg)
4346 {
4347 int ext = read_im16(env, s);
4348 TCGv dst = DREG(insn, 0);
4349 TCGv src = DREG(ext, 12);
4350 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4351 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4352 int pos = 32 - ofs - len; /* little bit-endian */
4353 TCGv tmp;
4354
4355 tmp = tcg_temp_new();
4356
4357 if (ext & 0x20) {
4358 /* Variable width */
4359 tcg_gen_neg_i32(tmp, DREG(ext, 0));
4360 tcg_gen_andi_i32(tmp, tmp, 31);
4361 tcg_gen_shl_i32(QREG_CC_N, src, tmp);
4362 } else {
4363 /* Immediate width */
4364 tcg_gen_shli_i32(QREG_CC_N, src, 32 - len);
4365 }
4366 set_cc_op(s, CC_OP_LOGIC);
4367
4368 /* Immediate width and offset */
4369 if ((ext & 0x820) == 0) {
4370 /* Check for suitability for deposit. */
4371 if (pos >= 0) {
4372 tcg_gen_deposit_i32(dst, dst, src, pos, len);
4373 } else {
4374 uint32_t maski = -2U << (len - 1);
4375 uint32_t roti = (ofs + len) & 31;
4376 tcg_gen_andi_i32(tmp, src, ~maski);
4377 tcg_gen_rotri_i32(tmp, tmp, roti);
4378 tcg_gen_andi_i32(dst, dst, ror32(maski, roti));
4379 tcg_gen_or_i32(dst, dst, tmp);
4380 }
4381 } else {
4382 TCGv mask = tcg_temp_new();
4383 TCGv rot = tcg_temp_new();
4384
4385 if (ext & 0x20) {
4386 /* Variable width */
4387 tcg_gen_subi_i32(rot, DREG(ext, 0), 1);
4388 tcg_gen_andi_i32(rot, rot, 31);
4389 tcg_gen_movi_i32(mask, -2);
4390 tcg_gen_shl_i32(mask, mask, rot);
4391 tcg_gen_mov_i32(rot, DREG(ext, 0));
4392 tcg_gen_andc_i32(tmp, src, mask);
4393 } else {
4394 /* Immediate width (variable offset) */
4395 uint32_t maski = -2U << (len - 1);
4396 tcg_gen_andi_i32(tmp, src, ~maski);
4397 tcg_gen_movi_i32(mask, maski);
4398 tcg_gen_movi_i32(rot, len & 31);
4399 }
4400 if (ext & 0x800) {
4401 /* Variable offset */
4402 tcg_gen_add_i32(rot, rot, DREG(ext, 6));
4403 } else {
4404 /* Immediate offset (variable width) */
4405 tcg_gen_addi_i32(rot, rot, ofs);
4406 }
4407 tcg_gen_andi_i32(rot, rot, 31);
4408 tcg_gen_rotr_i32(mask, mask, rot);
4409 tcg_gen_rotr_i32(tmp, tmp, rot);
4410 tcg_gen_and_i32(dst, dst, mask);
4411 tcg_gen_or_i32(dst, dst, tmp);
4412
4413 tcg_temp_free(rot);
4414 tcg_temp_free(mask);
4415 }
4416 tcg_temp_free(tmp);
4417 }
4418
4419 DISAS_INSN(bfins_mem)
4420 {
4421 int ext = read_im16(env, s);
4422 TCGv src = DREG(ext, 12);
4423 TCGv addr, len, ofs;
4424
4425 addr = gen_lea(env, s, insn, OS_UNSIZED);
4426 if (IS_NULL_QREG(addr)) {
4427 gen_addr_fault(s);
4428 return;
4429 }
4430
4431 if (ext & 0x20) {
4432 len = DREG(ext, 0);
4433 } else {
4434 len = tcg_const_i32(extract32(ext, 0, 5));
4435 }
4436 if (ext & 0x800) {
4437 ofs = DREG(ext, 6);
4438 } else {
4439 ofs = tcg_const_i32(extract32(ext, 6, 5));
4440 }
4441
4442 gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
4443 set_cc_op(s, CC_OP_LOGIC);
4444
4445 if (!(ext & 0x20)) {
4446 tcg_temp_free(len);
4447 }
4448 if (!(ext & 0x800)) {
4449 tcg_temp_free(ofs);
4450 }
4451 }
4452
4453 DISAS_INSN(ff1)
4454 {
4455 TCGv reg;
4456 reg = DREG(insn, 0);
4457 gen_logic_cc(s, reg, OS_LONG);
4458 gen_helper_ff1(reg, reg);
4459 }
4460
4461 DISAS_INSN(chk)
4462 {
4463 TCGv src, reg;
4464 int opsize;
4465
4466 switch ((insn >> 7) & 3) {
4467 case 3:
4468 opsize = OS_WORD;
4469 break;
4470 case 2:
4471 if (m68k_feature(env, M68K_FEATURE_CHK2)) {
4472 opsize = OS_LONG;
4473 break;
4474 }
4475 /* fallthru */
4476 default:
4477 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4478 return;
4479 }
4480 SRC_EA(env, src, opsize, 1, NULL);
4481 reg = gen_extend(s, DREG(insn, 9), opsize, 1);
4482
4483 gen_flush_flags(s);
4484 gen_helper_chk(cpu_env, reg, src);
4485 }
4486
4487 DISAS_INSN(chk2)
4488 {
4489 uint16_t ext;
4490 TCGv addr1, addr2, bound1, bound2, reg;
4491 int opsize;
4492
4493 switch ((insn >> 9) & 3) {
4494 case 0:
4495 opsize = OS_BYTE;
4496 break;
4497 case 1:
4498 opsize = OS_WORD;
4499 break;
4500 case 2:
4501 opsize = OS_LONG;
4502 break;
4503 default:
4504 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4505 return;
4506 }
4507
4508 ext = read_im16(env, s);
4509 if ((ext & 0x0800) == 0) {
4510 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4511 return;
4512 }
4513
4514 addr1 = gen_lea(env, s, insn, OS_UNSIZED);
4515 addr2 = tcg_temp_new();
4516 tcg_gen_addi_i32(addr2, addr1, opsize_bytes(opsize));
4517
4518 bound1 = gen_load(s, opsize, addr1, 1, IS_USER(s));
4519 tcg_temp_free(addr1);
4520 bound2 = gen_load(s, opsize, addr2, 1, IS_USER(s));
4521 tcg_temp_free(addr2);
4522
4523 reg = tcg_temp_new();
4524 if (ext & 0x8000) {
4525 tcg_gen_mov_i32(reg, AREG(ext, 12));
4526 } else {
4527 gen_ext(reg, DREG(ext, 12), opsize, 1);
4528 }
4529
4530 gen_flush_flags(s);
4531 gen_helper_chk2(cpu_env, reg, bound1, bound2);
4532 tcg_temp_free(reg);
4533 tcg_temp_free(bound1);
4534 tcg_temp_free(bound2);
4535 }
4536
4537 static void m68k_copy_line(TCGv dst, TCGv src, int index)
4538 {
4539 TCGv addr;
4540 TCGv_i64 t0, t1;
4541
4542 addr = tcg_temp_new();
4543
4544 t0 = tcg_temp_new_i64();
4545 t1 = tcg_temp_new_i64();
4546
4547 tcg_gen_andi_i32(addr, src, ~15);
4548 tcg_gen_qemu_ld64(t0, addr, index);
4549 tcg_gen_addi_i32(addr, addr, 8);
4550 tcg_gen_qemu_ld64(t1, addr, index);
4551
4552 tcg_gen_andi_i32(addr, dst, ~15);
4553 tcg_gen_qemu_st64(t0, addr, index);
4554 tcg_gen_addi_i32(addr, addr, 8);
4555 tcg_gen_qemu_st64(t1, addr, index);
4556
4557 tcg_temp_free_i64(t0);
4558 tcg_temp_free_i64(t1);
4559 tcg_temp_free(addr);
4560 }
4561
4562 DISAS_INSN(move16_reg)
4563 {
4564 int index = IS_USER(s);
4565 TCGv tmp;
4566 uint16_t ext;
4567
4568 ext = read_im16(env, s);
4569 if ((ext & (1 << 15)) == 0) {
4570 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4571 }
4572
4573 m68k_copy_line(AREG(ext, 12), AREG(insn, 0), index);
4574
4575 /* Ax can be Ay, so save Ay before incrementing Ax */
4576 tmp = tcg_temp_new();
4577 tcg_gen_mov_i32(tmp, AREG(ext, 12));
4578 tcg_gen_addi_i32(AREG(insn, 0), AREG(insn, 0), 16);
4579 tcg_gen_addi_i32(AREG(ext, 12), tmp, 16);
4580 tcg_temp_free(tmp);
4581 }
4582
4583 DISAS_INSN(move16_mem)
4584 {
4585 int index = IS_USER(s);
4586 TCGv reg, addr;
4587
4588 reg = AREG(insn, 0);
4589 addr = tcg_const_i32(read_im32(env, s));
4590
4591 if ((insn >> 3) & 1) {
4592 /* MOVE16 (xxx).L, (Ay) */
4593 m68k_copy_line(reg, addr, index);
4594 } else {
4595 /* MOVE16 (Ay), (xxx).L */
4596 m68k_copy_line(addr, reg, index);
4597 }
4598
4599 tcg_temp_free(addr);
4600
4601 if (((insn >> 3) & 2) == 0) {
4602 /* (Ay)+ */
4603 tcg_gen_addi_i32(reg, reg, 16);
4604 }
4605 }
4606
4607 DISAS_INSN(strldsr)
4608 {
4609 uint16_t ext;
4610 uint32_t addr;
4611
4612 addr = s->pc - 2;
4613 ext = read_im16(env, s);
4614 if (ext != 0x46FC) {
4615 gen_exception(s, addr, EXCP_ILLEGAL);
4616 return;
4617 }
4618 ext = read_im16(env, s);
4619 if (IS_USER(s) || (ext & SR_S) == 0) {
4620 gen_exception(s, addr, EXCP_PRIVILEGE);
4621 return;
4622 }
4623 gen_push(s, gen_get_sr(s));
4624 gen_set_sr_im(s, ext, 0);
4625 }
4626
4627 DISAS_INSN(move_from_sr)
4628 {
4629 TCGv sr;
4630
4631 if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) {
4632 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4633 return;
4634 }
4635 sr = gen_get_sr(s);
4636 DEST_EA(env, insn, OS_WORD, sr, NULL);
4637 }
4638
4639 #if defined(CONFIG_SOFTMMU)
4640 DISAS_INSN(moves)
4641 {
4642 int opsize;
4643 uint16_t ext;
4644 TCGv reg;
4645 TCGv addr;
4646 int extend;
4647
4648 if (IS_USER(s)) {
4649 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4650 return;
4651 }
4652
4653 ext = read_im16(env, s);
4654
4655 opsize = insn_opsize(insn);
4656
4657 if (ext & 0x8000) {
4658 /* address register */
4659 reg = AREG(ext, 12);
4660 extend = 1;
4661 } else {
4662 /* data register */
4663 reg = DREG(ext, 12);
4664 extend = 0;
4665 }
4666
4667 addr = gen_lea(env, s, insn, opsize);
4668 if (IS_NULL_QREG(addr)) {
4669 gen_addr_fault(s);
4670 return;
4671 }
4672
4673 if (ext & 0x0800) {
4674 /* from reg to ea */
4675 gen_store(s, opsize, addr, reg, DFC_INDEX(s));
4676 } else {
4677 /* from ea to reg */
4678 TCGv tmp = gen_load(s, opsize, addr, 0, SFC_INDEX(s));
4679 if (extend) {
4680 gen_ext(reg, tmp, opsize, 1);
4681 } else {
4682 gen_partset_reg(opsize, reg, tmp);
4683 }
4684 tcg_temp_free(tmp);
4685 }
4686 switch (extract32(insn, 3, 3)) {
4687 case 3: /* Indirect postincrement. */
4688 tcg_gen_addi_i32(AREG(insn, 0), addr,
4689 REG(insn, 0) == 7 && opsize == OS_BYTE
4690 ? 2
4691 : opsize_bytes(opsize));
4692 break;
4693 case 4: /* Indirect predecrememnt. */
4694 tcg_gen_mov_i32(AREG(insn, 0), addr);
4695 break;
4696 }
4697 }
4698
4699 DISAS_INSN(move_to_sr)
4700 {
4701 if (IS_USER(s)) {
4702 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4703 return;
4704 }
4705 gen_move_to_sr(env, s, insn, false);
4706 gen_exit_tb(s);
4707 }
4708
4709 DISAS_INSN(move_from_usp)
4710 {
4711 if (IS_USER(s)) {
4712 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4713 return;
4714 }
4715 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
4716 offsetof(CPUM68KState, sp[M68K_USP]));
4717 }
4718
4719 DISAS_INSN(move_to_usp)
4720 {
4721 if (IS_USER(s)) {
4722 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4723 return;
4724 }
4725 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
4726 offsetof(CPUM68KState, sp[M68K_USP]));
4727 }
4728
4729 DISAS_INSN(halt)
4730 {
4731 if (IS_USER(s)) {
4732 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4733 return;
4734 }
4735
4736 gen_exception(s, s->pc, EXCP_HALT_INSN);
4737 }
4738
4739 DISAS_INSN(stop)
4740 {
4741 uint16_t ext;
4742
4743 if (IS_USER(s)) {
4744 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4745 return;
4746 }
4747
4748 ext = read_im16(env, s);
4749
4750 gen_set_sr_im(s, ext, 0);
4751 tcg_gen_movi_i32(cpu_halted, 1);
4752 gen_exception(s, s->pc, EXCP_HLT);
4753 }
4754
4755 DISAS_INSN(rte)
4756 {
4757 if (IS_USER(s)) {
4758 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4759 return;
4760 }
4761 gen_exception(s, s->base.pc_next, EXCP_RTE);
4762 }
4763
4764 DISAS_INSN(cf_movec)
4765 {
4766 uint16_t ext;
4767 TCGv reg;
4768
4769 if (IS_USER(s)) {
4770 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4771 return;
4772 }
4773
4774 ext = read_im16(env, s);
4775
4776 if (ext & 0x8000) {
4777 reg = AREG(ext, 12);
4778 } else {
4779 reg = DREG(ext, 12);
4780 }
4781 gen_helper_cf_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
4782 gen_exit_tb(s);
4783 }
4784
4785 DISAS_INSN(m68k_movec)
4786 {
4787 uint16_t ext;
4788 TCGv reg;
4789
4790 if (IS_USER(s)) {
4791 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4792 return;
4793 }
4794
4795 ext = read_im16(env, s);
4796
4797 if (ext & 0x8000) {
4798 reg = AREG(ext, 12);
4799 } else {
4800 reg = DREG(ext, 12);
4801 }
4802 if (insn & 1) {
4803 gen_helper_m68k_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
4804 } else {
4805 gen_helper_m68k_movec_from(reg, cpu_env, tcg_const_i32(ext & 0xfff));
4806 }
4807 gen_exit_tb(s);
4808 }
4809
4810 DISAS_INSN(intouch)
4811 {
4812 if (IS_USER(s)) {
4813 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4814 return;
4815 }
4816 /* ICache fetch. Implement as no-op. */
4817 }
4818
4819 DISAS_INSN(cpushl)
4820 {
4821 if (IS_USER(s)) {
4822 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4823 return;
4824 }
4825 /* Cache push/invalidate. Implement as no-op. */
4826 }
4827
4828 DISAS_INSN(cpush)
4829 {
4830 if (IS_USER(s)) {
4831 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4832 return;
4833 }
4834 /* Cache push/invalidate. Implement as no-op. */
4835 }
4836
4837 DISAS_INSN(cinv)
4838 {
4839 if (IS_USER(s)) {
4840 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4841 return;
4842 }
4843 /* Invalidate cache line. Implement as no-op. */
4844 }
4845
4846 #if defined(CONFIG_SOFTMMU)
4847 DISAS_INSN(pflush)
4848 {
4849 TCGv opmode;
4850
4851 if (IS_USER(s)) {
4852 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4853 return;
4854 }
4855
4856 opmode = tcg_const_i32((insn >> 3) & 3);
4857 gen_helper_pflush(cpu_env, AREG(insn, 0), opmode);
4858 tcg_temp_free(opmode);
4859 }
4860
4861 DISAS_INSN(ptest)
4862 {
4863 TCGv is_read;
4864
4865 if (IS_USER(s)) {
4866 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4867 return;
4868 }
4869 is_read = tcg_const_i32((insn >> 5) & 1);
4870 gen_helper_ptest(cpu_env, AREG(insn, 0), is_read);
4871 tcg_temp_free(is_read);
4872 }
4873 #endif
4874
4875 DISAS_INSN(wddata)
4876 {
4877 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4878 }
4879
4880 DISAS_INSN(wdebug)
4881 {
4882 if (IS_USER(s)) {
4883 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
4884 return;
4885 }
4886 /* TODO: Implement wdebug. */
4887 cpu_abort(env_cpu(env), "WDEBUG not implemented");
4888 }
4889 #endif
4890
4891 DISAS_INSN(trap)
4892 {
4893 gen_exception(s, s->base.pc_next, EXCP_TRAP0 + (insn & 0xf));
4894 }
4895
4896 static void gen_load_fcr(DisasContext *s, TCGv res, int reg)
4897 {
4898 switch (reg) {
4899 case M68K_FPIAR:
4900 tcg_gen_movi_i32(res, 0);
4901 break;
4902 case M68K_FPSR:
4903 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpsr));
4904 break;
4905 case M68K_FPCR:
4906 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpcr));
4907 break;
4908 }
4909 }
4910
4911 static void gen_store_fcr(DisasContext *s, TCGv val, int reg)
4912 {
4913 switch (reg) {
4914 case M68K_FPIAR:
4915 break;
4916 case M68K_FPSR:
4917 tcg_gen_st_i32(val, cpu_env, offsetof(CPUM68KState, fpsr));
4918 break;
4919 case M68K_FPCR:
4920 gen_helper_set_fpcr(cpu_env, val);
4921 break;
4922 }
4923 }
4924
4925 static void gen_qemu_store_fcr(DisasContext *s, TCGv addr, int reg)
4926 {
4927 int index = IS_USER(s);
4928 TCGv tmp;
4929
4930 tmp = tcg_temp_new();
4931 gen_load_fcr(s, tmp, reg);
4932 tcg_gen_qemu_st32(tmp, addr, index);
4933 tcg_temp_free(tmp);
4934 }
4935
4936 static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
4937 {
4938 int index = IS_USER(s);
4939 TCGv tmp;
4940
4941 tmp = tcg_temp_new();
4942 tcg_gen_qemu_ld32u(tmp, addr, index);
4943 gen_store_fcr(s, tmp, reg);
4944 tcg_temp_free(tmp);
4945 }
4946
4947
4948 static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
4949 uint32_t insn, uint32_t ext)
4950 {
4951 int mask = (ext >> 10) & 7;
4952 int is_write = (ext >> 13) & 1;
4953 int mode = extract32(insn, 3, 3);
4954 int i;
4955 TCGv addr, tmp;
4956
4957 switch (mode) {
4958 case 0: /* Dn */
4959 if (mask != M68K_FPIAR && mask != M68K_FPSR && mask != M68K_FPCR) {
4960 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4961 return;
4962 }
4963 if (is_write) {
4964 gen_load_fcr(s, DREG(insn, 0), mask);
4965 } else {
4966 gen_store_fcr(s, DREG(insn, 0), mask);
4967 }
4968 return;
4969 case 1: /* An, only with FPIAR */
4970 if (mask != M68K_FPIAR) {
4971 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4972 return;
4973 }
4974 if (is_write) {
4975 gen_load_fcr(s, AREG(insn, 0), mask);
4976 } else {
4977 gen_store_fcr(s, AREG(insn, 0), mask);
4978 }
4979 return;
4980 case 7: /* Immediate */
4981 if (REG(insn, 0) == 4) {
4982 if (is_write ||
4983 (mask != M68K_FPIAR && mask != M68K_FPSR &&
4984 mask != M68K_FPCR)) {
4985 gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
4986 return;
4987 }
4988 tmp = tcg_const_i32(read_im32(env, s));
4989 gen_store_fcr(s, tmp, mask);
4990 tcg_temp_free(tmp);
4991 return;
4992 }
4993 break;
4994 default:
4995 break;
4996 }
4997
4998 tmp = gen_lea(env, s, insn, OS_LONG);
4999 if (IS_NULL_QREG(tmp)) {
5000 gen_addr_fault(s);
5001 return;
5002 }
5003
5004 addr = tcg_temp_new();
5005 tcg_gen_mov_i32(addr, tmp);
5006
5007 /*
5008 * mask:
5009 *
5010 * 0b100 Floating-Point Control Register
5011 * 0b010 Floating-Point Status Register
5012 * 0b001 Floating-Point Instruction Address Register
5013 *
5014 */
5015
5016 if (is_write && mode == 4) {
5017 for (i = 2; i >= 0; i--, mask >>= 1) {
5018 if (mask & 1) {
5019 gen_qemu_store_fcr(s, addr, 1 << i);
5020 if (mask != 1) {
5021 tcg_gen_subi_i32(addr, addr, opsize_bytes(OS_LONG));
5022 }
5023 }
5024 }
5025 tcg_gen_mov_i32(AREG(insn, 0), addr);
5026 } else {
5027 for (i = 0; i < 3; i++, mask >>= 1) {
5028 if (mask & 1) {
5029 if (is_write) {
5030 gen_qemu_store_fcr(s, addr, 1 << i);
5031 } else {
5032 gen_qemu_load_fcr(s, addr, 1 << i);
5033 }
5034 if (mask != 1 || mode == 3) {
5035 tcg_gen_addi_i32(addr, addr, opsize_bytes(OS_LONG));
5036 }
5037 }
5038 }
5039 if (mode == 3) {
5040 tcg_gen_mov_i32(AREG(insn, 0), addr);
5041 }
5042 }
5043 tcg_temp_free_i32(addr);
5044 }
5045
5046 static void gen_op_fmovem(CPUM68KState *env, DisasContext *s,
5047 uint32_t insn, uint32_t ext)
5048 {
5049 int opsize;
5050 TCGv addr, tmp;
5051 int mode = (ext >> 11) & 0x3;
5052 int is_load = ((ext & 0x2000) == 0);
5053
5054 if (m68k_feature(s->env, M68K_FEATURE_FPU)) {
5055 opsize = OS_EXTENDED;
5056 } else {
5057 opsize = OS_DOUBLE; /* FIXME */
5058 }
5059
5060 addr = gen_lea(env, s, insn, opsize);
5061 if (IS_NULL_QREG(addr)) {
5062 gen_addr_fault(s);
5063 return;
5064 }
5065
5066 tmp = tcg_temp_new();
5067 if (mode & 0x1) {
5068 /* Dynamic register list */
5069 tcg_gen_ext8u_i32(tmp, DREG(ext, 4));
5070 } else {
5071 /* Static register list */
5072 tcg_gen_movi_i32(tmp, ext & 0xff);
5073 }
5074
5075 if (!is_load && (mode & 2) == 0) {
5076 /*
5077 * predecrement addressing mode
5078 * only available to store register to memory
5079 */
5080 if (opsize == OS_EXTENDED) {
5081 gen_helper_fmovemx_st_predec(tmp, cpu_env, addr, tmp);
5082 } else {
5083 gen_helper_fmovemd_st_predec(tmp, cpu_env, addr, tmp);
5084 }
5085 } else {
5086 /* postincrement addressing mode */
5087 if (opsize == OS_EXTENDED) {
5088 if (is_load) {
5089 gen_helper_fmovemx_ld_postinc(tmp, cpu_env, addr, tmp);
5090 } else {
5091 gen_helper_fmovemx_st_postinc(tmp, cpu_env, addr, tmp);
5092 }
5093 } else {
5094 if (is_load) {
5095 gen_helper_fmovemd_ld_postinc(tmp, cpu_env, addr, tmp);
5096 } else {
5097 gen_helper_fmovemd_st_postinc(tmp, cpu_env, addr, tmp);
5098 }
5099 }
5100 }
5101 if ((insn & 070) == 030 || (insn & 070) == 040) {
5102 tcg_gen_mov_i32(AREG(insn, 0), tmp);
5103 }
5104 tcg_temp_free(tmp);
5105 }
5106
5107 /*
5108 * ??? FP exceptions are not implemented. Most exceptions are deferred until
5109 * immediately before the next FP instruction is executed.
5110 */
5111 DISAS_INSN(fpu)
5112 {
5113 uint16_t ext;
5114 int opmode;
5115 int opsize;
5116 TCGv_ptr cpu_src, cpu_dest;
5117
5118 ext = read_im16(env, s);
5119 opmode = ext & 0x7f;
5120 switch ((ext >> 13) & 7) {
5121 case 0:
5122 break;
5123 case 1:
5124 goto undef;
5125 case 2:
5126 if (insn == 0xf200 && (ext & 0xfc00) == 0x5c00) {
5127 /* fmovecr */
5128 TCGv rom_offset = tcg_const_i32(opmode);
5129 cpu_dest = gen_fp_ptr(REG(ext, 7));
5130 gen_helper_fconst(cpu_env, cpu_dest, rom_offset);
5131 tcg_temp_free_ptr(cpu_dest);
5132 tcg_temp_free(rom_offset);
5133 return;
5134 }
5135 break;
5136 case 3: /* fmove out */
5137 cpu_src = gen_fp_ptr(REG(ext, 7));
5138 opsize = ext_opsize(ext, 10);
5139 if (gen_ea_fp(env, s, insn, opsize, cpu_src,
5140 EA_STORE, IS_USER(s)) == -1) {
5141 gen_addr_fault(s);
5142 }
5143 gen_helper_ftst(cpu_env, cpu_src);
5144 tcg_temp_free_ptr(cpu_src);
5145 return;
5146 case 4: /* fmove to control register. */
5147 case 5: /* fmove from control register. */
5148 gen_op_fmove_fcr(env, s, insn, ext);
5149 return;
5150 case 6: /* fmovem */
5151 case 7:
5152 if ((ext & 0x1000) == 0 && !m68k_feature(s->env, M68K_FEATURE_FPU)) {
5153 goto undef;
5154 }
5155 gen_op_fmovem(env, s, insn, ext);
5156 return;
5157 }
5158 if (ext & (1 << 14)) {
5159 /* Source effective address. */
5160 opsize = ext_opsize(ext, 10);
5161 cpu_src = gen_fp_result_ptr();
5162 if (gen_ea_fp(env, s, insn, opsize, cpu_src,
5163 EA_LOADS, IS_USER(s)) == -1) {
5164 gen_addr_fault(s);
5165 return;
5166 }
5167 } else {
5168 /* Source register. */
5169 opsize = OS_EXTENDED;
5170 cpu_src = gen_fp_ptr(REG(ext, 10));
5171 }
5172 cpu_dest = gen_fp_ptr(REG(ext, 7));
5173 switch (opmode) {
5174 case 0: /* fmove */
5175 gen_fp_move(cpu_dest, cpu_src);
5176 break;
5177 case 0x40: /* fsmove */
5178 gen_helper_fsround(cpu_env, cpu_dest, cpu_src);
5179 break;
5180 case 0x44: /* fdmove */
5181 gen_helper_fdround(cpu_env, cpu_dest, cpu_src);
5182 break;
5183 case 1: /* fint */
5184 gen_helper_firound(cpu_env, cpu_dest, cpu_src);
5185 break;
5186 case 2: /* fsinh */
5187 gen_helper_fsinh(cpu_env, cpu_dest, cpu_src);
5188 break;
5189 case 3: /* fintrz */
5190 gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src);
5191 break;
5192 case 4: /* fsqrt */
5193 gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src);
5194 break;
5195 case 0x41: /* fssqrt */
5196 gen_helper_fssqrt(cpu_env, cpu_dest, cpu_src);
5197 break;
5198 case 0x45: /* fdsqrt */
5199 gen_helper_fdsqrt(cpu_env, cpu_dest, cpu_src);
5200 break;
5201 case 0x06: /* flognp1 */
5202 gen_helper_flognp1(cpu_env, cpu_dest, cpu_src);
5203 break;
5204 case 0x08: /* fetoxm1 */
5205 gen_helper_fetoxm1(cpu_env, cpu_dest, cpu_src);
5206 break;
5207 case 0x09: /* ftanh */
5208 gen_helper_ftanh(cpu_env, cpu_dest, cpu_src);
5209 break;
5210 case 0x0a: /* fatan */
5211 gen_helper_fatan(cpu_env, cpu_dest, cpu_src);
5212 break;
5213 case 0x0c: /* fasin */
5214 gen_helper_fasin(cpu_env, cpu_dest, cpu_src);
5215 break;
5216 case 0x0d: /* fatanh */
5217 gen_helper_fatanh(cpu_env, cpu_dest, cpu_src);
5218 break;
5219 case 0x0e: /* fsin */
5220 gen_helper_fsin(cpu_env, cpu_dest, cpu_src);
5221 break;
5222 case 0x0f: /* ftan */
5223 gen_helper_ftan(cpu_env, cpu_dest, cpu_src);
5224 break;
5225 case 0x10: /* fetox */
5226 gen_helper_fetox(cpu_env, cpu_dest, cpu_src);
5227 break;
5228 case 0x11: /* ftwotox */
5229 gen_helper_ftwotox(cpu_env, cpu_dest, cpu_src);
5230 break;
5231 case 0x12: /* ftentox */
5232 gen_helper_ftentox(cpu_env, cpu_dest, cpu_src);
5233 break;
5234 case 0x14: /* flogn */
5235 gen_helper_flogn(cpu_env, cpu_dest, cpu_src);
5236 break;
5237 case 0x15: /* flog10 */
5238 gen_helper_flog10(cpu_env, cpu_dest, cpu_src);
5239 break;
5240 case 0x16: /* flog2 */
5241 gen_helper_flog2(cpu_env, cpu_dest, cpu_src);
5242 break;
5243 case 0x18: /* fabs */
5244 gen_helper_fabs(cpu_env, cpu_dest, cpu_src);
5245 break;
5246 case 0x58: /* fsabs */
5247 gen_helper_fsabs(cpu_env, cpu_dest, cpu_src);
5248 break;
5249 case 0x5c: /* fdabs */
5250 gen_helper_fdabs(cpu_env, cpu_dest, cpu_src);
5251 break;
5252 case 0x19: /* fcosh */
5253 gen_helper_fcosh(cpu_env, cpu_dest, cpu_src);
5254 break;
5255 case 0x1a: /* fneg */
5256 gen_helper_fneg(cpu_env, cpu_dest, cpu_src);
5257 break;
5258 case 0x5a: /* fsneg */
5259 gen_helper_fsneg(cpu_env, cpu_dest, cpu_src);
5260 break;
5261 case 0x5e: /* fdneg */
5262 gen_helper_fdneg(cpu_env, cpu_dest, cpu_src);
5263 break;
5264 case 0x1c: /* facos */
5265 gen_helper_facos(cpu_env, cpu_dest, cpu_src);
5266 break;
5267 case 0x1d: /* fcos */
5268 gen_helper_fcos(cpu_env, cpu_dest, cpu_src);
5269 break;
5270 case 0x1e: /* fgetexp */
5271 gen_helper_fgetexp(cpu_env, cpu_dest, cpu_src);
5272 break;
5273 case 0x1f: /* fgetman */
5274 gen_helper_fgetman(cpu_env, cpu_dest, cpu_src);
5275 break;
5276 case 0x20: /* fdiv */
5277 gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5278 break;
5279 case 0x60: /* fsdiv */
5280 gen_helper_fsdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5281 break;
5282 case 0x64: /* fddiv */
5283 gen_helper_fddiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5284 break;
5285 case 0x21: /* fmod */
5286 gen_helper_fmod(cpu_env, cpu_dest, cpu_src, cpu_dest);
5287 break;
5288 case 0x22: /* fadd */
5289 gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
5290 break;
5291 case 0x62: /* fsadd */
5292 gen_helper_fsadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
5293 break;
5294 case 0x66: /* fdadd */
5295 gen_helper_fdadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
5296 break;
5297 case 0x23: /* fmul */
5298 gen_helper_fmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5299 break;
5300 case 0x63: /* fsmul */
5301 gen_helper_fsmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5302 break;
5303 case 0x67: /* fdmul */
5304 gen_helper_fdmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5305 break;
5306 case 0x24: /* fsgldiv */
5307 gen_helper_fsgldiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5308 break;
5309 case 0x25: /* frem */
5310 gen_helper_frem(cpu_env, cpu_dest, cpu_src, cpu_dest);
5311 break;
5312 case 0x26: /* fscale */
5313 gen_helper_fscale(cpu_env, cpu_dest, cpu_src, cpu_dest);
5314 break;
5315 case 0x27: /* fsglmul */
5316 gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5317 break;
5318 case 0x28: /* fsub */
5319 gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
5320 break;
5321 case 0x68: /* fssub */
5322 gen_helper_fssub(cpu_env, cpu_dest, cpu_src, cpu_dest);
5323 break;
5324 case 0x6c: /* fdsub */
5325 gen_helper_fdsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
5326 break;
5327 case 0x30: case 0x31: case 0x32:
5328 case 0x33: case 0x34: case 0x35:
5329 case 0x36: case 0x37: {
5330 TCGv_ptr cpu_dest2 = gen_fp_ptr(REG(ext, 0));
5331 gen_helper_fsincos(cpu_env, cpu_dest, cpu_dest2, cpu_src);
5332 tcg_temp_free_ptr(cpu_dest2);
5333 }
5334 break;
5335 case 0x38: /* fcmp */
5336 gen_helper_fcmp(cpu_env, cpu_src, cpu_dest);
5337 return;
5338 case 0x3a: /* ftst */
5339 gen_helper_ftst(cpu_env, cpu_src);
5340 return;
5341 default:
5342 goto undef;
5343 }
5344 tcg_temp_free_ptr(cpu_src);
5345 gen_helper_ftst(cpu_env, cpu_dest);
5346 tcg_temp_free_ptr(cpu_dest);
5347 return;
5348 undef:
5349 /* FIXME: Is this right for offset addressing modes? */
5350 s->pc -= 2;
5351 disas_undef_fpu(env, s, insn);
5352 }
5353
5354 static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
5355 {
5356 TCGv fpsr;
5357
5358 c->g1 = 1;
5359 c->v2 = tcg_const_i32(0);
5360 c->g2 = 0;
5361 /* TODO: Raise BSUN exception. */
5362 fpsr = tcg_temp_new();
5363 gen_load_fcr(s, fpsr, M68K_FPSR);
5364 switch (cond) {
5365 case 0: /* False */
5366 case 16: /* Signaling False */
5367 c->v1 = c->v2;
5368 c->tcond = TCG_COND_NEVER;
5369 break;
5370 case 1: /* EQual Z */
5371 case 17: /* Signaling EQual Z */
5372 c->v1 = tcg_temp_new();
5373 c->g1 = 0;
5374 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5375 c->tcond = TCG_COND_NE;
5376 break;
5377 case 2: /* Ordered Greater Than !(A || Z || N) */
5378 case 18: /* Greater Than !(A || Z || N) */
5379 c->v1 = tcg_temp_new();
5380 c->g1 = 0;
5381 tcg_gen_andi_i32(c->v1, fpsr,
5382 FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
5383 c->tcond = TCG_COND_EQ;
5384 break;
5385 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
5386 case 19: /* Greater than or Equal Z || !(A || N) */
5387 c->v1 = tcg_temp_new();
5388 c->g1 = 0;
5389 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5390 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
5391 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_Z | FPSR_CC_N);
5392 tcg_gen_or_i32(c->v1, c->v1, fpsr);
5393 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
5394 c->tcond = TCG_COND_NE;
5395 break;
5396 case 4: /* Ordered Less Than !(!N || A || Z); */
5397 case 20: /* Less Than !(!N || A || Z); */
5398 c->v1 = tcg_temp_new();
5399 c->g1 = 0;
5400 tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N);
5401 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z);
5402 c->tcond = TCG_COND_EQ;
5403 break;
5404 case 5: /* Ordered Less than or Equal Z || (N && !A) */
5405 case 21: /* Less than or Equal Z || (N && !A) */
5406 c->v1 = tcg_temp_new();
5407 c->g1 = 0;
5408 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5409 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
5410 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
5411 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_Z | FPSR_CC_N);
5412 c->tcond = TCG_COND_NE;
5413 break;
5414 case 6: /* Ordered Greater or Less than !(A || Z) */
5415 case 22: /* Greater or Less than !(A || Z) */
5416 c->v1 = tcg_temp_new();
5417 c->g1 = 0;
5418 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
5419 c->tcond = TCG_COND_EQ;
5420 break;
5421 case 7: /* Ordered !A */
5422 case 23: /* Greater, Less or Equal !A */
5423 c->v1 = tcg_temp_new();
5424 c->g1 = 0;
5425 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5426 c->tcond = TCG_COND_EQ;
5427 break;
5428 case 8: /* Unordered A */
5429 case 24: /* Not Greater, Less or Equal A */
5430 c->v1 = tcg_temp_new();
5431 c->g1 = 0;
5432 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5433 c->tcond = TCG_COND_NE;
5434 break;
5435 case 9: /* Unordered or Equal A || Z */
5436 case 25: /* Not Greater or Less then A || Z */
5437 c->v1 = tcg_temp_new();
5438 c->g1 = 0;
5439 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
5440 c->tcond = TCG_COND_NE;
5441 break;
5442 case 10: /* Unordered or Greater Than A || !(N || Z)) */
5443 case 26: /* Not Less or Equal A || !(N || Z)) */
5444 c->v1 = tcg_temp_new();
5445 c->g1 = 0;
5446 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5447 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
5448 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_A | FPSR_CC_N);
5449 tcg_gen_or_i32(c->v1, c->v1, fpsr);
5450 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
5451 c->tcond = TCG_COND_NE;
5452 break;
5453 case 11: /* Unordered or Greater or Equal A || Z || !N */
5454 case 27: /* Not Less Than A || Z || !N */
5455 c->v1 = tcg_temp_new();
5456 c->g1 = 0;
5457 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
5458 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
5459 c->tcond = TCG_COND_NE;
5460 break;
5461 case 12: /* Unordered or Less Than A || (N && !Z) */
5462 case 28: /* Not Greater than or Equal A || (N && !Z) */
5463 c->v1 = tcg_temp_new();
5464 c->g1 = 0;
5465 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5466 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
5467 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
5468 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_A | FPSR_CC_N);
5469 c->tcond = TCG_COND_NE;
5470 break;
5471 case 13: /* Unordered or Less or Equal A || Z || N */
5472 case 29: /* Not Greater Than A || Z || N */
5473 c->v1 = tcg_temp_new();
5474 c->g1 = 0;
5475 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
5476 c->tcond = TCG_COND_NE;
5477 break;
5478 case 14: /* Not Equal !Z */
5479 case 30: /* Signaling Not Equal !Z */
5480 c->v1 = tcg_temp_new();
5481 c->g1 = 0;
5482 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5483 c->tcond = TCG_COND_EQ;
5484 break;
5485 case 15: /* True */
5486 case 31: /* Signaling True */
5487 c->v1 = c->v2;
5488 c->tcond = TCG_COND_ALWAYS;
5489 break;
5490 }
5491 tcg_temp_free(fpsr);
5492 }
5493
5494 static void gen_fjmpcc(DisasContext *s, int cond, TCGLabel *l1)
5495 {
5496 DisasCompare c;
5497
5498 gen_fcc_cond(&c, s, cond);
5499 update_cc_op(s);
5500 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
5501 free_cond(&c);
5502 }
5503
5504 DISAS_INSN(fbcc)
5505 {
5506 uint32_t offset;
5507 uint32_t base;
5508 TCGLabel *l1;
5509
5510 base = s->pc;
5511 offset = (int16_t)read_im16(env, s);
5512 if (insn & (1 << 6)) {
5513 offset = (offset << 16) | read_im16(env, s);
5514 }
5515
5516 l1 = gen_new_label();
5517 update_cc_op(s);
5518 gen_fjmpcc(s, insn & 0x3f, l1);
5519 gen_jmp_tb(s, 0, s->pc);
5520 gen_set_label(l1);
5521 gen_jmp_tb(s, 1, base + offset);
5522 }
5523
5524 DISAS_INSN(fscc)
5525 {
5526 DisasCompare c;
5527 int cond;
5528 TCGv tmp;
5529 uint16_t ext;
5530
5531 ext = read_im16(env, s);
5532 cond = ext & 0x3f;
5533 gen_fcc_cond(&c, s, cond);
5534
5535 tmp = tcg_temp_new();
5536 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
5537 free_cond(&c);
5538
5539 tcg_gen_neg_i32(tmp, tmp);
5540 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
5541 tcg_temp_free(tmp);
5542 }
5543
5544 #if defined(CONFIG_SOFTMMU)
5545 DISAS_INSN(frestore)
5546 {
5547 TCGv addr;
5548
5549 if (IS_USER(s)) {
5550 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
5551 return;
5552 }
5553 if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
5554 SRC_EA(env, addr, OS_LONG, 0, NULL);
5555 /* FIXME: check the state frame */
5556 } else {
5557 disas_undef(env, s, insn);
5558 }
5559 }
5560
5561 DISAS_INSN(fsave)
5562 {
5563 if (IS_USER(s)) {
5564 gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
5565 return;
5566 }
5567
5568 if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
5569 /* always write IDLE */
5570 TCGv idle = tcg_const_i32(0x41000000);
5571 DEST_EA(env, insn, OS_LONG, idle, NULL);
5572 tcg_temp_free(idle);
5573 } else {
5574 disas_undef(env, s, insn);
5575 }
5576 }
5577 #endif
5578
5579 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
5580 {
5581 TCGv tmp = tcg_temp_new();
5582 if (s->env->macsr & MACSR_FI) {
5583 if (upper)
5584 tcg_gen_andi_i32(tmp, val, 0xffff0000);
5585 else
5586 tcg_gen_shli_i32(tmp, val, 16);
5587 } else if (s->env->macsr & MACSR_SU) {
5588 if (upper)
5589 tcg_gen_sari_i32(tmp, val, 16);
5590 else
5591 tcg_gen_ext16s_i32(tmp, val);
5592 } else {
5593 if (upper)
5594 tcg_gen_shri_i32(tmp, val, 16);
5595 else
5596 tcg_gen_ext16u_i32(tmp, val);
5597 }
5598 return tmp;
5599 }
5600
5601 static void gen_mac_clear_flags(void)
5602 {
5603 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
5604 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
5605 }
5606
5607 DISAS_INSN(mac)
5608 {
5609 TCGv rx;
5610 TCGv ry;
5611 uint16_t ext;
5612 int acc;
5613 TCGv tmp;
5614 TCGv addr;
5615 TCGv loadval;
5616 int dual;
5617 TCGv saved_flags;
5618
5619 if (!s->done_mac) {
5620 s->mactmp = tcg_temp_new_i64();
5621 s->done_mac = 1;
5622 }
5623
5624 ext = read_im16(env, s);
5625
5626 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
5627 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
5628 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
5629 disas_undef(env, s, insn);
5630 return;
5631 }
5632 if (insn & 0x30) {
5633 /* MAC with load. */
5634 tmp = gen_lea(env, s, insn, OS_LONG);
5635 addr = tcg_temp_new();
5636 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
5637 /*
5638 * Load the value now to ensure correct exception behavior.
5639 * Perform writeback after reading the MAC inputs.
5640 */
5641 loadval = gen_load(s, OS_LONG, addr, 0, IS_USER(s));
5642
5643 acc ^= 1;
5644 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
5645 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
5646 } else {
5647 loadval = addr = NULL_QREG;
5648 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
5649 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5650 }
5651
5652 gen_mac_clear_flags();
5653 #if 0
5654 l1 = -1;
5655 /* Disabled because conditional branches clobber temporary vars. */
5656 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
5657 /* Skip the multiply if we know we will ignore it. */
5658 l1 = gen_new_label();
5659 tmp = tcg_temp_new();
5660 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
5661 gen_op_jmp_nz32(tmp, l1);
5662 }
5663 #endif
5664
5665 if ((ext & 0x0800) == 0) {
5666 /* Word. */
5667 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
5668 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
5669 }
5670 if (s->env->macsr & MACSR_FI) {
5671 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
5672 } else {
5673 if (s->env->macsr & MACSR_SU)
5674 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
5675 else
5676 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
5677 switch ((ext >> 9) & 3) {
5678 case 1:
5679 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
5680 break;
5681 case 3:
5682 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
5683 break;
5684 }
5685 }
5686
5687 if (dual) {
5688 /* Save the overflow flag from the multiply. */
5689 saved_flags = tcg_temp_new();
5690 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
5691 } else {
5692 saved_flags = NULL_QREG;
5693 }
5694
5695 #if 0
5696 /* Disabled because conditional branches clobber temporary vars. */
5697 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
5698 /* Skip the accumulate if the value is already saturated. */
5699 l1 = gen_new_label();
5700 tmp = tcg_temp_new();
5701 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
5702 gen_op_jmp_nz32(tmp, l1);
5703 }
5704 #endif
5705
5706 if (insn & 0x100)
5707 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
5708 else
5709 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
5710
5711 if (s->env->macsr & MACSR_FI)
5712 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
5713 else if (s->env->macsr & MACSR_SU)
5714 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
5715 else
5716 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5717
5718 #if 0
5719 /* Disabled because conditional branches clobber temporary vars. */
5720 if (l1 != -1)
5721 gen_set_label(l1);
5722 #endif
5723
5724 if (dual) {
5725 /* Dual accumulate variant. */
5726 acc = (ext >> 2) & 3;
5727 /* Restore the overflow flag from the multiplier. */
5728 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
5729 #if 0
5730 /* Disabled because conditional branches clobber temporary vars. */
5731 if ((s->env->macsr & MACSR_OMC) != 0) {
5732 /* Skip the accumulate if the value is already saturated. */
5733 l1 = gen_new_label();
5734 tmp = tcg_temp_new();
5735 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
5736 gen_op_jmp_nz32(tmp, l1);
5737 }
5738 #endif
5739 if (ext & 2)
5740 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
5741 else
5742 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
5743 if (s->env->macsr & MACSR_FI)
5744 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
5745 else if (s->env->macsr & MACSR_SU)
5746 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
5747 else
5748 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5749 #if 0
5750 /* Disabled because conditional branches clobber temporary vars. */
5751 if (l1 != -1)
5752 gen_set_label(l1);
5753 #endif
5754 }
5755 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
5756
5757 if (insn & 0x30) {
5758 TCGv rw;
5759 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
5760 tcg_gen_mov_i32(rw, loadval);
5761 /*
5762 * FIXME: Should address writeback happen with the masked or
5763 * unmasked value?
5764 */
5765 switch ((insn >> 3) & 7) {
5766 case 3: /* Post-increment. */
5767 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
5768 break;
5769 case 4: /* Pre-decrement. */
5770 tcg_gen_mov_i32(AREG(insn, 0), addr);
5771 }
5772 tcg_temp_free(loadval);
5773 }
5774 }
5775
5776 DISAS_INSN(from_mac)
5777 {
5778 TCGv rx;
5779 TCGv_i64 acc;
5780 int accnum;
5781
5782 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5783 accnum = (insn >> 9) & 3;
5784 acc = MACREG(accnum);
5785 if (s->env->macsr & MACSR_FI) {
5786 gen_helper_get_macf(rx, cpu_env, acc);
5787 } else if ((s->env->macsr & MACSR_OMC) == 0) {
5788 tcg_gen_extrl_i64_i32(rx, acc);
5789 } else if (s->env->macsr & MACSR_SU) {
5790 gen_helper_get_macs(rx, acc);
5791 } else {
5792 gen_helper_get_macu(rx, acc);
5793 }
5794 if (insn & 0x40) {
5795 tcg_gen_movi_i64(acc, 0);
5796 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5797 }
5798 }
5799
5800 DISAS_INSN(move_mac)
5801 {
5802 /* FIXME: This can be done without a helper. */
5803 int src;
5804 TCGv dest;
5805 src = insn & 3;
5806 dest = tcg_const_i32((insn >> 9) & 3);
5807 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
5808 gen_mac_clear_flags();
5809 gen_helper_mac_set_flags(cpu_env, dest);
5810 }
5811
5812 DISAS_INSN(from_macsr)
5813 {
5814 TCGv reg;
5815
5816 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5817 tcg_gen_mov_i32(reg, QREG_MACSR);
5818 }
5819
5820 DISAS_INSN(from_mask)
5821 {
5822 TCGv reg;
5823 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5824 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
5825 }
5826
5827 DISAS_INSN(from_mext)
5828 {
5829 TCGv reg;
5830 TCGv acc;
5831 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5832 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
5833 if (s->env->macsr & MACSR_FI)
5834 gen_helper_get_mac_extf(reg, cpu_env, acc);
5835 else
5836 gen_helper_get_mac_exti(reg, cpu_env, acc);
5837 }
5838
5839 DISAS_INSN(macsr_to_ccr)
5840 {
5841 TCGv tmp = tcg_temp_new();
5842 tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
5843 gen_helper_set_sr(cpu_env, tmp);
5844 tcg_temp_free(tmp);
5845 set_cc_op(s, CC_OP_FLAGS);
5846 }
5847
5848 DISAS_INSN(to_mac)
5849 {
5850 TCGv_i64 acc;
5851 TCGv val;
5852 int accnum;
5853 accnum = (insn >> 9) & 3;
5854 acc = MACREG(accnum);
5855 SRC_EA(env, val, OS_LONG, 0, NULL);
5856 if (s->env->macsr & MACSR_FI) {
5857 tcg_gen_ext_i32_i64(acc, val);
5858 tcg_gen_shli_i64(acc, acc, 8);
5859 } else if (s->env->macsr & MACSR_SU) {
5860 tcg_gen_ext_i32_i64(acc, val);
5861 } else {
5862 tcg_gen_extu_i32_i64(acc, val);
5863 }
5864 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5865 gen_mac_clear_flags();
5866 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
5867 }
5868
5869 DISAS_INSN(to_macsr)
5870 {
5871 TCGv val;
5872 SRC_EA(env, val, OS_LONG, 0, NULL);
5873 gen_helper_set_macsr(cpu_env, val);
5874 gen_exit_tb(s);
5875 }
5876
5877 DISAS_INSN(to_mask)
5878 {
5879 TCGv val;
5880 SRC_EA(env, val, OS_LONG, 0, NULL);
5881 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
5882 }
5883
5884 DISAS_INSN(to_mext)
5885 {
5886 TCGv val;
5887 TCGv acc;
5888 SRC_EA(env, val, OS_LONG, 0, NULL);
5889 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
5890 if (s->env->macsr & MACSR_FI)
5891 gen_helper_set_mac_extf(cpu_env, val, acc);
5892 else if (s->env->macsr & MACSR_SU)
5893 gen_helper_set_mac_exts(cpu_env, val, acc);
5894 else
5895 gen_helper_set_mac_extu(cpu_env, val, acc);
5896 }
5897
5898 static disas_proc opcode_table[65536];
5899
5900 static void
5901 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
5902 {
5903 int i;
5904 int from;
5905 int to;
5906
5907 /* Sanity check. All set bits must be included in the mask. */
5908 if (opcode & ~mask) {
5909 fprintf(stderr,
5910 "qemu internal error: bogus opcode definition %04x/%04x\n",
5911 opcode, mask);
5912 abort();
5913 }
5914 /*
5915 * This could probably be cleverer. For now just optimize the case where
5916 * the top bits are known.
5917 */
5918 /* Find the first zero bit in the mask. */
5919 i = 0x8000;
5920 while ((i & mask) != 0)
5921 i >>= 1;
5922 /* Iterate over all combinations of this and lower bits. */
5923 if (i == 0)
5924 i = 1;
5925 else
5926 i <<= 1;
5927 from = opcode & ~(i - 1);
5928 to = from + i;
5929 for (i = from; i < to; i++) {
5930 if ((i & mask) == opcode)
5931 opcode_table[i] = proc;
5932 }
5933 }
5934
5935 /*
5936 * Register m68k opcode handlers. Order is important.
5937 * Later insn override earlier ones.
5938 */
5939 void register_m68k_insns (CPUM68KState *env)
5940 {
5941 /*
5942 * Build the opcode table only once to avoid
5943 * multithreading issues.
5944 */
5945 if (opcode_table[0] != NULL) {
5946 return;
5947 }
5948
5949 /*
5950 * use BASE() for instruction available
5951 * for CF_ISA_A and M68000.
5952 */
5953 #define BASE(name, opcode, mask) \
5954 register_opcode(disas_##name, 0x##opcode, 0x##mask)
5955 #define INSN(name, opcode, mask, feature) do { \
5956 if (m68k_feature(env, M68K_FEATURE_##feature)) \
5957 BASE(name, opcode, mask); \
5958 } while(0)
5959 BASE(undef, 0000, 0000);
5960 INSN(arith_im, 0080, fff8, CF_ISA_A);
5961 INSN(arith_im, 0000, ff00, M68000);
5962 INSN(chk2, 00c0, f9c0, CHK2);
5963 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
5964 BASE(bitop_reg, 0100, f1c0);
5965 BASE(bitop_reg, 0140, f1c0);
5966 BASE(bitop_reg, 0180, f1c0);
5967 BASE(bitop_reg, 01c0, f1c0);
5968 INSN(movep, 0108, f138, MOVEP);
5969 INSN(arith_im, 0280, fff8, CF_ISA_A);
5970 INSN(arith_im, 0200, ff00, M68000);
5971 INSN(undef, 02c0, ffc0, M68000);
5972 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
5973 INSN(arith_im, 0480, fff8, CF_ISA_A);
5974 INSN(arith_im, 0400, ff00, M68000);
5975 INSN(undef, 04c0, ffc0, M68000);
5976 INSN(arith_im, 0600, ff00, M68000);
5977 INSN(undef, 06c0, ffc0, M68000);
5978 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
5979 INSN(arith_im, 0680, fff8, CF_ISA_A);
5980 INSN(arith_im, 0c00, ff38, CF_ISA_A);
5981 INSN(arith_im, 0c00, ff00, M68000);
5982 BASE(bitop_im, 0800, ffc0);
5983 BASE(bitop_im, 0840, ffc0);
5984 BASE(bitop_im, 0880, ffc0);
5985 BASE(bitop_im, 08c0, ffc0);
5986 INSN(arith_im, 0a80, fff8, CF_ISA_A);
5987 INSN(arith_im, 0a00, ff00, M68000);
5988 #if defined(CONFIG_SOFTMMU)
5989 INSN(moves, 0e00, ff00, M68000);
5990 #endif
5991 INSN(cas, 0ac0, ffc0, CAS);
5992 INSN(cas, 0cc0, ffc0, CAS);
5993 INSN(cas, 0ec0, ffc0, CAS);
5994 INSN(cas2w, 0cfc, ffff, CAS);
5995 INSN(cas2l, 0efc, ffff, CAS);
5996 BASE(move, 1000, f000);
5997 BASE(move, 2000, f000);
5998 BASE(move, 3000, f000);
5999 INSN(chk, 4000, f040, M68000);
6000 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
6001 INSN(negx, 4080, fff8, CF_ISA_A);
6002 INSN(negx, 4000, ff00, M68000);
6003 INSN(undef, 40c0, ffc0, M68000);
6004 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
6005 INSN(move_from_sr, 40c0, ffc0, M68000);
6006 BASE(lea, 41c0, f1c0);
6007 BASE(clr, 4200, ff00);
6008 BASE(undef, 42c0, ffc0);
6009 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
6010 INSN(move_from_ccr, 42c0, ffc0, M68000);
6011 INSN(neg, 4480, fff8, CF_ISA_A);
6012 INSN(neg, 4400, ff00, M68000);
6013 INSN(undef, 44c0, ffc0, M68000);
6014 BASE(move_to_ccr, 44c0, ffc0);
6015 INSN(not, 4680, fff8, CF_ISA_A);
6016 INSN(not, 4600, ff00, M68000);
6017 #if defined(CONFIG_SOFTMMU)
6018 BASE(move_to_sr, 46c0, ffc0);
6019 #endif
6020 INSN(nbcd, 4800, ffc0, M68000);
6021 INSN(linkl, 4808, fff8, M68000);
6022 BASE(pea, 4840, ffc0);
6023 BASE(swap, 4840, fff8);
6024 INSN(bkpt, 4848, fff8, BKPT);
6025 INSN(movem, 48d0, fbf8, CF_ISA_A);
6026 INSN(movem, 48e8, fbf8, CF_ISA_A);
6027 INSN(movem, 4880, fb80, M68000);
6028 BASE(ext, 4880, fff8);
6029 BASE(ext, 48c0, fff8);
6030 BASE(ext, 49c0, fff8);
6031 BASE(tst, 4a00, ff00);
6032 INSN(tas, 4ac0, ffc0, CF_ISA_B);
6033 INSN(tas, 4ac0, ffc0, M68000);
6034 #if defined(CONFIG_SOFTMMU)
6035 INSN(halt, 4ac8, ffff, CF_ISA_A);
6036 #endif
6037 INSN(pulse, 4acc, ffff, CF_ISA_A);
6038 BASE(illegal, 4afc, ffff);
6039 INSN(mull, 4c00, ffc0, CF_ISA_A);
6040 INSN(mull, 4c00, ffc0, LONG_MULDIV);
6041 INSN(divl, 4c40, ffc0, CF_ISA_A);
6042 INSN(divl, 4c40, ffc0, LONG_MULDIV);
6043 INSN(sats, 4c80, fff8, CF_ISA_B);
6044 BASE(trap, 4e40, fff0);
6045 BASE(link, 4e50, fff8);
6046 BASE(unlk, 4e58, fff8);
6047 #if defined(CONFIG_SOFTMMU)
6048 INSN(move_to_usp, 4e60, fff8, USP);
6049 INSN(move_from_usp, 4e68, fff8, USP);
6050 INSN(reset, 4e70, ffff, M68000);
6051 BASE(stop, 4e72, ffff);
6052 BASE(rte, 4e73, ffff);
6053 INSN(cf_movec, 4e7b, ffff, CF_ISA_A);
6054 INSN(m68k_movec, 4e7a, fffe, MOVEC);
6055 #endif
6056 BASE(nop, 4e71, ffff);
6057 INSN(rtd, 4e74, ffff, RTD);
6058 BASE(rts, 4e75, ffff);
6059 INSN(rtr, 4e77, ffff, M68000);
6060 BASE(jump, 4e80, ffc0);
6061 BASE(jump, 4ec0, ffc0);
6062 INSN(addsubq, 5000, f080, M68000);
6063 BASE(addsubq, 5080, f0c0);
6064 INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */
6065 INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */
6066 INSN(dbcc, 50c8, f0f8, M68000);
6067 INSN(tpf, 51f8, fff8, CF_ISA_A);
6068
6069 /* Branch instructions. */
6070 BASE(branch, 6000, f000);
6071 /* Disable long branch instructions, then add back the ones we want. */
6072 BASE(undef, 60ff, f0ff); /* All long branches. */
6073 INSN(branch, 60ff, f0ff, CF_ISA_B);
6074 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
6075 INSN(branch, 60ff, ffff, BRAL);
6076 INSN(branch, 60ff, f0ff, BCCL);
6077
6078 BASE(moveq, 7000, f100);
6079 INSN(mvzs, 7100, f100, CF_ISA_B);
6080 BASE(or, 8000, f000);
6081 BASE(divw, 80c0, f0c0);
6082 INSN(sbcd_reg, 8100, f1f8, M68000);
6083 INSN(sbcd_mem, 8108, f1f8, M68000);
6084 BASE(addsub, 9000, f000);
6085 INSN(undef, 90c0, f0c0, CF_ISA_A);
6086 INSN(subx_reg, 9180, f1f8, CF_ISA_A);
6087 INSN(subx_reg, 9100, f138, M68000);
6088 INSN(subx_mem, 9108, f138, M68000);
6089 INSN(suba, 91c0, f1c0, CF_ISA_A);
6090 INSN(suba, 90c0, f0c0, M68000);
6091
6092 BASE(undef_mac, a000, f000);
6093 INSN(mac, a000, f100, CF_EMAC);
6094 INSN(from_mac, a180, f9b0, CF_EMAC);
6095 INSN(move_mac, a110, f9fc, CF_EMAC);
6096 INSN(from_macsr,a980, f9f0, CF_EMAC);
6097 INSN(from_mask, ad80, fff0, CF_EMAC);
6098 INSN(from_mext, ab80, fbf0, CF_EMAC);
6099 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
6100 INSN(to_mac, a100, f9c0, CF_EMAC);
6101 INSN(to_macsr, a900, ffc0, CF_EMAC);
6102 INSN(to_mext, ab00, fbc0, CF_EMAC);
6103 INSN(to_mask, ad00, ffc0, CF_EMAC);
6104
6105 INSN(mov3q, a140, f1c0, CF_ISA_B);
6106 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
6107 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
6108 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
6109 INSN(cmp, b080, f1c0, CF_ISA_A);
6110 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
6111 INSN(cmp, b000, f100, M68000);
6112 INSN(eor, b100, f100, M68000);
6113 INSN(cmpm, b108, f138, M68000);
6114 INSN(cmpa, b0c0, f0c0, M68000);
6115 INSN(eor, b180, f1c0, CF_ISA_A);
6116 BASE(and, c000, f000);
6117 INSN(exg_dd, c140, f1f8, M68000);
6118 INSN(exg_aa, c148, f1f8, M68000);
6119 INSN(exg_da, c188, f1f8, M68000);
6120 BASE(mulw, c0c0, f0c0);
6121 INSN(abcd_reg, c100, f1f8, M68000);
6122 INSN(abcd_mem, c108, f1f8, M68000);
6123 BASE(addsub, d000, f000);
6124 INSN(undef, d0c0, f0c0, CF_ISA_A);
6125 INSN(addx_reg, d180, f1f8, CF_ISA_A);
6126 INSN(addx_reg, d100, f138, M68000);
6127 INSN(addx_mem, d108, f138, M68000);
6128 INSN(adda, d1c0, f1c0, CF_ISA_A);
6129 INSN(adda, d0c0, f0c0, M68000);
6130 INSN(shift_im, e080, f0f0, CF_ISA_A);
6131 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
6132 INSN(shift8_im, e000, f0f0, M68000);
6133 INSN(shift16_im, e040, f0f0, M68000);
6134 INSN(shift_im, e080, f0f0, M68000);
6135 INSN(shift8_reg, e020, f0f0, M68000);
6136 INSN(shift16_reg, e060, f0f0, M68000);
6137 INSN(shift_reg, e0a0, f0f0, M68000);
6138 INSN(shift_mem, e0c0, fcc0, M68000);
6139 INSN(rotate_im, e090, f0f0, M68000);
6140 INSN(rotate8_im, e010, f0f0, M68000);
6141 INSN(rotate16_im, e050, f0f0, M68000);
6142 INSN(rotate_reg, e0b0, f0f0, M68000);
6143 INSN(rotate8_reg, e030, f0f0, M68000);
6144 INSN(rotate16_reg, e070, f0f0, M68000);
6145 INSN(rotate_mem, e4c0, fcc0, M68000);
6146 INSN(bfext_mem, e9c0, fdc0, BITFIELD); /* bfextu & bfexts */
6147 INSN(bfext_reg, e9c0, fdf8, BITFIELD);
6148 INSN(bfins_mem, efc0, ffc0, BITFIELD);
6149 INSN(bfins_reg, efc0, fff8, BITFIELD);
6150 INSN(bfop_mem, eac0, ffc0, BITFIELD); /* bfchg */
6151 INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */
6152 INSN(bfop_mem, ecc0, ffc0, BITFIELD); /* bfclr */
6153 INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */
6154 INSN(bfop_mem, edc0, ffc0, BITFIELD); /* bfffo */
6155 INSN(bfop_reg, edc0, fff8, BITFIELD); /* bfffo */
6156 INSN(bfop_mem, eec0, ffc0, BITFIELD); /* bfset */
6157 INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */
6158 INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */
6159 INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */
6160 BASE(undef_fpu, f000, f000);
6161 INSN(fpu, f200, ffc0, CF_FPU);
6162 INSN(fbcc, f280, ffc0, CF_FPU);
6163 INSN(fpu, f200, ffc0, FPU);
6164 INSN(fscc, f240, ffc0, FPU);
6165 INSN(fbcc, f280, ff80, FPU);
6166 #if defined(CONFIG_SOFTMMU)
6167 INSN(frestore, f340, ffc0, CF_FPU);
6168 INSN(fsave, f300, ffc0, CF_FPU);
6169 INSN(frestore, f340, ffc0, FPU);
6170 INSN(fsave, f300, ffc0, FPU);
6171 INSN(intouch, f340, ffc0, CF_ISA_A);
6172 INSN(cpushl, f428, ff38, CF_ISA_A);
6173 INSN(cpush, f420, ff20, M68040);
6174 INSN(cinv, f400, ff20, M68040);
6175 INSN(pflush, f500, ffe0, M68040);
6176 INSN(ptest, f548, ffd8, M68040);
6177 INSN(wddata, fb00, ff00, CF_ISA_A);
6178 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
6179 #endif
6180 INSN(move16_mem, f600, ffe0, M68040);
6181 INSN(move16_reg, f620, fff8, M68040);
6182 #undef INSN
6183 }
6184
6185 static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
6186 {
6187 DisasContext *dc = container_of(dcbase, DisasContext, base);
6188 CPUM68KState *env = cpu->env_ptr;
6189
6190 dc->env = env;
6191 dc->pc = dc->base.pc_first;
6192 dc->cc_op = CC_OP_DYNAMIC;
6193 dc->cc_op_synced = 1;
6194 dc->done_mac = 0;
6195 dc->writeback_mask = 0;
6196 init_release_array(dc);
6197 }
6198
6199 static void m68k_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
6200 {
6201 }
6202
6203 static void m68k_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
6204 {
6205 DisasContext *dc = container_of(dcbase, DisasContext, base);
6206 tcg_gen_insn_start(dc->base.pc_next, dc->cc_op);
6207 }
6208
6209 static bool m68k_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
6210 const CPUBreakpoint *bp)
6211 {
6212 DisasContext *dc = container_of(dcbase, DisasContext, base);
6213
6214 gen_exception(dc, dc->base.pc_next, EXCP_DEBUG);
6215 /*
6216 * The address covered by the breakpoint must be included in
6217 * [tb->pc, tb->pc + tb->size) in order to for it to be
6218 * properly cleared -- thus we increment the PC here so that
6219 * the logic setting tb->size below does the right thing.
6220 */
6221 dc->base.pc_next += 2;
6222
6223 return true;
6224 }
6225
6226 static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
6227 {
6228 DisasContext *dc = container_of(dcbase, DisasContext, base);
6229 CPUM68KState *env = cpu->env_ptr;
6230 uint16_t insn = read_im16(env, dc);
6231
6232 opcode_table[insn](env, dc, insn);
6233 do_writebacks(dc);
6234 do_release(dc);
6235
6236 dc->base.pc_next = dc->pc;
6237
6238 if (dc->base.is_jmp == DISAS_NEXT) {
6239 /*
6240 * Stop translation when the next insn might touch a new page.
6241 * This ensures that prefetch aborts at the right place.
6242 *
6243 * We cannot determine the size of the next insn without
6244 * completely decoding it. However, the maximum insn size
6245 * is 32 bytes, so end if we do not have that much remaining.
6246 * This may produce several small TBs at the end of each page,
6247 * but they will all be linked with goto_tb.
6248 *
6249 * ??? ColdFire maximum is 4 bytes; MC68000's maximum is also
6250 * smaller than MC68020's.
6251 */
6252 target_ulong start_page_offset
6253 = dc->pc - (dc->base.pc_first & TARGET_PAGE_MASK);
6254
6255 if (start_page_offset >= TARGET_PAGE_SIZE - 32) {
6256 dc->base.is_jmp = DISAS_TOO_MANY;
6257 }
6258 }
6259 }
6260
6261 static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
6262 {
6263 DisasContext *dc = container_of(dcbase, DisasContext, base);
6264
6265 switch (dc->base.is_jmp) {
6266 case DISAS_NORETURN:
6267 break;
6268 case DISAS_TOO_MANY:
6269 update_cc_op(dc);
6270 if (is_singlestepping(dc)) {
6271 tcg_gen_movi_i32(QREG_PC, dc->pc);
6272 gen_singlestep_exception(dc);
6273 } else {
6274 gen_jmp_tb(dc, 0, dc->pc);
6275 }
6276 break;
6277 case DISAS_JUMP:
6278 /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
6279 if (is_singlestepping(dc)) {
6280 gen_singlestep_exception(dc);
6281 } else {
6282 tcg_gen_lookup_and_goto_ptr();
6283 }
6284 break;
6285 case DISAS_EXIT:
6286 /*
6287 * We updated CC_OP and PC in gen_exit_tb, but also modified
6288 * other state that may require returning to the main loop.
6289 */
6290 if (is_singlestepping(dc)) {
6291 gen_singlestep_exception(dc);
6292 } else {
6293 tcg_gen_exit_tb(NULL, 0);
6294 }
6295 break;
6296 default:
6297 g_assert_not_reached();
6298 }
6299 }
6300
6301 static void m68k_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
6302 {
6303 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
6304 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
6305 }
6306
6307 static const TranslatorOps m68k_tr_ops = {
6308 .init_disas_context = m68k_tr_init_disas_context,
6309 .tb_start = m68k_tr_tb_start,
6310 .insn_start = m68k_tr_insn_start,
6311 .breakpoint_check = m68k_tr_breakpoint_check,
6312 .translate_insn = m68k_tr_translate_insn,
6313 .tb_stop = m68k_tr_tb_stop,
6314 .disas_log = m68k_tr_disas_log,
6315 };
6316
6317 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
6318 {
6319 DisasContext dc;
6320 translator_loop(&m68k_tr_ops, &dc.base, cpu, tb, max_insns);
6321 }
6322
6323 static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
6324 {
6325 floatx80 a = { .high = high, .low = low };
6326 union {
6327 float64 f64;
6328 double d;
6329 } u;
6330
6331 u.f64 = floatx80_to_float64(a, &env->fp_status);
6332 return u.d;
6333 }
6334
6335 void m68k_cpu_dump_state(CPUState *cs, FILE *f, int flags)
6336 {
6337 M68kCPU *cpu = M68K_CPU(cs);
6338 CPUM68KState *env = &cpu->env;
6339 int i;
6340 uint16_t sr;
6341 for (i = 0; i < 8; i++) {
6342 qemu_fprintf(f, "D%d = %08x A%d = %08x "
6343 "F%d = %04x %016"PRIx64" (%12g)\n",
6344 i, env->dregs[i], i, env->aregs[i],
6345 i, env->fregs[i].l.upper, env->fregs[i].l.lower,
6346 floatx80_to_double(env, env->fregs[i].l.upper,
6347 env->fregs[i].l.lower));
6348 }
6349 qemu_fprintf(f, "PC = %08x ", env->pc);
6350 sr = env->sr | cpu_m68k_get_ccr(env);
6351 qemu_fprintf(f, "SR = %04x T:%x I:%x %c%c %c%c%c%c%c\n",
6352 sr, (sr & SR_T) >> SR_T_SHIFT, (sr & SR_I) >> SR_I_SHIFT,
6353 (sr & SR_S) ? 'S' : 'U', (sr & SR_M) ? '%' : 'I',
6354 (sr & CCF_X) ? 'X' : '-', (sr & CCF_N) ? 'N' : '-',
6355 (sr & CCF_Z) ? 'Z' : '-', (sr & CCF_V) ? 'V' : '-',
6356 (sr & CCF_C) ? 'C' : '-');
6357 qemu_fprintf(f, "FPSR = %08x %c%c%c%c ", env->fpsr,
6358 (env->fpsr & FPSR_CC_A) ? 'A' : '-',
6359 (env->fpsr & FPSR_CC_I) ? 'I' : '-',
6360 (env->fpsr & FPSR_CC_Z) ? 'Z' : '-',
6361 (env->fpsr & FPSR_CC_N) ? 'N' : '-');
6362 qemu_fprintf(f, "\n "
6363 "FPCR = %04x ", env->fpcr);
6364 switch (env->fpcr & FPCR_PREC_MASK) {
6365 case FPCR_PREC_X:
6366 qemu_fprintf(f, "X ");
6367 break;
6368 case FPCR_PREC_S:
6369 qemu_fprintf(f, "S ");
6370 break;
6371 case FPCR_PREC_D:
6372 qemu_fprintf(f, "D ");
6373 break;
6374 }
6375 switch (env->fpcr & FPCR_RND_MASK) {
6376 case FPCR_RND_N:
6377 qemu_fprintf(f, "RN ");
6378 break;
6379 case FPCR_RND_Z:
6380 qemu_fprintf(f, "RZ ");
6381 break;
6382 case FPCR_RND_M:
6383 qemu_fprintf(f, "RM ");
6384 break;
6385 case FPCR_RND_P:
6386 qemu_fprintf(f, "RP ");
6387 break;
6388 }
6389 qemu_fprintf(f, "\n");
6390 #ifdef CONFIG_SOFTMMU
6391 qemu_fprintf(f, "%sA7(MSP) = %08x %sA7(USP) = %08x %sA7(ISP) = %08x\n",
6392 env->current_sp == M68K_SSP ? "->" : " ", env->sp[M68K_SSP],
6393 env->current_sp == M68K_USP ? "->" : " ", env->sp[M68K_USP],
6394 env->current_sp == M68K_ISP ? "->" : " ", env->sp[M68K_ISP]);
6395 qemu_fprintf(f, "VBR = 0x%08x\n", env->vbr);
6396 qemu_fprintf(f, "SFC = %x DFC %x\n", env->sfc, env->dfc);
6397 qemu_fprintf(f, "SSW %08x TCR %08x URP %08x SRP %08x\n",
6398 env->mmu.ssw, env->mmu.tcr, env->mmu.urp, env->mmu.srp);
6399 qemu_fprintf(f, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n",
6400 env->mmu.ttr[M68K_DTTR0], env->mmu.ttr[M68K_DTTR1],
6401 env->mmu.ttr[M68K_ITTR0], env->mmu.ttr[M68K_ITTR1]);
6402 qemu_fprintf(f, "MMUSR %08x, fault at %08x\n",
6403 env->mmu.mmusr, env->mmu.ar);
6404 #endif
6405 }
6406
6407 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
6408 target_ulong *data)
6409 {
6410 int cc_op = data[1];
6411 env->pc = data[0];
6412 if (cc_op != CC_OP_DYNAMIC) {
6413 env->cc_op = cc_op;
6414 }
6415 }
AR7 emulation for QEMU