include/hw/i386/apic_internal.h

   1 /*
   2  *  APIC support - internal interfaces
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *  Copyright (c) 2011      Jan Kiszka, Siemens AG
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  19  */
  20
  21 #ifndef QEMU_APIC_INTERNAL_H
  22 #define QEMU_APIC_INTERNAL_H
  23
  24 #include "cpu.h"
  25 #include "exec/memory.h"
  26 #include "qemu/timer.h"
  27 #include "target/i386/cpu-qom.h"
  28 #include "qom/object.h"
  29
  30 /* APIC Local Vector Table */
  31 #define APIC_LVT_TIMER                  0
  32 #define APIC_LVT_THERMAL                1
  33 #define APIC_LVT_PERFORM                2
  34 #define APIC_LVT_LINT0                  3
  35 #define APIC_LVT_LINT1                  4
  36 #define APIC_LVT_ERROR                  5
  37 #define APIC_LVT_NB                     6
  38
  39 /* APIC delivery modes */
  40 #define APIC_DM_FIXED                   0
  41 #define APIC_DM_LOWPRI                  1
  42 #define APIC_DM_SMI                     2
  43 #define APIC_DM_NMI                     4
  44 #define APIC_DM_INIT                    5
  45 #define APIC_DM_SIPI                    6
  46 #define APIC_DM_EXTINT                  7
  47
  48 /* APIC destination mode */
  49 #define APIC_DESTMODE_FLAT              0xf
  50 #define APIC_DESTMODE_CLUSTER           1
  51
  52 #define APIC_TRIGGER_EDGE               0
  53 #define APIC_TRIGGER_LEVEL              1
  54
  55 #define APIC_VECTOR_MASK                0xff
  56 #define APIC_DCR_MASK                   0xf
  57
  58 #define APIC_LVT_TIMER_SHIFT            17
  59 #define APIC_LVT_MASKED_SHIFT           16
  60 #define APIC_LVT_LEVEL_TRIGGER_SHIFT    15
  61 #define APIC_LVT_REMOTE_IRR_SHIFT       14
  62 #define APIC_LVT_INT_POLARITY_SHIFT     13
  63 #define APIC_LVT_DELIV_STS_SHIFT        12
  64 #define APIC_LVT_DELIV_MOD_SHIFT        8
  65
  66 #define APIC_LVT_TIMER_TSCDEADLINE      (2 << APIC_LVT_TIMER_SHIFT)
  67 #define APIC_LVT_TIMER_PERIODIC         (1 << APIC_LVT_TIMER_SHIFT)
  68 #define APIC_LVT_MASKED                 (1 << APIC_LVT_MASKED_SHIFT)
  69 #define APIC_LVT_LEVEL_TRIGGER          (1 << APIC_LVT_LEVEL_TRIGGER_SHIFT)
  70 #define APIC_LVT_REMOTE_IRR             (1 << APIC_LVT_REMOTE_IRR_SHIFT)
  71 #define APIC_LVT_INT_POLARITY           (1 << APIC_LVT_INT_POLARITY_SHIFT)
  72 #define APIC_LVT_DELIV_STS              (1 << APIC_LVT_DELIV_STS_SHIFT)
  73 #define APIC_LVT_DELIV_MOD              (7 << APIC_LVT_DELIV_MOD_SHIFT)
  74
  75 #define APIC_ESR_ILL_ADDRESS_SHIFT      7
  76 #define APIC_ESR_RECV_ILL_VECT_SHIFT    6
  77 #define APIC_ESR_SEND_ILL_VECT_SHIFT    5
  78 #define APIC_ESR_RECV_ACCEPT_SHIFT      3
  79 #define APIC_ESR_SEND_ACCEPT_SHIFT      2
  80 #define APIC_ESR_RECV_CHECK_SUM_SHIFT   1
  81
  82 #define APIC_ESR_ILLEGAL_ADDRESS        (1 << APIC_ESR_ILL_ADDRESS_SHIFT)
  83 #define APIC_ESR_RECV_ILLEGAL_VECT      (1 << APIC_ESR_RECV_ILL_VECT_SHIFT)
  84 #define APIC_ESR_SEND_ILLEGAL_VECT      (1 << APIC_ESR_SEND_ILL_VECT_SHIFT)
  85 #define APIC_ESR_RECV_ACCEPT            (1 << APIC_ESR_RECV_ACCEPT_SHIFT)
  86 #define APIC_ESR_SEND_ACCEPT            (1 << APIC_ESR_SEND_ACCEPT_SHIFT)
  87 #define APIC_ESR_RECV_CHECK_SUM         (1 << APIC_ESR_RECV_CHECK_SUM_SHIFT)
  88 #define APIC_ESR_SEND_CHECK_SUM         1
  89
  90 #define APIC_ICR_DEST_SHIFT             24
  91 #define APIC_ICR_DEST_SHORT_SHIFT       18
  92 #define APIC_ICR_TRIGGER_MOD_SHIFT      15
  93 #define APIC_ICR_LEVEL_SHIFT            14
  94 #define APIC_ICR_DELIV_STS_SHIFT        12
  95 #define APIC_ICR_DEST_MOD_SHIFT         11
  96 #define APIC_ICR_DELIV_MOD_SHIFT        8
  97
  98 #define APIC_ICR_DEST_SHORT             (3 << APIC_ICR_DEST_SHORT_SHIFT)
  99 #define APIC_ICR_TRIGGER_MOD            (1 << APIC_ICR_TRIGGER_MOD_SHIFT)
 100 #define APIC_ICR_LEVEL                  (1 << APIC_ICR_LEVEL_SHIFT)
 101 #define APIC_ICR_DELIV_STS              (1 << APIC_ICR_DELIV_STS_SHIFT)
 102 #define APIC_ICR_DEST_MOD               (1 << APIC_ICR_DEST_MOD_SHIFT)
 103 #define APIC_ICR_DELIV_MOD              (7 << APIC_ICR_DELIV_MOD_SHIFT)
 104
 105 #define APIC_PR_CLASS_SHIFT             4
 106 #define APIC_PR_SUB_CLASS               0xf
 107
 108 #define APIC_LOGDEST_XAPIC_SHIFT        4
 109 #define APIC_LOGDEST_XAPIC_ID           0xf
 110
 111 #define APIC_LOGDEST_X2APIC_SHIFT       16
 112 #define APIC_LOGDEST_X2APIC_ID          0xffff
 113
 114 #define APIC_SPURIO_FOCUS_SHIFT         9
 115 #define APIC_SPURIO_ENABLED_SHIFT       8
 116
 117 #define APIC_SPURIO_FOCUS               (1 << APIC_SPURIO_FOCUS_SHIFT)
 118 #define APIC_SPURIO_ENABLED             (1 << APIC_SPURIO_ENABLED_SHIFT)
 119
 120 #define APIC_SV_DIRECTED_IO             (1 << 12)
 121 #define APIC_SV_ENABLE                  (1 << 8)
 122
 123 #define VAPIC_ENABLE_BIT                0
 124 #define VAPIC_ENABLE_MASK               (1 << VAPIC_ENABLE_BIT)
 125
 126 typedef struct APICCommonState APICCommonState;
 127
 128 #define TYPE_APIC_COMMON "apic-common"
 129 typedef struct APICCommonClass APICCommonClass;
 130 DECLARE_OBJ_CHECKERS(APICCommonState, APICCommonClass,
 131                      APIC_COMMON, TYPE_APIC_COMMON)
 132
 133 struct APICCommonClass {
 134     DeviceClass parent_class;
 135
 136     DeviceRealize realize;
 137     DeviceUnrealize unrealize;
 138     void (*set_base)(APICCommonState *s, uint64_t val);
 139     void (*set_tpr)(APICCommonState *s, uint8_t val);
 140     uint8_t (*get_tpr)(APICCommonState *s);
 141     void (*enable_tpr_reporting)(APICCommonState *s, bool enable);
 142     void (*vapic_base_update)(APICCommonState *s);
 143     void (*external_nmi)(APICCommonState *s);
 144     void (*pre_save)(APICCommonState *s);
 145     void (*post_load)(APICCommonState *s);
 146     void (*reset)(APICCommonState *s);
 147     /* send_msi emulates an APIC bus and its proper place would be in a new
 148      * device, but it's convenient to have it here for now.
 149      */
 150     void (*send_msi)(MSIMessage *msi);
 151 };
 152
 153 struct APICCommonState {
 154     /*< private >*/
 155     DeviceState parent_obj;
 156     /*< public >*/
 157
 158     MemoryRegion io_memory;
 159     X86CPU *cpu;
 160     uint32_t apicbase;
 161     uint8_t id; /* legacy APIC ID */
 162     uint32_t initial_apic_id;
 163     uint8_t version;
 164     uint8_t arb_id;
 165     uint8_t tpr;
 166     uint32_t spurious_vec;
 167     uint8_t log_dest;
 168     uint8_t dest_mode;
 169     uint32_t isr[8];  /* in service register */
 170     uint32_t tmr[8];  /* trigger mode register */
 171     uint32_t irr[8]; /* interrupt request register */
 172     uint32_t lvt[APIC_LVT_NB];
 173     uint32_t esr; /* error register */
 174     uint32_t icr[2];
 175
 176     uint32_t divide_conf;
 177     int count_shift;
 178     uint32_t initial_count;
 179     int64_t initial_count_load_time;
 180     int64_t next_time;
 181     QEMUTimer *timer;
 182     int64_t timer_expiry;
 183     int sipi_vector;
 184     int wait_for_sipi;
 185
 186     uint32_t vapic_control;
 187     DeviceState *vapic;
 188     hwaddr vapic_paddr; /* note: persistence via kvmvapic */
 189     bool legacy_instance_id;
 190 };
 191
 192 typedef struct VAPICState {
 193     uint8_t tpr;
 194     uint8_t isr;
 195     uint8_t zero;
 196     uint8_t irr;
 197     uint8_t enabled;
 198 } QEMU_PACKED VAPICState;
 199
 200 extern bool apic_report_tpr_access;
 201
 202 void apic_report_irq_delivered(int delivered);
 203 bool apic_next_timer(APICCommonState *s, int64_t current_time);
 204 void apic_enable_tpr_access_reporting(DeviceState *d, bool enable);
 205 void apic_enable_vapic(DeviceState *d, hwaddr paddr);
 206
 207 void vapic_report_tpr_access(DeviceState *dev, CPUState *cpu, target_ulong ip,
 208                              TPRAccess access);
 209
 210 int apic_get_ppr(APICCommonState *s);
 211 uint32_t apic_get_current_count(APICCommonState *s);
 212
 213 static inline void apic_set_bit(uint32_t *tab, int index)
 214 {
 215     int i, mask;
 216     i = index >> 5;
 217     mask = 1 << (index & 0x1f);
 218     tab[i] |= mask;
 219 }
 220
 221 static inline int apic_get_bit(uint32_t *tab, int index)
 222 {
 223     int i, mask;
 224     i = index >> 5;
 225     mask = 1 << (index & 0x1f);
 226     return !!(tab[i] & mask);
 227 }
 228
 229 APICCommonClass *apic_get_class(void);
 230
 231 #endif /* QEMU_APIC_INTERNAL_H */