include/hw/arm/omap.h

   1 /*
   2  * Texas Instruments OMAP processors.
   3  *
   4  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef HW_ARM_OMAP_H
  21 #define HW_ARM_OMAP_H
  22
  23 #include "exec/memory.h"
  24 #include "hw/input/tsc2xxx.h"
  25 #include "target/arm/cpu-qom.h"
  26 #include "qemu/log.h"
  27 #include "qom/object.h"
  28
  29 # define OMAP_EMIFS_BASE        0x00000000
  30 # define OMAP2_Q0_BASE          0x00000000
  31 # define OMAP_CS0_BASE          0x00000000
  32 # define OMAP_CS1_BASE          0x04000000
  33 # define OMAP_CS2_BASE          0x08000000
  34 # define OMAP_CS3_BASE          0x0c000000
  35 # define OMAP_EMIFF_BASE        0x10000000
  36 # define OMAP_IMIF_BASE         0x20000000
  37 # define OMAP_LOCALBUS_BASE     0x30000000
  38 # define OMAP2_Q1_BASE          0x40000000
  39 # define OMAP2_L4_BASE          0x48000000
  40 # define OMAP2_SRAM_BASE        0x40200000
  41 # define OMAP2_L3_BASE          0x68000000
  42 # define OMAP2_Q2_BASE          0x80000000
  43 # define OMAP2_Q3_BASE          0xc0000000
  44 # define OMAP_MPUI_BASE         0xe1000000
  45
  46 # define OMAP730_SRAM_SIZE      0x00032000
  47 # define OMAP15XX_SRAM_SIZE     0x00030000
  48 # define OMAP16XX_SRAM_SIZE     0x00004000
  49 # define OMAP1611_SRAM_SIZE     0x0003e800
  50 # define OMAP242X_SRAM_SIZE     0x000a0000
  51 # define OMAP243X_SRAM_SIZE     0x00010000
  52 # define OMAP_CS0_SIZE          0x04000000
  53 # define OMAP_CS1_SIZE          0x04000000
  54 # define OMAP_CS2_SIZE          0x04000000
  55 # define OMAP_CS3_SIZE          0x04000000
  56
  57 /* omap_clk.c */
  58 struct omap_mpu_state_s;
  59 typedef struct clk *omap_clk;
  60 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
  61 void omap_clk_init(struct omap_mpu_state_s *mpu);
  62 void omap_clk_adduser(struct clk *clk, qemu_irq user);
  63 void omap_clk_get(omap_clk clk);
  64 void omap_clk_put(omap_clk clk);
  65 void omap_clk_onoff(omap_clk clk, int on);
  66 void omap_clk_canidle(omap_clk clk, int can);
  67 void omap_clk_setrate(omap_clk clk, int divide, int multiply);
  68 int64_t omap_clk_getrate(omap_clk clk);
  69 void omap_clk_reparent(omap_clk clk, omap_clk parent);
  70
  71 /* omap_intc.c */
  72 #define TYPE_OMAP_INTC "common-omap-intc"
  73 typedef struct omap_intr_handler_s omap_intr_handler;
  74 DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC,
  75                          TYPE_OMAP_INTC)
  76
  77
  78 /*
  79  * TODO: Ideally we should have a clock framework that
  80  * let us wire these clocks up with QOM properties or links.
  81  *
  82  * qdev should support a generic means of defining a 'port' with
  83  * an arbitrary interface for connecting two devices. Then we
  84  * could reframe the omap clock API in terms of clock ports,
  85  * and get some type safety. For now the best qdev provides is
  86  * passing an arbitrary pointer.
  87  * (It's not possible to pass in the string which is the clock
  88  * name, because this device does not have the necessary information
  89  * (ie the struct omap_mpu_state_s*) to do the clockname to pointer
  90  * translation.)
  91  */
  92 void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk);
  93 void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk);
  94
  95 /* omap_i2c.c */
  96 #define TYPE_OMAP_I2C "omap_i2c"
  97 OBJECT_DECLARE_SIMPLE_TYPE(OMAPI2CState, OMAP_I2C)
  98
  99
 100 /* TODO: clock framework (see above) */
 101 void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk);
 102 void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk);
 103
 104 /* omap_gpio.c */
 105 #define TYPE_OMAP1_GPIO "omap-gpio"
 106 DECLARE_INSTANCE_CHECKER(struct omap_gpif_s, OMAP1_GPIO,
 107                          TYPE_OMAP1_GPIO)
 108
 109 #define TYPE_OMAP2_GPIO "omap2-gpio"
 110 DECLARE_INSTANCE_CHECKER(struct omap2_gpif_s, OMAP2_GPIO,
 111                          TYPE_OMAP2_GPIO)
 112
 113 typedef struct omap_gpif_s omap_gpif;
 114 typedef struct omap2_gpif_s omap2_gpif;
 115
 116 /* TODO: clock framework (see above) */
 117 void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk);
 118
 119 void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk);
 120 void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk);
 121
 122 /* OMAP2 l4 Interconnect */
 123 struct omap_l4_s;
 124 struct omap_l4_region_s {
 125     hwaddr offset;
 126     size_t size;
 127     int access;
 128 };
 129 struct omap_l4_agent_info_s {
 130     int ta;
 131     int region;
 132     int regions;
 133     int ta_region;
 134 };
 135 struct omap_target_agent_s {
 136     MemoryRegion iomem;
 137     struct omap_l4_s *bus;
 138     int regions;
 139     const struct omap_l4_region_s *start;
 140     hwaddr base;
 141     uint32_t component;
 142     uint32_t control;
 143     uint32_t status;
 144 };
 145 struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
 146                                hwaddr base, int ta_num);
 147
 148 struct omap_target_agent_s;
 149 struct omap_target_agent_s *omap_l4ta_get(
 150     struct omap_l4_s *bus,
 151     const struct omap_l4_region_s *regions,
 152     const struct omap_l4_agent_info_s *agents,
 153     int cs);
 154 hwaddr omap_l4_attach(struct omap_target_agent_s *ta,
 155                                          int region, MemoryRegion *mr);
 156 hwaddr omap_l4_region_base(struct omap_target_agent_s *ta,
 157                                        int region);
 158 hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
 159                                        int region);
 160
 161 /* OMAP2 SDRAM controller */
 162 struct omap_sdrc_s;
 163 struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
 164                                    hwaddr base);
 165 void omap_sdrc_reset(struct omap_sdrc_s *s);
 166
 167 /* OMAP2 general purpose memory controller */
 168 struct omap_gpmc_s;
 169 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
 170                                    hwaddr base,
 171                                    qemu_irq irq, qemu_irq drq);
 172 void omap_gpmc_reset(struct omap_gpmc_s *s);
 173 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);
 174 void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand);
 175
 176 /*
 177  * Common IRQ numbers for level 1 interrupt handler
 178  * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
 179  */
 180 # define OMAP_INT_CAMERA                1
 181 # define OMAP_INT_FIQ                   3
 182 # define OMAP_INT_RTDX                  6
 183 # define OMAP_INT_DSP_MMU_ABORT         7
 184 # define OMAP_INT_HOST                  8
 185 # define OMAP_INT_ABORT                 9
 186 # define OMAP_INT_BRIDGE_PRIV           13
 187 # define OMAP_INT_GPIO_BANK1            14
 188 # define OMAP_INT_UART3                 15
 189 # define OMAP_INT_TIMER3                16
 190 # define OMAP_INT_DMA_CH0_6             19
 191 # define OMAP_INT_DMA_CH1_7             20
 192 # define OMAP_INT_DMA_CH2_8             21
 193 # define OMAP_INT_DMA_CH3               22
 194 # define OMAP_INT_DMA_CH4               23
 195 # define OMAP_INT_DMA_CH5               24
 196 # define OMAP_INT_DMA_LCD               25
 197 # define OMAP_INT_TIMER1                26
 198 # define OMAP_INT_WD_TIMER              27
 199 # define OMAP_INT_BRIDGE_PUB            28
 200 # define OMAP_INT_TIMER2                30
 201 # define OMAP_INT_LCD_CTRL              31
 202
 203 /*
 204  * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
 205  */
 206 # define OMAP_INT_15XX_IH2_IRQ          0
 207 # define OMAP_INT_15XX_LB_MMU           17
 208 # define OMAP_INT_15XX_LOCAL_BUS        29
 209
 210 /*
 211  * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
 212  */
 213 # define OMAP_INT_1510_SPI_TX           4
 214 # define OMAP_INT_1510_SPI_RX           5
 215 # define OMAP_INT_1510_DSP_MAILBOX1     10
 216 # define OMAP_INT_1510_DSP_MAILBOX2     11
 217
 218 /*
 219  * OMAP-310 specific IRQ numbers for level 1 interrupt handler
 220  */
 221 # define OMAP_INT_310_McBSP2_TX         4
 222 # define OMAP_INT_310_McBSP2_RX         5
 223 # define OMAP_INT_310_HSB_MAILBOX1      12
 224 # define OMAP_INT_310_HSAB_MMU          18
 225
 226 /*
 227  * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
 228  */
 229 # define OMAP_INT_1610_IH2_IRQ          0
 230 # define OMAP_INT_1610_IH2_FIQ          2
 231 # define OMAP_INT_1610_McBSP2_TX        4
 232 # define OMAP_INT_1610_McBSP2_RX        5
 233 # define OMAP_INT_1610_DSP_MAILBOX1     10
 234 # define OMAP_INT_1610_DSP_MAILBOX2     11
 235 # define OMAP_INT_1610_LCD_LINE         12
 236 # define OMAP_INT_1610_GPTIMER1         17
 237 # define OMAP_INT_1610_GPTIMER2         18
 238 # define OMAP_INT_1610_SSR_FIFO_0       29
 239
 240 /*
 241  * OMAP-730 specific IRQ numbers for level 1 interrupt handler
 242  */
 243 # define OMAP_INT_730_IH2_FIQ           0
 244 # define OMAP_INT_730_IH2_IRQ           1
 245 # define OMAP_INT_730_USB_NON_ISO       2
 246 # define OMAP_INT_730_USB_ISO           3
 247 # define OMAP_INT_730_ICR               4
 248 # define OMAP_INT_730_EAC               5
 249 # define OMAP_INT_730_GPIO_BANK1        6
 250 # define OMAP_INT_730_GPIO_BANK2        7
 251 # define OMAP_INT_730_GPIO_BANK3        8
 252 # define OMAP_INT_730_McBSP2TX          10
 253 # define OMAP_INT_730_McBSP2RX          11
 254 # define OMAP_INT_730_McBSP2RX_OVF      12
 255 # define OMAP_INT_730_LCD_LINE          14
 256 # define OMAP_INT_730_GSM_PROTECT       15
 257 # define OMAP_INT_730_TIMER3            16
 258 # define OMAP_INT_730_GPIO_BANK5        17
 259 # define OMAP_INT_730_GPIO_BANK6        18
 260 # define OMAP_INT_730_SPGIO_WR          29
 261
 262 /*
 263  * Common IRQ numbers for level 2 interrupt handler
 264  */
 265 # define OMAP_INT_KEYBOARD              1
 266 # define OMAP_INT_uWireTX               2
 267 # define OMAP_INT_uWireRX               3
 268 # define OMAP_INT_I2C                   4
 269 # define OMAP_INT_MPUIO                 5
 270 # define OMAP_INT_USB_HHC_1             6
 271 # define OMAP_INT_McBSP3TX              10
 272 # define OMAP_INT_McBSP3RX              11
 273 # define OMAP_INT_McBSP1TX              12
 274 # define OMAP_INT_McBSP1RX              13
 275 # define OMAP_INT_UART1                 14
 276 # define OMAP_INT_UART2                 15
 277 # define OMAP_INT_USB_W2FC              20
 278 # define OMAP_INT_1WIRE                 21
 279 # define OMAP_INT_OS_TIMER              22
 280 # define OMAP_INT_OQN                   23
 281 # define OMAP_INT_GAUGE_32K             24
 282 # define OMAP_INT_RTC_TIMER             25
 283 # define OMAP_INT_RTC_ALARM             26
 284 # define OMAP_INT_DSP_MMU               28
 285
 286 /*
 287  * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
 288  */
 289 # define OMAP_INT_1510_BT_MCSI1TX       16
 290 # define OMAP_INT_1510_BT_MCSI1RX       17
 291 # define OMAP_INT_1510_SoSSI_MATCH      19
 292 # define OMAP_INT_1510_MEM_STICK        27
 293 # define OMAP_INT_1510_COM_SPI_RO       31
 294
 295 /*
 296  * OMAP-310 specific IRQ numbers for level 2 interrupt handler
 297  */
 298 # define OMAP_INT_310_FAC               0
 299 # define OMAP_INT_310_USB_HHC_2         7
 300 # define OMAP_INT_310_MCSI1_FE          16
 301 # define OMAP_INT_310_MCSI2_FE          17
 302 # define OMAP_INT_310_USB_W2FC_ISO      29
 303 # define OMAP_INT_310_USB_W2FC_NON_ISO  30
 304 # define OMAP_INT_310_McBSP2RX_OF       31
 305
 306 /*
 307  * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
 308  */
 309 # define OMAP_INT_1610_FAC              0
 310 # define OMAP_INT_1610_USB_HHC_2        7
 311 # define OMAP_INT_1610_USB_OTG          8
 312 # define OMAP_INT_1610_SoSSI            9
 313 # define OMAP_INT_1610_BT_MCSI1TX       16
 314 # define OMAP_INT_1610_BT_MCSI1RX       17
 315 # define OMAP_INT_1610_SoSSI_MATCH      19
 316 # define OMAP_INT_1610_MEM_STICK        27
 317 # define OMAP_INT_1610_McBSP2RX_OF      31
 318 # define OMAP_INT_1610_STI              32
 319 # define OMAP_INT_1610_STI_WAKEUP       33
 320 # define OMAP_INT_1610_GPTIMER3         34
 321 # define OMAP_INT_1610_GPTIMER4         35
 322 # define OMAP_INT_1610_GPTIMER5         36
 323 # define OMAP_INT_1610_GPTIMER6         37
 324 # define OMAP_INT_1610_GPTIMER7         38
 325 # define OMAP_INT_1610_GPTIMER8         39
 326 # define OMAP_INT_1610_GPIO_BANK2       40
 327 # define OMAP_INT_1610_GPIO_BANK3       41
 328 # define OMAP_INT_1610_MMC2             42
 329 # define OMAP_INT_1610_CF               43
 330 # define OMAP_INT_1610_WAKE_UP_REQ      46
 331 # define OMAP_INT_1610_GPIO_BANK4       48
 332 # define OMAP_INT_1610_SPI              49
 333 # define OMAP_INT_1610_DMA_CH6          53
 334 # define OMAP_INT_1610_DMA_CH7          54
 335 # define OMAP_INT_1610_DMA_CH8          55
 336 # define OMAP_INT_1610_DMA_CH9          56
 337 # define OMAP_INT_1610_DMA_CH10         57
 338 # define OMAP_INT_1610_DMA_CH11         58
 339 # define OMAP_INT_1610_DMA_CH12         59
 340 # define OMAP_INT_1610_DMA_CH13         60
 341 # define OMAP_INT_1610_DMA_CH14         61
 342 # define OMAP_INT_1610_DMA_CH15         62
 343 # define OMAP_INT_1610_NAND             63
 344
 345 /*
 346  * OMAP-730 specific IRQ numbers for level 2 interrupt handler
 347  */
 348 # define OMAP_INT_730_HW_ERRORS         0
 349 # define OMAP_INT_730_NFIQ_PWR_FAIL     1
 350 # define OMAP_INT_730_CFCD              2
 351 # define OMAP_INT_730_CFIREQ            3
 352 # define OMAP_INT_730_I2C               4
 353 # define OMAP_INT_730_PCC               5
 354 # define OMAP_INT_730_MPU_EXT_NIRQ      6
 355 # define OMAP_INT_730_SPI_100K_1        7
 356 # define OMAP_INT_730_SYREN_SPI         8
 357 # define OMAP_INT_730_VLYNQ             9
 358 # define OMAP_INT_730_GPIO_BANK4        10
 359 # define OMAP_INT_730_McBSP1TX          11
 360 # define OMAP_INT_730_McBSP1RX          12
 361 # define OMAP_INT_730_McBSP1RX_OF       13
 362 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
 363 # define OMAP_INT_730_UART_MODEM_1      15
 364 # define OMAP_INT_730_MCSI              16
 365 # define OMAP_INT_730_uWireTX           17
 366 # define OMAP_INT_730_uWireRX           18
 367 # define OMAP_INT_730_SMC_CD            19
 368 # define OMAP_INT_730_SMC_IREQ          20
 369 # define OMAP_INT_730_HDQ_1WIRE         21
 370 # define OMAP_INT_730_TIMER32K          22
 371 # define OMAP_INT_730_MMC_SDIO          23
 372 # define OMAP_INT_730_UPLD              24
 373 # define OMAP_INT_730_USB_HHC_1         27
 374 # define OMAP_INT_730_USB_HHC_2         28
 375 # define OMAP_INT_730_USB_GENI          29
 376 # define OMAP_INT_730_USB_OTG           30
 377 # define OMAP_INT_730_CAMERA_IF         31
 378 # define OMAP_INT_730_RNG               32
 379 # define OMAP_INT_730_DUAL_MODE_TIMER   33
 380 # define OMAP_INT_730_DBB_RF_EN         34
 381 # define OMAP_INT_730_MPUIO_KEYPAD      35
 382 # define OMAP_INT_730_SHA1_MD5          36
 383 # define OMAP_INT_730_SPI_100K_2        37
 384 # define OMAP_INT_730_RNG_IDLE          38
 385 # define OMAP_INT_730_MPUIO             39
 386 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
 387 # define OMAP_INT_730_LLPC_OE_FALLING   41
 388 # define OMAP_INT_730_LLPC_OE_RISING    42
 389 # define OMAP_INT_730_LLPC_VSYNC        43
 390 # define OMAP_INT_730_WAKE_UP_REQ       46
 391 # define OMAP_INT_730_DMA_CH6           53
 392 # define OMAP_INT_730_DMA_CH7           54
 393 # define OMAP_INT_730_DMA_CH8           55
 394 # define OMAP_INT_730_DMA_CH9           56
 395 # define OMAP_INT_730_DMA_CH10          57
 396 # define OMAP_INT_730_DMA_CH11          58
 397 # define OMAP_INT_730_DMA_CH12          59
 398 # define OMAP_INT_730_DMA_CH13          60
 399 # define OMAP_INT_730_DMA_CH14          61
 400 # define OMAP_INT_730_DMA_CH15          62
 401 # define OMAP_INT_730_NAND              63
 402
 403 /*
 404  * OMAP-24xx common IRQ numbers
 405  */
 406 # define OMAP_INT_24XX_STI              4
 407 # define OMAP_INT_24XX_SYS_NIRQ         7
 408 # define OMAP_INT_24XX_L3_IRQ           10
 409 # define OMAP_INT_24XX_PRCM_MPU_IRQ     11
 410 # define OMAP_INT_24XX_SDMA_IRQ0        12
 411 # define OMAP_INT_24XX_SDMA_IRQ1        13
 412 # define OMAP_INT_24XX_SDMA_IRQ2        14
 413 # define OMAP_INT_24XX_SDMA_IRQ3        15
 414 # define OMAP_INT_243X_MCBSP2_IRQ       16
 415 # define OMAP_INT_243X_MCBSP3_IRQ       17
 416 # define OMAP_INT_243X_MCBSP4_IRQ       18
 417 # define OMAP_INT_243X_MCBSP5_IRQ       19
 418 # define OMAP_INT_24XX_GPMC_IRQ         20
 419 # define OMAP_INT_24XX_GUFFAW_IRQ       21
 420 # define OMAP_INT_24XX_IVA_IRQ          22
 421 # define OMAP_INT_24XX_EAC_IRQ          23
 422 # define OMAP_INT_24XX_CAM_IRQ          24
 423 # define OMAP_INT_24XX_DSS_IRQ          25
 424 # define OMAP_INT_24XX_MAIL_U0_MPU      26
 425 # define OMAP_INT_24XX_DSP_UMA          27
 426 # define OMAP_INT_24XX_DSP_MMU          28
 427 # define OMAP_INT_24XX_GPIO_BANK1       29
 428 # define OMAP_INT_24XX_GPIO_BANK2       30
 429 # define OMAP_INT_24XX_GPIO_BANK3       31
 430 # define OMAP_INT_24XX_GPIO_BANK4       32
 431 # define OMAP_INT_243X_GPIO_BANK5       33
 432 # define OMAP_INT_24XX_MAIL_U3_MPU      34
 433 # define OMAP_INT_24XX_WDT3             35
 434 # define OMAP_INT_24XX_WDT4             36
 435 # define OMAP_INT_24XX_GPTIMER1         37
 436 # define OMAP_INT_24XX_GPTIMER2         38
 437 # define OMAP_INT_24XX_GPTIMER3         39
 438 # define OMAP_INT_24XX_GPTIMER4         40
 439 # define OMAP_INT_24XX_GPTIMER5         41
 440 # define OMAP_INT_24XX_GPTIMER6         42
 441 # define OMAP_INT_24XX_GPTIMER7         43
 442 # define OMAP_INT_24XX_GPTIMER8         44
 443 # define OMAP_INT_24XX_GPTIMER9         45
 444 # define OMAP_INT_24XX_GPTIMER10        46
 445 # define OMAP_INT_24XX_GPTIMER11        47
 446 # define OMAP_INT_24XX_GPTIMER12        48
 447 # define OMAP_INT_24XX_PKA_IRQ          50
 448 # define OMAP_INT_24XX_SHA1MD5_IRQ      51
 449 # define OMAP_INT_24XX_RNG_IRQ          52
 450 # define OMAP_INT_24XX_MG_IRQ           53
 451 # define OMAP_INT_24XX_I2C1_IRQ         56
 452 # define OMAP_INT_24XX_I2C2_IRQ         57
 453 # define OMAP_INT_24XX_MCBSP1_IRQ_TX    59
 454 # define OMAP_INT_24XX_MCBSP1_IRQ_RX    60
 455 # define OMAP_INT_24XX_MCBSP2_IRQ_TX    62
 456 # define OMAP_INT_24XX_MCBSP2_IRQ_RX    63
 457 # define OMAP_INT_243X_MCBSP1_IRQ       64
 458 # define OMAP_INT_24XX_MCSPI1_IRQ       65
 459 # define OMAP_INT_24XX_MCSPI2_IRQ       66
 460 # define OMAP_INT_24XX_SSI1_IRQ0        67
 461 # define OMAP_INT_24XX_SSI1_IRQ1        68
 462 # define OMAP_INT_24XX_SSI2_IRQ0        69
 463 # define OMAP_INT_24XX_SSI2_IRQ1        70
 464 # define OMAP_INT_24XX_SSI_GDD_IRQ      71
 465 # define OMAP_INT_24XX_UART1_IRQ        72
 466 # define OMAP_INT_24XX_UART2_IRQ        73
 467 # define OMAP_INT_24XX_UART3_IRQ        74
 468 # define OMAP_INT_24XX_USB_IRQ_GEN      75
 469 # define OMAP_INT_24XX_USB_IRQ_NISO     76
 470 # define OMAP_INT_24XX_USB_IRQ_ISO      77
 471 # define OMAP_INT_24XX_USB_IRQ_HGEN     78
 472 # define OMAP_INT_24XX_USB_IRQ_HSOF     79
 473 # define OMAP_INT_24XX_USB_IRQ_OTG      80
 474 # define OMAP_INT_24XX_VLYNQ_IRQ        81
 475 # define OMAP_INT_24XX_MMC_IRQ          83
 476 # define OMAP_INT_24XX_MS_IRQ           84
 477 # define OMAP_INT_24XX_FAC_IRQ          85
 478 # define OMAP_INT_24XX_MCSPI3_IRQ       91
 479 # define OMAP_INT_243X_HS_USB_MC        92
 480 # define OMAP_INT_243X_HS_USB_DMA       93
 481 # define OMAP_INT_243X_CARKIT           94
 482 # define OMAP_INT_34XX_GPTIMER12        95
 483
 484 /* omap_dma.c */
 485 enum omap_dma_model {
 486     omap_dma_3_0,
 487     omap_dma_3_1,
 488     omap_dma_3_2,
 489     omap_dma_4,
 490 };
 491
 492 struct soc_dma_s;
 493 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
 494                 MemoryRegion *sysmem,
 495                 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
 496                 enum omap_dma_model model);
 497 struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
 498                 MemoryRegion *sysmem,
 499                 struct omap_mpu_state_s *mpu, int fifo,
 500                 int chans, omap_clk iclk, omap_clk fclk);
 501 void omap_dma_reset(struct soc_dma_s *s);
 502
 503 struct dma_irq_map {
 504     int ih;
 505     int intr;
 506 };
 507
 508 /* Only used in OMAP DMA 3.x gigacells */
 509 enum omap_dma_port {
 510     emiff = 0,
 511     emifs,
 512     imif,       /* omap16xx: ocp_t1 */
 513     tipb,
 514     local,      /* omap16xx: ocp_t2 */
 515     tipb_mpui,
 516     __omap_dma_port_last,
 517 };
 518
 519 typedef enum {
 520     constant = 0,
 521     post_incremented,
 522     single_index,
 523     double_index,
 524 } omap_dma_addressing_t;
 525
 526 /* Only used in OMAP DMA 3.x gigacells */
 527 struct omap_dma_lcd_channel_s {
 528     enum omap_dma_port src;
 529     hwaddr src_f1_top;
 530     hwaddr src_f1_bottom;
 531     hwaddr src_f2_top;
 532     hwaddr src_f2_bottom;
 533
 534     /* Used in OMAP DMA 3.2 gigacell */
 535     unsigned char brust_f1;
 536     unsigned char pack_f1;
 537     unsigned char data_type_f1;
 538     unsigned char brust_f2;
 539     unsigned char pack_f2;
 540     unsigned char data_type_f2;
 541     unsigned char end_prog;
 542     unsigned char repeat;
 543     unsigned char auto_init;
 544     unsigned char priority;
 545     unsigned char fs;
 546     unsigned char running;
 547     unsigned char bs;
 548     unsigned char omap_3_1_compatible_disable;
 549     unsigned char dst;
 550     unsigned char lch_type;
 551     int16_t element_index_f1;
 552     int16_t element_index_f2;
 553     int32_t frame_index_f1;
 554     int32_t frame_index_f2;
 555     uint16_t elements_f1;
 556     uint16_t frames_f1;
 557     uint16_t elements_f2;
 558     uint16_t frames_f2;
 559     omap_dma_addressing_t mode_f1;
 560     omap_dma_addressing_t mode_f2;
 561
 562     /* Destination port is fixed.  */
 563     int interrupts;
 564     int condition;
 565     int dual;
 566
 567     int current_frame;
 568     hwaddr phys_framebuffer[2];
 569     qemu_irq irq;
 570     struct omap_mpu_state_s *mpu;
 571 } *omap_dma_get_lcdch(struct soc_dma_s *s);
 572
 573 /*
 574  * DMA request numbers for OMAP1
 575  * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
 576  */
 577 # define OMAP_DMA_NO_DEVICE             0
 578 # define OMAP_DMA_MCSI1_TX              1
 579 # define OMAP_DMA_MCSI1_RX              2
 580 # define OMAP_DMA_I2C_RX                3
 581 # define OMAP_DMA_I2C_TX                4
 582 # define OMAP_DMA_EXT_NDMA_REQ0         5
 583 # define OMAP_DMA_EXT_NDMA_REQ1         6
 584 # define OMAP_DMA_UWIRE_TX              7
 585 # define OMAP_DMA_MCBSP1_TX             8
 586 # define OMAP_DMA_MCBSP1_RX             9
 587 # define OMAP_DMA_MCBSP3_TX             10
 588 # define OMAP_DMA_MCBSP3_RX             11
 589 # define OMAP_DMA_UART1_TX              12
 590 # define OMAP_DMA_UART1_RX              13
 591 # define OMAP_DMA_UART2_TX              14
 592 # define OMAP_DMA_UART2_RX              15
 593 # define OMAP_DMA_MCBSP2_TX             16
 594 # define OMAP_DMA_MCBSP2_RX             17
 595 # define OMAP_DMA_UART3_TX              18
 596 # define OMAP_DMA_UART3_RX              19
 597 # define OMAP_DMA_CAMERA_IF_RX          20
 598 # define OMAP_DMA_MMC_TX                21
 599 # define OMAP_DMA_MMC_RX                22
 600 # define OMAP_DMA_NAND                  23      /* Not in OMAP310 */
 601 # define OMAP_DMA_IRQ_LCD_LINE          24      /* Not in OMAP310 */
 602 # define OMAP_DMA_MEMORY_STICK          25      /* Not in OMAP310 */
 603 # define OMAP_DMA_USB_W2FC_RX0          26
 604 # define OMAP_DMA_USB_W2FC_RX1          27
 605 # define OMAP_DMA_USB_W2FC_RX2          28
 606 # define OMAP_DMA_USB_W2FC_TX0          29
 607 # define OMAP_DMA_USB_W2FC_TX1          30
 608 # define OMAP_DMA_USB_W2FC_TX2          31
 609
 610 /* These are only for 1610 */
 611 # define OMAP_DMA_CRYPTO_DES_IN         32
 612 # define OMAP_DMA_SPI_TX                33
 613 # define OMAP_DMA_SPI_RX                34
 614 # define OMAP_DMA_CRYPTO_HASH           35
 615 # define OMAP_DMA_CCP_ATTN              36
 616 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY    37
 617 # define OMAP_DMA_CMT_APE_TX_CHAN_0     38
 618 # define OMAP_DMA_CMT_APE_RV_CHAN_0     39
 619 # define OMAP_DMA_CMT_APE_TX_CHAN_1     40
 620 # define OMAP_DMA_CMT_APE_RV_CHAN_1     41
 621 # define OMAP_DMA_CMT_APE_TX_CHAN_2     42
 622 # define OMAP_DMA_CMT_APE_RV_CHAN_2     43
 623 # define OMAP_DMA_CMT_APE_TX_CHAN_3     44
 624 # define OMAP_DMA_CMT_APE_RV_CHAN_3     45
 625 # define OMAP_DMA_CMT_APE_TX_CHAN_4     46
 626 # define OMAP_DMA_CMT_APE_RV_CHAN_4     47
 627 # define OMAP_DMA_CMT_APE_TX_CHAN_5     48
 628 # define OMAP_DMA_CMT_APE_RV_CHAN_5     49
 629 # define OMAP_DMA_CMT_APE_TX_CHAN_6     50
 630 # define OMAP_DMA_CMT_APE_RV_CHAN_6     51
 631 # define OMAP_DMA_CMT_APE_TX_CHAN_7     52
 632 # define OMAP_DMA_CMT_APE_RV_CHAN_7     53
 633 # define OMAP_DMA_MMC2_TX               54
 634 # define OMAP_DMA_MMC2_RX               55
 635 # define OMAP_DMA_CRYPTO_DES_OUT        56
 636
 637 /*
 638  * DMA request numbers for the OMAP2
 639  */
 640 # define OMAP24XX_DMA_NO_DEVICE         0
 641 # define OMAP24XX_DMA_XTI_DMA           1       /* Not in OMAP2420 */
 642 # define OMAP24XX_DMA_EXT_DMAREQ0       2
 643 # define OMAP24XX_DMA_EXT_DMAREQ1       3
 644 # define OMAP24XX_DMA_GPMC              4
 645 # define OMAP24XX_DMA_GFX               5       /* Not in OMAP2420 */
 646 # define OMAP24XX_DMA_DSS               6
 647 # define OMAP24XX_DMA_VLYNQ_TX          7       /* Not in OMAP2420 */
 648 # define OMAP24XX_DMA_CWT               8       /* Not in OMAP2420 */
 649 # define OMAP24XX_DMA_AES_TX            9       /* Not in OMAP2420 */
 650 # define OMAP24XX_DMA_AES_RX            10      /* Not in OMAP2420 */
 651 # define OMAP24XX_DMA_DES_TX            11      /* Not in OMAP2420 */
 652 # define OMAP24XX_DMA_DES_RX            12      /* Not in OMAP2420 */
 653 # define OMAP24XX_DMA_SHA1MD5_RX        13      /* Not in OMAP2420 */
 654 # define OMAP24XX_DMA_EXT_DMAREQ2       14
 655 # define OMAP24XX_DMA_EXT_DMAREQ3       15
 656 # define OMAP24XX_DMA_EXT_DMAREQ4       16
 657 # define OMAP24XX_DMA_EAC_AC_RD         17
 658 # define OMAP24XX_DMA_EAC_AC_WR         18
 659 # define OMAP24XX_DMA_EAC_MD_UL_RD      19
 660 # define OMAP24XX_DMA_EAC_MD_UL_WR      20
 661 # define OMAP24XX_DMA_EAC_MD_DL_RD      21
 662 # define OMAP24XX_DMA_EAC_MD_DL_WR      22
 663 # define OMAP24XX_DMA_EAC_BT_UL_RD      23
 664 # define OMAP24XX_DMA_EAC_BT_UL_WR      24
 665 # define OMAP24XX_DMA_EAC_BT_DL_RD      25
 666 # define OMAP24XX_DMA_EAC_BT_DL_WR      26
 667 # define OMAP24XX_DMA_I2C1_TX           27
 668 # define OMAP24XX_DMA_I2C1_RX           28
 669 # define OMAP24XX_DMA_I2C2_TX           29
 670 # define OMAP24XX_DMA_I2C2_RX           30
 671 # define OMAP24XX_DMA_MCBSP1_TX         31
 672 # define OMAP24XX_DMA_MCBSP1_RX         32
 673 # define OMAP24XX_DMA_MCBSP2_TX         33
 674 # define OMAP24XX_DMA_MCBSP2_RX         34
 675 # define OMAP24XX_DMA_SPI1_TX0          35
 676 # define OMAP24XX_DMA_SPI1_RX0          36
 677 # define OMAP24XX_DMA_SPI1_TX1          37
 678 # define OMAP24XX_DMA_SPI1_RX1          38
 679 # define OMAP24XX_DMA_SPI1_TX2          39
 680 # define OMAP24XX_DMA_SPI1_RX2          40
 681 # define OMAP24XX_DMA_SPI1_TX3          41
 682 # define OMAP24XX_DMA_SPI1_RX3          42
 683 # define OMAP24XX_DMA_SPI2_TX0          43
 684 # define OMAP24XX_DMA_SPI2_RX0          44
 685 # define OMAP24XX_DMA_SPI2_TX1          45
 686 # define OMAP24XX_DMA_SPI2_RX1          46
 687
 688 # define OMAP24XX_DMA_UART1_TX          49
 689 # define OMAP24XX_DMA_UART1_RX          50
 690 # define OMAP24XX_DMA_UART2_TX          51
 691 # define OMAP24XX_DMA_UART2_RX          52
 692 # define OMAP24XX_DMA_UART3_TX          53
 693 # define OMAP24XX_DMA_UART3_RX          54
 694 # define OMAP24XX_DMA_USB_W2FC_TX0      55
 695 # define OMAP24XX_DMA_USB_W2FC_RX0      56
 696 # define OMAP24XX_DMA_USB_W2FC_TX1      57
 697 # define OMAP24XX_DMA_USB_W2FC_RX1      58
 698 # define OMAP24XX_DMA_USB_W2FC_TX2      59
 699 # define OMAP24XX_DMA_USB_W2FC_RX2      60
 700 # define OMAP24XX_DMA_MMC1_TX           61
 701 # define OMAP24XX_DMA_MMC1_RX           62
 702 # define OMAP24XX_DMA_MS                63      /* Not in OMAP2420 */
 703 # define OMAP24XX_DMA_EXT_DMAREQ5       64
 704
 705 /* omap[123].c */
 706 /* OMAP2 gp timer */
 707 struct omap_gp_timer_s;
 708 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
 709                 qemu_irq irq, omap_clk fclk, omap_clk iclk);
 710 void omap_gp_timer_reset(struct omap_gp_timer_s *s);
 711
 712 /* OMAP2 sysctimer */
 713 struct omap_synctimer_s;
 714 struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,
 715                 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
 716 void omap_synctimer_reset(struct omap_synctimer_s *s);
 717
 718 struct omap_uart_s;
 719 struct omap_uart_s *omap_uart_init(hwaddr base,
 720                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
 721                 qemu_irq txdma, qemu_irq rxdma,
 722                 const char *label, Chardev *chr);
 723 struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
 724                 struct omap_target_agent_s *ta,
 725                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
 726                 qemu_irq txdma, qemu_irq rxdma,
 727                 const char *label, Chardev *chr);
 728 void omap_uart_reset(struct omap_uart_s *s);
 729 void omap_uart_attach(struct omap_uart_s *s, Chardev *chr);
 730
 731 struct omap_mpuio_s;
 732 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
 733 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
 734 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
 735
 736 struct omap_uwire_s;
 737 void omap_uwire_attach(struct omap_uwire_s *s,
 738                 uWireSlave *slave, int chipselect);
 739
 740 /* OMAP2 spi */
 741 struct omap_mcspi_s;
 742 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
 743                 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
 744 void omap_mcspi_attach(struct omap_mcspi_s *s,
 745                 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
 746                 int chipselect);
 747 void omap_mcspi_reset(struct omap_mcspi_s *s);
 748
 749 struct I2SCodec {
 750     void *opaque;
 751
 752     /* The CPU can call this if it is generating the clock signal on the
 753      * i2s port.  The CODEC can ignore it if it is set up as a clock
 754      * master and generates its own clock.  */
 755     void (*set_rate)(void *opaque, int in, int out);
 756
 757     void (*tx_swallow)(void *opaque);
 758     qemu_irq rx_swallow;
 759     qemu_irq tx_start;
 760
 761     int tx_rate;
 762     int cts;
 763     int rx_rate;
 764     int rts;
 765
 766     struct i2s_fifo_s {
 767         uint8_t *fifo;
 768         int len;
 769         int start;
 770         int size;
 771     } in, out;
 772 };
 773 struct omap_mcbsp_s;
 774 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
 775
 776 void omap_tap_init(struct omap_target_agent_s *ta,
 777                 struct omap_mpu_state_s *mpu);
 778
 779 /* omap_lcdc.c */
 780 struct omap_lcd_panel_s;
 781 void omap_lcdc_reset(struct omap_lcd_panel_s *s);
 782 struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
 783                                         hwaddr base,
 784                                         qemu_irq irq,
 785                                         struct omap_dma_lcd_channel_s *dma,
 786                                         omap_clk clk);
 787
 788 /* omap_dss.c */
 789 struct rfbi_chip_s {
 790     void *opaque;
 791     void (*write)(void *opaque, int dc, uint16_t value);
 792     void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
 793     uint16_t (*read)(void *opaque, int dc);
 794 };
 795 struct omap_dss_s;
 796 void omap_dss_reset(struct omap_dss_s *s);
 797 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
 798                 MemoryRegion *sysmem,
 799                 hwaddr l3_base,
 800                 qemu_irq irq, qemu_irq drq,
 801                 omap_clk fck1, omap_clk fck2, omap_clk ck54m,
 802                 omap_clk ick1, omap_clk ick2);
 803 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
 804
 805 /* omap_mmc.c */
 806 struct omap_mmc_s;
 807 struct omap_mmc_s *omap_mmc_init(hwaddr base,
 808                 MemoryRegion *sysmem,
 809                 BlockBackend *blk,
 810                 qemu_irq irq, qemu_irq dma[], omap_clk clk);
 811 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
 812                 BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
 813                 omap_clk fclk, omap_clk iclk);
 814 void omap_mmc_reset(struct omap_mmc_s *s);
 815 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
 816 void omap_mmc_enable(struct omap_mmc_s *s, int enable);
 817
 818 /* omap_i2c.c */
 819 I2CBus *omap_i2c_bus(DeviceState *omap_i2c);
 820
 821 # define cpu_is_omap310(cpu)            (cpu->mpu_model == omap310)
 822 # define cpu_is_omap1510(cpu)           (cpu->mpu_model == omap1510)
 823 # define cpu_is_omap1610(cpu)           (cpu->mpu_model == omap1610)
 824 # define cpu_is_omap1710(cpu)           (cpu->mpu_model == omap1710)
 825 # define cpu_is_omap2410(cpu)           (cpu->mpu_model == omap2410)
 826 # define cpu_is_omap2420(cpu)           (cpu->mpu_model == omap2420)
 827 # define cpu_is_omap2430(cpu)           (cpu->mpu_model == omap2430)
 828 # define cpu_is_omap3430(cpu)           (cpu->mpu_model == omap3430)
 829 # define cpu_is_omap3630(cpu)           (cpu->mpu_model == omap3630)
 830
 831 # define cpu_is_omap15xx(cpu)           \
 832         (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
 833 # define cpu_is_omap16xx(cpu)           \
 834         (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
 835 # define cpu_is_omap24xx(cpu)           \
 836         (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
 837
 838 # define cpu_class_omap1(cpu)           \
 839         (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
 840 # define cpu_class_omap2(cpu)           cpu_is_omap24xx(cpu)
 841 # define cpu_class_omap3(cpu) \
 842         (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu))
 843
 844 struct omap_mpu_state_s {
 845     enum omap_mpu_model {
 846         omap310,
 847         omap1510,
 848         omap1610,
 849         omap1710,
 850         omap2410,
 851         omap2420,
 852         omap2422,
 853         omap2423,
 854         omap2430,
 855         omap3430,
 856         omap3630,
 857     } mpu_model;
 858
 859     ARMCPU *cpu;
 860
 861     qemu_irq *drq;
 862
 863     qemu_irq wakeup;
 864
 865     MemoryRegion ulpd_pm_iomem;
 866     MemoryRegion pin_cfg_iomem;
 867     MemoryRegion id_iomem;
 868     MemoryRegion id_iomem_e18;
 869     MemoryRegion id_iomem_ed4;
 870     MemoryRegion id_iomem_e20;
 871     MemoryRegion mpui_iomem;
 872     MemoryRegion tcmi_iomem;
 873     MemoryRegion clkm_iomem;
 874     MemoryRegion clkdsp_iomem;
 875     MemoryRegion mpui_io_iomem;
 876     MemoryRegion tap_iomem;
 877     MemoryRegion imif_ram;
 878     MemoryRegion sram;
 879
 880     struct omap_dma_port_if_s {
 881         uint32_t (*read[3])(struct omap_mpu_state_s *s,
 882                         hwaddr offset);
 883         void (*write[3])(struct omap_mpu_state_s *s,
 884                         hwaddr offset, uint32_t value);
 885         int (*addr_valid)(struct omap_mpu_state_s *s,
 886                         hwaddr addr);
 887     } port[__omap_dma_port_last];
 888
 889     uint64_t sdram_size;
 890     unsigned long sram_size;
 891
 892     /* MPUI-TIPB peripherals */
 893     struct omap_uart_s *uart[3];
 894
 895     DeviceState *gpio;
 896
 897     struct omap_mcbsp_s *mcbsp1;
 898     struct omap_mcbsp_s *mcbsp3;
 899
 900     /* MPU public TIPB peripherals */
 901     struct omap_32khz_timer_s *os_timer;
 902
 903     struct omap_mmc_s *mmc;
 904
 905     struct omap_mpuio_s *mpuio;
 906
 907     struct omap_uwire_s *microwire;
 908
 909     struct omap_pwl_s *pwl;
 910     struct omap_pwt_s *pwt;
 911     DeviceState *i2c[2];
 912
 913     struct omap_rtc_s *rtc;
 914
 915     struct omap_mcbsp_s *mcbsp2;
 916
 917     struct omap_lpg_s *led[2];
 918
 919     /* MPU private TIPB peripherals */
 920     DeviceState *ih[2];
 921
 922     struct soc_dma_s *dma;
 923
 924     struct omap_mpu_timer_s *timer[3];
 925     struct omap_watchdog_timer_s *wdt;
 926
 927     struct omap_lcd_panel_s *lcd;
 928
 929     uint32_t ulpd_pm_regs[21];
 930     int64_t ulpd_gauge_start;
 931
 932     uint32_t func_mux_ctrl[14];
 933     uint32_t comp_mode_ctrl[1];
 934     uint32_t pull_dwn_ctrl[4];
 935     uint32_t gate_inh_ctrl[1];
 936     uint32_t voltage_ctrl[1];
 937     uint32_t test_dbg_ctrl[1];
 938     uint32_t mod_conf_ctrl[1];
 939     int compat1509;
 940
 941     uint32_t mpui_ctrl;
 942
 943     struct omap_tipb_bridge_s *private_tipb;
 944     struct omap_tipb_bridge_s *public_tipb;
 945
 946     uint32_t tcmi_regs[17];
 947
 948     struct dpll_ctl_s *dpll[3];
 949
 950     omap_clk clks;
 951     struct {
 952         int cold_start;
 953         int clocking_scheme;
 954         uint16_t arm_ckctl;
 955         uint16_t arm_idlect1;
 956         uint16_t arm_idlect2;
 957         uint16_t arm_ewupct;
 958         uint16_t arm_rstct1;
 959         uint16_t arm_rstct2;
 960         uint16_t arm_ckout1;
 961         int dpll1_mode;
 962         uint16_t dsp_idlect1;
 963         uint16_t dsp_idlect2;
 964         uint16_t dsp_rstct2;
 965     } clkm;
 966
 967     /* OMAP2-only peripherals */
 968     struct omap_l4_s *l4;
 969
 970     struct omap_gp_timer_s *gptimer[12];
 971     struct omap_synctimer_s *synctimer;
 972
 973     struct omap_prcm_s *prcm;
 974     struct omap_sdrc_s *sdrc;
 975     struct omap_gpmc_s *gpmc;
 976     struct omap_sysctl_s *sysc;
 977
 978     struct omap_mcspi_s *mcspi[2];
 979
 980     struct omap_dss_s *dss;
 981
 982     struct omap_eac_s *eac;
 983 };
 984
 985 /* omap1.c */
 986 struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram,
 987                 const char *core);
 988
 989 /* omap2.c */
 990 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
 991                 const char *core);
 992
 993 uint32_t omap_badwidth_read8(void *opaque, hwaddr addr);
 994 void omap_badwidth_write8(void *opaque, hwaddr addr,
 995                 uint32_t value);
 996 uint32_t omap_badwidth_read16(void *opaque, hwaddr addr);
 997 void omap_badwidth_write16(void *opaque, hwaddr addr,
 998                 uint32_t value);
 999 uint32_t omap_badwidth_read32(void *opaque, hwaddr addr);
1000 void omap_badwidth_write32(void *opaque, hwaddr addr,
1001                 uint32_t value);
1002
1003 void omap_mpu_wakeup(void *opaque, int irq, int req);
1004
1005 # define OMAP_BAD_REG(paddr)            \
1006         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \
1007                       __func__, paddr)
1008 # define OMAP_RO_REG(paddr)             \
1009         qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \
1010                                        HWADDR_PRIx "\n", \
1011                       __func__, paddr)
1012
1013 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
1014    (Board-specifc tags are not here)  */
1015 #define OMAP_TAG_CLOCK          0x4f01
1016 #define OMAP_TAG_MMC            0x4f02
1017 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
1018 #define OMAP_TAG_USB            0x4f04
1019 #define OMAP_TAG_LCD            0x4f05
1020 #define OMAP_TAG_GPIO_SWITCH    0x4f06
1021 #define OMAP_TAG_UART           0x4f07
1022 #define OMAP_TAG_FBMEM          0x4f08
1023 #define OMAP_TAG_STI_CONSOLE    0x4f09
1024 #define OMAP_TAG_CAMERA_SENSOR  0x4f0a
1025 #define OMAP_TAG_PARTITION      0x4f0b
1026 #define OMAP_TAG_TEA5761        0x4f10
1027 #define OMAP_TAG_TMP105         0x4f11
1028 #define OMAP_TAG_BOOT_REASON    0x4f80
1029 #define OMAP_TAG_FLASH_PART_STR 0x4f81
1030 #define OMAP_TAG_VERSION_STR    0x4f82
1031
1032 enum {
1033     OMAP_GPIOSW_TYPE_COVER      = 0 << 4,
1034     OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
1035     OMAP_GPIOSW_TYPE_ACTIVITY   = 2 << 4,
1036 };
1037
1038 #define OMAP_GPIOSW_INVERTED    0x0001
1039 #define OMAP_GPIOSW_OUTPUT      0x0002
1040
1041 # define OMAP_MPUI_REG_MASK             0x000007ff
1042
1043 #endif