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Merge tag 'v4.2.0-rc2'
[qemu/ar7.git] / memory.c
blob67b283f2e21c59c4f2cb5e97573cedcbcdabd3d5
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qapi/error.h"
18 #include "cpu.h"
19 #include "exec/exec-all.h" /* qemu_sprint_backtrace */
20 #include "exec/memory.h"
21 #include "exec/address-spaces.h"
22 #include "qapi/visitor.h"
23 #include "qemu/bitops.h"
24 #include "qemu/error-report.h"
25 #include "qemu/main-loop.h"
26 #include "qemu/qemu-print.h"
27 #include "qemu-common.h" /* trace_unassigned */
28 #include "qom/object.h"
29 #include "trace-root.h"
30
31 #include "exec/memory-internal.h"
32 #include "exec/ram_addr.h"
33 #include "sysemu/kvm.h"
34 #include "sysemu/runstate.h"
35 #include "sysemu/tcg.h"
36 #include "sysemu/accel.h"
37 #include "hw/boards.h"
38 #include "migration/vmstate.h"
39
40 //#define DEBUG_UNASSIGNED
41
42 static unsigned memory_region_transaction_depth;
43 static bool memory_region_update_pending;
44 static bool ioeventfd_update_pending;
45 bool global_dirty_log;
46
47 static QTAILQ_HEAD(, MemoryListener) memory_listeners
48 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
49
50 static QTAILQ_HEAD(, AddressSpace) address_spaces
51 = QTAILQ_HEAD_INITIALIZER(address_spaces);
52
53 static GHashTable *flat_views;
54
55 typedef struct AddrRange AddrRange;
56
57 /*
58 * Note that signed integers are needed for negative offsetting in aliases
59 * (large MemoryRegion::alias_offset).
60 */
61 struct AddrRange {
62 Int128 start;
63 Int128 size;
64 };
65
66 static AddrRange addrrange_make(Int128 start, Int128 size)
67 {
68 return (AddrRange) { start, size };
69 }
70
71 static bool addrrange_equal(AddrRange r1, AddrRange r2)
72 {
73 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
74 }
75
76 static Int128 addrrange_end(AddrRange r)
77 {
78 return int128_add(r.start, r.size);
79 }
80
81 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
82 {
83 int128_addto(&range.start, delta);
84 return range;
85 }
86
87 static bool addrrange_contains(AddrRange range, Int128 addr)
88 {
89 return int128_ge(addr, range.start)
90 && int128_lt(addr, addrrange_end(range));
91 }
92
93 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
94 {
95 return addrrange_contains(r1, r2.start)
96 || addrrange_contains(r2, r1.start);
97 }
98
99 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
100 {
101 Int128 start = int128_max(r1.start, r2.start);
102 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
103 return addrrange_make(start, int128_sub(end, start));
104 }
105
106 enum ListenerDirection { Forward, Reverse };
107
108 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
109 do { \
110 MemoryListener *_listener; \
111 \
112 switch (_direction) { \
113 case Forward: \
114 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
115 if (_listener->_callback) { \
116 _listener->_callback(_listener, ##_args); \
117 } \
118 } \
119 break; \
120 case Reverse: \
121 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \
122 if (_listener->_callback) { \
123 _listener->_callback(_listener, ##_args); \
124 } \
125 } \
126 break; \
127 default: \
128 abort(); \
129 } \
130 } while (0)
131
132 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
133 do { \
134 MemoryListener *_listener; \
135 \
136 switch (_direction) { \
137 case Forward: \
138 QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \
139 if (_listener->_callback) { \
140 _listener->_callback(_listener, _section, ##_args); \
141 } \
142 } \
143 break; \
144 case Reverse: \
145 QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \
146 if (_listener->_callback) { \
147 _listener->_callback(_listener, _section, ##_args); \
148 } \
149 } \
150 break; \
151 default: \
152 abort(); \
153 } \
154 } while (0)
155
156 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
157 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
158 do { \
159 MemoryRegionSection mrs = section_from_flat_range(fr, \
160 address_space_to_flatview(as)); \
161 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
162 } while(0)
163
164 struct CoalescedMemoryRange {
165 AddrRange addr;
166 QTAILQ_ENTRY(CoalescedMemoryRange) link;
167 };
168
169 struct MemoryRegionIoeventfd {
170 AddrRange addr;
171 bool match_data;
172 uint64_t data;
173 EventNotifier *e;
174 };
175
176 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
177 MemoryRegionIoeventfd *b)
178 {
179 if (int128_lt(a->addr.start, b->addr.start)) {
180 return true;
181 } else if (int128_gt(a->addr.start, b->addr.start)) {
182 return false;
183 } else if (int128_lt(a->addr.size, b->addr.size)) {
184 return true;
185 } else if (int128_gt(a->addr.size, b->addr.size)) {
186 return false;
187 } else if (a->match_data < b->match_data) {
188 return true;
189 } else if (a->match_data > b->match_data) {
190 return false;
191 } else if (a->match_data) {
192 if (a->data < b->data) {
193 return true;
194 } else if (a->data > b->data) {
195 return false;
196 }
197 }
198 if (a->e < b->e) {
199 return true;
200 } else if (a->e > b->e) {
201 return false;
202 }
203 return false;
204 }
205
206 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
207 MemoryRegionIoeventfd *b)
208 {
209 return !memory_region_ioeventfd_before(a, b)
210 && !memory_region_ioeventfd_before(b, a);
211 }
212
213 /* Range of memory in the global map. Addresses are absolute. */
214 struct FlatRange {
215 MemoryRegion *mr;
216 hwaddr offset_in_region;
217 AddrRange addr;
218 uint8_t dirty_log_mask;
219 bool romd_mode;
220 bool readonly;
221 bool nonvolatile;
222 };
223
224 #define FOR_EACH_FLAT_RANGE(var, view) \
225 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
226
227 static inline MemoryRegionSection
228 section_from_flat_range(FlatRange *fr, FlatView *fv)
229 {
230 return (MemoryRegionSection) {
231 .mr = fr->mr,
232 .fv = fv,
233 .offset_within_region = fr->offset_in_region,
234 .size = fr->addr.size,
235 .offset_within_address_space = int128_get64(fr->addr.start),
236 .readonly = fr->readonly,
237 .nonvolatile = fr->nonvolatile,
238 };
239 }
240
241 static bool flatrange_equal(FlatRange *a, FlatRange *b)
242 {
243 return a->mr == b->mr
244 && addrrange_equal(a->addr, b->addr)
245 && a->offset_in_region == b->offset_in_region
246 && a->romd_mode == b->romd_mode
247 && a->readonly == b->readonly
248 && a->nonvolatile == b->nonvolatile;
249 }
250
251 static FlatView *flatview_new(MemoryRegion *mr_root)
252 {
253 FlatView *view;
254
255 view = g_new0(FlatView, 1);
256 view->ref = 1;
257 view->root = mr_root;
258 memory_region_ref(mr_root);
259 trace_flatview_new(view, mr_root);
260
261 return view;
262 }
263
264 /* Insert a range into a given position. Caller is responsible for maintaining
265 * sorting order.
266 */
267 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
268 {
269 if (view->nr == view->nr_allocated) {
270 view->nr_allocated = MAX(2 * view->nr, 10);
271 view->ranges = g_realloc(view->ranges,
272 view->nr_allocated * sizeof(*view->ranges));
273 }
274 memmove(view->ranges + pos + 1, view->ranges + pos,
275 (view->nr - pos) * sizeof(FlatRange));
276 view->ranges[pos] = *range;
277 memory_region_ref(range->mr);
278 ++view->nr;
279 }
280
281 static void flatview_destroy(FlatView *view)
282 {
283 int i;
284
285 trace_flatview_destroy(view, view->root);
286 if (view->dispatch) {
287 address_space_dispatch_free(view->dispatch);
288 }
289 for (i = 0; i < view->nr; i++) {
290 memory_region_unref(view->ranges[i].mr);
291 }
292 g_free(view->ranges);
293 memory_region_unref(view->root);
294 g_free(view);
295 }
296
297 static bool flatview_ref(FlatView *view)
298 {
299 return atomic_fetch_inc_nonzero(&view->ref) > 0;
300 }
301
302 void flatview_unref(FlatView *view)
303 {
304 if (atomic_fetch_dec(&view->ref) == 1) {
305 trace_flatview_destroy_rcu(view, view->root);
306 assert(view->root);
307 call_rcu(view, flatview_destroy, rcu);
308 }
309 }
310
311 static bool can_merge(FlatRange *r1, FlatRange *r2)
312 {
313 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
314 && r1->mr == r2->mr
315 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
316 r1->addr.size),
317 int128_make64(r2->offset_in_region))
318 && r1->dirty_log_mask == r2->dirty_log_mask
319 && r1->romd_mode == r2->romd_mode
320 && r1->readonly == r2->readonly
321 && r1->nonvolatile == r2->nonvolatile;
322 }
323
324 /* Attempt to simplify a view by merging adjacent ranges */
325 static void flatview_simplify(FlatView *view)
326 {
327 unsigned i, j, k;
328
329 i = 0;
330 while (i < view->nr) {
331 j = i + 1;
332 while (j < view->nr
333 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
334 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
335 ++j;
336 }
337 ++i;
338 for (k = i; k < j; k++) {
339 memory_region_unref(view->ranges[k].mr);
340 }
341 memmove(&view->ranges[i], &view->ranges[j],
342 (view->nr - j) * sizeof(view->ranges[j]));
343 view->nr -= j - i;
344 }
345 }
346
347 static bool memory_region_big_endian(MemoryRegion *mr)
348 {
349 #ifdef TARGET_WORDS_BIGENDIAN
350 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
351 #else
352 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
353 #endif
354 }
355
356 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op)
357 {
358 if ((op & MO_BSWAP) != devend_memop(mr->ops->endianness)) {
359 switch (op & MO_SIZE) {
360 case MO_8:
361 break;
362 case MO_16:
363 *data = bswap16(*data);
364 break;
365 case MO_32:
366 *data = bswap32(*data);
367 break;
368 case MO_64:
369 *data = bswap64(*data);
370 break;
371 default:
372 g_assert_not_reached();
373 }
374 }
375 }
376
377 static inline void memory_region_shift_read_access(uint64_t *value,
378 signed shift,
379 uint64_t mask,
380 uint64_t tmp)
381 {
382 if (shift >= 0) {
383 *value |= (tmp & mask) << shift;
384 } else {
385 *value |= (tmp & mask) >> -shift;
386 }
387 }
388
389 static inline uint64_t memory_region_shift_write_access(uint64_t *value,
390 signed shift,
391 uint64_t mask)
392 {
393 uint64_t tmp;
394
395 if (shift >= 0) {
396 tmp = (*value >> shift) & mask;
397 } else {
398 tmp = (*value << -shift) & mask;
399 }
400
401 return tmp;
402 }
403
404 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
405 {
406 MemoryRegion *root;
407 hwaddr abs_addr = offset;
408
409 abs_addr += mr->addr;
410 for (root = mr; root->container; ) {
411 root = root->container;
412 abs_addr += root->addr;
413 }
414
415 return abs_addr;
416 }
417
418 static int get_cpu_index(void)
419 {
420 if (current_cpu) {
421 return current_cpu->cpu_index;
422 }
423 return -1;
424 }
425
426 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
427 hwaddr addr,
428 uint64_t *value,
429 unsigned size,
430 signed shift,
431 uint64_t mask,
432 MemTxAttrs attrs)
433 {
434 uint64_t tmp;
435
436 tmp = mr->ops->read(mr->opaque, addr, size);
437 if (mr->subpage) {
438 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
439 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
440 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
441 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
442 }
443 memory_region_shift_read_access(value, shift, mask, tmp);
444 return MEMTX_OK;
445 }
446
447 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
448 hwaddr addr,
449 uint64_t *value,
450 unsigned size,
451 signed shift,
452 uint64_t mask,
453 MemTxAttrs attrs)
454 {
455 uint64_t tmp = 0;
456 MemTxResult r;
457
458 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
459 if (mr->subpage) {
460 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
461 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
462 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
463 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
464 }
465 memory_region_shift_read_access(value, shift, mask, tmp);
466 return r;
467 }
468
469 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
470 hwaddr addr,
471 uint64_t *value,
472 unsigned size,
473 signed shift,
474 uint64_t mask,
475 MemTxAttrs attrs)
476 {
477 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
478
479 if (mr->subpage) {
480 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
481 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
482 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
483 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
484 }
485 mr->ops->write(mr->opaque, addr, tmp, size);
486 return MEMTX_OK;
487 }
488
489 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
490 hwaddr addr,
491 uint64_t *value,
492 unsigned size,
493 signed shift,
494 uint64_t mask,
495 MemTxAttrs attrs)
496 {
497 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
498
499 if (mr->subpage) {
500 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
501 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
502 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
503 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
504 }
505 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
506 }
507
508 static MemTxResult access_with_adjusted_size(hwaddr addr,
509 uint64_t *value,
510 unsigned size,
511 unsigned access_size_min,
512 unsigned access_size_max,
513 MemTxResult (*access_fn)
514 (MemoryRegion *mr,
515 hwaddr addr,
516 uint64_t *value,
517 unsigned size,
518 signed shift,
519 uint64_t mask,
520 MemTxAttrs attrs),
521 MemoryRegion *mr,
522 MemTxAttrs attrs)
523 {
524 uint64_t access_mask;
525 unsigned access_size;
526 unsigned i;
527 MemTxResult r = MEMTX_OK;
528
529 if (!access_size_min) {
530 access_size_min = 1;
531 }
532 if (!access_size_max) {
533 access_size_max = 4;
534 }
535
536 /* FIXME: support unaligned access? */
537 access_size = MAX(MIN(size, access_size_max), access_size_min);
538 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
539 if (memory_region_big_endian(mr)) {
540 for (i = 0; i < size; i += access_size) {
541 r |= access_fn(mr, addr + i, value, access_size,
542 (size - access_size - i) * 8, access_mask, attrs);
543 }
544 } else {
545 for (i = 0; i < size; i += access_size) {
546 r |= access_fn(mr, addr + i, value, access_size, i * 8,
547 access_mask, attrs);
548 }
549 }
550 return r;
551 }
552
553 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
554 {
555 AddressSpace *as;
556
557 while (mr->container) {
558 mr = mr->container;
559 }
560 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
561 if (mr == as->root) {
562 return as;
563 }
564 }
565 return NULL;
566 }
567
568 /* Render a memory region into the global view. Ranges in @view obscure
569 * ranges in @mr.
570 */
571 static void render_memory_region(FlatView *view,
572 MemoryRegion *mr,
573 Int128 base,
574 AddrRange clip,
575 bool readonly,
576 bool nonvolatile)
577 {
578 MemoryRegion *subregion;
579 unsigned i;
580 hwaddr offset_in_region;
581 Int128 remain;
582 Int128 now;
583 FlatRange fr;
584 AddrRange tmp;
585
586 if (!mr->enabled) {
587 return;
588 }
589
590 int128_addto(&base, int128_make64(mr->addr));
591 readonly |= mr->readonly;
592 nonvolatile |= mr->nonvolatile;
593
594 tmp = addrrange_make(base, mr->size);
595
596 if (!addrrange_intersects(tmp, clip)) {
597 return;
598 }
599
600 clip = addrrange_intersection(tmp, clip);
601
602 if (mr->alias) {
603 int128_subfrom(&base, int128_make64(mr->alias->addr));
604 int128_subfrom(&base, int128_make64(mr->alias_offset));
605 render_memory_region(view, mr->alias, base, clip,
606 readonly, nonvolatile);
607 return;
608 }
609
610 /* Render subregions in priority order. */
611 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
612 render_memory_region(view, subregion, base, clip,
613 readonly, nonvolatile);
614 }
615
616 if (!mr->terminates) {
617 return;
618 }
619
620 offset_in_region = int128_get64(int128_sub(clip.start, base));
621 base = clip.start;
622 remain = clip.size;
623
624 fr.mr = mr;
625 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
626 fr.romd_mode = mr->romd_mode;
627 fr.readonly = readonly;
628 fr.nonvolatile = nonvolatile;
629
630 /* Render the region itself into any gaps left by the current view. */
631 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
632 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
633 continue;
634 }
635 if (int128_lt(base, view->ranges[i].addr.start)) {
636 now = int128_min(remain,
637 int128_sub(view->ranges[i].addr.start, base));
638 fr.offset_in_region = offset_in_region;
639 fr.addr = addrrange_make(base, now);
640 flatview_insert(view, i, &fr);
641 ++i;
642 int128_addto(&base, now);
643 offset_in_region += int128_get64(now);
644 int128_subfrom(&remain, now);
645 }
646 now = int128_sub(int128_min(int128_add(base, remain),
647 addrrange_end(view->ranges[i].addr)),
648 base);
649 int128_addto(&base, now);
650 offset_in_region += int128_get64(now);
651 int128_subfrom(&remain, now);
652 }
653 if (int128_nz(remain)) {
654 fr.offset_in_region = offset_in_region;
655 fr.addr = addrrange_make(base, remain);
656 flatview_insert(view, i, &fr);
657 }
658 }
659
660 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
661 {
662 while (mr->enabled) {
663 if (mr->alias) {
664 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
665 /* The alias is included in its entirety. Use it as
666 * the "real" root, so that we can share more FlatViews.
667 */
668 mr = mr->alias;
669 continue;
670 }
671 } else if (!mr->terminates) {
672 unsigned int found = 0;
673 MemoryRegion *child, *next = NULL;
674 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
675 if (child->enabled) {
676 if (++found > 1) {
677 next = NULL;
678 break;
679 }
680 if (!child->addr && int128_ge(mr->size, child->size)) {
681 /* A child is included in its entirety. If it's the only
682 * enabled one, use it in the hope of finding an alias down the
683 * way. This will also let us share FlatViews.
684 */
685 next = child;
686 }
687 }
688 }
689 if (found == 0) {
690 return NULL;
691 }
692 if (next) {
693 mr = next;
694 continue;
695 }
696 }
697
698 return mr;
699 }
700
701 return NULL;
702 }
703
704 /* Render a memory topology into a list of disjoint absolute ranges. */
705 static FlatView *generate_memory_topology(MemoryRegion *mr)
706 {
707 int i;
708 FlatView *view;
709
710 view = flatview_new(mr);
711
712 if (mr) {
713 render_memory_region(view, mr, int128_zero(),
714 addrrange_make(int128_zero(), int128_2_64()),
715 false, false);
716 }
717 flatview_simplify(view);
718
719 view->dispatch = address_space_dispatch_new(view);
720 for (i = 0; i < view->nr; i++) {
721 MemoryRegionSection mrs =
722 section_from_flat_range(&view->ranges[i], view);
723 flatview_add_to_dispatch(view, &mrs);
724 }
725 address_space_dispatch_compact(view->dispatch);
726 g_hash_table_replace(flat_views, mr, view);
727
728 return view;
729 }
730
731 static void address_space_add_del_ioeventfds(AddressSpace *as,
732 MemoryRegionIoeventfd *fds_new,
733 unsigned fds_new_nb,
734 MemoryRegionIoeventfd *fds_old,
735 unsigned fds_old_nb)
736 {
737 unsigned iold, inew;
738 MemoryRegionIoeventfd *fd;
739 MemoryRegionSection section;
740
741 /* Generate a symmetric difference of the old and new fd sets, adding
742 * and deleting as necessary.
743 */
744
745 iold = inew = 0;
746 while (iold < fds_old_nb || inew < fds_new_nb) {
747 if (iold < fds_old_nb
748 && (inew == fds_new_nb
749 || memory_region_ioeventfd_before(&fds_old[iold],
750 &fds_new[inew]))) {
751 fd = &fds_old[iold];
752 section = (MemoryRegionSection) {
753 .fv = address_space_to_flatview(as),
754 .offset_within_address_space = int128_get64(fd->addr.start),
755 .size = fd->addr.size,
756 };
757 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
758 fd->match_data, fd->data, fd->e);
759 ++iold;
760 } else if (inew < fds_new_nb
761 && (iold == fds_old_nb
762 || memory_region_ioeventfd_before(&fds_new[inew],
763 &fds_old[iold]))) {
764 fd = &fds_new[inew];
765 section = (MemoryRegionSection) {
766 .fv = address_space_to_flatview(as),
767 .offset_within_address_space = int128_get64(fd->addr.start),
768 .size = fd->addr.size,
769 };
770 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
771 fd->match_data, fd->data, fd->e);
772 ++inew;
773 } else {
774 ++iold;
775 ++inew;
776 }
777 }
778 }
779
780 FlatView *address_space_get_flatview(AddressSpace *as)
781 {
782 FlatView *view;
783
784 RCU_READ_LOCK_GUARD();
785 do {
786 view = address_space_to_flatview(as);
787 /* If somebody has replaced as->current_map concurrently,
788 * flatview_ref returns false.
789 */
790 } while (!flatview_ref(view));
791 return view;
792 }
793
794 static void address_space_update_ioeventfds(AddressSpace *as)
795 {
796 FlatView *view;
797 FlatRange *fr;
798 unsigned ioeventfd_nb = 0;
799 MemoryRegionIoeventfd *ioeventfds = NULL;
800 AddrRange tmp;
801 unsigned i;
802
803 view = address_space_get_flatview(as);
804 FOR_EACH_FLAT_RANGE(fr, view) {
805 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
806 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
807 int128_sub(fr->addr.start,
808 int128_make64(fr->offset_in_region)));
809 if (addrrange_intersects(fr->addr, tmp)) {
810 ++ioeventfd_nb;
811 ioeventfds = g_realloc(ioeventfds,
812 ioeventfd_nb * sizeof(*ioeventfds));
813 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
814 ioeventfds[ioeventfd_nb-1].addr = tmp;
815 }
816 }
817 }
818
819 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
820 as->ioeventfds, as->ioeventfd_nb);
821
822 g_free(as->ioeventfds);
823 as->ioeventfds = ioeventfds;
824 as->ioeventfd_nb = ioeventfd_nb;
825 flatview_unref(view);
826 }
827
828 /*
829 * Notify the memory listeners about the coalesced IO change events of
830 * range `cmr'. Only the part that has intersection of the specified
831 * FlatRange will be sent.
832 */
833 static void flat_range_coalesced_io_notify(FlatRange *fr, AddressSpace *as,
834 CoalescedMemoryRange *cmr, bool add)
835 {
836 AddrRange tmp;
837
838 tmp = addrrange_shift(cmr->addr,
839 int128_sub(fr->addr.start,
840 int128_make64(fr->offset_in_region)));
841 if (!addrrange_intersects(tmp, fr->addr)) {
842 return;
843 }
844 tmp = addrrange_intersection(tmp, fr->addr);
845
846 if (add) {
847 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
848 int128_get64(tmp.start),
849 int128_get64(tmp.size));
850 } else {
851 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
852 int128_get64(tmp.start),
853 int128_get64(tmp.size));
854 }
855 }
856
857 static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
858 {
859 CoalescedMemoryRange *cmr;
860
861 QTAILQ_FOREACH(cmr, &fr->mr->coalesced, link) {
862 flat_range_coalesced_io_notify(fr, as, cmr, false);
863 }
864 }
865
866 static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
867 {
868 MemoryRegion *mr = fr->mr;
869 CoalescedMemoryRange *cmr;
870
871 if (QTAILQ_EMPTY(&mr->coalesced)) {
872 return;
873 }
874
875 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
876 flat_range_coalesced_io_notify(fr, as, cmr, true);
877 }
878 }
879
880 static void address_space_update_topology_pass(AddressSpace *as,
881 const FlatView *old_view,
882 const FlatView *new_view,
883 bool adding)
884 {
885 unsigned iold, inew;
886 FlatRange *frold, *frnew;
887
888 /* Generate a symmetric difference of the old and new memory maps.
889 * Kill ranges in the old map, and instantiate ranges in the new map.
890 */
891 iold = inew = 0;
892 while (iold < old_view->nr || inew < new_view->nr) {
893 if (iold < old_view->nr) {
894 frold = &old_view->ranges[iold];
895 } else {
896 frold = NULL;
897 }
898 if (inew < new_view->nr) {
899 frnew = &new_view->ranges[inew];
900 } else {
901 frnew = NULL;
902 }
903
904 if (frold
905 && (!frnew
906 || int128_lt(frold->addr.start, frnew->addr.start)
907 || (int128_eq(frold->addr.start, frnew->addr.start)
908 && !flatrange_equal(frold, frnew)))) {
909 /* In old but not in new, or in both but attributes changed. */
910
911 if (!adding) {
912 flat_range_coalesced_io_del(frold, as);
913 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
914 }
915
916 ++iold;
917 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
918 /* In both and unchanged (except logging may have changed) */
919
920 if (adding) {
921 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
922 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
923 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
924 frold->dirty_log_mask,
925 frnew->dirty_log_mask);
926 }
927 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
928 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
929 frold->dirty_log_mask,
930 frnew->dirty_log_mask);
931 }
932 }
933
934 ++iold;
935 ++inew;
936 } else {
937 /* In new */
938
939 if (adding) {
940 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
941 flat_range_coalesced_io_add(frnew, as);
942 }
943
944 ++inew;
945 }
946 }
947 }
948
949 static void flatviews_init(void)
950 {
951 static FlatView *empty_view;
952
953 if (flat_views) {
954 return;
955 }
956
957 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
958 (GDestroyNotify) flatview_unref);
959 if (!empty_view) {
960 empty_view = generate_memory_topology(NULL);
961 /* We keep it alive forever in the global variable. */
962 flatview_ref(empty_view);
963 } else {
964 g_hash_table_replace(flat_views, NULL, empty_view);
965 flatview_ref(empty_view);
966 }
967 }
968
969 static void flatviews_reset(void)
970 {
971 AddressSpace *as;
972
973 if (flat_views) {
974 g_hash_table_unref(flat_views);
975 flat_views = NULL;
976 }
977 flatviews_init();
978
979 /* Render unique FVs */
980 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
981 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
982
983 if (g_hash_table_lookup(flat_views, physmr)) {
984 continue;
985 }
986
987 generate_memory_topology(physmr);
988 }
989 }
990
991 static void address_space_set_flatview(AddressSpace *as)
992 {
993 FlatView *old_view = address_space_to_flatview(as);
994 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
995 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
996
997 assert(new_view);
998
999 if (old_view == new_view) {
1000 return;
1001 }
1002
1003 if (old_view) {
1004 flatview_ref(old_view);
1005 }
1006
1007 flatview_ref(new_view);
1008
1009 if (!QTAILQ_EMPTY(&as->listeners)) {
1010 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1011
1012 if (!old_view2) {
1013 old_view2 = &tmpview;
1014 }
1015 address_space_update_topology_pass(as, old_view2, new_view, false);
1016 address_space_update_topology_pass(as, old_view2, new_view, true);
1017 }
1018
1019 /* Writes are protected by the BQL. */
1020 atomic_rcu_set(&as->current_map, new_view);
1021 if (old_view) {
1022 flatview_unref(old_view);
1023 }
1024
1025 /* Note that all the old MemoryRegions are still alive up to this
1026 * point. This relieves most MemoryListeners from the need to
1027 * ref/unref the MemoryRegions they get---unless they use them
1028 * outside the iothread mutex, in which case precise reference
1029 * counting is necessary.
1030 */
1031 if (old_view) {
1032 flatview_unref(old_view);
1033 }
1034 }
1035
1036 static void address_space_update_topology(AddressSpace *as)
1037 {
1038 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1039
1040 flatviews_init();
1041 if (!g_hash_table_lookup(flat_views, physmr)) {
1042 generate_memory_topology(physmr);
1043 }
1044 address_space_set_flatview(as);
1045 }
1046
1047 void memory_region_transaction_begin(void)
1048 {
1049 qemu_flush_coalesced_mmio_buffer();
1050 ++memory_region_transaction_depth;
1051 }
1052
1053 void memory_region_transaction_commit(void)
1054 {
1055 AddressSpace *as;
1056
1057 assert(memory_region_transaction_depth);
1058 assert(qemu_mutex_iothread_locked());
1059
1060 --memory_region_transaction_depth;
1061 if (!memory_region_transaction_depth) {
1062 if (memory_region_update_pending) {
1063 flatviews_reset();
1064
1065 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1066
1067 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1068 address_space_set_flatview(as);
1069 address_space_update_ioeventfds(as);
1070 }
1071 memory_region_update_pending = false;
1072 ioeventfd_update_pending = false;
1073 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1074 } else if (ioeventfd_update_pending) {
1075 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1076 address_space_update_ioeventfds(as);
1077 }
1078 ioeventfd_update_pending = false;
1079 }
1080 }
1081 }
1082
1083 static void memory_region_destructor_none(MemoryRegion *mr)
1084 {
1085 }
1086
1087 static void memory_region_destructor_ram(MemoryRegion *mr)
1088 {
1089 qemu_ram_free(mr->ram_block);
1090 }
1091
1092 static bool memory_region_need_escape(char c)
1093 {
1094 return c == '/' || c == '[' || c == '\\' || c == ']';
1095 }
1096
1097 static char *memory_region_escape_name(const char *name)
1098 {
1099 const char *p;
1100 char *escaped, *q;
1101 uint8_t c;
1102 size_t bytes = 0;
1103
1104 for (p = name; *p; p++) {
1105 bytes += memory_region_need_escape(*p) ? 4 : 1;
1106 }
1107 if (bytes == p - name) {
1108 return g_memdup(name, bytes + 1);
1109 }
1110
1111 escaped = g_malloc(bytes + 1);
1112 for (p = name, q = escaped; *p; p++) {
1113 c = *p;
1114 if (unlikely(memory_region_need_escape(c))) {
1115 *q++ = '\\';
1116 *q++ = 'x';
1117 *q++ = "0123456789abcdef"[c >> 4];
1118 c = "0123456789abcdef"[c & 15];
1119 }
1120 *q++ = c;
1121 }
1122 *q = 0;
1123 return escaped;
1124 }
1125
1126 static void memory_region_do_init(MemoryRegion *mr,
1127 Object *owner,
1128 const char *name,
1129 uint64_t size)
1130 {
1131 mr->size = int128_make64(size);
1132 if (size == UINT64_MAX) {
1133 mr->size = int128_2_64();
1134 }
1135 mr->name = g_strdup(name);
1136 mr->owner = owner;
1137 mr->ram_block = NULL;
1138
1139 if (name) {
1140 char *escaped_name = memory_region_escape_name(name);
1141 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1142
1143 if (!owner) {
1144 owner = container_get(qdev_get_machine(), "/unattached");
1145 }
1146
1147 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
1148 object_unref(OBJECT(mr));
1149 g_free(name_array);
1150 g_free(escaped_name);
1151 }
1152 }
1153
1154 void memory_region_init(MemoryRegion *mr,
1155 Object *owner,
1156 const char *name,
1157 uint64_t size)
1158 {
1159 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1160 memory_region_do_init(mr, owner, name, size);
1161 }
1162
1163 static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1164 void *opaque, Error **errp)
1165 {
1166 MemoryRegion *mr = MEMORY_REGION(obj);
1167 uint64_t value = mr->addr;
1168
1169 visit_type_uint64(v, name, &value, errp);
1170 }
1171
1172 static void memory_region_get_container(Object *obj, Visitor *v,
1173 const char *name, void *opaque,
1174 Error **errp)
1175 {
1176 MemoryRegion *mr = MEMORY_REGION(obj);
1177 gchar *path = (gchar *)"";
1178
1179 if (mr->container) {
1180 path = object_get_canonical_path(OBJECT(mr->container));
1181 }
1182 visit_type_str(v, name, &path, errp);
1183 if (mr->container) {
1184 g_free(path);
1185 }
1186 }
1187
1188 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1189 const char *part)
1190 {
1191 MemoryRegion *mr = MEMORY_REGION(obj);
1192
1193 return OBJECT(mr->container);
1194 }
1195
1196 static void memory_region_get_priority(Object *obj, Visitor *v,
1197 const char *name, void *opaque,
1198 Error **errp)
1199 {
1200 MemoryRegion *mr = MEMORY_REGION(obj);
1201 int32_t value = mr->priority;
1202
1203 visit_type_int32(v, name, &value, errp);
1204 }
1205
1206 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1207 void *opaque, Error **errp)
1208 {
1209 MemoryRegion *mr = MEMORY_REGION(obj);
1210 uint64_t value = memory_region_size(mr);
1211
1212 visit_type_uint64(v, name, &value, errp);
1213 }
1214
1215 static void memory_region_initfn(Object *obj)
1216 {
1217 MemoryRegion *mr = MEMORY_REGION(obj);
1218 ObjectProperty *op;
1219
1220 mr->ops = &unassigned_mem_ops;
1221 mr->enabled = true;
1222 mr->romd_mode = true;
1223 mr->global_locking = true;
1224 mr->destructor = memory_region_destructor_none;
1225 QTAILQ_INIT(&mr->subregions);
1226 QTAILQ_INIT(&mr->coalesced);
1227
1228 op = object_property_add(OBJECT(mr), "container",
1229 "link<" TYPE_MEMORY_REGION ">",
1230 memory_region_get_container,
1231 NULL, /* memory_region_set_container */
1232 NULL, NULL, &error_abort);
1233 op->resolve = memory_region_resolve_container;
1234
1235 object_property_add(OBJECT(mr), "addr", "uint64",
1236 memory_region_get_addr,
1237 NULL, /* memory_region_set_addr */
1238 NULL, NULL, &error_abort);
1239 object_property_add(OBJECT(mr), "priority", "uint32",
1240 memory_region_get_priority,
1241 NULL, /* memory_region_set_priority */
1242 NULL, NULL, &error_abort);
1243 object_property_add(OBJECT(mr), "size", "uint64",
1244 memory_region_get_size,
1245 NULL, /* memory_region_set_size, */
1246 NULL, NULL, &error_abort);
1247 }
1248
1249 static int qemu_target_backtrace(target_ulong *array, size_t size)
1250 {
1251 int n = 0;
1252 if (size >= 2) {
1253 #if defined(TARGET_ARM)
1254 CPUArchState *env = current_cpu->env_ptr;
1255 array[0] = env->regs[15];
1256 array[1] = env->regs[14];
1257 #elif defined(TARGET_MIPS)
1258 CPUArchState *env = current_cpu->env_ptr;
1259 array[0] = env->active_tc.PC;
1260 array[1] = env->active_tc.gpr[31];
1261 #else
1262 array[0] = 0;
1263 array[1] = 0;
1264 #endif
1265 n = 2;
1266 }
1267 return n;
1268 }
1269
1270 #include "disas/disas.h"
1271 const char *qemu_sprint_backtrace(char *buffer, size_t length)
1272 {
1273 char *p = buffer;
1274 if (current_cpu) {
1275 target_ulong caller[2];
1276 const char *symbol;
1277 qemu_target_backtrace(caller, 2);
1278 symbol = lookup_symbol(caller[0]);
1279 p += sprintf(p, "[%s]", symbol);
1280 symbol = lookup_symbol(caller[1]);
1281 p += sprintf(p, "[%s]", symbol);
1282 } else {
1283 p += sprintf(p, "[cpu not running]");
1284 }
1285 assert((p - buffer) < length);
1286 return buffer;
1287 }
1288
1289 static void iommu_memory_region_initfn(Object *obj)
1290 {
1291 MemoryRegion *mr = MEMORY_REGION(obj);
1292
1293 mr->is_iommu = true;
1294 }
1295
1296 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1297 unsigned size)
1298 {
1299 if (trace_unassigned) {
1300 char buffer[256];
1301 fprintf(stderr, "Unassigned mem read " TARGET_FMT_plx " %s\n",
1302 addr, qemu_sprint_backtrace(buffer, sizeof(buffer)));
1303 }
1304 //~ vm_stop(0);
1305 return 0;
1306 }
1307
1308 static void unassigned_mem_write(void *opaque, hwaddr addr,
1309 uint64_t val, unsigned size)
1310 {
1311 if (trace_unassigned) {
1312 char buffer[256];
1313 fprintf(stderr, "Unassigned mem write " TARGET_FMT_plx
1314 " = 0x%" PRIx64 " %s\n",
1315 addr, val, qemu_sprint_backtrace(buffer, sizeof(buffer)));
1316 }
1317 }
1318
1319 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1320 unsigned size, bool is_write,
1321 MemTxAttrs attrs)
1322 {
1323 return false;
1324 }
1325
1326 const MemoryRegionOps unassigned_mem_ops = {
1327 .valid.accepts = unassigned_mem_accepts,
1328 .endianness = DEVICE_NATIVE_ENDIAN,
1329 };
1330
1331 static uint64_t memory_region_ram_device_read(void *opaque,
1332 hwaddr addr, unsigned size)
1333 {
1334 MemoryRegion *mr = opaque;
1335 uint64_t data = (uint64_t)~0;
1336
1337 switch (size) {
1338 case 1:
1339 data = *(uint8_t *)(mr->ram_block->host + addr);
1340 break;
1341 case 2:
1342 data = *(uint16_t *)(mr->ram_block->host + addr);
1343 break;
1344 case 4:
1345 data = *(uint32_t *)(mr->ram_block->host + addr);
1346 break;
1347 case 8:
1348 data = *(uint64_t *)(mr->ram_block->host + addr);
1349 break;
1350 }
1351
1352 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1353
1354 return data;
1355 }
1356
1357 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1358 uint64_t data, unsigned size)
1359 {
1360 MemoryRegion *mr = opaque;
1361
1362 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1363
1364 switch (size) {
1365 case 1:
1366 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1367 break;
1368 case 2:
1369 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1370 break;
1371 case 4:
1372 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1373 break;
1374 case 8:
1375 *(uint64_t *)(mr->ram_block->host + addr) = data;
1376 break;
1377 }
1378 }
1379
1380 static const MemoryRegionOps ram_device_mem_ops = {
1381 .read = memory_region_ram_device_read,
1382 .write = memory_region_ram_device_write,
1383 .endianness = DEVICE_HOST_ENDIAN,
1384 .valid = {
1385 .min_access_size = 1,
1386 .max_access_size = 8,
1387 .unaligned = true,
1388 },
1389 .impl = {
1390 .min_access_size = 1,
1391 .max_access_size = 8,
1392 .unaligned = true,
1393 },
1394 };
1395
1396 bool memory_region_access_valid(MemoryRegion *mr,
1397 hwaddr addr,
1398 unsigned size,
1399 bool is_write,
1400 MemTxAttrs attrs)
1401 {
1402 int access_size_min, access_size_max;
1403 int access_size, i;
1404
1405 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1406 fprintf(stderr, "Misaligned i/o to address %08" HWADDR_PRIx
1407 " with size %u for memory region %s\n",
1408 addr, size, mr->name);
1409 return false;
1410 }
1411
1412 if (!mr->ops->valid.accepts) {
1413 return true;
1414 }
1415
1416 access_size_min = mr->ops->valid.min_access_size;
1417 if (!mr->ops->valid.min_access_size) {
1418 access_size_min = 1;
1419 }
1420
1421 access_size_max = mr->ops->valid.max_access_size;
1422 if (!mr->ops->valid.max_access_size) {
1423 access_size_max = 4;
1424 }
1425
1426 access_size = MAX(MIN(size, access_size_max), access_size_min);
1427 for (i = 0; i < size; i += access_size) {
1428 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1429 is_write, attrs)) {
1430 return false;
1431 }
1432 }
1433
1434 return true;
1435 }
1436
1437 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1438 hwaddr addr,
1439 uint64_t *pval,
1440 unsigned size,
1441 MemTxAttrs attrs)
1442 {
1443 *pval = 0;
1444
1445 if (mr->ops->read) {
1446 return access_with_adjusted_size(addr, pval, size,
1447 mr->ops->impl.min_access_size,
1448 mr->ops->impl.max_access_size,
1449 memory_region_read_accessor,
1450 mr, attrs);
1451 } else {
1452 return access_with_adjusted_size(addr, pval, size,
1453 mr->ops->impl.min_access_size,
1454 mr->ops->impl.max_access_size,
1455 memory_region_read_with_attrs_accessor,
1456 mr, attrs);
1457 }
1458 }
1459
1460 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1461 hwaddr addr,
1462 uint64_t *pval,
1463 MemOp op,
1464 MemTxAttrs attrs)
1465 {
1466 unsigned size = memop_size(op);
1467 MemTxResult r;
1468
1469 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
1470 *pval = unassigned_mem_read(mr, addr, size);
1471 return MEMTX_DECODE_ERROR;
1472 }
1473
1474 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1475 adjust_endianness(mr, pval, op);
1476 return r;
1477 }
1478
1479 /* Return true if an eventfd was signalled */
1480 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1481 hwaddr addr,
1482 uint64_t data,
1483 unsigned size,
1484 MemTxAttrs attrs)
1485 {
1486 MemoryRegionIoeventfd ioeventfd = {
1487 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1488 .data = data,
1489 };
1490 unsigned i;
1491
1492 for (i = 0; i < mr->ioeventfd_nb; i++) {
1493 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1494 ioeventfd.e = mr->ioeventfds[i].e;
1495
1496 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
1497 event_notifier_set(ioeventfd.e);
1498 return true;
1499 }
1500 }
1501
1502 return false;
1503 }
1504
1505 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1506 hwaddr addr,
1507 uint64_t data,
1508 MemOp op,
1509 MemTxAttrs attrs)
1510 {
1511 unsigned size = memop_size(op);
1512
1513 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
1514 unassigned_mem_write(mr, addr, data, size);
1515 return MEMTX_DECODE_ERROR;
1516 }
1517
1518 adjust_endianness(mr, &data, op);
1519
1520 if ((!kvm_eventfds_enabled()) &&
1521 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1522 return MEMTX_OK;
1523 }
1524
1525 if (mr->ops->write) {
1526 return access_with_adjusted_size(addr, &data, size,
1527 mr->ops->impl.min_access_size,
1528 mr->ops->impl.max_access_size,
1529 memory_region_write_accessor, mr,
1530 attrs);
1531 } else {
1532 return
1533 access_with_adjusted_size(addr, &data, size,
1534 mr->ops->impl.min_access_size,
1535 mr->ops->impl.max_access_size,
1536 memory_region_write_with_attrs_accessor,
1537 mr, attrs);
1538 }
1539 }
1540
1541 void memory_region_init_io(MemoryRegion *mr,
1542 Object *owner,
1543 const MemoryRegionOps *ops,
1544 void *opaque,
1545 const char *name,
1546 uint64_t size)
1547 {
1548 memory_region_init(mr, owner, name, size);
1549 mr->ops = ops ? ops : &unassigned_mem_ops;
1550 mr->opaque = opaque;
1551 mr->terminates = true;
1552 }
1553
1554 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1555 Object *owner,
1556 const char *name,
1557 uint64_t size,
1558 Error **errp)
1559 {
1560 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1561 }
1562
1563 void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1564 Object *owner,
1565 const char *name,
1566 uint64_t size,
1567 bool share,
1568 Error **errp)
1569 {
1570 Error *err = NULL;
1571 memory_region_init(mr, owner, name, size);
1572 mr->ram = true;
1573 mr->terminates = true;
1574 mr->destructor = memory_region_destructor_ram;
1575 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
1576 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1577 if (err) {
1578 mr->size = int128_zero();
1579 object_unparent(OBJECT(mr));
1580 error_propagate(errp, err);
1581 }
1582 }
1583
1584 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1585 Object *owner,
1586 const char *name,
1587 uint64_t size,
1588 uint64_t max_size,
1589 void (*resized)(const char*,
1590 uint64_t length,
1591 void *host),
1592 Error **errp)
1593 {
1594 Error *err = NULL;
1595 memory_region_init(mr, owner, name, size);
1596 mr->ram = true;
1597 mr->terminates = true;
1598 mr->destructor = memory_region_destructor_ram;
1599 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1600 mr, &err);
1601 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1602 if (err) {
1603 mr->size = int128_zero();
1604 object_unparent(OBJECT(mr));
1605 error_propagate(errp, err);
1606 }
1607 }
1608
1609 #ifdef CONFIG_POSIX
1610 void memory_region_init_ram_from_file(MemoryRegion *mr,
1611 struct Object *owner,
1612 const char *name,
1613 uint64_t size,
1614 uint64_t align,
1615 uint32_t ram_flags,
1616 const char *path,
1617 Error **errp)
1618 {
1619 Error *err = NULL;
1620 memory_region_init(mr, owner, name, size);
1621 mr->ram = true;
1622 mr->terminates = true;
1623 mr->destructor = memory_region_destructor_ram;
1624 mr->align = align;
1625 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err);
1626 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1627 if (err) {
1628 mr->size = int128_zero();
1629 object_unparent(OBJECT(mr));
1630 error_propagate(errp, err);
1631 }
1632 }
1633
1634 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1635 struct Object *owner,
1636 const char *name,
1637 uint64_t size,
1638 bool share,
1639 int fd,
1640 Error **errp)
1641 {
1642 Error *err = NULL;
1643 memory_region_init(mr, owner, name, size);
1644 mr->ram = true;
1645 mr->terminates = true;
1646 mr->destructor = memory_region_destructor_ram;
1647 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1648 share ? RAM_SHARED : 0,
1649 fd, &err);
1650 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1651 if (err) {
1652 mr->size = int128_zero();
1653 object_unparent(OBJECT(mr));
1654 error_propagate(errp, err);
1655 }
1656 }
1657 #endif
1658
1659 void memory_region_init_ram_ptr(MemoryRegion *mr,
1660 Object *owner,
1661 const char *name,
1662 uint64_t size,
1663 void *ptr)
1664 {
1665 memory_region_init(mr, owner, name, size);
1666 mr->ram = true;
1667 mr->terminates = true;
1668 mr->destructor = memory_region_destructor_ram;
1669 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1670
1671 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1672 assert(ptr != NULL);
1673 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1674 }
1675
1676 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1677 Object *owner,
1678 const char *name,
1679 uint64_t size,
1680 void *ptr)
1681 {
1682 memory_region_init(mr, owner, name, size);
1683 mr->ram = true;
1684 mr->terminates = true;
1685 mr->ram_device = true;
1686 mr->ops = &ram_device_mem_ops;
1687 mr->opaque = mr;
1688 mr->destructor = memory_region_destructor_ram;
1689 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1690 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1691 assert(ptr != NULL);
1692 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1693 }
1694
1695 void memory_region_init_alias(MemoryRegion *mr,
1696 Object *owner,
1697 const char *name,
1698 MemoryRegion *orig,
1699 hwaddr offset,
1700 uint64_t size)
1701 {
1702 memory_region_init(mr, owner, name, size);
1703 mr->alias = orig;
1704 mr->alias_offset = offset;
1705 }
1706
1707 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1708 struct Object *owner,
1709 const char *name,
1710 uint64_t size,
1711 Error **errp)
1712 {
1713 Error *err = NULL;
1714 memory_region_init(mr, owner, name, size);
1715 mr->ram = true;
1716 mr->readonly = true;
1717 mr->terminates = true;
1718 mr->destructor = memory_region_destructor_ram;
1719 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1720 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1721 if (err) {
1722 mr->size = int128_zero();
1723 object_unparent(OBJECT(mr));
1724 error_propagate(errp, err);
1725 }
1726 }
1727
1728 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1729 Object *owner,
1730 const MemoryRegionOps *ops,
1731 void *opaque,
1732 const char *name,
1733 uint64_t size,
1734 Error **errp)
1735 {
1736 Error *err = NULL;
1737 assert(ops);
1738 memory_region_init(mr, owner, name, size);
1739 mr->ops = ops;
1740 mr->opaque = opaque;
1741 mr->terminates = true;
1742 mr->rom_device = true;
1743 mr->destructor = memory_region_destructor_ram;
1744 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1745 if (err) {
1746 mr->size = int128_zero();
1747 object_unparent(OBJECT(mr));
1748 error_propagate(errp, err);
1749 }
1750 }
1751
1752 void memory_region_init_iommu(void *_iommu_mr,
1753 size_t instance_size,
1754 const char *mrtypename,
1755 Object *owner,
1756 const char *name,
1757 uint64_t size)
1758 {
1759 struct IOMMUMemoryRegion *iommu_mr;
1760 struct MemoryRegion *mr;
1761
1762 object_initialize(_iommu_mr, instance_size, mrtypename);
1763 mr = MEMORY_REGION(_iommu_mr);
1764 memory_region_do_init(mr, owner, name, size);
1765 iommu_mr = IOMMU_MEMORY_REGION(mr);
1766 mr->terminates = true; /* then re-forwards */
1767 QLIST_INIT(&iommu_mr->iommu_notify);
1768 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1769 }
1770
1771 static void memory_region_finalize(Object *obj)
1772 {
1773 MemoryRegion *mr = MEMORY_REGION(obj);
1774
1775 assert(!mr->container);
1776
1777 /* We know the region is not visible in any address space (it
1778 * does not have a container and cannot be a root either because
1779 * it has no references, so we can blindly clear mr->enabled.
1780 * memory_region_set_enabled instead could trigger a transaction
1781 * and cause an infinite loop.
1782 */
1783 mr->enabled = false;
1784 memory_region_transaction_begin();
1785 while (!QTAILQ_EMPTY(&mr->subregions)) {
1786 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1787 memory_region_del_subregion(mr, subregion);
1788 }
1789 memory_region_transaction_commit();
1790
1791 mr->destructor(mr);
1792 memory_region_clear_coalescing(mr);
1793 g_free((char *)mr->name);
1794 g_free(mr->ioeventfds);
1795 }
1796
1797 Object *memory_region_owner(MemoryRegion *mr)
1798 {
1799 Object *obj = OBJECT(mr);
1800 return obj->parent;
1801 }
1802
1803 void memory_region_ref(MemoryRegion *mr)
1804 {
1805 /* MMIO callbacks most likely will access data that belongs
1806 * to the owner, hence the need to ref/unref the owner whenever
1807 * the memory region is in use.
1808 *
1809 * The memory region is a child of its owner. As long as the
1810 * owner doesn't call unparent itself on the memory region,
1811 * ref-ing the owner will also keep the memory region alive.
1812 * Memory regions without an owner are supposed to never go away;
1813 * we do not ref/unref them because it slows down DMA sensibly.
1814 */
1815 if (mr && mr->owner) {
1816 object_ref(mr->owner);
1817 }
1818 }
1819
1820 void memory_region_unref(MemoryRegion *mr)
1821 {
1822 if (mr && mr->owner) {
1823 object_unref(mr->owner);
1824 }
1825 }
1826
1827 uint64_t memory_region_size(MemoryRegion *mr)
1828 {
1829 if (int128_eq(mr->size, int128_2_64())) {
1830 return UINT64_MAX;
1831 }
1832 return int128_get64(mr->size);
1833 }
1834
1835 const char *memory_region_name(const MemoryRegion *mr)
1836 {
1837 if (!mr->name) {
1838 ((MemoryRegion *)mr)->name =
1839 object_get_canonical_path_component(OBJECT(mr));
1840 }
1841 return mr->name;
1842 }
1843
1844 bool memory_region_is_ram_device(MemoryRegion *mr)
1845 {
1846 return mr->ram_device;
1847 }
1848
1849 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1850 {
1851 uint8_t mask = mr->dirty_log_mask;
1852 if (global_dirty_log && mr->ram_block) {
1853 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1854 }
1855 return mask;
1856 }
1857
1858 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1859 {
1860 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1861 }
1862
1863 static int memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr,
1864 Error **errp)
1865 {
1866 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1867 IOMMUNotifier *iommu_notifier;
1868 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1869 int ret = 0;
1870
1871 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1872 flags |= iommu_notifier->notifier_flags;
1873 }
1874
1875 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1876 ret = imrc->notify_flag_changed(iommu_mr,
1877 iommu_mr->iommu_notify_flags,
1878 flags, errp);
1879 }
1880
1881 if (!ret) {
1882 iommu_mr->iommu_notify_flags = flags;
1883 }
1884 return ret;
1885 }
1886
1887 int memory_region_register_iommu_notifier(MemoryRegion *mr,
1888 IOMMUNotifier *n, Error **errp)
1889 {
1890 IOMMUMemoryRegion *iommu_mr;
1891 int ret;
1892
1893 if (mr->alias) {
1894 return memory_region_register_iommu_notifier(mr->alias, n, errp);
1895 }
1896
1897 /* We need to register for at least one bitfield */
1898 iommu_mr = IOMMU_MEMORY_REGION(mr);
1899 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1900 assert(n->start <= n->end);
1901 assert(n->iommu_idx >= 0 &&
1902 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1903
1904 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1905 ret = memory_region_update_iommu_notify_flags(iommu_mr, errp);
1906 if (ret) {
1907 QLIST_REMOVE(n, node);
1908 }
1909 return ret;
1910 }
1911
1912 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1913 {
1914 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1915
1916 if (imrc->get_min_page_size) {
1917 return imrc->get_min_page_size(iommu_mr);
1918 }
1919 return TARGET_PAGE_SIZE;
1920 }
1921
1922 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1923 {
1924 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1925 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1926 hwaddr addr, granularity;
1927 IOMMUTLBEntry iotlb;
1928
1929 /* If the IOMMU has its own replay callback, override */
1930 if (imrc->replay) {
1931 imrc->replay(iommu_mr, n);
1932 return;
1933 }
1934
1935 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1936
1937 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1938 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
1939 if (iotlb.perm != IOMMU_NONE) {
1940 n->notify(n, &iotlb);
1941 }
1942
1943 /* if (2^64 - MR size) < granularity, it's possible to get an
1944 * infinite loop here. This should catch such a wraparound */
1945 if ((addr + granularity) < addr) {
1946 break;
1947 }
1948 }
1949 }
1950
1951 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1952 IOMMUNotifier *n)
1953 {
1954 IOMMUMemoryRegion *iommu_mr;
1955
1956 if (mr->alias) {
1957 memory_region_unregister_iommu_notifier(mr->alias, n);
1958 return;
1959 }
1960 QLIST_REMOVE(n, node);
1961 iommu_mr = IOMMU_MEMORY_REGION(mr);
1962 memory_region_update_iommu_notify_flags(iommu_mr, NULL);
1963 }
1964
1965 void memory_region_notify_one(IOMMUNotifier *notifier,
1966 IOMMUTLBEntry *entry)
1967 {
1968 IOMMUNotifierFlag request_flags;
1969 hwaddr entry_end = entry->iova + entry->addr_mask;
1970
1971 /*
1972 * Skip the notification if the notification does not overlap
1973 * with registered range.
1974 */
1975 if (notifier->start > entry_end || notifier->end < entry->iova) {
1976 return;
1977 }
1978
1979 assert(entry->iova >= notifier->start && entry_end <= notifier->end);
1980
1981 if (entry->perm & IOMMU_RW) {
1982 request_flags = IOMMU_NOTIFIER_MAP;
1983 } else {
1984 request_flags = IOMMU_NOTIFIER_UNMAP;
1985 }
1986
1987 if (notifier->notifier_flags & request_flags) {
1988 notifier->notify(notifier, entry);
1989 }
1990 }
1991
1992 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1993 int iommu_idx,
1994 IOMMUTLBEntry entry)
1995 {
1996 IOMMUNotifier *iommu_notifier;
1997
1998 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1999
2000 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
2001 if (iommu_notifier->iommu_idx == iommu_idx) {
2002 memory_region_notify_one(iommu_notifier, &entry);
2003 }
2004 }
2005 }
2006
2007 int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
2008 enum IOMMUMemoryRegionAttr attr,
2009 void *data)
2010 {
2011 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2012
2013 if (!imrc->get_attr) {
2014 return -EINVAL;
2015 }
2016
2017 return imrc->get_attr(iommu_mr, attr, data);
2018 }
2019
2020 int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
2021 MemTxAttrs attrs)
2022 {
2023 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2024
2025 if (!imrc->attrs_to_index) {
2026 return 0;
2027 }
2028
2029 return imrc->attrs_to_index(iommu_mr, attrs);
2030 }
2031
2032 int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
2033 {
2034 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2035
2036 if (!imrc->num_indexes) {
2037 return 1;
2038 }
2039
2040 return imrc->num_indexes(iommu_mr);
2041 }
2042
2043 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2044 {
2045 uint8_t mask = 1 << client;
2046 uint8_t old_logging;
2047
2048 assert(client == DIRTY_MEMORY_VGA);
2049 old_logging = mr->vga_logging_count;
2050 mr->vga_logging_count += log ? 1 : -1;
2051 if (!!old_logging == !!mr->vga_logging_count) {
2052 return;
2053 }
2054
2055 memory_region_transaction_begin();
2056 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
2057 memory_region_update_pending |= mr->enabled;
2058 memory_region_transaction_commit();
2059 }
2060
2061 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2062 hwaddr size)
2063 {
2064 assert(mr->ram_block);
2065 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2066 size,
2067 memory_region_get_dirty_log_mask(mr));
2068 }
2069
2070 static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
2071 {
2072 MemoryListener *listener;
2073 AddressSpace *as;
2074 FlatView *view;
2075 FlatRange *fr;
2076
2077 /* If the same address space has multiple log_sync listeners, we
2078 * visit that address space's FlatView multiple times. But because
2079 * log_sync listeners are rare, it's still cheaper than walking each
2080 * address space once.
2081 */
2082 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2083 if (!listener->log_sync) {
2084 continue;
2085 }
2086 as = listener->address_space;
2087 view = address_space_get_flatview(as);
2088 FOR_EACH_FLAT_RANGE(fr, view) {
2089 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
2090 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2091 listener->log_sync(listener, &mrs);
2092 }
2093 }
2094 flatview_unref(view);
2095 }
2096 }
2097
2098 void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start,
2099 hwaddr len)
2100 {
2101 MemoryRegionSection mrs;
2102 MemoryListener *listener;
2103 AddressSpace *as;
2104 FlatView *view;
2105 FlatRange *fr;
2106 hwaddr sec_start, sec_end, sec_size;
2107
2108 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2109 if (!listener->log_clear) {
2110 continue;
2111 }
2112 as = listener->address_space;
2113 view = address_space_get_flatview(as);
2114 FOR_EACH_FLAT_RANGE(fr, view) {
2115 if (!fr->dirty_log_mask || fr->mr != mr) {
2116 /*
2117 * Clear dirty bitmap operation only applies to those
2118 * regions whose dirty logging is at least enabled
2119 */
2120 continue;
2121 }
2122
2123 mrs = section_from_flat_range(fr, view);
2124
2125 sec_start = MAX(mrs.offset_within_region, start);
2126 sec_end = mrs.offset_within_region + int128_get64(mrs.size);
2127 sec_end = MIN(sec_end, start + len);
2128
2129 if (sec_start >= sec_end) {
2130 /*
2131 * If this memory region section has no intersection
2132 * with the requested range, skip.
2133 */
2134 continue;
2135 }
2136
2137 /* Valid case; shrink the section if needed */
2138 mrs.offset_within_address_space +=
2139 sec_start - mrs.offset_within_region;
2140 mrs.offset_within_region = sec_start;
2141 sec_size = sec_end - sec_start;
2142 mrs.size = int128_make64(sec_size);
2143 listener->log_clear(listener, &mrs);
2144 }
2145 flatview_unref(view);
2146 }
2147 }
2148
2149 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2150 hwaddr addr,
2151 hwaddr size,
2152 unsigned client)
2153 {
2154 DirtyBitmapSnapshot *snapshot;
2155 assert(mr->ram_block);
2156 memory_region_sync_dirty_bitmap(mr);
2157 snapshot = cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client);
2158 memory_global_after_dirty_log_sync();
2159 return snapshot;
2160 }
2161
2162 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2163 hwaddr addr, hwaddr size)
2164 {
2165 assert(mr->ram_block);
2166 return cpu_physical_memory_snapshot_get_dirty(snap,
2167 memory_region_get_ram_addr(mr) + addr, size);
2168 }
2169
2170 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2171 {
2172 if (mr->readonly != readonly) {
2173 memory_region_transaction_begin();
2174 mr->readonly = readonly;
2175 memory_region_update_pending |= mr->enabled;
2176 memory_region_transaction_commit();
2177 }
2178 }
2179
2180 void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2181 {
2182 if (mr->nonvolatile != nonvolatile) {
2183 memory_region_transaction_begin();
2184 mr->nonvolatile = nonvolatile;
2185 memory_region_update_pending |= mr->enabled;
2186 memory_region_transaction_commit();
2187 }
2188 }
2189
2190 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2191 {
2192 if (mr->romd_mode != romd_mode) {
2193 memory_region_transaction_begin();
2194 mr->romd_mode = romd_mode;
2195 memory_region_update_pending |= mr->enabled;
2196 memory_region_transaction_commit();
2197 }
2198 }
2199
2200 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2201 hwaddr size, unsigned client)
2202 {
2203 assert(mr->ram_block);
2204 cpu_physical_memory_test_and_clear_dirty(
2205 memory_region_get_ram_addr(mr) + addr, size, client);
2206 }
2207
2208 int memory_region_get_fd(MemoryRegion *mr)
2209 {
2210 int fd;
2211
2212 RCU_READ_LOCK_GUARD();
2213 while (mr->alias) {
2214 mr = mr->alias;
2215 }
2216 fd = mr->ram_block->fd;
2217
2218 return fd;
2219 }
2220
2221 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2222 {
2223 void *ptr;
2224 uint64_t offset = 0;
2225
2226 RCU_READ_LOCK_GUARD();
2227 while (mr->alias) {
2228 offset += mr->alias_offset;
2229 mr = mr->alias;
2230 }
2231 assert(mr->ram_block);
2232 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2233
2234 return ptr;
2235 }
2236
2237 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2238 {
2239 RAMBlock *block;
2240
2241 block = qemu_ram_block_from_host(ptr, false, offset);
2242 if (!block) {
2243 return NULL;
2244 }
2245
2246 return block->mr;
2247 }
2248
2249 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2250 {
2251 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2252 }
2253
2254 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2255 {
2256 assert(mr->ram_block);
2257
2258 qemu_ram_resize(mr->ram_block, newsize, errp);
2259 }
2260
2261 /*
2262 * Call proper memory listeners about the change on the newly
2263 * added/removed CoalescedMemoryRange.
2264 */
2265 static void memory_region_update_coalesced_range(MemoryRegion *mr,
2266 CoalescedMemoryRange *cmr,
2267 bool add)
2268 {
2269 AddressSpace *as;
2270 FlatView *view;
2271 FlatRange *fr;
2272
2273 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2274 view = address_space_get_flatview(as);
2275 FOR_EACH_FLAT_RANGE(fr, view) {
2276 if (fr->mr == mr) {
2277 flat_range_coalesced_io_notify(fr, as, cmr, add);
2278 }
2279 }
2280 flatview_unref(view);
2281 }
2282 }
2283
2284 void memory_region_set_coalescing(MemoryRegion *mr)
2285 {
2286 memory_region_clear_coalescing(mr);
2287 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2288 }
2289
2290 void memory_region_add_coalescing(MemoryRegion *mr,
2291 hwaddr offset,
2292 uint64_t size)
2293 {
2294 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2295
2296 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2297 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2298 memory_region_update_coalesced_range(mr, cmr, true);
2299 memory_region_set_flush_coalesced(mr);
2300 }
2301
2302 void memory_region_clear_coalescing(MemoryRegion *mr)
2303 {
2304 CoalescedMemoryRange *cmr;
2305
2306 if (QTAILQ_EMPTY(&mr->coalesced)) {
2307 return;
2308 }
2309
2310 qemu_flush_coalesced_mmio_buffer();
2311 mr->flush_coalesced_mmio = false;
2312
2313 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2314 cmr = QTAILQ_FIRST(&mr->coalesced);
2315 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2316 memory_region_update_coalesced_range(mr, cmr, false);
2317 g_free(cmr);
2318 }
2319 }
2320
2321 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2322 {
2323 mr->flush_coalesced_mmio = true;
2324 }
2325
2326 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2327 {
2328 qemu_flush_coalesced_mmio_buffer();
2329 if (QTAILQ_EMPTY(&mr->coalesced)) {
2330 mr->flush_coalesced_mmio = false;
2331 }
2332 }
2333
2334 void memory_region_clear_global_locking(MemoryRegion *mr)
2335 {
2336 mr->global_locking = false;
2337 }
2338
2339 static bool userspace_eventfd_warning;
2340
2341 void memory_region_add_eventfd(MemoryRegion *mr,
2342 hwaddr addr,
2343 unsigned size,
2344 bool match_data,
2345 uint64_t data,
2346 EventNotifier *e)
2347 {
2348 MemoryRegionIoeventfd mrfd = {
2349 .addr.start = int128_make64(addr),
2350 .addr.size = int128_make64(size),
2351 .match_data = match_data,
2352 .data = data,
2353 .e = e,
2354 };
2355 unsigned i;
2356
2357 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2358 userspace_eventfd_warning))) {
2359 userspace_eventfd_warning = true;
2360 error_report("Using eventfd without MMIO binding in KVM. "
2361 "Suboptimal performance expected");
2362 }
2363
2364 if (size) {
2365 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
2366 }
2367 memory_region_transaction_begin();
2368 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2369 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
2370 break;
2371 }
2372 }
2373 ++mr->ioeventfd_nb;
2374 mr->ioeventfds = g_realloc(mr->ioeventfds,
2375 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2376 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2377 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2378 mr->ioeventfds[i] = mrfd;
2379 ioeventfd_update_pending |= mr->enabled;
2380 memory_region_transaction_commit();
2381 }
2382
2383 void memory_region_del_eventfd(MemoryRegion *mr,
2384 hwaddr addr,
2385 unsigned size,
2386 bool match_data,
2387 uint64_t data,
2388 EventNotifier *e)
2389 {
2390 MemoryRegionIoeventfd mrfd = {
2391 .addr.start = int128_make64(addr),
2392 .addr.size = int128_make64(size),
2393 .match_data = match_data,
2394 .data = data,
2395 .e = e,
2396 };
2397 unsigned i;
2398
2399 if (size) {
2400 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
2401 }
2402 memory_region_transaction_begin();
2403 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2404 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
2405 break;
2406 }
2407 }
2408 assert(i != mr->ioeventfd_nb);
2409 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2410 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2411 --mr->ioeventfd_nb;
2412 mr->ioeventfds = g_realloc(mr->ioeventfds,
2413 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2414 ioeventfd_update_pending |= mr->enabled;
2415 memory_region_transaction_commit();
2416 }
2417
2418 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2419 {
2420 MemoryRegion *mr = subregion->container;
2421 MemoryRegion *other;
2422
2423 memory_region_transaction_begin();
2424
2425 memory_region_ref(subregion);
2426 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2427 if (subregion->priority >= other->priority) {
2428 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2429 goto done;
2430 }
2431 }
2432 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2433 done:
2434 memory_region_update_pending |= mr->enabled && subregion->enabled;
2435 memory_region_transaction_commit();
2436 }
2437
2438 static void memory_region_add_subregion_common(MemoryRegion *mr,
2439 hwaddr offset,
2440 MemoryRegion *subregion)
2441 {
2442 assert(!subregion->container);
2443 subregion->container = mr;
2444 subregion->addr = offset;
2445 memory_region_update_container_subregions(subregion);
2446 }
2447
2448 void memory_region_add_subregion(MemoryRegion *mr,
2449 hwaddr offset,
2450 MemoryRegion *subregion)
2451 {
2452 subregion->priority = 0;
2453 memory_region_add_subregion_common(mr, offset, subregion);
2454 }
2455
2456 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2457 hwaddr offset,
2458 MemoryRegion *subregion,
2459 int priority)
2460 {
2461 subregion->priority = priority;
2462 memory_region_add_subregion_common(mr, offset, subregion);
2463 }
2464
2465 void memory_region_del_subregion(MemoryRegion *mr,
2466 MemoryRegion *subregion)
2467 {
2468 memory_region_transaction_begin();
2469 assert(subregion->container == mr);
2470 subregion->container = NULL;
2471 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2472 memory_region_unref(subregion);
2473 memory_region_update_pending |= mr->enabled && subregion->enabled;
2474 memory_region_transaction_commit();
2475 }
2476
2477 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2478 {
2479 if (enabled == mr->enabled) {
2480 return;
2481 }
2482 memory_region_transaction_begin();
2483 mr->enabled = enabled;
2484 memory_region_update_pending = true;
2485 memory_region_transaction_commit();
2486 }
2487
2488 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2489 {
2490 Int128 s = int128_make64(size);
2491
2492 if (size == UINT64_MAX) {
2493 s = int128_2_64();
2494 }
2495 if (int128_eq(s, mr->size)) {
2496 return;
2497 }
2498 memory_region_transaction_begin();
2499 mr->size = s;
2500 memory_region_update_pending = true;
2501 memory_region_transaction_commit();
2502 }
2503
2504 static void memory_region_readd_subregion(MemoryRegion *mr)
2505 {
2506 MemoryRegion *container = mr->container;
2507
2508 if (container) {
2509 memory_region_transaction_begin();
2510 memory_region_ref(mr);
2511 memory_region_del_subregion(container, mr);
2512 mr->container = container;
2513 memory_region_update_container_subregions(mr);
2514 memory_region_unref(mr);
2515 memory_region_transaction_commit();
2516 }
2517 }
2518
2519 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2520 {
2521 if (addr != mr->addr) {
2522 mr->addr = addr;
2523 memory_region_readd_subregion(mr);
2524 }
2525 }
2526
2527 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2528 {
2529 assert(mr->alias);
2530
2531 if (offset == mr->alias_offset) {
2532 return;
2533 }
2534
2535 memory_region_transaction_begin();
2536 mr->alias_offset = offset;
2537 memory_region_update_pending |= mr->enabled;
2538 memory_region_transaction_commit();
2539 }
2540
2541 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2542 {
2543 return mr->align;
2544 }
2545
2546 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2547 {
2548 const AddrRange *addr = addr_;
2549 const FlatRange *fr = fr_;
2550
2551 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2552 return -1;
2553 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2554 return 1;
2555 }
2556 return 0;
2557 }
2558
2559 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2560 {
2561 return bsearch(&addr, view->ranges, view->nr,
2562 sizeof(FlatRange), cmp_flatrange_addr);
2563 }
2564
2565 bool memory_region_is_mapped(MemoryRegion *mr)
2566 {
2567 return mr->container ? true : false;
2568 }
2569
2570 /* Same as memory_region_find, but it does not add a reference to the
2571 * returned region. It must be called from an RCU critical section.
2572 */
2573 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2574 hwaddr addr, uint64_t size)
2575 {
2576 MemoryRegionSection ret = { .mr = NULL };
2577 MemoryRegion *root;
2578 AddressSpace *as;
2579 AddrRange range;
2580 FlatView *view;
2581 FlatRange *fr;
2582
2583 addr += mr->addr;
2584 for (root = mr; root->container; ) {
2585 root = root->container;
2586 addr += root->addr;
2587 }
2588
2589 as = memory_region_to_address_space(root);
2590 if (!as) {
2591 return ret;
2592 }
2593 range = addrrange_make(int128_make64(addr), int128_make64(size));
2594
2595 view = address_space_to_flatview(as);
2596 fr = flatview_lookup(view, range);
2597 if (!fr) {
2598 return ret;
2599 }
2600
2601 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2602 --fr;
2603 }
2604
2605 ret.mr = fr->mr;
2606 ret.fv = view;
2607 range = addrrange_intersection(range, fr->addr);
2608 ret.offset_within_region = fr->offset_in_region;
2609 ret.offset_within_region += int128_get64(int128_sub(range.start,
2610 fr->addr.start));
2611 ret.size = range.size;
2612 ret.offset_within_address_space = int128_get64(range.start);
2613 ret.readonly = fr->readonly;
2614 ret.nonvolatile = fr->nonvolatile;
2615 return ret;
2616 }
2617
2618 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2619 hwaddr addr, uint64_t size)
2620 {
2621 MemoryRegionSection ret;
2622 RCU_READ_LOCK_GUARD();
2623 ret = memory_region_find_rcu(mr, addr, size);
2624 if (ret.mr) {
2625 memory_region_ref(ret.mr);
2626 }
2627 return ret;
2628 }
2629
2630 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2631 {
2632 MemoryRegion *mr;
2633
2634 RCU_READ_LOCK_GUARD();
2635 mr = memory_region_find_rcu(container, addr, 1).mr;
2636 return mr && mr != container;
2637 }
2638
2639 void memory_global_dirty_log_sync(void)
2640 {
2641 memory_region_sync_dirty_bitmap(NULL);
2642 }
2643
2644 void memory_global_after_dirty_log_sync(void)
2645 {
2646 MEMORY_LISTENER_CALL_GLOBAL(log_global_after_sync, Forward);
2647 }
2648
2649 static VMChangeStateEntry *vmstate_change;
2650
2651 void memory_global_dirty_log_start(void)
2652 {
2653 if (vmstate_change) {
2654 qemu_del_vm_change_state_handler(vmstate_change);
2655 vmstate_change = NULL;
2656 }
2657
2658 global_dirty_log = true;
2659
2660 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2661
2662 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2663 memory_region_transaction_begin();
2664 memory_region_update_pending = true;
2665 memory_region_transaction_commit();
2666 }
2667
2668 static void memory_global_dirty_log_do_stop(void)
2669 {
2670 global_dirty_log = false;
2671
2672 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2673 memory_region_transaction_begin();
2674 memory_region_update_pending = true;
2675 memory_region_transaction_commit();
2676
2677 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2678 }
2679
2680 static void memory_vm_change_state_handler(void *opaque, int running,
2681 RunState state)
2682 {
2683 if (running) {
2684 memory_global_dirty_log_do_stop();
2685
2686 if (vmstate_change) {
2687 qemu_del_vm_change_state_handler(vmstate_change);
2688 vmstate_change = NULL;
2689 }
2690 }
2691 }
2692
2693 void memory_global_dirty_log_stop(void)
2694 {
2695 if (!runstate_is_running()) {
2696 if (vmstate_change) {
2697 return;
2698 }
2699 vmstate_change = qemu_add_vm_change_state_handler(
2700 memory_vm_change_state_handler, NULL);
2701 return;
2702 }
2703
2704 memory_global_dirty_log_do_stop();
2705 }
2706
2707 static void listener_add_address_space(MemoryListener *listener,
2708 AddressSpace *as)
2709 {
2710 FlatView *view;
2711 FlatRange *fr;
2712
2713 if (listener->begin) {
2714 listener->begin(listener);
2715 }
2716 if (global_dirty_log) {
2717 if (listener->log_global_start) {
2718 listener->log_global_start(listener);
2719 }
2720 }
2721
2722 view = address_space_get_flatview(as);
2723 FOR_EACH_FLAT_RANGE(fr, view) {
2724 MemoryRegionSection section = section_from_flat_range(fr, view);
2725
2726 if (listener->region_add) {
2727 listener->region_add(listener, &section);
2728 }
2729 if (fr->dirty_log_mask && listener->log_start) {
2730 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2731 }
2732 }
2733 if (listener->commit) {
2734 listener->commit(listener);
2735 }
2736 flatview_unref(view);
2737 }
2738
2739 static void listener_del_address_space(MemoryListener *listener,
2740 AddressSpace *as)
2741 {
2742 FlatView *view;
2743 FlatRange *fr;
2744
2745 if (listener->begin) {
2746 listener->begin(listener);
2747 }
2748 view = address_space_get_flatview(as);
2749 FOR_EACH_FLAT_RANGE(fr, view) {
2750 MemoryRegionSection section = section_from_flat_range(fr, view);
2751
2752 if (fr->dirty_log_mask && listener->log_stop) {
2753 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2754 }
2755 if (listener->region_del) {
2756 listener->region_del(listener, &section);
2757 }
2758 }
2759 if (listener->commit) {
2760 listener->commit(listener);
2761 }
2762 flatview_unref(view);
2763 }
2764
2765 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2766 {
2767 MemoryListener *other = NULL;
2768
2769 listener->address_space = as;
2770 if (QTAILQ_EMPTY(&memory_listeners)
2771 || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) {
2772 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2773 } else {
2774 QTAILQ_FOREACH(other, &memory_listeners, link) {
2775 if (listener->priority < other->priority) {
2776 break;
2777 }
2778 }
2779 QTAILQ_INSERT_BEFORE(other, listener, link);
2780 }
2781
2782 if (QTAILQ_EMPTY(&as->listeners)
2783 || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) {
2784 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2785 } else {
2786 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2787 if (listener->priority < other->priority) {
2788 break;
2789 }
2790 }
2791 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2792 }
2793
2794 listener_add_address_space(listener, as);
2795 }
2796
2797 void memory_listener_unregister(MemoryListener *listener)
2798 {
2799 if (!listener->address_space) {
2800 return;
2801 }
2802
2803 listener_del_address_space(listener, listener->address_space);
2804 QTAILQ_REMOVE(&memory_listeners, listener, link);
2805 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2806 listener->address_space = NULL;
2807 }
2808
2809 void address_space_remove_listeners(AddressSpace *as)
2810 {
2811 while (!QTAILQ_EMPTY(&as->listeners)) {
2812 memory_listener_unregister(QTAILQ_FIRST(&as->listeners));
2813 }
2814 }
2815
2816 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2817 {
2818 memory_region_ref(root);
2819 as->root = root;
2820 as->current_map = NULL;
2821 as->ioeventfd_nb = 0;
2822 as->ioeventfds = NULL;
2823 QTAILQ_INIT(&as->listeners);
2824 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2825 as->name = g_strdup(name ? name : "anonymous");
2826 address_space_update_topology(as);
2827 address_space_update_ioeventfds(as);
2828 }
2829
2830 static void do_address_space_destroy(AddressSpace *as)
2831 {
2832 assert(QTAILQ_EMPTY(&as->listeners));
2833
2834 flatview_unref(as->current_map);
2835 g_free(as->name);
2836 g_free(as->ioeventfds);
2837 memory_region_unref(as->root);
2838 }
2839
2840 void address_space_destroy(AddressSpace *as)
2841 {
2842 MemoryRegion *root = as->root;
2843
2844 /* Flush out anything from MemoryListeners listening in on this */
2845 memory_region_transaction_begin();
2846 as->root = NULL;
2847 memory_region_transaction_commit();
2848 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2849
2850 /* At this point, as->dispatch and as->current_map are dummy
2851 * entries that the guest should never use. Wait for the old
2852 * values to expire before freeing the data.
2853 */
2854 as->root = root;
2855 call_rcu(as, do_address_space_destroy, rcu);
2856 }
2857
2858 static const char *memory_region_type(MemoryRegion *mr)
2859 {
2860 if (memory_region_is_ram_device(mr)) {
2861 return "ramd";
2862 } else if (memory_region_is_romd(mr)) {
2863 return "romd";
2864 } else if (memory_region_is_rom(mr)) {
2865 return "rom";
2866 } else if (memory_region_is_ram(mr)) {
2867 return "ram";
2868 } else {
2869 return "i/o";
2870 }
2871 }
2872
2873 typedef struct MemoryRegionList MemoryRegionList;
2874
2875 struct MemoryRegionList {
2876 const MemoryRegion *mr;
2877 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2878 };
2879
2880 typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead;
2881
2882 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2883 int128_sub((size), int128_one())) : 0)
2884 #define MTREE_INDENT " "
2885
2886 static void mtree_expand_owner(const char *label, Object *obj)
2887 {
2888 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2889
2890 qemu_printf(" %s:{%s", label, dev ? "dev" : "obj");
2891 if (dev && dev->id) {
2892 qemu_printf(" id=%s", dev->id);
2893 } else {
2894 gchar *canonical_path = object_get_canonical_path(obj);
2895 if (canonical_path) {
2896 qemu_printf(" path=%s", canonical_path);
2897 g_free(canonical_path);
2898 } else {
2899 qemu_printf(" type=%s", object_get_typename(obj));
2900 }
2901 }
2902 qemu_printf("}");
2903 }
2904
2905 static void mtree_print_mr_owner(const MemoryRegion *mr)
2906 {
2907 Object *owner = mr->owner;
2908 Object *parent = memory_region_owner((MemoryRegion *)mr);
2909
2910 if (!owner && !parent) {
2911 qemu_printf(" orphan");
2912 return;
2913 }
2914 if (owner) {
2915 mtree_expand_owner("owner", owner);
2916 }
2917 if (parent && parent != owner) {
2918 mtree_expand_owner("parent", parent);
2919 }
2920 }
2921
2922 static void mtree_print_mr(const MemoryRegion *mr, unsigned int level,
2923 hwaddr base,
2924 MemoryRegionListHead *alias_print_queue,
2925 bool owner)
2926 {
2927 MemoryRegionList *new_ml, *ml, *next_ml;
2928 MemoryRegionListHead submr_print_queue;
2929 const MemoryRegion *submr;
2930 unsigned int i;
2931 hwaddr cur_start, cur_end;
2932
2933 if (!mr) {
2934 return;
2935 }
2936
2937 for (i = 0; i < level; i++) {
2938 qemu_printf(MTREE_INDENT);
2939 }
2940
2941 cur_start = base + mr->addr;
2942 cur_end = cur_start + MR_SIZE(mr->size);
2943
2944 /*
2945 * Try to detect overflow of memory region. This should never
2946 * happen normally. When it happens, we dump something to warn the
2947 * user who is observing this.
2948 */
2949 if (cur_start < base || cur_end < cur_start) {
2950 qemu_printf("[DETECTED OVERFLOW!] ");
2951 }
2952
2953 if (mr->alias) {
2954 MemoryRegionList *ml;
2955 bool found = false;
2956
2957 /* check if the alias is already in the queue */
2958 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2959 if (ml->mr == mr->alias) {
2960 found = true;
2961 }
2962 }
2963
2964 if (!found) {
2965 ml = g_new(MemoryRegionList, 1);
2966 ml->mr = mr->alias;
2967 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2968 }
2969 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2970 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
2971 "-" TARGET_FMT_plx "%s",
2972 cur_start, cur_end,
2973 mr->priority,
2974 mr->nonvolatile ? "nv-" : "",
2975 memory_region_type((MemoryRegion *)mr),
2976 memory_region_name(mr),
2977 memory_region_name(mr->alias),
2978 mr->alias_offset,
2979 mr->alias_offset + MR_SIZE(mr->size),
2980 mr->enabled ? "" : " [disabled]");
2981 if (owner) {
2982 mtree_print_mr_owner(mr);
2983 }
2984 } else {
2985 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2986 " (prio %d, %s%s): %s%s",
2987 cur_start, cur_end,
2988 mr->priority,
2989 mr->nonvolatile ? "nv-" : "",
2990 memory_region_type((MemoryRegion *)mr),
2991 memory_region_name(mr),
2992 mr->enabled ? "" : " [disabled]");
2993 if (owner) {
2994 mtree_print_mr_owner(mr);
2995 }
2996 }
2997 qemu_printf("\n");
2998
2999 QTAILQ_INIT(&submr_print_queue);
3000
3001 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
3002 new_ml = g_new(MemoryRegionList, 1);
3003 new_ml->mr = submr;
3004 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
3005 if (new_ml->mr->addr < ml->mr->addr ||
3006 (new_ml->mr->addr == ml->mr->addr &&
3007 new_ml->mr->priority > ml->mr->priority)) {
3008 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
3009 new_ml = NULL;
3010 break;
3011 }
3012 }
3013 if (new_ml) {
3014 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
3015 }
3016 }
3017
3018 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
3019 mtree_print_mr(ml->mr, level + 1, cur_start,
3020 alias_print_queue, owner);
3021 }
3022
3023 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
3024 g_free(ml);
3025 }
3026 }
3027
3028 struct FlatViewInfo {
3029 int counter;
3030 bool dispatch_tree;
3031 bool owner;
3032 AccelClass *ac;
3033 const char *ac_name;
3034 };
3035
3036 static void mtree_print_flatview(gpointer key, gpointer value,
3037 gpointer user_data)
3038 {
3039 FlatView *view = key;
3040 GArray *fv_address_spaces = value;
3041 struct FlatViewInfo *fvi = user_data;
3042 FlatRange *range = &view->ranges[0];
3043 MemoryRegion *mr;
3044 int n = view->nr;
3045 int i;
3046 AddressSpace *as;
3047
3048 qemu_printf("FlatView #%d\n", fvi->counter);
3049 ++fvi->counter;
3050
3051 for (i = 0; i < fv_address_spaces->len; ++i) {
3052 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3053 qemu_printf(" AS \"%s\", root: %s",
3054 as->name, memory_region_name(as->root));
3055 if (as->root->alias) {
3056 qemu_printf(", alias %s", memory_region_name(as->root->alias));
3057 }
3058 qemu_printf("\n");
3059 }
3060
3061 qemu_printf(" Root memory region: %s\n",
3062 view->root ? memory_region_name(view->root) : "(none)");
3063
3064 if (n <= 0) {
3065 qemu_printf(MTREE_INDENT "No rendered FlatView\n\n");
3066 return;
3067 }
3068
3069 while (n--) {
3070 mr = range->mr;
3071 if (range->offset_in_region) {
3072 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3073 " (prio %d, %s%s): %s @" TARGET_FMT_plx,
3074 int128_get64(range->addr.start),
3075 int128_get64(range->addr.start)
3076 + MR_SIZE(range->addr.size),
3077 mr->priority,
3078 range->nonvolatile ? "nv-" : "",
3079 range->readonly ? "rom" : memory_region_type(mr),
3080 memory_region_name(mr),
3081 range->offset_in_region);
3082 } else {
3083 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3084 " (prio %d, %s%s): %s",
3085 int128_get64(range->addr.start),
3086 int128_get64(range->addr.start)
3087 + MR_SIZE(range->addr.size),
3088 mr->priority,
3089 range->nonvolatile ? "nv-" : "",
3090 range->readonly ? "rom" : memory_region_type(mr),
3091 memory_region_name(mr));
3092 }
3093 if (fvi->owner) {
3094 mtree_print_mr_owner(mr);
3095 }
3096
3097 if (fvi->ac) {
3098 for (i = 0; i < fv_address_spaces->len; ++i) {
3099 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3100 if (fvi->ac->has_memory(current_machine, as,
3101 int128_get64(range->addr.start),
3102 MR_SIZE(range->addr.size) + 1)) {
3103 qemu_printf(" %s", fvi->ac_name);
3104 }
3105 }
3106 }
3107 qemu_printf("\n");
3108 range++;
3109 }
3110
3111 #if !defined(CONFIG_USER_ONLY)
3112 if (fvi->dispatch_tree && view->root) {
3113 mtree_print_dispatch(view->dispatch, view->root);
3114 }
3115 #endif
3116
3117 qemu_printf("\n");
3118 }
3119
3120 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3121 gpointer user_data)
3122 {
3123 FlatView *view = key;
3124 GArray *fv_address_spaces = value;
3125
3126 g_array_unref(fv_address_spaces);
3127 flatview_unref(view);
3128
3129 return true;
3130 }
3131
3132 void mtree_info(bool flatview, bool dispatch_tree, bool owner)
3133 {
3134 MemoryRegionListHead ml_head;
3135 MemoryRegionList *ml, *ml2;
3136 AddressSpace *as;
3137
3138 if (flatview) {
3139 FlatView *view;
3140 struct FlatViewInfo fvi = {
3141 .counter = 0,
3142 .dispatch_tree = dispatch_tree,
3143 .owner = owner,
3144 };
3145 GArray *fv_address_spaces;
3146 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3147 AccelClass *ac = ACCEL_GET_CLASS(current_machine->accelerator);
3148
3149 if (ac->has_memory) {
3150 fvi.ac = ac;
3151 fvi.ac_name = current_machine->accel ? current_machine->accel :
3152 object_class_get_name(OBJECT_CLASS(ac));
3153 }
3154
3155 /* Gather all FVs in one table */
3156 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3157 view = address_space_get_flatview(as);
3158
3159 fv_address_spaces = g_hash_table_lookup(views, view);
3160 if (!fv_address_spaces) {
3161 fv_address_spaces = g_array_new(false, false, sizeof(as));
3162 g_hash_table_insert(views, view, fv_address_spaces);
3163 }
3164
3165 g_array_append_val(fv_address_spaces, as);
3166 }
3167
3168 /* Print */
3169 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3170
3171 /* Free */
3172 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3173 g_hash_table_unref(views);
3174
3175 return;
3176 }
3177
3178 QTAILQ_INIT(&ml_head);
3179
3180 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3181 qemu_printf("address-space: %s\n", as->name);
3182 mtree_print_mr(as->root, 1, 0, &ml_head, owner);
3183 qemu_printf("\n");
3184 }
3185
3186 /* print aliased regions */
3187 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3188 qemu_printf("memory-region: %s\n", memory_region_name(ml->mr));
3189 mtree_print_mr(ml->mr, 1, 0, &ml_head, owner);
3190 qemu_printf("\n");
3191 }
3192
3193 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3194 g_free(ml);
3195 }
3196 }
3197
3198 void memory_region_init_ram(MemoryRegion *mr,
3199 struct Object *owner,
3200 const char *name,
3201 uint64_t size,
3202 Error **errp)
3203 {
3204 DeviceState *owner_dev;
3205 Error *err = NULL;
3206
3207 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3208 if (err) {
3209 error_propagate(errp, err);
3210 return;
3211 }
3212 /* This will assert if owner is neither NULL nor a DeviceState.
3213 * We only want the owner here for the purposes of defining a
3214 * unique name for migration. TODO: Ideally we should implement
3215 * a naming scheme for Objects which are not DeviceStates, in
3216 * which case we can relax this restriction.
3217 */
3218 owner_dev = DEVICE(owner);
3219 vmstate_register_ram(mr, owner_dev);
3220 }
3221
3222 void memory_region_init_rom(MemoryRegion *mr,
3223 struct Object *owner,
3224 const char *name,
3225 uint64_t size,
3226 Error **errp)
3227 {
3228 DeviceState *owner_dev;
3229 Error *err = NULL;
3230
3231 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3232 if (err) {
3233 error_propagate(errp, err);
3234 return;
3235 }
3236 /* This will assert if owner is neither NULL nor a DeviceState.
3237 * We only want the owner here for the purposes of defining a
3238 * unique name for migration. TODO: Ideally we should implement
3239 * a naming scheme for Objects which are not DeviceStates, in
3240 * which case we can relax this restriction.
3241 */
3242 owner_dev = DEVICE(owner);
3243 vmstate_register_ram(mr, owner_dev);
3244 }
3245
3246 void memory_region_init_rom_device(MemoryRegion *mr,
3247 struct Object *owner,
3248 const MemoryRegionOps *ops,
3249 void *opaque,
3250 const char *name,
3251 uint64_t size,
3252 Error **errp)
3253 {
3254 DeviceState *owner_dev;
3255 Error *err = NULL;
3256
3257 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3258 name, size, &err);
3259 if (err) {
3260 error_propagate(errp, err);
3261 return;
3262 }
3263 /* This will assert if owner is neither NULL nor a DeviceState.
3264 * We only want the owner here for the purposes of defining a
3265 * unique name for migration. TODO: Ideally we should implement
3266 * a naming scheme for Objects which are not DeviceStates, in
3267 * which case we can relax this restriction.
3268 */
3269 owner_dev = DEVICE(owner);
3270 vmstate_register_ram(mr, owner_dev);
3271 }
3272
3273 static const TypeInfo memory_region_info = {
3274 .parent = TYPE_OBJECT,
3275 .name = TYPE_MEMORY_REGION,
3276 .class_size = sizeof(MemoryRegionClass),
3277 .instance_size = sizeof(MemoryRegion),
3278 .instance_init = memory_region_initfn,
3279 .instance_finalize = memory_region_finalize,
3280 };
3281
3282 static const TypeInfo iommu_memory_region_info = {
3283 .parent = TYPE_MEMORY_REGION,
3284 .name = TYPE_IOMMU_MEMORY_REGION,
3285 .class_size = sizeof(IOMMUMemoryRegionClass),
3286 .instance_size = sizeof(IOMMUMemoryRegion),
3287 .instance_init = iommu_memory_region_initfn,
3288 .abstract = true,
3289 };
3290
3291 static void memory_register_types(void)
3292 {
3293 type_register_static(&memory_region_info);
3294 type_register_static(&iommu_memory_region_info);
3295 }
3296
3297 type_init(memory_register_types)
AR7 emulation for QEMU