hw/sparc64/niagara.c

   1 /*
   2  * QEMU Sun4v/Niagara System Emulator
   3  *
   4  * Copyright (c) 2016 Artyom Tarasenko
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "qemu-common.h"
  28 #include "cpu.h"
  29 #include "hw/hw.h"
  30 #include "hw/boards.h"
  31 #include "hw/char/serial.h"
  32 #include "hw/empty_slot.h"
  33 #include "hw/loader.h"
  34 #include "hw/sparc/sparc64.h"
  35 #include "hw/timer/sun4v-rtc.h"
  36 #include "exec/address-spaces.h"
  37 #include "sysemu/block-backend.h"
  38
  39
  40 typedef struct NiagaraBoardState {
  41     MemoryRegion hv_ram;
  42     MemoryRegion partition_ram;
  43     MemoryRegion nvram;
  44     MemoryRegion md_rom;
  45     MemoryRegion hv_rom;
  46     MemoryRegion vdisk_ram;
  47     MemoryRegion prom;
  48 } NiagaraBoardState;
  49
  50 #define NIAGARA_HV_RAM_BASE 0x100000ULL
  51 #define NIAGARA_HV_RAM_SIZE 0x3f00000ULL /* 63 MiB */
  52
  53 #define NIAGARA_PARTITION_RAM_BASE 0x80000000ULL
  54
  55 #define NIAGARA_UART_BASE   0x1f10000000ULL
  56
  57 #define NIAGARA_NVRAM_BASE  0x1f11000000ULL
  58 #define NIAGARA_NVRAM_SIZE  0x2000
  59
  60 #define NIAGARA_MD_ROM_BASE 0x1f12000000ULL
  61 #define NIAGARA_MD_ROM_SIZE 0x2000
  62
  63 #define NIAGARA_HV_ROM_BASE 0x1f12080000ULL
  64 #define NIAGARA_HV_ROM_SIZE 0x2000
  65
  66 #define NIAGARA_IOBBASE     0x9800000000ULL
  67 #define NIAGARA_IOBSIZE     0x0100000000ULL
  68
  69 #define NIAGARA_VDISK_BASE  0x1f40000000ULL
  70 #define NIAGARA_RTC_BASE    0xfff0c1fff8ULL
  71 #define NIAGARA_UART_BASE   0x1f10000000ULL
  72
  73 /* Firmware layout
  74  *
  75  * |------------------|
  76  * |   openboot.bin   |
  77  * |------------------| PROM_ADDR + OBP_OFFSET
  78  * |      q.bin       |
  79  * |------------------| PROM_ADDR + Q_OFFSET
  80  * |     reset.bin    |
  81  * |------------------| PROM_ADDR
  82  */
  83 #define NIAGARA_PROM_BASE   0xfff0000000ULL
  84 #define NIAGARA_Q_OFFSET    0x10000ULL
  85 #define NIAGARA_OBP_OFFSET  0x80000ULL
  86 #define PROM_SIZE_MAX       (4 * 1024 * 1024)
  87
  88 /* Niagara hardware initialisation */
  89 static void niagara_init(MachineState *machine)
  90 {
  91     NiagaraBoardState *s = g_new(NiagaraBoardState, 1);
  92     DriveInfo *dinfo = drive_get_next(IF_PFLASH);
  93     MemoryRegion *sysmem = get_system_memory();
  94
  95     /* init CPUs */
  96     sparc64_cpu_devinit(machine->cpu_model, "Sun UltraSparc T1",
  97                         NIAGARA_PROM_BASE);
  98     /* set up devices */
  99     memory_region_allocate_system_memory(&s->hv_ram, NULL, "sun4v-hv.ram",
 100                                          NIAGARA_HV_RAM_SIZE);
 101     memory_region_add_subregion(sysmem, NIAGARA_HV_RAM_BASE, &s->hv_ram);
 102
 103     memory_region_allocate_system_memory(&s->partition_ram, NULL,
 104                                          "sun4v-partition.ram",
 105                                          machine->ram_size);
 106     memory_region_add_subregion(sysmem, NIAGARA_PARTITION_RAM_BASE,
 107                                 &s->partition_ram);
 108
 109     memory_region_allocate_system_memory(&s->nvram, NULL,
 110                                          "sun4v.nvram", NIAGARA_NVRAM_SIZE);
 111     memory_region_add_subregion(sysmem, NIAGARA_NVRAM_BASE, &s->nvram);
 112     memory_region_allocate_system_memory(&s->md_rom, NULL,
 113                                          "sun4v-md.rom", NIAGARA_MD_ROM_SIZE);
 114     memory_region_add_subregion(sysmem, NIAGARA_MD_ROM_BASE, &s->md_rom);
 115     memory_region_allocate_system_memory(&s->hv_rom, NULL,
 116                                          "sun4v-hv.rom", NIAGARA_HV_ROM_SIZE);
 117     memory_region_add_subregion(sysmem, NIAGARA_HV_ROM_BASE, &s->hv_rom);
 118     memory_region_allocate_system_memory(&s->prom, NULL,
 119                                          "sun4v.prom", PROM_SIZE_MAX);
 120     memory_region_add_subregion(sysmem, NIAGARA_PROM_BASE, &s->prom);
 121
 122     rom_add_file_fixed("nvram1", NIAGARA_NVRAM_BASE, -1);
 123     rom_add_file_fixed("1up-md.bin", NIAGARA_MD_ROM_BASE, -1);
 124     rom_add_file_fixed("1up-hv.bin", NIAGARA_HV_ROM_BASE, -1);
 125
 126     rom_add_file_fixed("reset.bin", NIAGARA_PROM_BASE, -1);
 127     rom_add_file_fixed("q.bin", NIAGARA_PROM_BASE + NIAGARA_Q_OFFSET, -1);
 128     rom_add_file_fixed("openboot.bin", NIAGARA_PROM_BASE + NIAGARA_OBP_OFFSET,
 129                        -1);
 130
 131     /* the virtual ramdisk is kind of initrd, but it resides
 132        outside of the partition RAM */
 133     if (dinfo) {
 134         BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 135         int size = blk_getlength(blk);
 136         if (size > 0) {
 137             memory_region_allocate_system_memory(&s->vdisk_ram, NULL,
 138                                                  "sun4v_vdisk.ram", size);
 139             memory_region_add_subregion(get_system_memory(),
 140                                         NIAGARA_VDISK_BASE, &s->vdisk_ram);
 141             dinfo->is_default = 1;
 142             rom_add_file_fixed(blk_bs(blk)->filename, NIAGARA_VDISK_BASE, -1);
 143         } else {
 144             fprintf(stderr, "qemu: could not load ram disk '%s'\n",
 145                     blk_bs(blk)->filename);
 146             exit(1);
 147         }
 148     }
 149     serial_mm_init(sysmem, NIAGARA_UART_BASE, 0, NULL, 115200,
 150                    serial_hds[0], DEVICE_BIG_ENDIAN);
 151
 152     empty_slot_init(NIAGARA_IOBBASE, NIAGARA_IOBSIZE);
 153     sun4v_rtc_init(NIAGARA_RTC_BASE);
 154 }
 155
 156 static void niagara_class_init(ObjectClass *oc, void *data)
 157 {
 158     MachineClass *mc = MACHINE_CLASS(oc);
 159
 160     mc->desc = "Sun4v platform, Niagara";
 161     mc->init = niagara_init;
 162     mc->max_cpus = 1; /* XXX for now */
 163     mc->default_boot_order = "c";
 164 }
 165
 166 static const TypeInfo niagara_type = {
 167     .name = MACHINE_TYPE_NAME("niagara"),
 168     .parent = TYPE_MACHINE,
 169     .class_init = niagara_class_init,
 170 };
 171
 172 static void niagara_register_types(void)
 173 {
 174     type_register_static(&niagara_type);
 175 }
 176
 177 type_init(niagara_register_types)