2 * ARM Generic Interrupt Controller v3
4 * Copyright (c) 2016 Linaro Limited
5 * Written by Peter Maydell
7 * This code is licensed under the GPL, version 2 or (at your option)
11 /* This file contains the code for the system register interface
12 * portions of the GICv3.
15 #include "qemu/osdep.h"
16 #include "qemu/bitops.h"
18 #include "gicv3_internal.h"
21 static GICv3CPUState
*icc_cs_from_env(CPUARMState
*env
)
23 /* Given the CPU, find the right GICv3CPUState struct.
24 * Since we registered the CPU interface with the EL change hook as
25 * the opaque pointer, we can just directly get from the CPU to it.
27 return arm_get_el_change_hook_opaque(arm_env_get_cpu(env
));
30 static bool gicv3_use_ns_bank(CPUARMState
*env
)
32 /* Return true if we should use the NonSecure bank for a banked GIC
33 * CPU interface register. Note that this differs from the
34 * access_secure_reg() function because GICv3 banked registers are
35 * banked even for AArch64, unlike the other CPU system registers.
37 return !arm_is_secure_below_el3(env
);
40 /* The minimum BPR for the virtual interface is a configurable property */
41 static inline int icv_min_vbpr(GICv3CPUState
*cs
)
43 return 7 - cs
->vprebits
;
46 /* Simple accessor functions for LR fields */
47 static uint32_t ich_lr_vintid(uint64_t lr
)
49 return extract64(lr
, ICH_LR_EL2_VINTID_SHIFT
, ICH_LR_EL2_VINTID_LENGTH
);
52 static uint32_t ich_lr_pintid(uint64_t lr
)
54 return extract64(lr
, ICH_LR_EL2_PINTID_SHIFT
, ICH_LR_EL2_PINTID_LENGTH
);
57 static uint32_t ich_lr_prio(uint64_t lr
)
59 return extract64(lr
, ICH_LR_EL2_PRIORITY_SHIFT
, ICH_LR_EL2_PRIORITY_LENGTH
);
62 static int ich_lr_state(uint64_t lr
)
64 return extract64(lr
, ICH_LR_EL2_STATE_SHIFT
, ICH_LR_EL2_STATE_LENGTH
);
67 static bool icv_access(CPUARMState
*env
, int hcr_flags
)
69 /* Return true if this ICC_ register access should really be
70 * directed to an ICV_ access. hcr_flags is a mask of
71 * HCR_EL2 bits to check: we treat this as an ICV_ access
72 * if we are in NS EL1 and at least one of the specified
73 * HCR_EL2 bits is set.
75 * ICV registers fall into four categories:
76 * * access if NS EL1 and HCR_EL2.FMO == 1:
77 * all ICV regs with '0' in their name
78 * * access if NS EL1 and HCR_EL2.IMO == 1:
79 * all ICV regs with '1' in their name
80 * * access if NS EL1 and either IMO or FMO == 1:
83 return (env
->cp15
.hcr_el2
& hcr_flags
) && arm_current_el(env
) == 1
84 && !arm_is_secure_below_el3(env
);
87 static int read_vbpr(GICv3CPUState
*cs
, int grp
)
89 /* Read VBPR value out of the VMCR field (caller must handle
90 * VCBPR effects if required)
92 if (grp
== GICV3_G0
) {
93 return extract64(cs
->ich_vmcr_el2
, ICH_VMCR_EL2_VBPR0_SHIFT
,
94 ICH_VMCR_EL2_VBPR0_LENGTH
);
96 return extract64(cs
->ich_vmcr_el2
, ICH_VMCR_EL2_VBPR1_SHIFT
,
97 ICH_VMCR_EL2_VBPR1_LENGTH
);
101 static void write_vbpr(GICv3CPUState
*cs
, int grp
, int value
)
103 /* Write new VBPR1 value, handling the "writing a value less than
104 * the minimum sets it to the minimum" semantics.
106 int min
= icv_min_vbpr(cs
);
108 if (grp
!= GICV3_G0
) {
112 value
= MAX(value
, min
);
114 if (grp
== GICV3_G0
) {
115 cs
->ich_vmcr_el2
= deposit64(cs
->ich_vmcr_el2
, ICH_VMCR_EL2_VBPR0_SHIFT
,
116 ICH_VMCR_EL2_VBPR0_LENGTH
, value
);
118 cs
->ich_vmcr_el2
= deposit64(cs
->ich_vmcr_el2
, ICH_VMCR_EL2_VBPR1_SHIFT
,
119 ICH_VMCR_EL2_VBPR1_LENGTH
, value
);
123 static uint32_t icv_fullprio_mask(GICv3CPUState
*cs
)
125 /* Return a mask word which clears the unimplemented priority bits
126 * from a priority value for a virtual interrupt. (Not to be confused
127 * with the group priority, whose mask depends on the value of VBPR
128 * for the interrupt group.)
130 return ~0U << (8 - cs
->vpribits
);
133 static int ich_highest_active_virt_prio(GICv3CPUState
*cs
)
135 /* Calculate the current running priority based on the set bits
136 * in the ICH Active Priority Registers.
139 int aprmax
= 1 << (cs
->vprebits
- 5);
141 assert(aprmax
<= ARRAY_SIZE(cs
->ich_apr
[0]));
143 for (i
= 0; i
< aprmax
; i
++) {
144 uint32_t apr
= cs
->ich_apr
[GICV3_G0
][i
] |
145 cs
->ich_apr
[GICV3_G1NS
][i
];
150 return (i
* 32 + ctz32(apr
)) << (icv_min_vbpr(cs
) + 1);
152 /* No current active interrupts: return idle priority */
156 static int hppvi_index(GICv3CPUState
*cs
)
158 /* Return the list register index of the highest priority pending
159 * virtual interrupt, as per the HighestPriorityVirtualInterrupt
160 * pseudocode. If no pending virtual interrupts, return -1.
164 /* Note that a list register entry with a priority of 0xff will
165 * never be reported by this function; this is the architecturally
170 if (!(cs
->ich_vmcr_el2
& (ICH_VMCR_EL2_VENG0
| ICH_VMCR_EL2_VENG1
))) {
171 /* Both groups disabled, definitely nothing to do */
175 for (i
= 0; i
< cs
->num_list_regs
; i
++) {
176 uint64_t lr
= cs
->ich_lr_el2
[i
];
179 if (ich_lr_state(lr
) != ICH_LR_EL2_STATE_PENDING
) {
184 /* Ignore interrupts if relevant group enable not set */
185 if (lr
& ICH_LR_EL2_GROUP
) {
186 if (!(cs
->ich_vmcr_el2
& ICH_VMCR_EL2_VENG1
)) {
190 if (!(cs
->ich_vmcr_el2
& ICH_VMCR_EL2_VENG0
)) {
195 thisprio
= ich_lr_prio(lr
);
197 if (thisprio
< prio
) {
206 static uint32_t icv_gprio_mask(GICv3CPUState
*cs
, int group
)
208 /* Return a mask word which clears the subpriority bits from
209 * a priority value for a virtual interrupt in the specified group.
210 * This depends on the VBPR value:
211 * a BPR of 0 means the group priority bits are [7:1];
212 * a BPR of 1 means they are [7:2], and so on down to
213 * a BPR of 7 meaning no group priority bits at all.
214 * Which BPR to use depends on the group of the interrupt and
215 * the current ICH_VMCR_EL2.VCBPR settings.
217 if (group
== GICV3_G1NS
&& cs
->ich_vmcr_el2
& ICH_VMCR_EL2_VCBPR
) {
221 return ~0U << (read_vbpr(cs
, group
) + 1);
224 static bool icv_hppi_can_preempt(GICv3CPUState
*cs
, uint64_t lr
)
226 /* Return true if we can signal this virtual interrupt defined by
227 * the given list register value; see the pseudocode functions
228 * CanSignalVirtualInterrupt and CanSignalVirtualInt.
229 * Compare also icc_hppi_can_preempt() which is the non-virtual
230 * equivalent of these checks.
233 uint32_t mask
, prio
, rprio
, vpmr
;
235 if (!(cs
->ich_hcr_el2
& ICH_HCR_EL2_EN
)) {
236 /* Virtual interface disabled */
240 /* We don't need to check that this LR is in Pending state because
241 * that has already been done in hppvi_index().
244 prio
= ich_lr_prio(lr
);
245 vpmr
= extract64(cs
->ich_vmcr_el2
, ICH_VMCR_EL2_VPMR_SHIFT
,
246 ICH_VMCR_EL2_VPMR_LENGTH
);
249 /* Priority mask masks this interrupt */
253 rprio
= ich_highest_active_virt_prio(cs
);
255 /* No running interrupt so we can preempt */
259 grp
= (lr
& ICH_LR_EL2_GROUP
) ? GICV3_G1NS
: GICV3_G0
;
261 mask
= icv_gprio_mask(cs
, grp
);
263 /* We only preempt a running interrupt if the pending interrupt's
264 * group priority is sufficient (the subpriorities are not considered).
266 if ((prio
& mask
) < (rprio
& mask
)) {
273 static uint32_t eoi_maintenance_interrupt_state(GICv3CPUState
*cs
,
276 /* Return a set of bits indicating the EOI maintenance interrupt status
277 * for each list register. The EOI maintenance interrupt status is
278 * 1 if LR.State == 0 && LR.HW == 0 && LR.EOI == 1
279 * (see the GICv3 spec for the ICH_EISR_EL2 register).
280 * If misr is not NULL then we should also collect the information
281 * about the MISR.EOI, MISR.NP and MISR.U bits.
285 bool seenpending
= false;
288 for (i
= 0; i
< cs
->num_list_regs
; i
++) {
289 uint64_t lr
= cs
->ich_lr_el2
[i
];
291 if ((lr
& (ICH_LR_EL2_STATE_MASK
| ICH_LR_EL2_HW
| ICH_LR_EL2_EOI
))
295 if ((lr
& ICH_LR_EL2_STATE_MASK
)) {
298 if (ich_lr_state(lr
) == ICH_LR_EL2_STATE_PENDING
) {
304 if (validcount
< 2 && (cs
->ich_hcr_el2
& ICH_HCR_EL2_UIE
)) {
305 *misr
|= ICH_MISR_EL2_U
;
307 if (!seenpending
&& (cs
->ich_hcr_el2
& ICH_HCR_EL2_NPIE
)) {
308 *misr
|= ICH_MISR_EL2_NP
;
311 *misr
|= ICH_MISR_EL2_EOI
;
317 static uint32_t maintenance_interrupt_state(GICv3CPUState
*cs
)
319 /* Return a set of bits indicating the maintenance interrupt status
320 * (as seen in the ICH_MISR_EL2 register).
324 /* Scan list registers and fill in the U, NP and EOI bits */
325 eoi_maintenance_interrupt_state(cs
, &value
);
327 if (cs
->ich_hcr_el2
& (ICH_HCR_EL2_LRENPIE
| ICH_HCR_EL2_EOICOUNT_MASK
)) {
328 value
|= ICH_MISR_EL2_LRENP
;
331 if ((cs
->ich_hcr_el2
& ICH_HCR_EL2_VGRP0EIE
) &&
332 (cs
->ich_vmcr_el2
& ICH_VMCR_EL2_VENG0
)) {
333 value
|= ICH_MISR_EL2_VGRP0E
;
336 if ((cs
->ich_hcr_el2
& ICH_HCR_EL2_VGRP0DIE
) &&
337 !(cs
->ich_vmcr_el2
& ICH_VMCR_EL2_VENG1
)) {
338 value
|= ICH_MISR_EL2_VGRP0D
;
340 if ((cs
->ich_hcr_el2
& ICH_HCR_EL2_VGRP1EIE
) &&
341 (cs
->ich_vmcr_el2
& ICH_VMCR_EL2_VENG1
)) {
342 value
|= ICH_MISR_EL2_VGRP1E
;
345 if ((cs
->ich_hcr_el2
& ICH_HCR_EL2_VGRP1DIE
) &&
346 !(cs
->ich_vmcr_el2
& ICH_VMCR_EL2_VENG1
)) {
347 value
|= ICH_MISR_EL2_VGRP1D
;
353 static void gicv3_cpuif_virt_update(GICv3CPUState
*cs
)
355 /* Tell the CPU about any pending virtual interrupts or
356 * maintenance interrupts, following a change to the state
357 * of the CPU interface relevant to virtual interrupts.
359 * CAUTION: this function will call qemu_set_irq() on the
360 * CPU maintenance IRQ line, which is typically wired up
361 * to the GIC as a per-CPU interrupt. This means that it
362 * will recursively call back into the GIC code via
363 * gicv3_redist_set_irq() and thus into the CPU interface code's
364 * gicv3_cpuif_update(). It is therefore important that this
365 * function is only called as the final action of a CPU interface
366 * register write implementation, after all the GIC state
367 * fields have been updated. gicv3_cpuif_update() also must
368 * not cause this function to be called, but that happens
369 * naturally as a result of there being no architectural
370 * linkage between the physical and virtual GIC logic.
377 idx
= hppvi_index(cs
);
378 trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs
), idx
);
380 uint64_t lr
= cs
->ich_lr_el2
[idx
];
382 if (icv_hppi_can_preempt(cs
, lr
)) {
383 /* Virtual interrupts are simple: G0 are always FIQ, and G1 IRQ */
384 if (lr
& ICH_LR_EL2_GROUP
) {
392 if (cs
->ich_hcr_el2
& ICH_HCR_EL2_EN
) {
393 maintlevel
= maintenance_interrupt_state(cs
);
396 trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs
), fiqlevel
,
397 irqlevel
, maintlevel
);
399 qemu_set_irq(cs
->parent_vfiq
, fiqlevel
);
400 qemu_set_irq(cs
->parent_virq
, irqlevel
);
401 qemu_set_irq(cs
->maintenance_irq
, maintlevel
);
404 static uint64_t icv_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
406 GICv3CPUState
*cs
= icc_cs_from_env(env
);
407 int regno
= ri
->opc2
& 3;
408 int grp
= ri
->crm
& 1 ? GICV3_G0
: GICV3_G1NS
;
409 uint64_t value
= cs
->ich_apr
[grp
][regno
];
411 trace_gicv3_icv_ap_read(ri
->crm
& 1, regno
, gicv3_redist_affid(cs
), value
);
415 static void icv_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
418 GICv3CPUState
*cs
= icc_cs_from_env(env
);
419 int regno
= ri
->opc2
& 3;
420 int grp
= ri
->crm
& 1 ? GICV3_G0
: GICV3_G1NS
;
422 trace_gicv3_icv_ap_write(ri
->crm
& 1, regno
, gicv3_redist_affid(cs
), value
);
424 cs
->ich_apr
[grp
][regno
] = value
& 0xFFFFFFFFU
;
426 gicv3_cpuif_virt_update(cs
);
430 static uint64_t icv_bpr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
432 GICv3CPUState
*cs
= icc_cs_from_env(env
);
433 int grp
= (ri
->crm
== 8) ? GICV3_G0
: GICV3_G1NS
;
437 if (grp
== GICV3_G1NS
&& (cs
->ich_vmcr_el2
& ICH_VMCR_EL2_VCBPR
)) {
438 /* reads return bpr0 + 1 saturated to 7, writes ignored */
443 bpr
= read_vbpr(cs
, grp
);
450 trace_gicv3_icv_bpr_read(ri
->crm
== 8 ? 0 : 1, gicv3_redist_affid(cs
), bpr
);
455 static void icv_bpr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
458 GICv3CPUState
*cs
= icc_cs_from_env(env
);
459 int grp
= (ri
->crm
== 8) ? GICV3_G0
: GICV3_G1NS
;
461 trace_gicv3_icv_bpr_write(ri
->crm
== 8 ? 0 : 1,
462 gicv3_redist_affid(cs
), value
);
464 if (grp
== GICV3_G1NS
&& (cs
->ich_vmcr_el2
& ICH_VMCR_EL2_VCBPR
)) {
465 /* reads return bpr0 + 1 saturated to 7, writes ignored */
469 write_vbpr(cs
, grp
, value
);
471 gicv3_cpuif_virt_update(cs
);
474 static uint64_t icv_pmr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
476 GICv3CPUState
*cs
= icc_cs_from_env(env
);
479 value
= extract64(cs
->ich_vmcr_el2
, ICH_VMCR_EL2_VPMR_SHIFT
,
480 ICH_VMCR_EL2_VPMR_LENGTH
);
482 trace_gicv3_icv_pmr_read(gicv3_redist_affid(cs
), value
);
486 static void icv_pmr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
489 GICv3CPUState
*cs
= icc_cs_from_env(env
);
491 trace_gicv3_icv_pmr_write(gicv3_redist_affid(cs
), value
);
493 value
&= icv_fullprio_mask(cs
);
495 cs
->ich_vmcr_el2
= deposit64(cs
->ich_vmcr_el2
, ICH_VMCR_EL2_VPMR_SHIFT
,
496 ICH_VMCR_EL2_VPMR_LENGTH
, value
);
498 gicv3_cpuif_virt_update(cs
);
501 static uint64_t icv_igrpen_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
503 GICv3CPUState
*cs
= icc_cs_from_env(env
);
507 enbit
= ri
->opc2
& 1 ? ICH_VMCR_EL2_VENG1_SHIFT
: ICH_VMCR_EL2_VENG0_SHIFT
;
508 value
= extract64(cs
->ich_vmcr_el2
, enbit
, 1);
510 trace_gicv3_icv_igrpen_read(ri
->opc2
& 1 ? 1 : 0,
511 gicv3_redist_affid(cs
), value
);
515 static void icv_igrpen_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
518 GICv3CPUState
*cs
= icc_cs_from_env(env
);
521 trace_gicv3_icv_igrpen_write(ri
->opc2
& 1 ? 1 : 0,
522 gicv3_redist_affid(cs
), value
);
524 enbit
= ri
->opc2
& 1 ? ICH_VMCR_EL2_VENG1_SHIFT
: ICH_VMCR_EL2_VENG0_SHIFT
;
526 cs
->ich_vmcr_el2
= deposit64(cs
->ich_vmcr_el2
, enbit
, 1, value
);
527 gicv3_cpuif_virt_update(cs
);
530 static uint64_t icv_ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
532 GICv3CPUState
*cs
= icc_cs_from_env(env
);
535 /* Note that the fixed fields here (A3V, SEIS, IDbits, PRIbits)
536 * should match the ones reported in ich_vtr_read().
538 value
= ICC_CTLR_EL1_A3V
| (1 << ICC_CTLR_EL1_IDBITS_SHIFT
) |
539 (7 << ICC_CTLR_EL1_PRIBITS_SHIFT
);
541 if (cs
->ich_vmcr_el2
& ICH_VMCR_EL2_VEOIM
) {
542 value
|= ICC_CTLR_EL1_EOIMODE
;
545 if (cs
->ich_vmcr_el2
& ICH_VMCR_EL2_VCBPR
) {
546 value
|= ICC_CTLR_EL1_CBPR
;
549 trace_gicv3_icv_ctlr_read(gicv3_redist_affid(cs
), value
);
553 static void icv_ctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
556 GICv3CPUState
*cs
= icc_cs_from_env(env
);
558 trace_gicv3_icv_ctlr_write(gicv3_redist_affid(cs
), value
);
560 cs
->ich_vmcr_el2
= deposit64(cs
->ich_vmcr_el2
, ICH_VMCR_EL2_VCBPR_SHIFT
,
561 1, value
& ICC_CTLR_EL1_CBPR
? 1 : 0);
562 cs
->ich_vmcr_el2
= deposit64(cs
->ich_vmcr_el2
, ICH_VMCR_EL2_VEOIM_SHIFT
,
563 1, value
& ICC_CTLR_EL1_EOIMODE
? 1 : 0);
565 gicv3_cpuif_virt_update(cs
);
568 static uint64_t icv_rpr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
570 GICv3CPUState
*cs
= icc_cs_from_env(env
);
571 int prio
= ich_highest_active_virt_prio(cs
);
573 trace_gicv3_icv_rpr_read(gicv3_redist_affid(cs
), prio
);
577 static uint64_t icv_hppir_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
579 GICv3CPUState
*cs
= icc_cs_from_env(env
);
580 int grp
= ri
->crm
== 8 ? GICV3_G0
: GICV3_G1NS
;
581 int idx
= hppvi_index(cs
);
582 uint64_t value
= INTID_SPURIOUS
;
585 uint64_t lr
= cs
->ich_lr_el2
[idx
];
586 int thisgrp
= (lr
& ICH_LR_EL2_GROUP
) ? GICV3_G1NS
: GICV3_G0
;
588 if (grp
== thisgrp
) {
589 value
= ich_lr_vintid(lr
);
593 trace_gicv3_icv_hppir_read(grp
, gicv3_redist_affid(cs
), value
);
597 static void icv_activate_irq(GICv3CPUState
*cs
, int idx
, int grp
)
599 /* Activate the interrupt in the specified list register
600 * by moving it from Pending to Active state, and update the
601 * Active Priority Registers.
603 uint32_t mask
= icv_gprio_mask(cs
, grp
);
604 int prio
= ich_lr_prio(cs
->ich_lr_el2
[idx
]) & mask
;
605 int aprbit
= prio
>> (8 - cs
->vprebits
);
606 int regno
= aprbit
/ 32;
607 int regbit
= aprbit
% 32;
609 cs
->ich_lr_el2
[idx
] &= ~ICH_LR_EL2_STATE_PENDING_BIT
;
610 cs
->ich_lr_el2
[idx
] |= ICH_LR_EL2_STATE_ACTIVE_BIT
;
611 cs
->ich_apr
[grp
][regno
] |= (1 << regbit
);
614 static uint64_t icv_iar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
616 GICv3CPUState
*cs
= icc_cs_from_env(env
);
617 int grp
= ri
->crm
== 8 ? GICV3_G0
: GICV3_G1NS
;
618 int idx
= hppvi_index(cs
);
619 uint64_t intid
= INTID_SPURIOUS
;
622 uint64_t lr
= cs
->ich_lr_el2
[idx
];
623 int thisgrp
= (lr
& ICH_LR_EL2_GROUP
) ? GICV3_G1NS
: GICV3_G0
;
625 if (thisgrp
== grp
&& icv_hppi_can_preempt(cs
, lr
)) {
626 intid
= ich_lr_vintid(lr
);
627 if (intid
< INTID_SECURE
) {
628 icv_activate_irq(cs
, idx
, grp
);
630 /* Interrupt goes from Pending to Invalid */
631 cs
->ich_lr_el2
[idx
] &= ~ICH_LR_EL2_STATE_PENDING_BIT
;
632 /* We will now return the (bogus) ID from the list register,
633 * as per the pseudocode.
639 trace_gicv3_icv_iar_read(ri
->crm
== 8 ? 0 : 1,
640 gicv3_redist_affid(cs
), intid
);
644 static int icc_highest_active_prio(GICv3CPUState
*cs
)
646 /* Calculate the current running priority based on the set bits
647 * in the Active Priority Registers.
651 for (i
= 0; i
< ARRAY_SIZE(cs
->icc_apr
[0]); i
++) {
652 uint32_t apr
= cs
->icc_apr
[GICV3_G0
][i
] |
653 cs
->icc_apr
[GICV3_G1
][i
] | cs
->icc_apr
[GICV3_G1NS
][i
];
658 return (i
* 32 + ctz32(apr
)) << (GIC_MIN_BPR
+ 1);
660 /* No current active interrupts: return idle priority */
664 static uint32_t icc_gprio_mask(GICv3CPUState
*cs
, int group
)
666 /* Return a mask word which clears the subpriority bits from
667 * a priority value for an interrupt in the specified group.
668 * This depends on the BPR value:
669 * a BPR of 0 means the group priority bits are [7:1];
670 * a BPR of 1 means they are [7:2], and so on down to
671 * a BPR of 7 meaning no group priority bits at all.
672 * Which BPR to use depends on the group of the interrupt and
673 * the current ICC_CTLR.CBPR settings.
675 if ((group
== GICV3_G1
&& cs
->icc_ctlr_el1
[GICV3_S
] & ICC_CTLR_EL1_CBPR
) ||
676 (group
== GICV3_G1NS
&&
677 cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_CBPR
)) {
681 return ~0U << ((cs
->icc_bpr
[group
] & 7) + 1);
684 static bool icc_no_enabled_hppi(GICv3CPUState
*cs
)
686 /* Return true if there is no pending interrupt, or the
687 * highest priority pending interrupt is in a group which has been
688 * disabled at the CPU interface by the ICC_IGRPEN* register enable bits.
690 return cs
->hppi
.prio
== 0xff || (cs
->icc_igrpen
[cs
->hppi
.grp
] == 0);
693 static bool icc_hppi_can_preempt(GICv3CPUState
*cs
)
695 /* Return true if we have a pending interrupt of sufficient
696 * priority to preempt.
701 if (icc_no_enabled_hppi(cs
)) {
705 if (cs
->hppi
.prio
>= cs
->icc_pmr_el1
) {
706 /* Priority mask masks this interrupt */
710 rprio
= icc_highest_active_prio(cs
);
712 /* No currently running interrupt so we can preempt */
716 mask
= icc_gprio_mask(cs
, cs
->hppi
.grp
);
718 /* We only preempt a running interrupt if the pending interrupt's
719 * group priority is sufficient (the subpriorities are not considered).
721 if ((cs
->hppi
.prio
& mask
) < (rprio
& mask
)) {
728 void gicv3_cpuif_update(GICv3CPUState
*cs
)
730 /* Tell the CPU about its highest priority pending interrupt */
733 ARMCPU
*cpu
= ARM_CPU(cs
->cpu
);
734 CPUARMState
*env
= &cpu
->env
;
736 trace_gicv3_cpuif_update(gicv3_redist_affid(cs
), cs
->hppi
.irq
,
737 cs
->hppi
.grp
, cs
->hppi
.prio
);
739 if (cs
->hppi
.grp
== GICV3_G1
&& !arm_feature(env
, ARM_FEATURE_EL3
)) {
740 /* If a Security-enabled GIC sends a G1S interrupt to a
741 * Security-disabled CPU, we must treat it as if it were G0.
743 cs
->hppi
.grp
= GICV3_G0
;
746 if (icc_hppi_can_preempt(cs
)) {
747 /* We have an interrupt: should we signal it as IRQ or FIQ?
748 * This is described in the GICv3 spec section 4.6.2.
752 switch (cs
->hppi
.grp
) {
757 isfiq
= (!arm_is_secure(env
) ||
758 (arm_current_el(env
) == 3 && arm_el_is_aa64(env
, 3)));
761 isfiq
= arm_is_secure(env
);
764 g_assert_not_reached();
774 trace_gicv3_cpuif_set_irqs(gicv3_redist_affid(cs
), fiqlevel
, irqlevel
);
776 qemu_set_irq(cs
->parent_fiq
, fiqlevel
);
777 qemu_set_irq(cs
->parent_irq
, irqlevel
);
780 static uint64_t icc_pmr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
782 GICv3CPUState
*cs
= icc_cs_from_env(env
);
783 uint32_t value
= cs
->icc_pmr_el1
;
785 if (icv_access(env
, HCR_FMO
| HCR_IMO
)) {
786 return icv_pmr_read(env
, ri
);
789 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_is_secure(env
) &&
790 (env
->cp15
.scr_el3
& SCR_FIQ
)) {
791 /* NS access and Group 0 is inaccessible to NS: return the
792 * NS view of the current priority
795 /* Secure priorities not visible to NS */
797 } else if (value
!= 0xff) {
798 value
= (value
<< 1) & 0xff;
802 trace_gicv3_icc_pmr_read(gicv3_redist_affid(cs
), value
);
807 static void icc_pmr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
810 GICv3CPUState
*cs
= icc_cs_from_env(env
);
812 if (icv_access(env
, HCR_FMO
| HCR_IMO
)) {
813 return icv_pmr_write(env
, ri
, value
);
816 trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs
), value
);
820 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_is_secure(env
) &&
821 (env
->cp15
.scr_el3
& SCR_FIQ
)) {
822 /* NS access and Group 0 is inaccessible to NS: return the
823 * NS view of the current priority
825 if (!(cs
->icc_pmr_el1
& 0x80)) {
826 /* Current PMR in the secure range, don't allow NS to change it */
829 value
= (value
>> 1) & 0x80;
831 cs
->icc_pmr_el1
= value
;
832 gicv3_cpuif_update(cs
);
835 static void icc_activate_irq(GICv3CPUState
*cs
, int irq
)
837 /* Move the interrupt from the Pending state to Active, and update
838 * the Active Priority Registers
840 uint32_t mask
= icc_gprio_mask(cs
, cs
->hppi
.grp
);
841 int prio
= cs
->hppi
.prio
& mask
;
842 int aprbit
= prio
>> 1;
843 int regno
= aprbit
/ 32;
844 int regbit
= aprbit
% 32;
846 cs
->icc_apr
[cs
->hppi
.grp
][regno
] |= (1 << regbit
);
848 if (irq
< GIC_INTERNAL
) {
849 cs
->gicr_iactiver0
= deposit32(cs
->gicr_iactiver0
, irq
, 1, 1);
850 cs
->gicr_ipendr0
= deposit32(cs
->gicr_ipendr0
, irq
, 1, 0);
851 gicv3_redist_update(cs
);
853 gicv3_gicd_active_set(cs
->gic
, irq
);
854 gicv3_gicd_pending_clear(cs
->gic
, irq
);
855 gicv3_update(cs
->gic
, irq
, 1);
859 static uint64_t icc_hppir0_value(GICv3CPUState
*cs
, CPUARMState
*env
)
861 /* Return the highest priority pending interrupt register value
866 if (cs
->hppi
.prio
== 0xff) {
867 return INTID_SPURIOUS
;
870 /* Check whether we can return the interrupt or if we should return
871 * a special identifier, as per the CheckGroup0ForSpecialIdentifiers
872 * pseudocode. (We can simplify a little because for us ICC_SRE_EL1.RM
875 irq_is_secure
= (!(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
) &&
876 (cs
->hppi
.grp
!= GICV3_G1NS
));
878 if (cs
->hppi
.grp
!= GICV3_G0
&& !arm_is_el3_or_mon(env
)) {
879 return INTID_SPURIOUS
;
881 if (irq_is_secure
&& !arm_is_secure(env
)) {
882 /* Secure interrupts not visible to Nonsecure */
883 return INTID_SPURIOUS
;
886 if (cs
->hppi
.grp
!= GICV3_G0
) {
887 /* Indicate to EL3 that there's a Group 1 interrupt for the other
890 return irq_is_secure
? INTID_SECURE
: INTID_NONSECURE
;
896 static uint64_t icc_hppir1_value(GICv3CPUState
*cs
, CPUARMState
*env
)
898 /* Return the highest priority pending interrupt register value
903 if (cs
->hppi
.prio
== 0xff) {
904 return INTID_SPURIOUS
;
907 /* Check whether we can return the interrupt or if we should return
908 * a special identifier, as per the CheckGroup1ForSpecialIdentifiers
909 * pseudocode. (We can simplify a little because for us ICC_SRE_EL1.RM
912 irq_is_secure
= (!(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
) &&
913 (cs
->hppi
.grp
!= GICV3_G1NS
));
915 if (cs
->hppi
.grp
== GICV3_G0
) {
916 /* Group 0 interrupts not visible via HPPIR1 */
917 return INTID_SPURIOUS
;
920 if (!arm_is_secure(env
)) {
921 /* Secure interrupts not visible in Non-secure */
922 return INTID_SPURIOUS
;
924 } else if (!arm_is_el3_or_mon(env
) && arm_is_secure(env
)) {
925 /* Group 1 non-secure interrupts not visible in Secure EL1 */
926 return INTID_SPURIOUS
;
932 static uint64_t icc_iar0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
934 GICv3CPUState
*cs
= icc_cs_from_env(env
);
937 if (icv_access(env
, HCR_FMO
)) {
938 return icv_iar_read(env
, ri
);
941 if (!icc_hppi_can_preempt(cs
)) {
942 intid
= INTID_SPURIOUS
;
944 intid
= icc_hppir0_value(cs
, env
);
947 if (!(intid
>= INTID_SECURE
&& intid
<= INTID_SPURIOUS
)) {
948 icc_activate_irq(cs
, intid
);
951 trace_gicv3_icc_iar0_read(gicv3_redist_affid(cs
), intid
);
955 static uint64_t icc_iar1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
957 GICv3CPUState
*cs
= icc_cs_from_env(env
);
960 if (icv_access(env
, HCR_IMO
)) {
961 return icv_iar_read(env
, ri
);
964 if (!icc_hppi_can_preempt(cs
)) {
965 intid
= INTID_SPURIOUS
;
967 intid
= icc_hppir1_value(cs
, env
);
970 if (!(intid
>= INTID_SECURE
&& intid
<= INTID_SPURIOUS
)) {
971 icc_activate_irq(cs
, intid
);
974 trace_gicv3_icc_iar1_read(gicv3_redist_affid(cs
), intid
);
978 static void icc_drop_prio(GICv3CPUState
*cs
, int grp
)
980 /* Drop the priority of the currently active interrupt in
981 * the specified group.
983 * Note that we can guarantee (because of the requirement to nest
984 * ICC_IAR reads [which activate an interrupt and raise priority]
985 * with ICC_EOIR writes [which drop the priority for the interrupt])
986 * that the interrupt we're being called for is the highest priority
987 * active interrupt, meaning that it has the lowest set bit in the
990 * If the guest does not honour the ordering constraints then the
991 * behaviour of the GIC is UNPREDICTABLE, which for us means that
992 * the values of the APR registers might become incorrect and the
993 * running priority will be wrong, so interrupts that should preempt
994 * might not do so, and interrupts that should not preempt might do so.
998 for (i
= 0; i
< ARRAY_SIZE(cs
->icc_apr
[grp
]); i
++) {
999 uint64_t *papr
= &cs
->icc_apr
[grp
][i
];
1004 /* Clear the lowest set bit */
1009 /* running priority change means we need an update for this cpu i/f */
1010 gicv3_cpuif_update(cs
);
1013 static bool icc_eoi_split(CPUARMState
*env
, GICv3CPUState
*cs
)
1015 /* Return true if we should split priority drop and interrupt
1016 * deactivation, ie whether the relevant EOIMode bit is set.
1018 if (arm_is_el3_or_mon(env
)) {
1019 return cs
->icc_ctlr_el3
& ICC_CTLR_EL3_EOIMODE_EL3
;
1021 if (arm_is_secure_below_el3(env
)) {
1022 return cs
->icc_ctlr_el1
[GICV3_S
] & ICC_CTLR_EL1_EOIMODE
;
1024 return cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_EOIMODE
;
1028 static int icc_highest_active_group(GICv3CPUState
*cs
)
1030 /* Return the group with the highest priority active interrupt.
1031 * We can do this by just comparing the APRs to see which one
1032 * has the lowest set bit.
1033 * (If more than one group is active at the same priority then
1034 * we're in UNPREDICTABLE territory.)
1038 for (i
= 0; i
< ARRAY_SIZE(cs
->icc_apr
[0]); i
++) {
1039 int g0ctz
= ctz32(cs
->icc_apr
[GICV3_G0
][i
]);
1040 int g1ctz
= ctz32(cs
->icc_apr
[GICV3_G1
][i
]);
1041 int g1nsctz
= ctz32(cs
->icc_apr
[GICV3_G1NS
][i
]);
1043 if (g1nsctz
< g0ctz
&& g1nsctz
< g1ctz
) {
1046 if (g1ctz
< g0ctz
) {
1053 /* No set active bits? UNPREDICTABLE; return -1 so the caller
1054 * ignores the spurious EOI attempt.
1059 static void icc_deactivate_irq(GICv3CPUState
*cs
, int irq
)
1061 if (irq
< GIC_INTERNAL
) {
1062 cs
->gicr_iactiver0
= deposit32(cs
->gicr_iactiver0
, irq
, 1, 0);
1063 gicv3_redist_update(cs
);
1065 gicv3_gicd_active_clear(cs
->gic
, irq
);
1066 gicv3_update(cs
->gic
, irq
, 1);
1070 static bool icv_eoi_split(CPUARMState
*env
, GICv3CPUState
*cs
)
1072 /* Return true if we should split priority drop and interrupt
1073 * deactivation, ie whether the virtual EOIMode bit is set.
1075 return cs
->ich_vmcr_el2
& ICH_VMCR_EL2_VEOIM
;
1078 static int icv_find_active(GICv3CPUState
*cs
, int irq
)
1080 /* Given an interrupt number for an active interrupt, return the index
1081 * of the corresponding list register, or -1 if there is no match.
1082 * Corresponds to FindActiveVirtualInterrupt pseudocode.
1086 for (i
= 0; i
< cs
->num_list_regs
; i
++) {
1087 uint64_t lr
= cs
->ich_lr_el2
[i
];
1089 if ((lr
& ICH_LR_EL2_STATE_ACTIVE_BIT
) && ich_lr_vintid(lr
) == irq
) {
1097 static void icv_deactivate_irq(GICv3CPUState
*cs
, int idx
)
1099 /* Deactivate the interrupt in the specified list register index */
1100 uint64_t lr
= cs
->ich_lr_el2
[idx
];
1102 if (lr
& ICH_LR_EL2_HW
) {
1103 /* Deactivate the associated physical interrupt */
1104 int pirq
= ich_lr_pintid(lr
);
1106 if (pirq
< INTID_SECURE
) {
1107 icc_deactivate_irq(cs
, pirq
);
1111 /* Clear the 'active' part of the state, so ActivePending->Pending
1112 * and Active->Invalid.
1114 lr
&= ~ICH_LR_EL2_STATE_ACTIVE_BIT
;
1115 cs
->ich_lr_el2
[idx
] = lr
;
1118 static void icv_increment_eoicount(GICv3CPUState
*cs
)
1120 /* Increment the EOICOUNT field in ICH_HCR_EL2 */
1121 int eoicount
= extract64(cs
->ich_hcr_el2
, ICH_HCR_EL2_EOICOUNT_SHIFT
,
1122 ICH_HCR_EL2_EOICOUNT_LENGTH
);
1124 cs
->ich_hcr_el2
= deposit64(cs
->ich_hcr_el2
, ICH_HCR_EL2_EOICOUNT_SHIFT
,
1125 ICH_HCR_EL2_EOICOUNT_LENGTH
, eoicount
+ 1);
1128 static int icv_drop_prio(GICv3CPUState
*cs
)
1130 /* Drop the priority of the currently active virtual interrupt
1131 * (favouring group 0 if there is a set active bit at
1132 * the same priority for both group 0 and group 1).
1133 * Return the priority value for the bit we just cleared,
1134 * or 0xff if no bits were set in the AP registers at all.
1135 * Note that though the ich_apr[] are uint64_t only the low
1136 * 32 bits are actually relevant.
1139 int aprmax
= 1 << (cs
->vprebits
- 5);
1141 assert(aprmax
<= ARRAY_SIZE(cs
->ich_apr
[0]));
1143 for (i
= 0; i
< aprmax
; i
++) {
1144 uint64_t *papr0
= &cs
->ich_apr
[GICV3_G0
][i
];
1145 uint64_t *papr1
= &cs
->ich_apr
[GICV3_G1NS
][i
];
1146 int apr0count
, apr1count
;
1148 if (!*papr0
&& !*papr1
) {
1152 /* We can't just use the bit-twiddling hack icc_drop_prio() does
1153 * because we need to return the bit number we cleared so
1154 * it can be compared against the list register's priority field.
1156 apr0count
= ctz32(*papr0
);
1157 apr1count
= ctz32(*papr1
);
1159 if (apr0count
<= apr1count
) {
1160 *papr0
&= *papr0
- 1;
1161 return (apr0count
+ i
* 32) << (icv_min_vbpr(cs
) + 1);
1163 *papr1
&= *papr1
- 1;
1164 return (apr1count
+ i
* 32) << (icv_min_vbpr(cs
) + 1);
1170 static void icv_dir_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1173 /* Deactivate interrupt */
1174 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1176 int irq
= value
& 0xffffff;
1178 trace_gicv3_icv_dir_write(gicv3_redist_affid(cs
), value
);
1180 if (irq
>= cs
->gic
->num_irq
) {
1181 /* Also catches special interrupt numbers and LPIs */
1185 if (!icv_eoi_split(env
, cs
)) {
1189 idx
= icv_find_active(cs
, irq
);
1192 /* No list register matching this, so increment the EOI count
1193 * (might trigger a maintenance interrupt)
1195 icv_increment_eoicount(cs
);
1197 icv_deactivate_irq(cs
, idx
);
1200 gicv3_cpuif_virt_update(cs
);
1203 static void icv_eoir_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1206 /* End of Interrupt */
1207 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1208 int irq
= value
& 0xffffff;
1209 int grp
= ri
->crm
== 8 ? GICV3_G0
: GICV3_G1NS
;
1212 trace_gicv3_icv_eoir_write(ri
->crm
== 8 ? 0 : 1,
1213 gicv3_redist_affid(cs
), value
);
1215 if (irq
>= cs
->gic
->num_irq
) {
1216 /* Also catches special interrupt numbers and LPIs */
1220 /* We implement the IMPDEF choice of "drop priority before doing
1221 * error checks" (because that lets us avoid scanning the AP
1224 dropprio
= icv_drop_prio(cs
);
1225 if (dropprio
== 0xff) {
1226 /* No active interrupt. It is CONSTRAINED UNPREDICTABLE
1227 * whether the list registers are checked in this
1228 * situation; we choose not to.
1233 idx
= icv_find_active(cs
, irq
);
1236 /* No valid list register corresponding to EOI ID */
1237 icv_increment_eoicount(cs
);
1239 uint64_t lr
= cs
->ich_lr_el2
[idx
];
1240 int thisgrp
= (lr
& ICH_LR_EL2_GROUP
) ? GICV3_G1NS
: GICV3_G0
;
1241 int lr_gprio
= ich_lr_prio(lr
) & icv_gprio_mask(cs
, grp
);
1243 if (thisgrp
== grp
&& lr_gprio
== dropprio
) {
1244 if (!icv_eoi_split(env
, cs
)) {
1245 /* Priority drop and deactivate not split: deactivate irq now */
1246 icv_deactivate_irq(cs
, idx
);
1251 gicv3_cpuif_virt_update(cs
);
1254 static void icc_eoir_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1257 /* End of Interrupt */
1258 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1259 int irq
= value
& 0xffffff;
1262 if (icv_access(env
, ri
->crm
== 8 ? HCR_FMO
: HCR_IMO
)) {
1263 icv_eoir_write(env
, ri
, value
);
1267 trace_gicv3_icc_eoir_write(ri
->crm
== 8 ? 0 : 1,
1268 gicv3_redist_affid(cs
), value
);
1275 if (arm_is_secure(env
)) {
1282 if (irq
>= cs
->gic
->num_irq
) {
1283 /* This handles two cases:
1284 * 1. If software writes the ID of a spurious interrupt [ie 1020-1023]
1285 * to the GICC_EOIR, the GIC ignores that write.
1286 * 2. If software writes the number of a non-existent interrupt
1287 * this must be a subcase of "value written does not match the last
1288 * valid interrupt value read from the Interrupt Acknowledge
1289 * register" and so this is UNPREDICTABLE. We choose to ignore it.
1294 if (icc_highest_active_group(cs
) != grp
) {
1298 icc_drop_prio(cs
, grp
);
1300 if (!icc_eoi_split(env
, cs
)) {
1301 /* Priority drop and deactivate not split: deactivate irq now */
1302 icc_deactivate_irq(cs
, irq
);
1306 static uint64_t icc_hppir0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1308 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1311 if (icv_access(env
, HCR_FMO
)) {
1312 return icv_hppir_read(env
, ri
);
1315 value
= icc_hppir0_value(cs
, env
);
1316 trace_gicv3_icc_hppir0_read(gicv3_redist_affid(cs
), value
);
1320 static uint64_t icc_hppir1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1322 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1325 if (icv_access(env
, HCR_IMO
)) {
1326 return icv_hppir_read(env
, ri
);
1329 value
= icc_hppir1_value(cs
, env
);
1330 trace_gicv3_icc_hppir1_read(gicv3_redist_affid(cs
), value
);
1334 static uint64_t icc_bpr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1336 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1337 int grp
= (ri
->crm
== 8) ? GICV3_G0
: GICV3_G1
;
1338 bool satinc
= false;
1341 if (icv_access(env
, grp
== GICV3_G0
? HCR_FMO
: HCR_IMO
)) {
1342 return icv_bpr_read(env
, ri
);
1345 if (grp
== GICV3_G1
&& gicv3_use_ns_bank(env
)) {
1349 if (grp
== GICV3_G1
&& !arm_is_el3_or_mon(env
) &&
1350 (cs
->icc_ctlr_el1
[GICV3_S
] & ICC_CTLR_EL1_CBPR
)) {
1351 /* CBPR_EL1S means secure EL1 or AArch32 EL3 !Mon BPR1 accesses
1357 if (grp
== GICV3_G1NS
&& arm_current_el(env
) < 3 &&
1358 (cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_CBPR
)) {
1359 /* reads return bpr0 + 1 sat to 7, writes ignored */
1364 bpr
= cs
->icc_bpr
[grp
];
1370 trace_gicv3_icc_bpr_read(ri
->crm
== 8 ? 0 : 1, gicv3_redist_affid(cs
), bpr
);
1375 static void icc_bpr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1378 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1379 int grp
= (ri
->crm
== 8) ? GICV3_G0
: GICV3_G1
;
1381 if (icv_access(env
, grp
== GICV3_G0
? HCR_FMO
: HCR_IMO
)) {
1382 icv_bpr_write(env
, ri
, value
);
1386 trace_gicv3_icc_bpr_write(ri
->crm
== 8 ? 0 : 1,
1387 gicv3_redist_affid(cs
), value
);
1389 if (grp
== GICV3_G1
&& gicv3_use_ns_bank(env
)) {
1393 if (grp
== GICV3_G1
&& !arm_is_el3_or_mon(env
) &&
1394 (cs
->icc_ctlr_el1
[GICV3_S
] & ICC_CTLR_EL1_CBPR
)) {
1395 /* CBPR_EL1S means secure EL1 or AArch32 EL3 !Mon BPR1 accesses
1401 if (grp
== GICV3_G1NS
&& arm_current_el(env
) < 3 &&
1402 (cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_CBPR
)) {
1403 /* reads return bpr0 + 1 sat to 7, writes ignored */
1407 cs
->icc_bpr
[grp
] = value
& 7;
1408 gicv3_cpuif_update(cs
);
1411 static uint64_t icc_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1413 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1416 int regno
= ri
->opc2
& 3;
1417 int grp
= ri
->crm
& 1 ? GICV3_G0
: GICV3_G1
;
1419 if (icv_access(env
, grp
== GICV3_G0
? HCR_FMO
: HCR_IMO
)) {
1420 return icv_ap_read(env
, ri
);
1423 if (grp
== GICV3_G1
&& gicv3_use_ns_bank(env
)) {
1427 value
= cs
->icc_apr
[grp
][regno
];
1429 trace_gicv3_icc_ap_read(ri
->crm
& 1, regno
, gicv3_redist_affid(cs
), value
);
1433 static void icc_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1436 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1438 int regno
= ri
->opc2
& 3;
1439 int grp
= ri
->crm
& 1 ? GICV3_G0
: GICV3_G1
;
1441 if (icv_access(env
, grp
== GICV3_G0
? HCR_FMO
: HCR_IMO
)) {
1442 icv_ap_write(env
, ri
, value
);
1446 trace_gicv3_icc_ap_write(ri
->crm
& 1, regno
, gicv3_redist_affid(cs
), value
);
1448 if (grp
== GICV3_G1
&& gicv3_use_ns_bank(env
)) {
1452 /* It's not possible to claim that a Non-secure interrupt is active
1453 * at a priority outside the Non-secure range (128..255), since this
1454 * would otherwise allow malicious NS code to block delivery of S interrupts
1455 * by writing a bad value to these registers.
1457 if (grp
== GICV3_G1NS
&& regno
< 2 && arm_feature(env
, ARM_FEATURE_EL3
)) {
1461 cs
->icc_apr
[grp
][regno
] = value
& 0xFFFFFFFFU
;
1462 gicv3_cpuif_update(cs
);
1465 static void icc_dir_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1468 /* Deactivate interrupt */
1469 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1470 int irq
= value
& 0xffffff;
1471 bool irq_is_secure
, single_sec_state
, irq_is_grp0
;
1472 bool route_fiq_to_el3
, route_irq_to_el3
, route_fiq_to_el2
, route_irq_to_el2
;
1474 if (icv_access(env
, HCR_FMO
| HCR_IMO
)) {
1475 icv_dir_write(env
, ri
, value
);
1479 trace_gicv3_icc_dir_write(gicv3_redist_affid(cs
), value
);
1481 if (irq
>= cs
->gic
->num_irq
) {
1482 /* Also catches special interrupt numbers and LPIs */
1486 if (!icc_eoi_split(env
, cs
)) {
1490 int grp
= gicv3_irq_group(cs
->gic
, cs
, irq
);
1492 single_sec_state
= cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
;
1493 irq_is_secure
= !single_sec_state
&& (grp
!= GICV3_G1NS
);
1494 irq_is_grp0
= grp
== GICV3_G0
;
1496 /* Check whether we're allowed to deactivate this interrupt based
1497 * on its group and the current CPU state.
1498 * These checks are laid out to correspond to the spec's pseudocode.
1500 route_fiq_to_el3
= env
->cp15
.scr_el3
& SCR_FIQ
;
1501 route_irq_to_el3
= env
->cp15
.scr_el3
& SCR_IRQ
;
1502 /* No need to include !IsSecure in route_*_to_el2 as it's only
1503 * tested in cases where we know !IsSecure is true.
1505 route_fiq_to_el2
= env
->cp15
.hcr_el2
& HCR_FMO
;
1506 route_irq_to_el2
= env
->cp15
.hcr_el2
& HCR_FMO
;
1508 switch (arm_current_el(env
)) {
1512 if (single_sec_state
&& irq_is_grp0
&& !route_fiq_to_el3
) {
1515 if (!irq_is_secure
&& !irq_is_grp0
&& !route_irq_to_el3
) {
1520 if (!arm_is_secure_below_el3(env
)) {
1521 if (single_sec_state
&& irq_is_grp0
&&
1522 !route_fiq_to_el3
&& !route_fiq_to_el2
) {
1525 if (!irq_is_secure
&& !irq_is_grp0
&&
1526 !route_irq_to_el3
&& !route_irq_to_el2
) {
1530 if (irq_is_grp0
&& !route_fiq_to_el3
) {
1534 (!irq_is_secure
|| !single_sec_state
) &&
1535 !route_irq_to_el3
) {
1541 g_assert_not_reached();
1544 icc_deactivate_irq(cs
, irq
);
1547 static uint64_t icc_rpr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1549 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1552 if (icv_access(env
, HCR_FMO
| HCR_IMO
)) {
1553 return icv_rpr_read(env
, ri
);
1556 prio
= icc_highest_active_prio(cs
);
1558 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
1559 !arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_FIQ
)) {
1560 /* NS GIC access and Group 0 is inaccessible to NS */
1562 /* NS mustn't see priorities in the Secure half of the range */
1564 } else if (prio
!= 0xff) {
1565 /* Non-idle priority: show the Non-secure view of it */
1566 prio
= (prio
<< 1) & 0xff;
1570 trace_gicv3_icc_rpr_read(gicv3_redist_affid(cs
), prio
);
1574 static void icc_generate_sgi(CPUARMState
*env
, GICv3CPUState
*cs
,
1575 uint64_t value
, int grp
, bool ns
)
1577 GICv3State
*s
= cs
->gic
;
1579 /* Extract Aff3/Aff2/Aff1 and shift into the bottom 24 bits */
1580 uint64_t aff
= extract64(value
, 48, 8) << 16 |
1581 extract64(value
, 32, 8) << 8 |
1582 extract64(value
, 16, 8);
1583 uint32_t targetlist
= extract64(value
, 0, 16);
1584 uint32_t irq
= extract64(value
, 24, 4);
1585 bool irm
= extract64(value
, 40, 1);
1588 if (grp
== GICV3_G1
&& s
->gicd_ctlr
& GICD_CTLR_DS
) {
1589 /* If GICD_CTLR.DS == 1, the Distributor treats Secure Group 1
1590 * interrupts as Group 0 interrupts and must send Secure Group 0
1591 * interrupts to the target CPUs.
1596 trace_gicv3_icc_generate_sgi(gicv3_redist_affid(cs
), irq
, irm
,
1599 for (i
= 0; i
< s
->num_cpu
; i
++) {
1600 GICv3CPUState
*ocs
= &s
->cpu
[i
];
1603 /* IRM == 1 : route to all CPUs except self */
1608 /* IRM == 0 : route to Aff3.Aff2.Aff1.n for all n in [0..15]
1609 * where the corresponding bit is set in targetlist
1613 if (ocs
->gicr_typer
>> 40 != aff
) {
1616 aff0
= extract64(ocs
->gicr_typer
, 32, 8);
1617 if (aff0
> 15 || extract32(targetlist
, aff0
, 1) == 0) {
1622 /* The redistributor will check against its own GICR_NSACR as needed */
1623 gicv3_redist_send_sgi(ocs
, grp
, irq
, ns
);
1627 static void icc_sgi0r_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1630 /* Generate Secure Group 0 SGI. */
1631 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1632 bool ns
= !arm_is_secure(env
);
1634 icc_generate_sgi(env
, cs
, value
, GICV3_G0
, ns
);
1637 static void icc_sgi1r_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1640 /* Generate Group 1 SGI for the current Security state */
1641 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1643 bool ns
= !arm_is_secure(env
);
1645 grp
= ns
? GICV3_G1NS
: GICV3_G1
;
1646 icc_generate_sgi(env
, cs
, value
, grp
, ns
);
1649 static void icc_asgi1r_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1652 /* Generate Group 1 SGI for the Security state that is not
1655 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1657 bool ns
= !arm_is_secure(env
);
1659 grp
= ns
? GICV3_G1
: GICV3_G1NS
;
1660 icc_generate_sgi(env
, cs
, value
, grp
, ns
);
1663 static uint64_t icc_igrpen_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1665 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1666 int grp
= ri
->opc2
& 1 ? GICV3_G1
: GICV3_G0
;
1669 if (icv_access(env
, grp
== GICV3_G0
? HCR_FMO
: HCR_IMO
)) {
1670 return icv_igrpen_read(env
, ri
);
1673 if (grp
== GICV3_G1
&& gicv3_use_ns_bank(env
)) {
1677 value
= cs
->icc_igrpen
[grp
];
1678 trace_gicv3_icc_igrpen_read(ri
->opc2
& 1 ? 1 : 0,
1679 gicv3_redist_affid(cs
), value
);
1683 static void icc_igrpen_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1686 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1687 int grp
= ri
->opc2
& 1 ? GICV3_G1
: GICV3_G0
;
1689 if (icv_access(env
, grp
== GICV3_G0
? HCR_FMO
: HCR_IMO
)) {
1690 icv_igrpen_write(env
, ri
, value
);
1694 trace_gicv3_icc_igrpen_write(ri
->opc2
& 1 ? 1 : 0,
1695 gicv3_redist_affid(cs
), value
);
1697 if (grp
== GICV3_G1
&& gicv3_use_ns_bank(env
)) {
1701 cs
->icc_igrpen
[grp
] = value
& ICC_IGRPEN_ENABLE
;
1702 gicv3_cpuif_update(cs
);
1705 static uint64_t icc_igrpen1_el3_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1707 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1710 /* IGRPEN1_EL3 bits 0 and 1 are r/w aliases into IGRPEN1_EL1 NS and S */
1711 value
= cs
->icc_igrpen
[GICV3_G1NS
] | (cs
->icc_igrpen
[GICV3_G1
] << 1);
1712 trace_gicv3_icc_igrpen1_el3_read(gicv3_redist_affid(cs
), value
);
1716 static void icc_igrpen1_el3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1719 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1721 trace_gicv3_icc_igrpen1_el3_write(gicv3_redist_affid(cs
), value
);
1723 /* IGRPEN1_EL3 bits 0 and 1 are r/w aliases into IGRPEN1_EL1 NS and S */
1724 cs
->icc_igrpen
[GICV3_G1NS
] = extract32(value
, 0, 1);
1725 cs
->icc_igrpen
[GICV3_G1
] = extract32(value
, 1, 1);
1726 gicv3_cpuif_update(cs
);
1729 static uint64_t icc_ctlr_el1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1731 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1732 int bank
= gicv3_use_ns_bank(env
) ? GICV3_NS
: GICV3_S
;
1735 if (icv_access(env
, HCR_FMO
| HCR_IMO
)) {
1736 return icv_ctlr_read(env
, ri
);
1739 value
= cs
->icc_ctlr_el1
[bank
];
1740 trace_gicv3_icc_ctlr_read(gicv3_redist_affid(cs
), value
);
1744 static void icc_ctlr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1747 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1748 int bank
= gicv3_use_ns_bank(env
) ? GICV3_NS
: GICV3_S
;
1751 if (icv_access(env
, HCR_FMO
| HCR_IMO
)) {
1752 icv_ctlr_write(env
, ri
, value
);
1756 trace_gicv3_icc_ctlr_write(gicv3_redist_affid(cs
), value
);
1758 /* Only CBPR and EOIMODE can be RW;
1759 * for us PMHE is RAZ/WI (we don't implement 1-of-N interrupts or
1760 * the asseciated priority-based routing of them);
1761 * if EL3 is implemented and GICD_CTLR.DS == 0, then PMHE and CBPR are RO.
1763 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
1764 ((cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
) == 0)) {
1765 mask
= ICC_CTLR_EL1_EOIMODE
;
1767 mask
= ICC_CTLR_EL1_CBPR
| ICC_CTLR_EL1_EOIMODE
;
1770 cs
->icc_ctlr_el1
[bank
] &= ~mask
;
1771 cs
->icc_ctlr_el1
[bank
] |= (value
& mask
);
1772 gicv3_cpuif_update(cs
);
1776 static uint64_t icc_ctlr_el3_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1778 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1781 value
= cs
->icc_ctlr_el3
;
1782 if (cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_EOIMODE
) {
1783 value
|= ICC_CTLR_EL3_EOIMODE_EL1NS
;
1785 if (cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_CBPR
) {
1786 value
|= ICC_CTLR_EL3_CBPR_EL1NS
;
1788 if (cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_EOIMODE
) {
1789 value
|= ICC_CTLR_EL3_EOIMODE_EL1S
;
1791 if (cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_CBPR
) {
1792 value
|= ICC_CTLR_EL3_CBPR_EL1S
;
1795 trace_gicv3_icc_ctlr_el3_read(gicv3_redist_affid(cs
), value
);
1799 static void icc_ctlr_el3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1802 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1805 trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs
), value
);
1807 /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
1808 cs
->icc_ctlr_el1
[GICV3_NS
] &= (ICC_CTLR_EL1_CBPR
| ICC_CTLR_EL1_EOIMODE
);
1809 if (value
& ICC_CTLR_EL3_EOIMODE_EL1NS
) {
1810 cs
->icc_ctlr_el1
[GICV3_NS
] |= ICC_CTLR_EL1_EOIMODE
;
1812 if (value
& ICC_CTLR_EL3_CBPR_EL1NS
) {
1813 cs
->icc_ctlr_el1
[GICV3_NS
] |= ICC_CTLR_EL1_CBPR
;
1816 cs
->icc_ctlr_el1
[GICV3_S
] &= (ICC_CTLR_EL1_CBPR
| ICC_CTLR_EL1_EOIMODE
);
1817 if (value
& ICC_CTLR_EL3_EOIMODE_EL1S
) {
1818 cs
->icc_ctlr_el1
[GICV3_S
] |= ICC_CTLR_EL1_EOIMODE
;
1820 if (value
& ICC_CTLR_EL3_CBPR_EL1S
) {
1821 cs
->icc_ctlr_el1
[GICV3_S
] |= ICC_CTLR_EL1_CBPR
;
1824 /* The only bit stored in icc_ctlr_el3 which is writeable is EOIMODE_EL3: */
1825 mask
= ICC_CTLR_EL3_EOIMODE_EL3
;
1827 cs
->icc_ctlr_el3
&= ~mask
;
1828 cs
->icc_ctlr_el3
|= (value
& mask
);
1829 gicv3_cpuif_update(cs
);
1832 static CPAccessResult
gicv3_irqfiq_access(CPUARMState
*env
,
1833 const ARMCPRegInfo
*ri
, bool isread
)
1835 CPAccessResult r
= CP_ACCESS_OK
;
1836 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1837 int el
= arm_current_el(env
);
1839 if ((cs
->ich_hcr_el2
& ICH_HCR_EL2_TC
) &&
1840 el
== 1 && !arm_is_secure_below_el3(env
)) {
1841 /* Takes priority over a possible EL3 trap */
1842 return CP_ACCESS_TRAP_EL2
;
1845 if ((env
->cp15
.scr_el3
& (SCR_FIQ
| SCR_IRQ
)) == (SCR_FIQ
| SCR_IRQ
)) {
1848 if (arm_is_secure_below_el3(env
) ||
1849 ((env
->cp15
.hcr_el2
& (HCR_IMO
| HCR_FMO
)) == 0)) {
1850 r
= CP_ACCESS_TRAP_EL3
;
1854 r
= CP_ACCESS_TRAP_EL3
;
1857 if (!is_a64(env
) && !arm_is_el3_or_mon(env
)) {
1858 r
= CP_ACCESS_TRAP_EL3
;
1862 g_assert_not_reached();
1866 if (r
== CP_ACCESS_TRAP_EL3
&& !arm_el_is_aa64(env
, 3)) {
1872 static CPAccessResult
gicv3_dir_access(CPUARMState
*env
,
1873 const ARMCPRegInfo
*ri
, bool isread
)
1875 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1877 if ((cs
->ich_hcr_el2
& ICH_HCR_EL2_TDIR
) &&
1878 arm_current_el(env
) == 1 && !arm_is_secure_below_el3(env
)) {
1879 /* Takes priority over a possible EL3 trap */
1880 return CP_ACCESS_TRAP_EL2
;
1883 return gicv3_irqfiq_access(env
, ri
, isread
);
1886 static CPAccessResult
gicv3_sgi_access(CPUARMState
*env
,
1887 const ARMCPRegInfo
*ri
, bool isread
)
1889 if ((env
->cp15
.hcr_el2
& (HCR_IMO
| HCR_FMO
)) &&
1890 arm_current_el(env
) == 1 && !arm_is_secure_below_el3(env
)) {
1891 /* Takes priority over a possible EL3 trap */
1892 return CP_ACCESS_TRAP_EL2
;
1895 return gicv3_irqfiq_access(env
, ri
, isread
);
1898 static CPAccessResult
gicv3_fiq_access(CPUARMState
*env
,
1899 const ARMCPRegInfo
*ri
, bool isread
)
1901 CPAccessResult r
= CP_ACCESS_OK
;
1902 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1903 int el
= arm_current_el(env
);
1905 if ((cs
->ich_hcr_el2
& ICH_HCR_EL2_TALL0
) &&
1906 el
== 1 && !arm_is_secure_below_el3(env
)) {
1907 /* Takes priority over a possible EL3 trap */
1908 return CP_ACCESS_TRAP_EL2
;
1911 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
1914 if (arm_is_secure_below_el3(env
) ||
1915 ((env
->cp15
.hcr_el2
& HCR_FMO
) == 0)) {
1916 r
= CP_ACCESS_TRAP_EL3
;
1920 r
= CP_ACCESS_TRAP_EL3
;
1923 if (!is_a64(env
) && !arm_is_el3_or_mon(env
)) {
1924 r
= CP_ACCESS_TRAP_EL3
;
1928 g_assert_not_reached();
1932 if (r
== CP_ACCESS_TRAP_EL3
&& !arm_el_is_aa64(env
, 3)) {
1938 static CPAccessResult
gicv3_irq_access(CPUARMState
*env
,
1939 const ARMCPRegInfo
*ri
, bool isread
)
1941 CPAccessResult r
= CP_ACCESS_OK
;
1942 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1943 int el
= arm_current_el(env
);
1945 if ((cs
->ich_hcr_el2
& ICH_HCR_EL2_TALL1
) &&
1946 el
== 1 && !arm_is_secure_below_el3(env
)) {
1947 /* Takes priority over a possible EL3 trap */
1948 return CP_ACCESS_TRAP_EL2
;
1951 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
1954 if (arm_is_secure_below_el3(env
) ||
1955 ((env
->cp15
.hcr_el2
& HCR_IMO
) == 0)) {
1956 r
= CP_ACCESS_TRAP_EL3
;
1960 r
= CP_ACCESS_TRAP_EL3
;
1963 if (!is_a64(env
) && !arm_is_el3_or_mon(env
)) {
1964 r
= CP_ACCESS_TRAP_EL3
;
1968 g_assert_not_reached();
1972 if (r
== CP_ACCESS_TRAP_EL3
&& !arm_el_is_aa64(env
, 3)) {
1978 static void icc_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1980 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1982 cs
->icc_ctlr_el1
[GICV3_S
] = ICC_CTLR_EL1_A3V
|
1983 (1 << ICC_CTLR_EL1_IDBITS_SHIFT
) |
1984 (7 << ICC_CTLR_EL1_PRIBITS_SHIFT
);
1985 cs
->icc_ctlr_el1
[GICV3_NS
] = ICC_CTLR_EL1_A3V
|
1986 (1 << ICC_CTLR_EL1_IDBITS_SHIFT
) |
1987 (7 << ICC_CTLR_EL1_PRIBITS_SHIFT
);
1988 cs
->icc_pmr_el1
= 0;
1989 cs
->icc_bpr
[GICV3_G0
] = GIC_MIN_BPR
;
1990 cs
->icc_bpr
[GICV3_G1
] = GIC_MIN_BPR
;
1991 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1992 cs
->icc_bpr
[GICV3_G1NS
] = GIC_MIN_BPR_NS
;
1994 cs
->icc_bpr
[GICV3_G1NS
] = GIC_MIN_BPR
;
1996 memset(cs
->icc_apr
, 0, sizeof(cs
->icc_apr
));
1997 memset(cs
->icc_igrpen
, 0, sizeof(cs
->icc_igrpen
));
1998 cs
->icc_ctlr_el3
= ICC_CTLR_EL3_NDS
| ICC_CTLR_EL3_A3V
|
1999 (1 << ICC_CTLR_EL3_IDBITS_SHIFT
) |
2000 (7 << ICC_CTLR_EL3_PRIBITS_SHIFT
);
2002 memset(cs
->ich_apr
, 0, sizeof(cs
->ich_apr
));
2003 cs
->ich_hcr_el2
= 0;
2004 memset(cs
->ich_lr_el2
, 0, sizeof(cs
->ich_lr_el2
));
2005 cs
->ich_vmcr_el2
= ICH_VMCR_EL2_VFIQEN
|
2006 (icv_min_vbpr(cs
) << ICH_VMCR_EL2_VBPR1_SHIFT
) |
2007 (icv_min_vbpr(cs
) << ICH_VMCR_EL2_VBPR0_SHIFT
);
2010 static const ARMCPRegInfo gicv3_cpuif_reginfo
[] = {
2011 { .name
= "ICC_PMR_EL1", .state
= ARM_CP_STATE_BOTH
,
2012 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 6, .opc2
= 0,
2013 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2014 .access
= PL1_RW
, .accessfn
= gicv3_irqfiq_access
,
2015 .readfn
= icc_pmr_read
,
2016 .writefn
= icc_pmr_write
,
2017 /* We hang the whole cpu interface reset routine off here
2018 * rather than parcelling it out into one little function
2021 .resetfn
= icc_reset
,
2023 { .name
= "ICC_IAR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2024 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 0,
2025 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2026 .access
= PL1_R
, .accessfn
= gicv3_fiq_access
,
2027 .readfn
= icc_iar0_read
,
2029 { .name
= "ICC_EOIR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2030 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 1,
2031 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2032 .access
= PL1_W
, .accessfn
= gicv3_fiq_access
,
2033 .writefn
= icc_eoir_write
,
2035 { .name
= "ICC_HPPIR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2036 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 2,
2037 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2038 .access
= PL1_R
, .accessfn
= gicv3_fiq_access
,
2039 .readfn
= icc_hppir0_read
,
2041 { .name
= "ICC_BPR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2042 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 3,
2043 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2044 .access
= PL1_RW
, .accessfn
= gicv3_fiq_access
,
2045 .readfn
= icc_bpr_read
,
2046 .writefn
= icc_bpr_write
,
2048 { .name
= "ICC_AP0R0_EL1", .state
= ARM_CP_STATE_BOTH
,
2049 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 4,
2050 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2051 .access
= PL1_RW
, .accessfn
= gicv3_fiq_access
,
2052 .readfn
= icc_ap_read
,
2053 .writefn
= icc_ap_write
,
2055 { .name
= "ICC_AP0R1_EL1", .state
= ARM_CP_STATE_BOTH
,
2056 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 5,
2057 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2058 .access
= PL1_RW
, .accessfn
= gicv3_fiq_access
,
2059 .readfn
= icc_ap_read
,
2060 .writefn
= icc_ap_write
,
2062 { .name
= "ICC_AP0R2_EL1", .state
= ARM_CP_STATE_BOTH
,
2063 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 6,
2064 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2065 .access
= PL1_RW
, .accessfn
= gicv3_fiq_access
,
2066 .readfn
= icc_ap_read
,
2067 .writefn
= icc_ap_write
,
2069 { .name
= "ICC_AP0R3_EL1", .state
= ARM_CP_STATE_BOTH
,
2070 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 7,
2071 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2072 .access
= PL1_RW
, .accessfn
= gicv3_fiq_access
,
2073 .readfn
= icc_ap_read
,
2074 .writefn
= icc_ap_write
,
2076 /* All the ICC_AP1R*_EL1 registers are banked */
2077 { .name
= "ICC_AP1R0_EL1", .state
= ARM_CP_STATE_BOTH
,
2078 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 9, .opc2
= 0,
2079 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2080 .access
= PL1_RW
, .accessfn
= gicv3_irq_access
,
2081 .readfn
= icc_ap_read
,
2082 .writefn
= icc_ap_write
,
2084 { .name
= "ICC_AP1R1_EL1", .state
= ARM_CP_STATE_BOTH
,
2085 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 9, .opc2
= 1,
2086 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2087 .access
= PL1_RW
, .accessfn
= gicv3_irq_access
,
2088 .readfn
= icc_ap_read
,
2089 .writefn
= icc_ap_write
,
2091 { .name
= "ICC_AP1R2_EL1", .state
= ARM_CP_STATE_BOTH
,
2092 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 9, .opc2
= 2,
2093 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2094 .access
= PL1_RW
, .accessfn
= gicv3_irq_access
,
2095 .readfn
= icc_ap_read
,
2096 .writefn
= icc_ap_write
,
2098 { .name
= "ICC_AP1R3_EL1", .state
= ARM_CP_STATE_BOTH
,
2099 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 9, .opc2
= 3,
2100 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2101 .access
= PL1_RW
, .accessfn
= gicv3_irq_access
,
2102 .readfn
= icc_ap_read
,
2103 .writefn
= icc_ap_write
,
2105 { .name
= "ICC_DIR_EL1", .state
= ARM_CP_STATE_BOTH
,
2106 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 11, .opc2
= 1,
2107 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2108 .access
= PL1_W
, .accessfn
= gicv3_dir_access
,
2109 .writefn
= icc_dir_write
,
2111 { .name
= "ICC_RPR_EL1", .state
= ARM_CP_STATE_BOTH
,
2112 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 11, .opc2
= 3,
2113 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2114 .access
= PL1_R
, .accessfn
= gicv3_irqfiq_access
,
2115 .readfn
= icc_rpr_read
,
2117 { .name
= "ICC_SGI1R_EL1", .state
= ARM_CP_STATE_AA64
,
2118 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 11, .opc2
= 5,
2119 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2120 .access
= PL1_W
, .accessfn
= gicv3_sgi_access
,
2121 .writefn
= icc_sgi1r_write
,
2123 { .name
= "ICC_SGI1R",
2124 .cp
= 15, .opc1
= 0, .crm
= 12,
2125 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2126 .access
= PL1_W
, .accessfn
= gicv3_sgi_access
,
2127 .writefn
= icc_sgi1r_write
,
2129 { .name
= "ICC_ASGI1R_EL1", .state
= ARM_CP_STATE_AA64
,
2130 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 11, .opc2
= 6,
2131 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2132 .access
= PL1_W
, .accessfn
= gicv3_sgi_access
,
2133 .writefn
= icc_asgi1r_write
,
2135 { .name
= "ICC_ASGI1R",
2136 .cp
= 15, .opc1
= 1, .crm
= 12,
2137 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2138 .access
= PL1_W
, .accessfn
= gicv3_sgi_access
,
2139 .writefn
= icc_asgi1r_write
,
2141 { .name
= "ICC_SGI0R_EL1", .state
= ARM_CP_STATE_AA64
,
2142 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 11, .opc2
= 7,
2143 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2144 .access
= PL1_W
, .accessfn
= gicv3_sgi_access
,
2145 .writefn
= icc_sgi0r_write
,
2147 { .name
= "ICC_SGI0R",
2148 .cp
= 15, .opc1
= 2, .crm
= 12,
2149 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2150 .access
= PL1_W
, .accessfn
= gicv3_sgi_access
,
2151 .writefn
= icc_sgi0r_write
,
2153 { .name
= "ICC_IAR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2154 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 0,
2155 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2156 .access
= PL1_R
, .accessfn
= gicv3_irq_access
,
2157 .readfn
= icc_iar1_read
,
2159 { .name
= "ICC_EOIR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2160 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 1,
2161 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2162 .access
= PL1_W
, .accessfn
= gicv3_irq_access
,
2163 .writefn
= icc_eoir_write
,
2165 { .name
= "ICC_HPPIR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2166 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 2,
2167 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2168 .access
= PL1_R
, .accessfn
= gicv3_irq_access
,
2169 .readfn
= icc_hppir1_read
,
2171 /* This register is banked */
2172 { .name
= "ICC_BPR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2173 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 3,
2174 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2175 .access
= PL1_RW
, .accessfn
= gicv3_irq_access
,
2176 .readfn
= icc_bpr_read
,
2177 .writefn
= icc_bpr_write
,
2179 /* This register is banked */
2180 { .name
= "ICC_CTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
2181 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 4,
2182 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2183 .access
= PL1_RW
, .accessfn
= gicv3_irqfiq_access
,
2184 .readfn
= icc_ctlr_el1_read
,
2185 .writefn
= icc_ctlr_el1_write
,
2187 { .name
= "ICC_SRE_EL1", .state
= ARM_CP_STATE_BOTH
,
2188 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 5,
2189 .type
= ARM_CP_NO_RAW
| ARM_CP_CONST
,
2191 /* We don't support IRQ/FIQ bypass and system registers are
2192 * always enabled, so all our bits are RAZ/WI or RAO/WI.
2193 * This register is banked but since it's constant we don't
2194 * need to do anything special.
2198 { .name
= "ICC_IGRPEN0_EL1", .state
= ARM_CP_STATE_BOTH
,
2199 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 6,
2200 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2201 .access
= PL1_RW
, .accessfn
= gicv3_fiq_access
,
2202 .readfn
= icc_igrpen_read
,
2203 .writefn
= icc_igrpen_write
,
2205 /* This register is banked */
2206 { .name
= "ICC_IGRPEN1_EL1", .state
= ARM_CP_STATE_BOTH
,
2207 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 7,
2208 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2209 .access
= PL1_RW
, .accessfn
= gicv3_irq_access
,
2210 .readfn
= icc_igrpen_read
,
2211 .writefn
= icc_igrpen_write
,
2213 { .name
= "ICC_SRE_EL2", .state
= ARM_CP_STATE_BOTH
,
2214 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 9, .opc2
= 5,
2215 .type
= ARM_CP_NO_RAW
| ARM_CP_CONST
,
2217 /* We don't support IRQ/FIQ bypass and system registers are
2218 * always enabled, so all our bits are RAZ/WI or RAO/WI.
2222 { .name
= "ICC_CTLR_EL3", .state
= ARM_CP_STATE_BOTH
,
2223 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 12, .opc2
= 4,
2224 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2226 .readfn
= icc_ctlr_el3_read
,
2227 .writefn
= icc_ctlr_el3_write
,
2229 { .name
= "ICC_SRE_EL3", .state
= ARM_CP_STATE_BOTH
,
2230 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 12, .opc2
= 5,
2231 .type
= ARM_CP_NO_RAW
| ARM_CP_CONST
,
2233 /* We don't support IRQ/FIQ bypass and system registers are
2234 * always enabled, so all our bits are RAZ/WI or RAO/WI.
2238 { .name
= "ICC_IGRPEN1_EL3", .state
= ARM_CP_STATE_BOTH
,
2239 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 12, .opc2
= 7,
2240 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2242 .readfn
= icc_igrpen1_el3_read
,
2243 .writefn
= icc_igrpen1_el3_write
,
2248 static uint64_t ich_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2250 GICv3CPUState
*cs
= icc_cs_from_env(env
);
2251 int regno
= ri
->opc2
& 3;
2252 int grp
= ri
->crm
& 1 ? GICV3_G0
: GICV3_G1NS
;
2255 value
= cs
->ich_apr
[grp
][regno
];
2256 trace_gicv3_ich_ap_read(ri
->crm
& 1, regno
, gicv3_redist_affid(cs
), value
);
2260 static void ich_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2263 GICv3CPUState
*cs
= icc_cs_from_env(env
);
2264 int regno
= ri
->opc2
& 3;
2265 int grp
= ri
->crm
& 1 ? GICV3_G0
: GICV3_G1NS
;
2267 trace_gicv3_ich_ap_write(ri
->crm
& 1, regno
, gicv3_redist_affid(cs
), value
);
2269 cs
->ich_apr
[grp
][regno
] = value
& 0xFFFFFFFFU
;
2270 gicv3_cpuif_virt_update(cs
);
2273 static uint64_t ich_hcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2275 GICv3CPUState
*cs
= icc_cs_from_env(env
);
2276 uint64_t value
= cs
->ich_hcr_el2
;
2278 trace_gicv3_ich_hcr_read(gicv3_redist_affid(cs
), value
);
2282 static void ich_hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2285 GICv3CPUState
*cs
= icc_cs_from_env(env
);
2287 trace_gicv3_ich_hcr_write(gicv3_redist_affid(cs
), value
);
2289 value
&= ICH_HCR_EL2_EN
| ICH_HCR_EL2_UIE
| ICH_HCR_EL2_LRENPIE
|
2290 ICH_HCR_EL2_NPIE
| ICH_HCR_EL2_VGRP0EIE
| ICH_HCR_EL2_VGRP0DIE
|
2291 ICH_HCR_EL2_VGRP1EIE
| ICH_HCR_EL2_VGRP1DIE
| ICH_HCR_EL2_TC
|
2292 ICH_HCR_EL2_TALL0
| ICH_HCR_EL2_TALL1
| ICH_HCR_EL2_TSEI
|
2293 ICH_HCR_EL2_TDIR
| ICH_HCR_EL2_EOICOUNT_MASK
;
2295 cs
->ich_hcr_el2
= value
;
2296 gicv3_cpuif_virt_update(cs
);
2299 static uint64_t ich_vmcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2301 GICv3CPUState
*cs
= icc_cs_from_env(env
);
2302 uint64_t value
= cs
->ich_vmcr_el2
;
2304 trace_gicv3_ich_vmcr_read(gicv3_redist_affid(cs
), value
);
2308 static void ich_vmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2311 GICv3CPUState
*cs
= icc_cs_from_env(env
);
2313 trace_gicv3_ich_vmcr_write(gicv3_redist_affid(cs
), value
);
2315 value
&= ICH_VMCR_EL2_VENG0
| ICH_VMCR_EL2_VENG1
| ICH_VMCR_EL2_VCBPR
|
2316 ICH_VMCR_EL2_VEOIM
| ICH_VMCR_EL2_VBPR1_MASK
|
2317 ICH_VMCR_EL2_VBPR0_MASK
| ICH_VMCR_EL2_VPMR_MASK
;
2318 value
|= ICH_VMCR_EL2_VFIQEN
;
2320 cs
->ich_vmcr_el2
= value
;
2321 /* Enforce "writing BPRs to less than minimum sets them to the minimum"
2322 * by reading and writing back the fields.
2324 write_vbpr(cs
, GICV3_G1
, read_vbpr(cs
, GICV3_G0
));
2325 write_vbpr(cs
, GICV3_G1
, read_vbpr(cs
, GICV3_G1
));
2327 gicv3_cpuif_virt_update(cs
);
2330 static uint64_t ich_lr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2332 GICv3CPUState
*cs
= icc_cs_from_env(env
);
2333 int regno
= ri
->opc2
| ((ri
->crm
& 1) << 3);
2336 /* This read function handles all of:
2337 * 64-bit reads of the whole LR
2338 * 32-bit reads of the low half of the LR
2339 * 32-bit reads of the high half of the LR
2341 if (ri
->state
== ARM_CP_STATE_AA32
) {
2342 if (ri
->crm
>= 14) {
2343 value
= extract64(cs
->ich_lr_el2
[regno
], 32, 32);
2344 trace_gicv3_ich_lrc_read(regno
, gicv3_redist_affid(cs
), value
);
2346 value
= extract64(cs
->ich_lr_el2
[regno
], 0, 32);
2347 trace_gicv3_ich_lr32_read(regno
, gicv3_redist_affid(cs
), value
);
2350 value
= cs
->ich_lr_el2
[regno
];
2351 trace_gicv3_ich_lr_read(regno
, gicv3_redist_affid(cs
), value
);
2357 static void ich_lr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2360 GICv3CPUState
*cs
= icc_cs_from_env(env
);
2361 int regno
= ri
->opc2
| ((ri
->crm
& 1) << 3);
2363 /* This write function handles all of:
2364 * 64-bit writes to the whole LR
2365 * 32-bit writes to the low half of the LR
2366 * 32-bit writes to the high half of the LR
2368 if (ri
->state
== ARM_CP_STATE_AA32
) {
2369 if (ri
->crm
>= 14) {
2370 trace_gicv3_ich_lrc_write(regno
, gicv3_redist_affid(cs
), value
);
2371 value
= deposit64(cs
->ich_lr_el2
[regno
], 32, 32, value
);
2373 trace_gicv3_ich_lr32_write(regno
, gicv3_redist_affid(cs
), value
);
2374 value
= deposit64(cs
->ich_lr_el2
[regno
], 0, 32, value
);
2377 trace_gicv3_ich_lr_write(regno
, gicv3_redist_affid(cs
), value
);
2380 /* Enforce RES0 bits in priority field */
2381 if (cs
->vpribits
< 8) {
2382 value
= deposit64(value
, ICH_LR_EL2_PRIORITY_SHIFT
,
2383 8 - cs
->vpribits
, 0);
2386 cs
->ich_lr_el2
[regno
] = value
;
2387 gicv3_cpuif_virt_update(cs
);
2390 static uint64_t ich_vtr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2392 GICv3CPUState
*cs
= icc_cs_from_env(env
);
2395 value
= ((cs
->num_list_regs
- 1) << ICH_VTR_EL2_LISTREGS_SHIFT
)
2396 | ICH_VTR_EL2_TDS
| ICH_VTR_EL2_NV4
| ICH_VTR_EL2_A3V
2397 | (1 << ICH_VTR_EL2_IDBITS_SHIFT
)
2398 | ((cs
->vprebits
- 1) << ICH_VTR_EL2_PREBITS_SHIFT
)
2399 | ((cs
->vpribits
- 1) << ICH_VTR_EL2_PRIBITS_SHIFT
);
2401 trace_gicv3_ich_vtr_read(gicv3_redist_affid(cs
), value
);
2405 static uint64_t ich_misr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2407 GICv3CPUState
*cs
= icc_cs_from_env(env
);
2408 uint64_t value
= maintenance_interrupt_state(cs
);
2410 trace_gicv3_ich_misr_read(gicv3_redist_affid(cs
), value
);
2414 static uint64_t ich_eisr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2416 GICv3CPUState
*cs
= icc_cs_from_env(env
);
2417 uint64_t value
= eoi_maintenance_interrupt_state(cs
, NULL
);
2419 trace_gicv3_ich_eisr_read(gicv3_redist_affid(cs
), value
);
2423 static uint64_t ich_elrsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2425 GICv3CPUState
*cs
= icc_cs_from_env(env
);
2429 for (i
= 0; i
< cs
->num_list_regs
; i
++) {
2430 uint64_t lr
= cs
->ich_lr_el2
[i
];
2432 if ((lr
& ICH_LR_EL2_STATE_MASK
) == 0 &&
2433 ((lr
& ICH_LR_EL2_HW
) != 0 || (lr
& ICH_LR_EL2_EOI
) == 0)) {
2438 trace_gicv3_ich_elrsr_read(gicv3_redist_affid(cs
), value
);
2442 static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo
[] = {
2443 { .name
= "ICH_AP0R0_EL2", .state
= ARM_CP_STATE_BOTH
,
2444 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 8, .opc2
= 0,
2445 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2447 .readfn
= ich_ap_read
,
2448 .writefn
= ich_ap_write
,
2450 { .name
= "ICH_AP1R0_EL2", .state
= ARM_CP_STATE_BOTH
,
2451 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 9, .opc2
= 0,
2452 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2454 .readfn
= ich_ap_read
,
2455 .writefn
= ich_ap_write
,
2457 { .name
= "ICH_HCR_EL2", .state
= ARM_CP_STATE_BOTH
,
2458 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 11, .opc2
= 0,
2459 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2461 .readfn
= ich_hcr_read
,
2462 .writefn
= ich_hcr_write
,
2464 { .name
= "ICH_VTR_EL2", .state
= ARM_CP_STATE_BOTH
,
2465 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 11, .opc2
= 1,
2466 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2468 .readfn
= ich_vtr_read
,
2470 { .name
= "ICH_MISR_EL2", .state
= ARM_CP_STATE_BOTH
,
2471 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 11, .opc2
= 2,
2472 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2474 .readfn
= ich_misr_read
,
2476 { .name
= "ICH_EISR_EL2", .state
= ARM_CP_STATE_BOTH
,
2477 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 11, .opc2
= 3,
2478 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2480 .readfn
= ich_eisr_read
,
2482 { .name
= "ICH_ELRSR_EL2", .state
= ARM_CP_STATE_BOTH
,
2483 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 11, .opc2
= 5,
2484 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2486 .readfn
= ich_elrsr_read
,
2488 { .name
= "ICH_VMCR_EL2", .state
= ARM_CP_STATE_BOTH
,
2489 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 11, .opc2
= 7,
2490 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2492 .readfn
= ich_vmcr_read
,
2493 .writefn
= ich_vmcr_write
,
2498 static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo
[] = {
2499 { .name
= "ICH_AP0R1_EL2", .state
= ARM_CP_STATE_BOTH
,
2500 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 8, .opc2
= 1,
2501 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2503 .readfn
= ich_ap_read
,
2504 .writefn
= ich_ap_write
,
2506 { .name
= "ICH_AP1R1_EL2", .state
= ARM_CP_STATE_BOTH
,
2507 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 9, .opc2
= 1,
2508 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2510 .readfn
= ich_ap_read
,
2511 .writefn
= ich_ap_write
,
2516 static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo
[] = {
2517 { .name
= "ICH_AP0R2_EL2", .state
= ARM_CP_STATE_BOTH
,
2518 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 8, .opc2
= 2,
2519 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2521 .readfn
= ich_ap_read
,
2522 .writefn
= ich_ap_write
,
2524 { .name
= "ICH_AP0R3_EL2", .state
= ARM_CP_STATE_BOTH
,
2525 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 8, .opc2
= 3,
2526 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2528 .readfn
= ich_ap_read
,
2529 .writefn
= ich_ap_write
,
2531 { .name
= "ICH_AP1R2_EL2", .state
= ARM_CP_STATE_BOTH
,
2532 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 9, .opc2
= 2,
2533 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2535 .readfn
= ich_ap_read
,
2536 .writefn
= ich_ap_write
,
2538 { .name
= "ICH_AP1R3_EL2", .state
= ARM_CP_STATE_BOTH
,
2539 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 9, .opc2
= 3,
2540 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2542 .readfn
= ich_ap_read
,
2543 .writefn
= ich_ap_write
,
2548 static void gicv3_cpuif_el_change_hook(ARMCPU
*cpu
, void *opaque
)
2550 GICv3CPUState
*cs
= opaque
;
2552 gicv3_cpuif_update(cs
);
2555 void gicv3_init_cpuif(GICv3State
*s
)
2557 /* Called from the GICv3 realize function; register our system
2558 * registers with the CPU
2562 for (i
= 0; i
< s
->num_cpu
; i
++) {
2563 ARMCPU
*cpu
= ARM_CPU(qemu_get_cpu(i
));
2564 GICv3CPUState
*cs
= &s
->cpu
[i
];
2566 /* Note that we can't just use the GICv3CPUState as an opaque pointer
2567 * in define_arm_cp_regs_with_opaque(), because when we're called back
2568 * it might be with code translated by CPU 0 but run by CPU 1, in
2569 * which case we'd get the wrong value.
2570 * So instead we define the regs with no ri->opaque info, and
2571 * get back to the GICv3CPUState from the ARMCPU by reading back
2572 * the opaque pointer from the el_change_hook, which we're going
2573 * to need to register anyway.
2575 define_arm_cp_regs(cpu
, gicv3_cpuif_reginfo
);
2576 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)
2577 && cpu
->gic_num_lrs
) {
2580 cs
->maintenance_irq
= cpu
->gicv3_maintenance_interrupt
;
2582 cs
->num_list_regs
= cpu
->gic_num_lrs
;
2583 cs
->vpribits
= cpu
->gic_vpribits
;
2584 cs
->vprebits
= cpu
->gic_vprebits
;
2586 /* Check against architectural constraints: getting these
2587 * wrong would be a bug in the CPU code defining these,
2588 * and the implementation relies on them holding.
2590 g_assert(cs
->vprebits
<= cs
->vpribits
);
2591 g_assert(cs
->vprebits
>= 5 && cs
->vprebits
<= 7);
2592 g_assert(cs
->vpribits
>= 5 && cs
->vpribits
<= 8);
2594 define_arm_cp_regs(cpu
, gicv3_cpuif_hcr_reginfo
);
2596 for (j
= 0; j
< cs
->num_list_regs
; j
++) {
2597 /* Note that the AArch64 LRs are 64-bit; the AArch32 LRs
2598 * are split into two cp15 regs, LR (the low part, with the
2599 * same encoding as the AArch64 LR) and LRC (the high part).
2601 ARMCPRegInfo lr_regset
[] = {
2602 { .name
= "ICH_LRn_EL2", .state
= ARM_CP_STATE_BOTH
,
2603 .opc0
= 3, .opc1
= 4, .crn
= 12,
2604 .crm
= 12 + (j
>> 3), .opc2
= j
& 7,
2605 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2607 .readfn
= ich_lr_read
,
2608 .writefn
= ich_lr_write
,
2610 { .name
= "ICH_LRCn_EL2", .state
= ARM_CP_STATE_AA32
,
2611 .cp
= 15, .opc1
= 4, .crn
= 12,
2612 .crm
= 14 + (j
>> 3), .opc2
= j
& 7,
2613 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
2615 .readfn
= ich_lr_read
,
2616 .writefn
= ich_lr_write
,
2620 define_arm_cp_regs(cpu
, lr_regset
);
2622 if (cs
->vprebits
>= 6) {
2623 define_arm_cp_regs(cpu
, gicv3_cpuif_ich_apxr1_reginfo
);
2625 if (cs
->vprebits
== 7) {
2626 define_arm_cp_regs(cpu
, gicv3_cpuif_ich_apxr23_reginfo
);
2629 arm_register_el_change_hook(cpu
, gicv3_cpuif_el_change_hook
, cs
);