hw/pci-bridge/pci_expander_bridge.c

   1 /*
   2  * PCI Expander Bridge Device Emulation
   3  *
   4  * Copyright (C) 2015 Red Hat Inc
   5  *
   6  * Authors:
   7  *   Marcel Apfelbaum <marcel@redhat.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "hw/pci/pci.h"
  16 #include "hw/pci/pci_bus.h"
  17 #include "hw/pci/pci_host.h"
  18 #include "hw/qdev-properties.h"
  19 #include "hw/pci/pci_bridge.h"
  20 #include "hw/pci-bridge/pci_expander_bridge.h"
  21 #include "hw/cxl/cxl.h"
  22 #include "qemu/range.h"
  23 #include "qemu/error-report.h"
  24 #include "qemu/module.h"
  25 #include "sysemu/numa.h"
  26 #include "hw/boards.h"
  27 #include "qom/object.h"
  28
  29 enum BusType { PCI, PCIE, CXL };
  30
  31 #define TYPE_PXB_BUS "pxb-bus"
  32 typedef struct PXBBus PXBBus;
  33 DECLARE_INSTANCE_CHECKER(PXBBus, PXB_BUS,
  34                          TYPE_PXB_BUS)
  35
  36 #define TYPE_PXB_PCIE_BUS "pxb-pcie-bus"
  37 DECLARE_INSTANCE_CHECKER(PXBBus, PXB_PCIE_BUS,
  38                          TYPE_PXB_PCIE_BUS)
  39
  40 #define TYPE_PXB_CXL_BUS "pxb-cxl-bus"
  41 DECLARE_INSTANCE_CHECKER(PXBBus, PXB_CXL_BUS,
  42                          TYPE_PXB_CXL_BUS)
  43
  44 struct PXBBus {
  45     /*< private >*/
  46     PCIBus parent_obj;
  47     /*< public >*/
  48
  49     char bus_path[8];
  50 };
  51
  52 #define TYPE_PXB_DEVICE "pxb"
  53 typedef struct PXBDev PXBDev;
  54 DECLARE_INSTANCE_CHECKER(PXBDev, PXB_DEV,
  55                          TYPE_PXB_DEVICE)
  56
  57 #define TYPE_PXB_PCIE_DEVICE "pxb-pcie"
  58 DECLARE_INSTANCE_CHECKER(PXBDev, PXB_PCIE_DEV,
  59                          TYPE_PXB_PCIE_DEVICE)
  60
  61 static PXBDev *convert_to_pxb(PCIDevice *dev)
  62 {
  63     /* A CXL PXB's parent bus is PCIe, so the normal check won't work */
  64     if (object_dynamic_cast(OBJECT(dev), TYPE_PXB_CXL_DEVICE)) {
  65         return PXB_CXL_DEV(dev);
  66     }
  67
  68     return pci_bus_is_express(pci_get_bus(dev))
  69         ? PXB_PCIE_DEV(dev) : PXB_DEV(dev);
  70 }
  71
  72 static GList *pxb_dev_list;
  73
  74 #define TYPE_PXB_HOST "pxb-host"
  75
  76 CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb)
  77 {
  78     CXLHost *host = PXB_CXL_HOST(hb);
  79
  80     return &host->cxl_cstate;
  81 }
  82
  83 static int pxb_bus_num(PCIBus *bus)
  84 {
  85     PXBDev *pxb = convert_to_pxb(bus->parent_dev);
  86
  87     return pxb->bus_nr;
  88 }
  89
  90 static uint16_t pxb_bus_numa_node(PCIBus *bus)
  91 {
  92     PXBDev *pxb = convert_to_pxb(bus->parent_dev);
  93
  94     return pxb->numa_node;
  95 }
  96
  97 static void pxb_bus_class_init(ObjectClass *class, void *data)
  98 {
  99     PCIBusClass *pbc = PCI_BUS_CLASS(class);
 100
 101     pbc->bus_num = pxb_bus_num;
 102     pbc->numa_node = pxb_bus_numa_node;
 103 }
 104
 105 static const TypeInfo pxb_bus_info = {
 106     .name          = TYPE_PXB_BUS,
 107     .parent        = TYPE_PCI_BUS,
 108     .instance_size = sizeof(PXBBus),
 109     .class_init    = pxb_bus_class_init,
 110 };
 111
 112 static const TypeInfo pxb_pcie_bus_info = {
 113     .name          = TYPE_PXB_PCIE_BUS,
 114     .parent        = TYPE_PCIE_BUS,
 115     .instance_size = sizeof(PXBBus),
 116     .class_init    = pxb_bus_class_init,
 117 };
 118
 119 static const TypeInfo pxb_cxl_bus_info = {
 120     .name          = TYPE_PXB_CXL_BUS,
 121     .parent        = TYPE_CXL_BUS,
 122     .instance_size = sizeof(PXBBus),
 123     .class_init    = pxb_bus_class_init,
 124 };
 125
 126 static const char *pxb_host_root_bus_path(PCIHostState *host_bridge,
 127                                           PCIBus *rootbus)
 128 {
 129     PXBBus *bus = pci_bus_is_cxl(rootbus) ?
 130                       PXB_CXL_BUS(rootbus) :
 131                       pci_bus_is_express(rootbus) ? PXB_PCIE_BUS(rootbus) :
 132                                                     PXB_BUS(rootbus);
 133
 134     snprintf(bus->bus_path, 8, "0000:%02x", pxb_bus_num(rootbus));
 135     return bus->bus_path;
 136 }
 137
 138 static char *pxb_host_ofw_unit_address(const SysBusDevice *dev)
 139 {
 140     const PCIHostState *pxb_host;
 141     const PCIBus *pxb_bus;
 142     const PXBDev *pxb_dev;
 143     int position;
 144     const DeviceState *pxb_dev_base;
 145     const PCIHostState *main_host;
 146     const SysBusDevice *main_host_sbd;
 147
 148     pxb_host = PCI_HOST_BRIDGE(dev);
 149     pxb_bus = pxb_host->bus;
 150     pxb_dev = convert_to_pxb(pxb_bus->parent_dev);
 151     position = g_list_index(pxb_dev_list, pxb_dev);
 152     assert(position >= 0);
 153
 154     pxb_dev_base = DEVICE(pxb_dev);
 155     main_host = PCI_HOST_BRIDGE(pxb_dev_base->parent_bus->parent);
 156     main_host_sbd = SYS_BUS_DEVICE(main_host);
 157
 158     if (main_host_sbd->num_mmio > 0) {
 159         return g_strdup_printf(TARGET_FMT_plx ",%x",
 160                                main_host_sbd->mmio[0].addr, position + 1);
 161     }
 162     if (main_host_sbd->num_pio > 0) {
 163         return g_strdup_printf("i%04x,%x",
 164                                main_host_sbd->pio[0], position + 1);
 165     }
 166     return NULL;
 167 }
 168
 169 static void pxb_host_class_init(ObjectClass *class, void *data)
 170 {
 171     DeviceClass *dc = DEVICE_CLASS(class);
 172     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(class);
 173     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(class);
 174
 175     dc->fw_name = "pci";
 176     /* Reason: Internal part of the pxb/pxb-pcie device, not usable by itself */
 177     dc->user_creatable = false;
 178     sbc->explicit_ofw_unit_address = pxb_host_ofw_unit_address;
 179     hc->root_bus_path = pxb_host_root_bus_path;
 180 }
 181
 182 static const TypeInfo pxb_host_info = {
 183     .name          = TYPE_PXB_HOST,
 184     .parent        = TYPE_PCI_HOST_BRIDGE,
 185     .class_init    = pxb_host_class_init,
 186 };
 187
 188 static void pxb_cxl_realize(DeviceState *dev, Error **errp)
 189 {
 190     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 191     CXLHost *cxl = PXB_CXL_HOST(dev);
 192     CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
 193     struct MemoryRegion *mr = &cxl_cstate->crb.component_registers;
 194
 195     cxl_component_register_block_init(OBJECT(dev), cxl_cstate,
 196                                       TYPE_PXB_CXL_HOST);
 197     sysbus_init_mmio(sbd, mr);
 198 }
 199
 200 /*
 201  * Host bridge realization has no means of knowning state associated
 202  * with a particular machine. As such, it is nececssary to delay
 203  * final setup of the host bridge register space until later in the
 204  * machine bring up.
 205  */
 206 void pxb_cxl_hook_up_registers(CXLState *cxl_state, PCIBus *bus, Error **errp)
 207 {
 208     PXBDev *pxb =  PXB_CXL_DEV(pci_bridge_get_device(bus));
 209     CXLHost *cxl = pxb->cxl.cxl_host_bridge;
 210     CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
 211     struct MemoryRegion *mr = &cxl_cstate->crb.component_registers;
 212     hwaddr offset;
 213
 214     offset = memory_region_size(mr) * cxl_state->next_mr_idx;
 215     if (offset > memory_region_size(&cxl_state->host_mr)) {
 216         error_setg(errp, "Insufficient space for pxb cxl host register space");
 217         return;
 218     }
 219
 220     memory_region_add_subregion(&cxl_state->host_mr, offset, mr);
 221     cxl_state->next_mr_idx++;
 222 }
 223
 224 static void pxb_cxl_host_class_init(ObjectClass *class, void *data)
 225 {
 226     DeviceClass *dc = DEVICE_CLASS(class);
 227     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(class);
 228
 229     hc->root_bus_path = pxb_host_root_bus_path;
 230     dc->fw_name = "cxl";
 231     dc->realize = pxb_cxl_realize;
 232     /* Reason: Internal part of the pxb/pxb-pcie device, not usable by itself */
 233     dc->user_creatable = false;
 234 }
 235
 236 /*
 237  * This is a device to handle the MMIO for a CXL host bridge. It does nothing
 238  * else.
 239  */
 240 static const TypeInfo cxl_host_info = {
 241     .name          = TYPE_PXB_CXL_HOST,
 242     .parent        = TYPE_PCI_HOST_BRIDGE,
 243     .instance_size = sizeof(CXLHost),
 244     .class_init    = pxb_cxl_host_class_init,
 245 };
 246
 247 /*
 248  * Registers the PXB bus as a child of pci host root bus.
 249  */
 250 static void pxb_register_bus(PCIDevice *dev, PCIBus *pxb_bus, Error **errp)
 251 {
 252     PCIBus *bus = pci_get_bus(dev);
 253     int pxb_bus_num = pci_bus_num(pxb_bus);
 254
 255     if (bus->parent_dev) {
 256         error_setg(errp, "PXB devices can be attached only to root bus");
 257         return;
 258     }
 259
 260     QLIST_FOREACH(bus, &bus->child, sibling) {
 261         if (pci_bus_num(bus) == pxb_bus_num) {
 262             error_setg(errp, "Bus %d is already in use", pxb_bus_num);
 263             return;
 264         }
 265     }
 266     QLIST_INSERT_HEAD(&pci_get_bus(dev)->child, pxb_bus, sibling);
 267 }
 268
 269 static int pxb_map_irq_fn(PCIDevice *pci_dev, int pin)
 270 {
 271     PCIDevice *pxb = pci_get_bus(pci_dev)->parent_dev;
 272
 273     /*
 274      * First carry out normal swizzle to handle
 275      * multple root ports on a pxb instance.
 276      */
 277     pin = pci_swizzle_map_irq_fn(pci_dev, pin);
 278
 279     /*
 280      * The bios does not index the pxb slot number when
 281      * it computes the IRQ because it resides on bus 0
 282      * and not on the current bus.
 283      * However QEMU routes the irq through bus 0 and adds
 284      * the pxb slot to the IRQ computation of the PXB
 285      * device.
 286      *
 287      * Synchronize between bios and QEMU by canceling
 288      * pxb's effect.
 289      */
 290     return pin - PCI_SLOT(pxb->devfn);
 291 }
 292
 293 static void pxb_dev_reset(DeviceState *dev)
 294 {
 295     CXLHost *cxl = PXB_CXL_DEV(dev)->cxl.cxl_host_bridge;
 296     CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
 297     uint32_t *reg_state = cxl_cstate->crb.cache_mem_registers;
 298     uint32_t *write_msk = cxl_cstate->crb.cache_mem_regs_write_mask;
 299
 300     cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_PORT);
 301     ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 8);
 302 }
 303
 304 static gint pxb_compare(gconstpointer a, gconstpointer b)
 305 {
 306     const PXBDev *pxb_a = a, *pxb_b = b;
 307
 308     return pxb_a->bus_nr < pxb_b->bus_nr ? -1 :
 309            pxb_a->bus_nr > pxb_b->bus_nr ?  1 :
 310            0;
 311 }
 312
 313 static void pxb_dev_realize_common(PCIDevice *dev, enum BusType type,
 314                                    Error **errp)
 315 {
 316     PXBDev *pxb = convert_to_pxb(dev);
 317     DeviceState *ds, *bds = NULL;
 318     PCIBus *bus;
 319     const char *dev_name = NULL;
 320     Error *local_err = NULL;
 321     MachineState *ms = MACHINE(qdev_get_machine());
 322
 323     if (ms->numa_state == NULL) {
 324         error_setg(errp, "NUMA is not supported by this machine-type");
 325         return;
 326     }
 327
 328     if (pxb->numa_node != NUMA_NODE_UNASSIGNED &&
 329         pxb->numa_node >= ms->numa_state->num_nodes) {
 330         error_setg(errp, "Illegal numa node %d", pxb->numa_node);
 331         return;
 332     }
 333
 334     if (dev->qdev.id && *dev->qdev.id) {
 335         dev_name = dev->qdev.id;
 336     }
 337
 338     ds = qdev_new(type == CXL ? TYPE_PXB_CXL_HOST : TYPE_PXB_HOST);
 339     if (type == PCIE) {
 340         bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCIE_BUS);
 341     } else if (type == CXL) {
 342         bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_CXL_BUS);
 343         bus->flags |= PCI_BUS_CXL;
 344         PXB_CXL_DEV(dev)->cxl.cxl_host_bridge = PXB_CXL_HOST(ds);
 345     } else {
 346         bus = pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_PXB_BUS);
 347         bds = qdev_new("pci-bridge");
 348         bds->id = g_strdup(dev_name);
 349         qdev_prop_set_uint8(bds, PCI_BRIDGE_DEV_PROP_CHASSIS_NR, pxb->bus_nr);
 350         qdev_prop_set_bit(bds, PCI_BRIDGE_DEV_PROP_SHPC, false);
 351     }
 352
 353     bus->parent_dev = dev;
 354     bus->address_space_mem = pci_get_bus(dev)->address_space_mem;
 355     bus->address_space_io = pci_get_bus(dev)->address_space_io;
 356     bus->map_irq = pxb_map_irq_fn;
 357
 358     PCI_HOST_BRIDGE(ds)->bus = bus;
 359     PCI_HOST_BRIDGE(ds)->bypass_iommu = pxb->bypass_iommu;
 360
 361     pxb_register_bus(dev, bus, &local_err);
 362     if (local_err) {
 363         error_propagate(errp, local_err);
 364         goto err_register_bus;
 365     }
 366
 367     sysbus_realize_and_unref(SYS_BUS_DEVICE(ds), &error_fatal);
 368     if (bds) {
 369         qdev_realize_and_unref(bds, &bus->qbus, &error_fatal);
 370     }
 371
 372     pci_word_test_and_set_mask(dev->config + PCI_STATUS,
 373                                PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
 374     pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_HOST);
 375
 376     pxb_dev_list = g_list_insert_sorted(pxb_dev_list, pxb, pxb_compare);
 377     return;
 378
 379 err_register_bus:
 380     object_unref(OBJECT(bds));
 381     object_unparent(OBJECT(bus));
 382     object_unref(OBJECT(ds));
 383 }
 384
 385 static void pxb_dev_realize(PCIDevice *dev, Error **errp)
 386 {
 387     if (pci_bus_is_express(pci_get_bus(dev))) {
 388         error_setg(errp, "pxb devices cannot reside on a PCIe bus");
 389         return;
 390     }
 391
 392     pxb_dev_realize_common(dev, PCI, errp);
 393 }
 394
 395 static void pxb_dev_exitfn(PCIDevice *pci_dev)
 396 {
 397     PXBDev *pxb = convert_to_pxb(pci_dev);
 398
 399     pxb_dev_list = g_list_remove(pxb_dev_list, pxb);
 400 }
 401
 402 static Property pxb_dev_properties[] = {
 403     /* Note: 0 is not a legal PXB bus number. */
 404     DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0),
 405     DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNED),
 406     DEFINE_PROP_BOOL("bypass_iommu", PXBDev, bypass_iommu, false),
 407     DEFINE_PROP_END_OF_LIST(),
 408 };
 409
 410 static void pxb_dev_class_init(ObjectClass *klass, void *data)
 411 {
 412     DeviceClass *dc = DEVICE_CLASS(klass);
 413     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 414
 415     k->realize = pxb_dev_realize;
 416     k->exit = pxb_dev_exitfn;
 417     k->vendor_id = PCI_VENDOR_ID_REDHAT;
 418     k->device_id = PCI_DEVICE_ID_REDHAT_PXB;
 419     k->class_id = PCI_CLASS_BRIDGE_HOST;
 420
 421     dc->desc = "PCI Expander Bridge";
 422     device_class_set_props(dc, pxb_dev_properties);
 423     dc->hotpluggable = false;
 424     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 425 }
 426
 427 static const TypeInfo pxb_dev_info = {
 428     .name          = TYPE_PXB_DEVICE,
 429     .parent        = TYPE_PCI_DEVICE,
 430     .instance_size = sizeof(PXBDev),
 431     .class_init    = pxb_dev_class_init,
 432     .interfaces = (InterfaceInfo[]) {
 433         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 434         { },
 435     },
 436 };
 437
 438 static void pxb_pcie_dev_realize(PCIDevice *dev, Error **errp)
 439 {
 440     if (!pci_bus_is_express(pci_get_bus(dev))) {
 441         error_setg(errp, "pxb-pcie devices cannot reside on a PCI bus");
 442         return;
 443     }
 444
 445     pxb_dev_realize_common(dev, PCIE, errp);
 446 }
 447
 448 static void pxb_pcie_dev_class_init(ObjectClass *klass, void *data)
 449 {
 450     DeviceClass *dc = DEVICE_CLASS(klass);
 451     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 452
 453     k->realize = pxb_pcie_dev_realize;
 454     k->exit = pxb_dev_exitfn;
 455     k->vendor_id = PCI_VENDOR_ID_REDHAT;
 456     k->device_id = PCI_DEVICE_ID_REDHAT_PXB_PCIE;
 457     k->class_id = PCI_CLASS_BRIDGE_HOST;
 458
 459     dc->desc = "PCI Express Expander Bridge";
 460     device_class_set_props(dc, pxb_dev_properties);
 461     dc->hotpluggable = false;
 462     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 463 }
 464
 465 static const TypeInfo pxb_pcie_dev_info = {
 466     .name          = TYPE_PXB_PCIE_DEVICE,
 467     .parent        = TYPE_PCI_DEVICE,
 468     .instance_size = sizeof(PXBDev),
 469     .class_init    = pxb_pcie_dev_class_init,
 470     .interfaces = (InterfaceInfo[]) {
 471         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 472         { },
 473     },
 474 };
 475
 476 static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp)
 477 {
 478     /* A CXL PXB's parent bus is still PCIe */
 479     if (!pci_bus_is_express(pci_get_bus(dev))) {
 480         error_setg(errp, "pxb-cxl devices cannot reside on a PCI bus");
 481         return;
 482     }
 483
 484     pxb_dev_realize_common(dev, CXL, errp);
 485     pxb_dev_reset(DEVICE(dev));
 486 }
 487
 488 static void pxb_cxl_dev_class_init(ObjectClass *klass, void *data)
 489 {
 490     DeviceClass *dc   = DEVICE_CLASS(klass);
 491     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 492
 493     k->realize             = pxb_cxl_dev_realize;
 494     k->exit                = pxb_dev_exitfn;
 495     /*
 496      * XXX: These types of bridges don't actually show up in the hierarchy so
 497      * vendor, device, class, etc. ids are intentionally left out.
 498      */
 499
 500     dc->desc = "CXL Host Bridge";
 501     device_class_set_props(dc, pxb_dev_properties);
 502     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 503
 504     /* Host bridges aren't hotpluggable. FIXME: spec reference */
 505     dc->hotpluggable = false;
 506     dc->reset = pxb_dev_reset;
 507 }
 508
 509 static const TypeInfo pxb_cxl_dev_info = {
 510     .name          = TYPE_PXB_CXL_DEVICE,
 511     .parent        = TYPE_PCI_DEVICE,
 512     .instance_size = sizeof(PXBDev),
 513     .class_init    = pxb_cxl_dev_class_init,
 514     .interfaces =
 515         (InterfaceInfo[]){
 516             { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 517             {},
 518         },
 519 };
 520
 521 static void pxb_register_types(void)
 522 {
 523     type_register_static(&pxb_bus_info);
 524     type_register_static(&pxb_pcie_bus_info);
 525     type_register_static(&pxb_cxl_bus_info);
 526     type_register_static(&pxb_host_info);
 527     type_register_static(&cxl_host_info);
 528     type_register_static(&pxb_dev_info);
 529     type_register_static(&pxb_pcie_dev_info);
 530     type_register_static(&pxb_cxl_dev_info);
 531 }
 532
 533 type_init(pxb_register_types)