include/hw/char/escc.h

   1 #ifndef HW_ESCC_H
   2 #define HW_ESCC_H
   3
   4 #include "chardev/char-fe.h"
   5 #include "chardev/char-serial.h"
   6 #include "hw/sysbus.h"
   7 #include "ui/input.h"
   8 #include "qom/object.h"
   9
  10 /* escc.c */
  11 #define TYPE_ESCC "escc"
  12 #define ESCC_SIZE 4
  13
  14 typedef struct ESCCState ESCCState;
  15 DECLARE_INSTANCE_CHECKER(ESCCState, ESCC,
  16                          TYPE_ESCC)
  17
  18 typedef enum {
  19     escc_chn_a, escc_chn_b,
  20 } ESCCChnID;
  21
  22 typedef enum {
  23     escc_serial, escc_kbd, escc_mouse,
  24 } ESCCChnType;
  25
  26 #define ESCC_SERIO_QUEUE_SIZE 256
  27
  28 typedef struct {
  29     uint8_t data[ESCC_SERIO_QUEUE_SIZE];
  30     int rptr, wptr, count;
  31 } ESCCSERIOQueue;
  32
  33 #define ESCC_SERIAL_REGS 16
  34 typedef struct ESCCChannelState {
  35     qemu_irq irq;
  36     uint32_t rxint, txint, rxint_under_svc, txint_under_svc;
  37     struct ESCCChannelState *otherchn;
  38     uint32_t reg;
  39     uint8_t wregs[ESCC_SERIAL_REGS], rregs[ESCC_SERIAL_REGS];
  40     ESCCSERIOQueue queue;
  41     CharBackend chr;
  42     int e0_mode, led_mode, caps_lock_mode, num_lock_mode;
  43     int disabled;
  44     int clock;
  45     uint32_t vmstate_dummy;
  46     ESCCChnID chn; /* this channel, A (base+4) or B (base+0) */
  47     ESCCChnType type;
  48     uint8_t rx, tx;
  49     QemuInputHandlerState *hs;
  50 } ESCCChannelState;
  51
  52 struct ESCCState {
  53     SysBusDevice parent_obj;
  54
  55     struct ESCCChannelState chn[2];
  56     uint32_t it_shift;
  57     bool bit_swap;
  58     MemoryRegion mmio;
  59     uint32_t disabled;
  60     uint32_t frequency;
  61 };
  62
  63 #endif