2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
4 * i.MX31 SOC emulation.
6 * Based on hw/arm/fsl-imx31.c
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "hw/arm/fsl-imx31.h"
25 #include "sysemu/sysemu.h"
26 #include "exec/address-spaces.h"
27 #include "hw/qdev-properties.h"
28 #include "chardev/char.h"
29 #include "target/arm/cpu-qom.h"
31 static void fsl_imx31_init(Object
*obj
)
33 FslIMX31State
*s
= FSL_IMX31(obj
);
36 object_initialize_child(obj
, "cpu", &s
->cpu
, ARM_CPU_TYPE_NAME("arm1136"));
38 object_initialize_child(obj
, "avic", &s
->avic
, TYPE_IMX_AVIC
);
40 object_initialize_child(obj
, "ccm", &s
->ccm
, TYPE_IMX31_CCM
);
42 for (i
= 0; i
< FSL_IMX31_NUM_UARTS
; i
++) {
43 object_initialize_child(obj
, "uart[*]", &s
->uart
[i
], TYPE_IMX_SERIAL
);
46 object_initialize_child(obj
, "gpt", &s
->gpt
, TYPE_IMX31_GPT
);
48 for (i
= 0; i
< FSL_IMX31_NUM_EPITS
; i
++) {
49 object_initialize_child(obj
, "epit[*]", &s
->epit
[i
], TYPE_IMX_EPIT
);
52 for (i
= 0; i
< FSL_IMX31_NUM_I2CS
; i
++) {
53 object_initialize_child(obj
, "i2c[*]", &s
->i2c
[i
], TYPE_IMX_I2C
);
56 for (i
= 0; i
< FSL_IMX31_NUM_GPIOS
; i
++) {
57 object_initialize_child(obj
, "gpio[*]", &s
->gpio
[i
], TYPE_IMX_GPIO
);
60 object_initialize_child(obj
, "wdt", &s
->wdt
, TYPE_IMX2_WDT
);
63 static void fsl_imx31_realize(DeviceState
*dev
, Error
**errp
)
65 FslIMX31State
*s
= FSL_IMX31(dev
);
68 if (!qdev_realize(DEVICE(&s
->cpu
), NULL
, errp
)) {
72 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->avic
), errp
)) {
75 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->avic
), 0, FSL_IMX31_AVIC_ADDR
);
76 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->avic
), 0,
77 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_IRQ
));
78 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->avic
), 1,
79 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_FIQ
));
81 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->ccm
), errp
)) {
84 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ccm
), 0, FSL_IMX31_CCM_ADDR
);
86 /* Initialize all UARTS */
87 for (i
= 0; i
< FSL_IMX31_NUM_UARTS
; i
++) {
91 } serial_table
[FSL_IMX31_NUM_UARTS
] = {
92 { FSL_IMX31_UART1_ADDR
, FSL_IMX31_UART1_IRQ
},
93 { FSL_IMX31_UART2_ADDR
, FSL_IMX31_UART2_IRQ
},
96 qdev_prop_set_chr(DEVICE(&s
->uart
[i
]), "chardev", serial_hd(i
));
98 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->uart
[i
]), errp
)) {
102 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, serial_table
[i
].addr
);
103 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
104 qdev_get_gpio_in(DEVICE(&s
->avic
),
105 serial_table
[i
].irq
));
108 s
->gpt
.ccm
= IMX_CCM(&s
->ccm
);
110 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->gpt
), errp
)) {
114 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpt
), 0, FSL_IMX31_GPT_ADDR
);
115 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpt
), 0,
116 qdev_get_gpio_in(DEVICE(&s
->avic
), FSL_IMX31_GPT_IRQ
));
118 /* Initialize all EPIT timers */
119 for (i
= 0; i
< FSL_IMX31_NUM_EPITS
; i
++) {
120 static const struct {
123 } epit_table
[FSL_IMX31_NUM_EPITS
] = {
124 { FSL_IMX31_EPIT1_ADDR
, FSL_IMX31_EPIT1_IRQ
},
125 { FSL_IMX31_EPIT2_ADDR
, FSL_IMX31_EPIT2_IRQ
},
128 s
->epit
[i
].ccm
= IMX_CCM(&s
->ccm
);
130 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->epit
[i
]), errp
)) {
134 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->epit
[i
]), 0, epit_table
[i
].addr
);
135 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->epit
[i
]), 0,
136 qdev_get_gpio_in(DEVICE(&s
->avic
),
140 /* Initialize all I2C */
141 for (i
= 0; i
< FSL_IMX31_NUM_I2CS
; i
++) {
142 static const struct {
145 } i2c_table
[FSL_IMX31_NUM_I2CS
] = {
146 { FSL_IMX31_I2C1_ADDR
, FSL_IMX31_I2C1_IRQ
},
147 { FSL_IMX31_I2C2_ADDR
, FSL_IMX31_I2C2_IRQ
},
148 { FSL_IMX31_I2C3_ADDR
, FSL_IMX31_I2C3_IRQ
}
151 /* Initialize the I2C */
152 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->i2c
[i
]), errp
)) {
156 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0, i2c_table
[i
].addr
);
157 /* Connect I2C IRQ to PIC */
158 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0,
159 qdev_get_gpio_in(DEVICE(&s
->avic
),
163 /* Initialize all GPIOs */
164 for (i
= 0; i
< FSL_IMX31_NUM_GPIOS
; i
++) {
165 static const struct {
168 } gpio_table
[FSL_IMX31_NUM_GPIOS
] = {
169 { FSL_IMX31_GPIO1_ADDR
, FSL_IMX31_GPIO1_IRQ
},
170 { FSL_IMX31_GPIO2_ADDR
, FSL_IMX31_GPIO2_IRQ
},
171 { FSL_IMX31_GPIO3_ADDR
, FSL_IMX31_GPIO3_IRQ
}
174 object_property_set_bool(OBJECT(&s
->gpio
[i
]), "has-edge-sel", false,
176 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->gpio
[i
]), errp
)) {
179 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0, gpio_table
[i
].addr
);
180 /* Connect GPIO IRQ to PIC */
181 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0,
182 qdev_get_gpio_in(DEVICE(&s
->avic
),
187 sysbus_realize(SYS_BUS_DEVICE(&s
->wdt
), &error_abort
);
188 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->wdt
), 0, FSL_IMX31_WDT_ADDR
);
190 /* On a real system, the first 16k is a `secure boot rom' */
191 if (!memory_region_init_rom(&s
->secure_rom
, OBJECT(dev
), "imx31.secure_rom",
192 FSL_IMX31_SECURE_ROM_SIZE
, errp
)) {
195 memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR
,
198 /* There is also a 16k ROM */
199 if (!memory_region_init_rom(&s
->rom
, OBJECT(dev
), "imx31.rom",
200 FSL_IMX31_ROM_SIZE
, errp
)) {
203 memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR
,
206 /* initialize internal RAM (16 KB) */
207 if (!memory_region_init_ram(&s
->iram
, NULL
, "imx31.iram",
208 FSL_IMX31_IRAM_SIZE
, errp
)) {
211 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR
,
214 /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
215 memory_region_init_alias(&s
->iram_alias
, OBJECT(dev
), "imx31.iram_alias",
216 &s
->iram
, 0, FSL_IMX31_IRAM_ALIAS_SIZE
);
217 memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR
,
221 static void fsl_imx31_class_init(ObjectClass
*oc
, void *data
)
223 DeviceClass
*dc
= DEVICE_CLASS(oc
);
225 dc
->realize
= fsl_imx31_realize
;
226 dc
->desc
= "i.MX31 SOC";
228 * Reason: uses serial_hds in realize and the kzm board does not
229 * support multiple CPUs
231 dc
->user_creatable
= false;
234 static const TypeInfo fsl_imx31_type_info
= {
235 .name
= TYPE_FSL_IMX31
,
236 .parent
= TYPE_DEVICE
,
237 .instance_size
= sizeof(FslIMX31State
),
238 .instance_init
= fsl_imx31_init
,
239 .class_init
= fsl_imx31_class_init
,
242 static void fsl_imx31_register_types(void)
244 type_register_static(&fsl_imx31_type_info
);
247 type_init(fsl_imx31_register_types
)