3 # Copyright (c) 2019 Linaro, Ltd
5 # This library is free software; you can redistribute it and/or
6 # modify it under the terms of the GNU Lesser General Public
7 # License as published by the Free Software Foundation; either
8 # version 2 of the License, or (at your option) any later version.
10 # This library is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 # Lesser General Public License for more details.
15 # You should have received a copy of the GNU Lesser General Public
16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 # This file is processed by scripts/decodetree.py
23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
25 &s_rri_rot !extern s rn rd imm rot
26 &s_rrrr !extern s rd rn rm ra
27 &rrr_rot !extern rd rn rm rot
32 &ldst_rr !extern p w u rn rt rm shimm shtype
33 &ldst_ri !extern p w u rn rt imm
34 &ldst_block !extern rn i b u w list
36 &cps !extern mode imod M A I F
39 # Set S if the instruction is outside of an IT block.
40 %s !function=t16_setflags
42 # Data-processing (two low registers)
46 @lll_noshr ...... .... rm:3 rd:3 \
47 &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
48 @xll_noshr ...... .... rm:3 rn:3 \
49 &s_rrr_shi s=1 rd=0 shim=0 shty=0
50 @lxl_shr ...... .... rs:3 rd:3 \
51 &s_rrr_shr %s rm=%reg_0 rn=0
53 AND_rrri 010000 0000 ... ... @lll_noshr
54 EOR_rrri 010000 0001 ... ... @lll_noshr
55 MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
56 MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
57 MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
58 ADC_rrri 010000 0101 ... ... @lll_noshr
59 SBC_rrri 010000 0110 ... ... @lll_noshr
60 MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
61 TST_xrri 010000 1000 ... ... @xll_noshr
62 RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0
63 CMP_xrri 010000 1010 ... ... @xll_noshr
64 CMN_xrri 010000 1011 ... ... @xll_noshr
65 ORR_rrri 010000 1100 ... ... @lll_noshr
66 MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0
67 BIC_rrri 010000 1110 ... ... @lll_noshr
68 MVN_rxri 010000 1111 ... ... @lll_noshr
70 # Load/store (register offset)
72 @ldst_rr ....... rm:3 rn:3 rt:3 \
73 &ldst_rr p=1 w=0 u=1 shimm=0 shtype=0
75 STR_rr 0101 000 ... ... ... @ldst_rr
76 STRH_rr 0101 001 ... ... ... @ldst_rr
77 STRB_rr 0101 010 ... ... ... @ldst_rr
78 LDRSB_rr 0101 011 ... ... ... @ldst_rr
79 LDR_rr 0101 100 ... ... ... @ldst_rr
80 LDRH_rr 0101 101 ... ... ... @ldst_rr
81 LDRB_rr 0101 110 ... ... ... @ldst_rr
82 LDRSH_rr 0101 111 ... ... ... @ldst_rr
84 # Load/store word/byte (immediate offset)
86 %imm5_6x4 6:5 !function=times_4
88 @ldst_ri_1 ..... imm:5 rn:3 rt:3 \
90 @ldst_ri_4 ..... ..... rn:3 rt:3 \
91 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4
93 STR_ri 01100 ..... ... ... @ldst_ri_4
94 LDR_ri 01101 ..... ... ... @ldst_ri_4
95 STRB_ri 01110 ..... ... ... @ldst_ri_1
96 LDRB_ri 01111 ..... ... ... @ldst_ri_1
98 # Load/store halfword (immediate offset)
100 %imm5_6x2 6:5 !function=times_2
101 @ldst_ri_2 ..... ..... rn:3 rt:3 \
102 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2
104 STRH_ri 10000 ..... ... ... @ldst_ri_2
105 LDRH_ri 10001 ..... ... ... @ldst_ri_2
107 # Load/store (SP-relative)
109 %imm8_0x4 0:8 !function=times_4
110 @ldst_spec_i ..... rt:3 ........ \
111 &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4
113 STR_ri 10010 ... ........ @ldst_spec_i rn=13
114 LDR_ri 10011 ... ........ @ldst_spec_i rn=13
116 # Add PC/SP (immediate)
118 ADR 10100 rd:3 ........ imm=%imm8_0x4
119 ADD_rri 10101 rd:3 ........ \
120 &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP
122 # Load/store multiple
124 @ldstm ..... rn:3 list:8 &ldst_block i=1 b=0 u=0 w=1
126 STM 11000 ... ........ @ldstm
127 LDM_t16 11001 ... ........ @ldstm
129 # Add/subtract (three low registers)
131 @addsub_3 ....... rm:3 rn:3 rd:3 \
132 &s_rrr_shi %s shim=0 shty=0
134 ADD_rrri 0001100 ... ... ... @addsub_3
135 SUB_rrri 0001101 ... ... ... @addsub_3
137 # Add/subtract (two low registers and immediate)
139 @addsub_2i ....... imm:3 rn:3 rd:3 \
142 ADD_rri 0001 110 ... ... ... @addsub_2i
143 SUB_rri 0001 111 ... ... ... @addsub_2i
145 # Add, subtract, compare, move (one low register and immediate)
148 @arith_1i ..... rd:3 imm:8 \
149 &s_rri_rot rot=0 rn=%reg_8
151 MOV_rxi 00100 ... ........ @arith_1i %s
152 CMP_xri 00101 ... ........ @arith_1i s=1
153 ADD_rri 00110 ... ........ @arith_1i %s
154 SUB_rri 00111 ... ........ @arith_1i %s
156 # Add, compare, move (two high registers)
159 @addsub_2h .... .... . rm:4 ... \
160 &s_rrr_shi rd=%reg_0_7 rn=%reg_0_7 shim=0 shty=0
162 ADD_rrri 0100 0100 . .... ... @addsub_2h s=0
163 CMP_xrri 0100 0101 . .... ... @addsub_2h s=1
164 MOV_rxri 0100 0110 . .... ... @addsub_2h s=0
166 # Adjust SP (immediate)
168 %imm7_0x4 0:7 !function=times_4
169 @addsub_sp_i .... .... . ....... \
170 &s_rri_rot s=0 rd=13 rn=13 rot=0 imm=%imm7_0x4
172 ADD_rri 1011 0000 0 ....... @addsub_sp_i
173 SUB_rri 1011 0000 1 ....... @addsub_sp_i
175 # Branch and exchange
177 @branchr .... .... . rm:4 ... &r
179 BX 0100 0111 0 .... 000 @branchr
180 BLX_r 0100 0111 1 .... 000 @branchr
181 BXNS 0100 0111 0 .... 100 @branchr
182 BLXNS 0100 0111 1 .... 100 @branchr
186 @extend .... .... .. rm:3 rd:3 &rrr_rot rn=15 rot=0
188 SXTAH 1011 0010 00 ... ... @extend
189 SXTAB 1011 0010 01 ... ... @extend
190 UXTAH 1011 0010 10 ... ... @extend
191 UXTAB 1011 0010 11 ... ... @extend
193 # Change processor state
195 %imod 4:1 !function=plus_2
197 SETEND 1011 0110 010 1 E:1 000 &setend
199 CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod
200 CPS_v7m 1011 0110 011 im:1 00 I:1 F:1
205 @rdm .... .... .. rm:3 rd:3 &rr
207 REV 1011 1010 00 ... ... @rdm
208 REV16 1011 1010 01 ... ... @rdm
209 REVSH 1011 1010 11 ... ... @rdm
215 YIELD 1011 1111 0001 0000
216 WFE 1011 1111 0010 0000
217 WFI 1011 1111 0011 0000
219 # TODO: Implement SEV, SEVL; may help SMP performance.
220 # SEV 1011 1111 0100 0000
221 # SEVL 1011 1111 0101 0000
223 # The canonical nop has the second nibble as 0000, but the whole of the
224 # rest of the space is a reserved hint, behaves as nop.
225 NOP 1011 1111 ---- 0000
227 IT 1011 1111 cond_mask:8
230 # Miscellaneous 16-bit instructions
232 %imm6_9_3 9:1 3:5 !function=times_2
234 HLT 1011 1010 10 imm:6 &i
235 BKPT 1011 1110 imm:8 &i
236 CBZ 1011 nz:1 0.1 ..... rn:3 imm=%imm6_9_3
240 %push_list 0:9 !function=t16_push_list
241 %pop_list 0:9 !function=t16_pop_list
243 STM 1011 010 ......... \
244 &ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list
245 LDM_t16 1011 110 ......... \
246 &ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list
248 # Conditional branches, Supervisor call
250 %imm8_0x2 0:s8 !function=times_2
253 UDF 1101 1110 ---- ----
254 SVC 1101 1111 imm:8 &i
255 B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2