hw/sd/aspeed_sdhci.c

   1 /*
   2  * Aspeed SD Host Controller
   3  * Eddie James <eajames@linux.ibm.com>
   4  *
   5  * Copyright (C) 2019 IBM Corp
   6  * SPDX-License-Identifer: GPL-2.0-or-later
   7  */
   8
   9 #include "qemu/osdep.h"
  10 #include "qemu/log.h"
  11 #include "qemu/error-report.h"
  12 #include "hw/sd/aspeed_sdhci.h"
  13 #include "qapi/error.h"
  14 #include "hw/irq.h"
  15 #include "migration/vmstate.h"
  16
  17 #define ASPEED_SDHCI_INFO            0x00
  18 #define  ASPEED_SDHCI_INFO_RESET     0x00030000
  19 #define ASPEED_SDHCI_DEBOUNCE        0x04
  20 #define  ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005
  21 #define ASPEED_SDHCI_BUS             0x08
  22 #define ASPEED_SDHCI_SDIO_140        0x10
  23 #define ASPEED_SDHCI_SDIO_148        0x18
  24 #define ASPEED_SDHCI_SDIO_240        0x20
  25 #define ASPEED_SDHCI_SDIO_248        0x28
  26 #define ASPEED_SDHCI_WP_POL          0xec
  27 #define ASPEED_SDHCI_CARD_DET        0xf0
  28 #define ASPEED_SDHCI_IRQ_STAT        0xfc
  29
  30 #define TO_REG(addr) ((addr) / sizeof(uint32_t))
  31
  32 static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
  33 {
  34     uint32_t val = 0;
  35     AspeedSDHCIState *sdhci = opaque;
  36
  37     switch (addr) {
  38     case ASPEED_SDHCI_SDIO_140:
  39         val = (uint32_t)sdhci->slots[0].capareg;
  40         break;
  41     case ASPEED_SDHCI_SDIO_148:
  42         val = (uint32_t)sdhci->slots[0].maxcurr;
  43         break;
  44     case ASPEED_SDHCI_SDIO_240:
  45         val = (uint32_t)sdhci->slots[1].capareg;
  46         break;
  47     case ASPEED_SDHCI_SDIO_248:
  48         val = (uint32_t)sdhci->slots[1].maxcurr;
  49         break;
  50     default:
  51         if (addr < ASPEED_SDHCI_REG_SIZE) {
  52             val = sdhci->regs[TO_REG(addr)];
  53         } else {
  54             qemu_log_mask(LOG_GUEST_ERROR,
  55                           "%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n",
  56                           __func__, addr);
  57         }
  58     }
  59
  60     return (uint64_t)val;
  61 }
  62
  63 static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
  64                                unsigned int size)
  65 {
  66     AspeedSDHCIState *sdhci = opaque;
  67
  68     switch (addr) {
  69     case ASPEED_SDHCI_SDIO_140:
  70         sdhci->slots[0].capareg = (uint64_t)(uint32_t)val;
  71         break;
  72     case ASPEED_SDHCI_SDIO_148:
  73         sdhci->slots[0].maxcurr = (uint64_t)(uint32_t)val;
  74         break;
  75     case ASPEED_SDHCI_SDIO_240:
  76         sdhci->slots[1].capareg = (uint64_t)(uint32_t)val;
  77         break;
  78     case ASPEED_SDHCI_SDIO_248:
  79         sdhci->slots[1].maxcurr = (uint64_t)(uint32_t)val;
  80         break;
  81     default:
  82         if (addr < ASPEED_SDHCI_REG_SIZE) {
  83             sdhci->regs[TO_REG(addr)] = (uint32_t)val;
  84         } else {
  85             qemu_log_mask(LOG_GUEST_ERROR,
  86                           "%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n",
  87                           __func__, addr);
  88         }
  89     }
  90 }
  91
  92 static const MemoryRegionOps aspeed_sdhci_ops = {
  93     .read = aspeed_sdhci_read,
  94     .write = aspeed_sdhci_write,
  95     .endianness = DEVICE_NATIVE_ENDIAN,
  96     .valid.min_access_size = 4,
  97     .valid.max_access_size = 4,
  98 };
  99
 100 static void aspeed_sdhci_set_irq(void *opaque, int n, int level)
 101 {
 102     AspeedSDHCIState *sdhci = opaque;
 103
 104     if (level) {
 105         sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] |= BIT(n);
 106
 107         qemu_irq_raise(sdhci->irq);
 108     } else {
 109         sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] &= ~BIT(n);
 110
 111         qemu_irq_lower(sdhci->irq);
 112     }
 113 }
 114
 115 static void aspeed_sdhci_realize(DeviceState *dev, Error **errp)
 116 {
 117     Error *err = NULL;
 118     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 119     AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);
 120
 121     /* Create input irqs for the slots */
 122     qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq,
 123                                         sdhci, NULL, ASPEED_SDHCI_NUM_SLOTS);
 124
 125     sysbus_init_irq(sbd, &sdhci->irq);
 126     memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops,
 127                           sdhci, TYPE_ASPEED_SDHCI, 0x1000);
 128     sysbus_init_mmio(sbd, &sdhci->iomem);
 129
 130     for (int i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
 131         Object *sdhci_slot = OBJECT(&sdhci->slots[i]);
 132         SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]);
 133
 134         object_property_set_int(sdhci_slot, 2, "sd-spec-version", &err);
 135         if (err) {
 136             error_propagate(errp, err);
 137             return;
 138         }
 139
 140         object_property_set_uint(sdhci_slot, ASPEED_SDHCI_CAPABILITIES,
 141                                  "capareg", &err);
 142         if (err) {
 143             error_propagate(errp, err);
 144             return;
 145         }
 146
 147         object_property_set_bool(sdhci_slot, true, "realized", &err);
 148         if (err) {
 149             error_propagate(errp, err);
 150             return;
 151         }
 152
 153         sysbus_connect_irq(sbd_slot, 0, qdev_get_gpio_in(DEVICE(sbd), i));
 154         memory_region_add_subregion(&sdhci->iomem, (i + 1) * 0x100,
 155                                     &sdhci->slots[i].iomem);
 156     }
 157 }
 158
 159 static void aspeed_sdhci_reset(DeviceState *dev)
 160 {
 161     AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);
 162
 163     memset(sdhci->regs, 0, ASPEED_SDHCI_REG_SIZE);
 164     sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_RESET;
 165     sdhci->regs[TO_REG(ASPEED_SDHCI_DEBOUNCE)] = ASPEED_SDHCI_DEBOUNCE_RESET;
 166 }
 167
 168 static const VMStateDescription vmstate_aspeed_sdhci = {
 169     .name = TYPE_ASPEED_SDHCI,
 170     .version_id = 1,
 171     .fields = (VMStateField[]) {
 172         VMSTATE_UINT32_ARRAY(regs, AspeedSDHCIState, ASPEED_SDHCI_NUM_REGS),
 173         VMSTATE_END_OF_LIST(),
 174     },
 175 };
 176
 177 static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
 178 {
 179     DeviceClass *dc = DEVICE_CLASS(classp);
 180
 181     dc->realize = aspeed_sdhci_realize;
 182     dc->reset = aspeed_sdhci_reset;
 183     dc->vmsd = &vmstate_aspeed_sdhci;
 184 }
 185
 186 static TypeInfo aspeed_sdhci_info = {
 187     .name          = TYPE_ASPEED_SDHCI,
 188     .parent        = TYPE_SYS_BUS_DEVICE,
 189     .instance_size = sizeof(AspeedSDHCIState),
 190     .class_init    = aspeed_sdhci_class_init,
 191 };
 192
 193 static void aspeed_sdhci_register_types(void)
 194 {
 195     type_register_static(&aspeed_sdhci_info);
 196 }
 197
 198 type_init(aspeed_sdhci_register_types)