4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
24 #include "tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/qemu-print.h"
32 #include "hw/semihosting/semihost.h"
33 #include "exec/gen-icount.h"
35 #include "exec/helper-proto.h"
36 #include "exec/helper-gen.h"
39 #include "trace-tcg.h"
40 #include "translate-a64.h"
41 #include "qemu/atomic128.h"
43 static TCGv_i64 cpu_X
[32];
44 static TCGv_i64 cpu_pc
;
46 /* Load/store exclusive handling */
47 static TCGv_i64 cpu_exclusive_high
;
49 static const char *regnames
[] = {
50 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
51 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
52 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
53 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
57 A64_SHIFT_TYPE_LSL
= 0,
58 A64_SHIFT_TYPE_LSR
= 1,
59 A64_SHIFT_TYPE_ASR
= 2,
60 A64_SHIFT_TYPE_ROR
= 3
63 /* Table based decoder typedefs - used when the relevant bits for decode
64 * are too awkwardly scattered across the instruction (eg SIMD).
66 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
68 typedef struct AArch64DecodeTable
{
71 AArch64DecodeFn
*disas_fn
;
74 /* Function prototype for gen_ functions for calling Neon helpers */
75 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
76 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
78 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
80 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
81 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
82 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
83 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
84 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
85 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
86 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
87 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
88 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
89 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, TCGMemOp
);
91 /* initialize TCG globals. */
92 void a64_translate_init(void)
96 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
97 offsetof(CPUARMState
, pc
),
99 for (i
= 0; i
< 32; i
++) {
100 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
101 offsetof(CPUARMState
, xregs
[i
]),
105 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
106 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
109 static inline int get_a64_user_mem_index(DisasContext
*s
)
111 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
112 * if EL1, access as if EL0; otherwise access at current EL
116 switch (s
->mmu_idx
) {
117 case ARMMMUIdx_S12NSE1
:
118 useridx
= ARMMMUIdx_S12NSE0
;
120 case ARMMMUIdx_S1SE1
:
121 useridx
= ARMMMUIdx_S1SE0
;
124 g_assert_not_reached();
126 useridx
= s
->mmu_idx
;
129 return arm_to_core_mmu_idx(useridx
);
132 static void reset_btype(DisasContext
*s
)
135 TCGv_i32 zero
= tcg_const_i32(0);
136 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
137 tcg_temp_free_i32(zero
);
142 static void set_btype(DisasContext
*s
, int val
)
146 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
147 tcg_debug_assert(val
>= 1 && val
<= 3);
149 tcg_val
= tcg_const_i32(val
);
150 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
151 tcg_temp_free_i32(tcg_val
);
155 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
157 ARMCPU
*cpu
= ARM_CPU(cs
);
158 CPUARMState
*env
= &cpu
->env
;
159 uint32_t psr
= pstate_read(env
);
161 int el
= arm_current_el(env
);
162 const char *ns_status
;
164 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
165 for (i
= 0; i
< 32; i
++) {
167 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
169 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
170 (i
+ 2) % 3 ? " " : "\n");
174 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
175 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
179 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
181 psr
& PSTATE_N
? 'N' : '-',
182 psr
& PSTATE_Z
? 'Z' : '-',
183 psr
& PSTATE_C
? 'C' : '-',
184 psr
& PSTATE_V
? 'V' : '-',
187 psr
& PSTATE_SP
? 'h' : 't');
189 if (cpu_isar_feature(aa64_bti
, cpu
)) {
190 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
192 if (!(flags
& CPU_DUMP_FPU
)) {
193 qemu_fprintf(f
, "\n");
196 if (fp_exception_el(env
, el
) != 0) {
197 qemu_fprintf(f
, " FPU disabled\n");
200 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
201 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
203 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
204 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
206 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
208 if (i
== FFR_PRED_NUM
) {
209 qemu_fprintf(f
, "FFR=");
210 /* It's last, so end the line. */
213 qemu_fprintf(f
, "P%02d=", i
);
226 /* More than one quadword per predicate. */
231 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
233 if (j
* 4 + 4 <= zcr_len
+ 1) {
236 digits
= (zcr_len
% 4 + 1) * 4;
238 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
239 env
->vfp
.pregs
[i
].p
[j
],
240 j
? ":" : eol
? "\n" : " ");
244 for (i
= 0; i
< 32; i
++) {
246 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
247 i
, env
->vfp
.zregs
[i
].d
[1],
248 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
249 } else if (zcr_len
== 1) {
250 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
251 ":%016" PRIx64
":%016" PRIx64
"\n",
252 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
253 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
255 for (j
= zcr_len
; j
>= 0; j
--) {
256 bool odd
= (zcr_len
- j
) % 2 != 0;
258 qemu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
261 qemu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
263 qemu_fprintf(f
, " [%x]=", j
);
266 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
267 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
268 env
->vfp
.zregs
[i
].d
[j
* 2],
269 odd
|| j
== 0 ? "\n" : ":");
274 for (i
= 0; i
< 32; i
++) {
275 uint64_t *q
= aa64_vfp_qreg(env
, i
);
276 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
277 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
282 void gen_a64_set_pc_im(uint64_t val
)
284 tcg_gen_movi_i64(cpu_pc
, val
);
288 * Handle Top Byte Ignore (TBI) bits.
290 * If address tagging is enabled via the TCR TBI bits:
291 * + for EL2 and EL3 there is only one TBI bit, and if it is set
292 * then the address is zero-extended, clearing bits [63:56]
293 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
294 * and TBI1 controls addressses with bit 55 == 1.
295 * If the appropriate TBI bit is set for the address then
296 * the address is sign-extended from bit 55 into bits [63:56]
298 * Here We have concatenated TBI{1,0} into tbi.
300 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
301 TCGv_i64 src
, int tbi
)
304 /* Load unmodified address */
305 tcg_gen_mov_i64(dst
, src
);
306 } else if (s
->current_el
>= 2) {
307 /* FIXME: ARMv8.1-VHE S2 translation regime. */
308 /* Force tag byte to all zero */
309 tcg_gen_extract_i64(dst
, src
, 0, 56);
311 /* Sign-extend from bit 55. */
312 tcg_gen_sextract_i64(dst
, src
, 0, 56);
315 TCGv_i64 tcg_zero
= tcg_const_i64(0);
318 * The two TBI bits differ.
319 * If tbi0, then !tbi1: only use the extension if positive.
320 * if !tbi0, then tbi1: only use the extension if negative.
322 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
323 dst
, dst
, tcg_zero
, dst
, src
);
324 tcg_temp_free_i64(tcg_zero
);
329 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
332 * If address tagging is enabled for instructions via the TCR TBI bits,
333 * then loading an address into the PC will clear out any tag.
335 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
339 * Return a "clean" address for ADDR according to TBID.
340 * This is always a fresh temporary, as we need to be able to
341 * increment this independently of a dirty write-back address.
343 static TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
345 TCGv_i64 clean
= new_tmp_a64(s
);
346 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
350 typedef struct DisasCompare64
{
355 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
359 arm_test_cc(&c32
, cc
);
361 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
362 * properly. The NE/EQ comparisons are also fine with this choice. */
363 c64
->cond
= c32
.cond
;
364 c64
->value
= tcg_temp_new_i64();
365 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
370 static void a64_free_cc(DisasCompare64
*c64
)
372 tcg_temp_free_i64(c64
->value
);
375 static void gen_exception_internal(int excp
)
377 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
379 assert(excp_is_internal(excp
));
380 gen_helper_exception_internal(cpu_env
, tcg_excp
);
381 tcg_temp_free_i32(tcg_excp
);
384 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
386 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
387 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
388 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
390 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
392 tcg_temp_free_i32(tcg_el
);
393 tcg_temp_free_i32(tcg_syn
);
394 tcg_temp_free_i32(tcg_excp
);
397 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
399 gen_a64_set_pc_im(s
->pc
- offset
);
400 gen_exception_internal(excp
);
401 s
->base
.is_jmp
= DISAS_NORETURN
;
404 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
405 uint32_t syndrome
, uint32_t target_el
)
407 gen_a64_set_pc_im(s
->pc
- offset
);
408 gen_exception(excp
, syndrome
, target_el
);
409 s
->base
.is_jmp
= DISAS_NORETURN
;
412 static void gen_exception_bkpt_insn(DisasContext
*s
, int offset
,
417 gen_a64_set_pc_im(s
->pc
- offset
);
418 tcg_syn
= tcg_const_i32(syndrome
);
419 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
420 tcg_temp_free_i32(tcg_syn
);
421 s
->base
.is_jmp
= DISAS_NORETURN
;
424 static void gen_step_complete_exception(DisasContext
*s
)
426 /* We just completed step of an insn. Move from Active-not-pending
427 * to Active-pending, and then also take the swstep exception.
428 * This corresponds to making the (IMPDEF) choice to prioritize
429 * swstep exceptions over asynchronous exceptions taken to an exception
430 * level where debug is disabled. This choice has the advantage that
431 * we do not need to maintain internal state corresponding to the
432 * ISV/EX syndrome bits between completion of the step and generation
433 * of the exception, and our syndrome information is always correct.
436 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
437 default_exception_el(s
));
438 s
->base
.is_jmp
= DISAS_NORETURN
;
441 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
443 /* No direct tb linking with singlestep (either QEMU's or the ARM
444 * debug architecture kind) or deterministic io
446 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
447 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
451 #ifndef CONFIG_USER_ONLY
452 /* Only link tbs from inside the same guest page */
453 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
461 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
463 TranslationBlock
*tb
;
466 if (use_goto_tb(s
, n
, dest
)) {
468 gen_a64_set_pc_im(dest
);
469 tcg_gen_exit_tb(tb
, n
);
470 s
->base
.is_jmp
= DISAS_NORETURN
;
472 gen_a64_set_pc_im(dest
);
474 gen_step_complete_exception(s
);
475 } else if (s
->base
.singlestep_enabled
) {
476 gen_exception_internal(EXCP_DEBUG
);
478 tcg_gen_lookup_and_goto_ptr();
479 s
->base
.is_jmp
= DISAS_NORETURN
;
484 void unallocated_encoding(DisasContext
*s
)
486 /* Unallocated and reserved encodings are uncategorized */
487 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
488 default_exception_el(s
));
491 static void init_tmp_a64_array(DisasContext
*s
)
493 #ifdef CONFIG_DEBUG_TCG
494 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
496 s
->tmp_a64_count
= 0;
499 static void free_tmp_a64(DisasContext
*s
)
502 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
503 tcg_temp_free_i64(s
->tmp_a64
[i
]);
505 init_tmp_a64_array(s
);
508 TCGv_i64
new_tmp_a64(DisasContext
*s
)
510 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
511 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
514 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
516 TCGv_i64 t
= new_tmp_a64(s
);
517 tcg_gen_movi_i64(t
, 0);
522 * Register access functions
524 * These functions are used for directly accessing a register in where
525 * changes to the final register value are likely to be made. If you
526 * need to use a register for temporary calculation (e.g. index type
527 * operations) use the read_* form.
529 * B1.2.1 Register mappings
531 * In instruction register encoding 31 can refer to ZR (zero register) or
532 * the SP (stack pointer) depending on context. In QEMU's case we map SP
533 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
534 * This is the point of the _sp forms.
536 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
539 return new_tmp_a64_zero(s
);
545 /* register access for when 31 == SP */
546 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
551 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
552 * representing the register contents. This TCGv is an auto-freed
553 * temporary so it need not be explicitly freed, and may be modified.
555 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
557 TCGv_i64 v
= new_tmp_a64(s
);
560 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
562 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
565 tcg_gen_movi_i64(v
, 0);
570 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
572 TCGv_i64 v
= new_tmp_a64(s
);
574 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
576 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
581 /* Return the offset into CPUARMState of a slice (from
582 * the least significant end) of FP register Qn (ie
584 * (Note that this is not the same mapping as for A32; see cpu.h)
586 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
588 return vec_reg_offset(s
, regno
, 0, size
);
591 /* Offset of the high half of the 128 bit vector Qn */
592 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
594 return vec_reg_offset(s
, regno
, 1, MO_64
);
597 /* Convenience accessors for reading and writing single and double
598 * FP registers. Writing clears the upper parts of the associated
599 * 128 bit vector register, as required by the architecture.
600 * Note that unlike the GP register accessors, the values returned
601 * by the read functions must be manually freed.
603 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
605 TCGv_i64 v
= tcg_temp_new_i64();
607 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
611 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
613 TCGv_i32 v
= tcg_temp_new_i32();
615 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
619 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
621 TCGv_i32 v
= tcg_temp_new_i32();
623 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
627 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
628 * If SVE is not enabled, then there are only 128 bits in the vector.
630 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
632 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
633 unsigned vsz
= vec_full_reg_size(s
);
636 TCGv_i64 tcg_zero
= tcg_const_i64(0);
637 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
638 tcg_temp_free_i64(tcg_zero
);
641 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
645 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
647 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
649 tcg_gen_st_i64(v
, cpu_env
, ofs
);
650 clear_vec_high(s
, false, reg
);
653 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
655 TCGv_i64 tmp
= tcg_temp_new_i64();
657 tcg_gen_extu_i32_i64(tmp
, v
);
658 write_fp_dreg(s
, reg
, tmp
);
659 tcg_temp_free_i64(tmp
);
662 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
664 TCGv_ptr statusptr
= tcg_temp_new_ptr();
667 /* In A64 all instructions (both FP and Neon) use the FPCR; there
668 * is no equivalent of the A32 Neon "standard FPSCR value".
669 * However half-precision operations operate under a different
670 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
673 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
675 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
677 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
681 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
682 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
683 GVecGen2Fn
*gvec_fn
, int vece
)
685 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
686 is_q
? 16 : 8, vec_full_reg_size(s
));
689 /* Expand a 2-operand + immediate AdvSIMD vector operation using
690 * an expander function.
692 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
693 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
695 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
696 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
699 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
700 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
701 GVecGen3Fn
*gvec_fn
, int vece
)
703 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
704 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
707 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
708 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
709 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
711 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
712 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
713 is_q
? 16 : 8, vec_full_reg_size(s
));
716 /* Expand a 2-operand + immediate AdvSIMD vector operation using
719 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
720 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
722 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
723 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
726 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
727 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
728 int rn
, int rm
, const GVecGen3
*gvec_op
)
730 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
731 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
732 vec_full_reg_size(s
), gvec_op
);
735 /* Expand a 3-operand operation using an out-of-line helper. */
736 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
737 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
739 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
740 vec_full_reg_offset(s
, rn
),
741 vec_full_reg_offset(s
, rm
),
742 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
745 /* Expand a 3-operand + env pointer operation using
746 * an out-of-line helper.
748 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
749 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
751 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
752 vec_full_reg_offset(s
, rn
),
753 vec_full_reg_offset(s
, rm
), cpu_env
,
754 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
757 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
758 * an out-of-line helper.
760 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
761 int rm
, bool is_fp16
, int data
,
762 gen_helper_gvec_3_ptr
*fn
)
764 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
765 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
766 vec_full_reg_offset(s
, rn
),
767 vec_full_reg_offset(s
, rm
), fpst
,
768 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
769 tcg_temp_free_ptr(fpst
);
772 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
773 * than the 32 bit equivalent.
775 static inline void gen_set_NZ64(TCGv_i64 result
)
777 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
778 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
781 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
782 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
785 gen_set_NZ64(result
);
787 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
788 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
790 tcg_gen_movi_i32(cpu_CF
, 0);
791 tcg_gen_movi_i32(cpu_VF
, 0);
794 /* dest = T0 + T1; compute C, N, V and Z flags */
795 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
798 TCGv_i64 result
, flag
, tmp
;
799 result
= tcg_temp_new_i64();
800 flag
= tcg_temp_new_i64();
801 tmp
= tcg_temp_new_i64();
803 tcg_gen_movi_i64(tmp
, 0);
804 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
806 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
808 gen_set_NZ64(result
);
810 tcg_gen_xor_i64(flag
, result
, t0
);
811 tcg_gen_xor_i64(tmp
, t0
, t1
);
812 tcg_gen_andc_i64(flag
, flag
, tmp
);
813 tcg_temp_free_i64(tmp
);
814 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
816 tcg_gen_mov_i64(dest
, result
);
817 tcg_temp_free_i64(result
);
818 tcg_temp_free_i64(flag
);
820 /* 32 bit arithmetic */
821 TCGv_i32 t0_32
= tcg_temp_new_i32();
822 TCGv_i32 t1_32
= tcg_temp_new_i32();
823 TCGv_i32 tmp
= tcg_temp_new_i32();
825 tcg_gen_movi_i32(tmp
, 0);
826 tcg_gen_extrl_i64_i32(t0_32
, t0
);
827 tcg_gen_extrl_i64_i32(t1_32
, t1
);
828 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
829 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
830 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
831 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
832 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
833 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
835 tcg_temp_free_i32(tmp
);
836 tcg_temp_free_i32(t0_32
);
837 tcg_temp_free_i32(t1_32
);
841 /* dest = T0 - T1; compute C, N, V and Z flags */
842 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
845 /* 64 bit arithmetic */
846 TCGv_i64 result
, flag
, tmp
;
848 result
= tcg_temp_new_i64();
849 flag
= tcg_temp_new_i64();
850 tcg_gen_sub_i64(result
, t0
, t1
);
852 gen_set_NZ64(result
);
854 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
855 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
857 tcg_gen_xor_i64(flag
, result
, t0
);
858 tmp
= tcg_temp_new_i64();
859 tcg_gen_xor_i64(tmp
, t0
, t1
);
860 tcg_gen_and_i64(flag
, flag
, tmp
);
861 tcg_temp_free_i64(tmp
);
862 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
863 tcg_gen_mov_i64(dest
, result
);
864 tcg_temp_free_i64(flag
);
865 tcg_temp_free_i64(result
);
867 /* 32 bit arithmetic */
868 TCGv_i32 t0_32
= tcg_temp_new_i32();
869 TCGv_i32 t1_32
= tcg_temp_new_i32();
872 tcg_gen_extrl_i64_i32(t0_32
, t0
);
873 tcg_gen_extrl_i64_i32(t1_32
, t1
);
874 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
875 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
876 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
877 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
878 tmp
= tcg_temp_new_i32();
879 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
880 tcg_temp_free_i32(t0_32
);
881 tcg_temp_free_i32(t1_32
);
882 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
883 tcg_temp_free_i32(tmp
);
884 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
888 /* dest = T0 + T1 + CF; do not compute flags. */
889 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
891 TCGv_i64 flag
= tcg_temp_new_i64();
892 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
893 tcg_gen_add_i64(dest
, t0
, t1
);
894 tcg_gen_add_i64(dest
, dest
, flag
);
895 tcg_temp_free_i64(flag
);
898 tcg_gen_ext32u_i64(dest
, dest
);
902 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
903 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
906 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
907 result
= tcg_temp_new_i64();
908 cf_64
= tcg_temp_new_i64();
909 vf_64
= tcg_temp_new_i64();
910 tmp
= tcg_const_i64(0);
912 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
913 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
914 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
915 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
916 gen_set_NZ64(result
);
918 tcg_gen_xor_i64(vf_64
, result
, t0
);
919 tcg_gen_xor_i64(tmp
, t0
, t1
);
920 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
921 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
923 tcg_gen_mov_i64(dest
, result
);
925 tcg_temp_free_i64(tmp
);
926 tcg_temp_free_i64(vf_64
);
927 tcg_temp_free_i64(cf_64
);
928 tcg_temp_free_i64(result
);
930 TCGv_i32 t0_32
, t1_32
, tmp
;
931 t0_32
= tcg_temp_new_i32();
932 t1_32
= tcg_temp_new_i32();
933 tmp
= tcg_const_i32(0);
935 tcg_gen_extrl_i64_i32(t0_32
, t0
);
936 tcg_gen_extrl_i64_i32(t1_32
, t1
);
937 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
938 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
940 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
941 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
942 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
943 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
944 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
946 tcg_temp_free_i32(tmp
);
947 tcg_temp_free_i32(t1_32
);
948 tcg_temp_free_i32(t0_32
);
953 * Load/Store generators
957 * Store from GPR register to memory.
959 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
960 TCGv_i64 tcg_addr
, int size
, int memidx
,
962 unsigned int iss_srt
,
963 bool iss_sf
, bool iss_ar
)
966 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
971 syn
= syn_data_abort_with_iss(0,
977 0, 0, 0, 0, 0, false);
978 disas_set_insn_syndrome(s
, syn
);
982 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
983 TCGv_i64 tcg_addr
, int size
,
985 unsigned int iss_srt
,
986 bool iss_sf
, bool iss_ar
)
988 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
989 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
993 * Load from memory to GPR register
995 static void do_gpr_ld_memidx(DisasContext
*s
,
996 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
997 int size
, bool is_signed
,
998 bool extend
, int memidx
,
999 bool iss_valid
, unsigned int iss_srt
,
1000 bool iss_sf
, bool iss_ar
)
1002 TCGMemOp memop
= s
->be_data
+ size
;
1004 g_assert(size
<= 3);
1010 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
1012 if (extend
&& is_signed
) {
1014 tcg_gen_ext32u_i64(dest
, dest
);
1020 syn
= syn_data_abort_with_iss(0,
1026 0, 0, 0, 0, 0, false);
1027 disas_set_insn_syndrome(s
, syn
);
1031 static void do_gpr_ld(DisasContext
*s
,
1032 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
1033 int size
, bool is_signed
, bool extend
,
1034 bool iss_valid
, unsigned int iss_srt
,
1035 bool iss_sf
, bool iss_ar
)
1037 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
1039 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
1043 * Store from FP register to memory
1045 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
1047 /* This writes the bottom N bits of a 128 bit wide vector to memory */
1048 TCGv_i64 tmp
= tcg_temp_new_i64();
1049 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
1051 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
1054 bool be
= s
->be_data
== MO_BE
;
1055 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
1057 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1058 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1060 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
1061 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1063 tcg_temp_free_i64(tcg_hiaddr
);
1066 tcg_temp_free_i64(tmp
);
1070 * Load from memory to FP register
1072 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1074 /* This always zero-extends and writes to a full 128 bit wide vector */
1075 TCGv_i64 tmplo
= tcg_temp_new_i64();
1079 TCGMemOp memop
= s
->be_data
+ size
;
1080 tmphi
= tcg_const_i64(0);
1081 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1083 bool be
= s
->be_data
== MO_BE
;
1084 TCGv_i64 tcg_hiaddr
;
1086 tmphi
= tcg_temp_new_i64();
1087 tcg_hiaddr
= tcg_temp_new_i64();
1089 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1090 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1092 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1094 tcg_temp_free_i64(tcg_hiaddr
);
1097 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1098 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1100 tcg_temp_free_i64(tmplo
);
1101 tcg_temp_free_i64(tmphi
);
1103 clear_vec_high(s
, true, destidx
);
1107 * Vector load/store helpers.
1109 * The principal difference between this and a FP load is that we don't
1110 * zero extend as we are filling a partial chunk of the vector register.
1111 * These functions don't support 128 bit loads/stores, which would be
1112 * normal load/store operations.
1114 * The _i32 versions are useful when operating on 32 bit quantities
1115 * (eg for floating point single or using Neon helper functions).
1118 /* Get value of an element within a vector register */
1119 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1120 int element
, TCGMemOp memop
)
1122 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1125 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1128 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1131 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1134 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1137 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1140 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1144 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1147 g_assert_not_reached();
1151 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1152 int element
, TCGMemOp memop
)
1154 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1157 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1160 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1163 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1166 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1170 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1173 g_assert_not_reached();
1177 /* Set value of an element within a vector register */
1178 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1179 int element
, TCGMemOp memop
)
1181 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1184 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1187 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1190 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1193 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1196 g_assert_not_reached();
1200 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1201 int destidx
, int element
, TCGMemOp memop
)
1203 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1206 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1209 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1212 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1215 g_assert_not_reached();
1219 /* Store from vector register to memory */
1220 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1221 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1223 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1225 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1226 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1228 tcg_temp_free_i64(tcg_tmp
);
1231 /* Load from memory to vector register */
1232 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1233 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1235 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1237 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1238 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1240 tcg_temp_free_i64(tcg_tmp
);
1243 /* Check that FP/Neon access is enabled. If it is, return
1244 * true. If not, emit code to generate an appropriate exception,
1245 * and return false; the caller should not emit any code for
1246 * the instruction. Note that this check must happen after all
1247 * unallocated-encoding checks (otherwise the syndrome information
1248 * for the resulting exception will be incorrect).
1250 static inline bool fp_access_check(DisasContext
*s
)
1252 assert(!s
->fp_access_checked
);
1253 s
->fp_access_checked
= true;
1255 if (!s
->fp_excp_el
) {
1259 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1264 /* Check that SVE access is enabled. If it is, return true.
1265 * If not, emit code to generate an appropriate exception and return false.
1267 bool sve_access_check(DisasContext
*s
)
1269 if (s
->sve_excp_el
) {
1270 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_sve_access_trap(),
1274 return fp_access_check(s
);
1278 * This utility function is for doing register extension with an
1279 * optional shift. You will likely want to pass a temporary for the
1280 * destination register. See DecodeRegExtend() in the ARM ARM.
1282 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1283 int option
, unsigned int shift
)
1285 int extsize
= extract32(option
, 0, 2);
1286 bool is_signed
= extract32(option
, 2, 1);
1291 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1294 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1297 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1300 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1306 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1309 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1312 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1315 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1321 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1325 static inline void gen_check_sp_alignment(DisasContext
*s
)
1327 /* The AArch64 architecture mandates that (if enabled via PSTATE
1328 * or SCTLR bits) there is a check that SP is 16-aligned on every
1329 * SP-relative load or store (with an exception generated if it is not).
1330 * In line with general QEMU practice regarding misaligned accesses,
1331 * we omit these checks for the sake of guest program performance.
1332 * This function is provided as a hook so we can more easily add these
1333 * checks in future (possibly as a "favour catching guest program bugs
1334 * over speed" user selectable option).
1339 * This provides a simple table based table lookup decoder. It is
1340 * intended to be used when the relevant bits for decode are too
1341 * awkwardly placed and switch/if based logic would be confusing and
1342 * deeply nested. Since it's a linear search through the table, tables
1343 * should be kept small.
1345 * It returns the first handler where insn & mask == pattern, or
1346 * NULL if there is no match.
1347 * The table is terminated by an empty mask (i.e. 0)
1349 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1352 const AArch64DecodeTable
*tptr
= table
;
1354 while (tptr
->mask
) {
1355 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1356 return tptr
->disas_fn
;
1364 * The instruction disassembly implemented here matches
1365 * the instruction encoding classifications in chapter C4
1366 * of the ARM Architecture Reference Manual (DDI0487B_a);
1367 * classification names and decode diagrams here should generally
1368 * match up with those in the manual.
1371 /* Unconditional branch (immediate)
1373 * +----+-----------+-------------------------------------+
1374 * | op | 0 0 1 0 1 | imm26 |
1375 * +----+-----------+-------------------------------------+
1377 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1379 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1381 if (insn
& (1U << 31)) {
1382 /* BL Branch with link */
1383 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1386 /* B Branch / BL Branch with link */
1388 gen_goto_tb(s
, 0, addr
);
1391 /* Compare and branch (immediate)
1392 * 31 30 25 24 23 5 4 0
1393 * +----+-------------+----+---------------------+--------+
1394 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1395 * +----+-------------+----+---------------------+--------+
1397 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1399 unsigned int sf
, op
, rt
;
1401 TCGLabel
*label_match
;
1404 sf
= extract32(insn
, 31, 1);
1405 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1406 rt
= extract32(insn
, 0, 5);
1407 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1409 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1410 label_match
= gen_new_label();
1413 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1414 tcg_cmp
, 0, label_match
);
1416 gen_goto_tb(s
, 0, s
->pc
);
1417 gen_set_label(label_match
);
1418 gen_goto_tb(s
, 1, addr
);
1421 /* Test and branch (immediate)
1422 * 31 30 25 24 23 19 18 5 4 0
1423 * +----+-------------+----+-------+-------------+------+
1424 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1425 * +----+-------------+----+-------+-------------+------+
1427 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1429 unsigned int bit_pos
, op
, rt
;
1431 TCGLabel
*label_match
;
1434 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1435 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1436 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1437 rt
= extract32(insn
, 0, 5);
1439 tcg_cmp
= tcg_temp_new_i64();
1440 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1441 label_match
= gen_new_label();
1444 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1445 tcg_cmp
, 0, label_match
);
1446 tcg_temp_free_i64(tcg_cmp
);
1447 gen_goto_tb(s
, 0, s
->pc
);
1448 gen_set_label(label_match
);
1449 gen_goto_tb(s
, 1, addr
);
1452 /* Conditional branch (immediate)
1453 * 31 25 24 23 5 4 3 0
1454 * +---------------+----+---------------------+----+------+
1455 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1456 * +---------------+----+---------------------+----+------+
1458 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1463 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1464 unallocated_encoding(s
);
1467 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1468 cond
= extract32(insn
, 0, 4);
1472 /* genuinely conditional branches */
1473 TCGLabel
*label_match
= gen_new_label();
1474 arm_gen_test_cc(cond
, label_match
);
1475 gen_goto_tb(s
, 0, s
->pc
);
1476 gen_set_label(label_match
);
1477 gen_goto_tb(s
, 1, addr
);
1479 /* 0xe and 0xf are both "always" conditions */
1480 gen_goto_tb(s
, 0, addr
);
1484 /* HINT instruction group, including various allocated HINTs */
1485 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1486 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1488 unsigned int selector
= crm
<< 3 | op2
;
1491 unallocated_encoding(s
);
1496 case 0b00000: /* NOP */
1498 case 0b00011: /* WFI */
1499 s
->base
.is_jmp
= DISAS_WFI
;
1501 case 0b00001: /* YIELD */
1502 /* When running in MTTCG we don't generate jumps to the yield and
1503 * WFE helpers as it won't affect the scheduling of other vCPUs.
1504 * If we wanted to more completely model WFE/SEV so we don't busy
1505 * spin unnecessarily we would need to do something more involved.
1507 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1508 s
->base
.is_jmp
= DISAS_YIELD
;
1511 case 0b00010: /* WFE */
1512 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1513 s
->base
.is_jmp
= DISAS_WFE
;
1516 case 0b00100: /* SEV */
1517 case 0b00101: /* SEVL */
1518 /* we treat all as NOP at least for now */
1520 case 0b00111: /* XPACLRI */
1521 if (s
->pauth_active
) {
1522 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1525 case 0b01000: /* PACIA1716 */
1526 if (s
->pauth_active
) {
1527 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1530 case 0b01010: /* PACIB1716 */
1531 if (s
->pauth_active
) {
1532 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1535 case 0b01100: /* AUTIA1716 */
1536 if (s
->pauth_active
) {
1537 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1540 case 0b01110: /* AUTIB1716 */
1541 if (s
->pauth_active
) {
1542 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1545 case 0b11000: /* PACIAZ */
1546 if (s
->pauth_active
) {
1547 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1548 new_tmp_a64_zero(s
));
1551 case 0b11001: /* PACIASP */
1552 if (s
->pauth_active
) {
1553 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1556 case 0b11010: /* PACIBZ */
1557 if (s
->pauth_active
) {
1558 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1559 new_tmp_a64_zero(s
));
1562 case 0b11011: /* PACIBSP */
1563 if (s
->pauth_active
) {
1564 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1567 case 0b11100: /* AUTIAZ */
1568 if (s
->pauth_active
) {
1569 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1570 new_tmp_a64_zero(s
));
1573 case 0b11101: /* AUTIASP */
1574 if (s
->pauth_active
) {
1575 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1578 case 0b11110: /* AUTIBZ */
1579 if (s
->pauth_active
) {
1580 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1581 new_tmp_a64_zero(s
));
1584 case 0b11111: /* AUTIBSP */
1585 if (s
->pauth_active
) {
1586 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1590 /* default specified as NOP equivalent */
1595 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1597 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1600 /* CLREX, DSB, DMB, ISB */
1601 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1602 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1607 unallocated_encoding(s
);
1618 case 1: /* MBReqTypes_Reads */
1619 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1621 case 2: /* MBReqTypes_Writes */
1622 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1624 default: /* MBReqTypes_All */
1625 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1631 /* We need to break the TB after this insn to execute
1632 * a self-modified code correctly and also to take
1633 * any pending interrupts immediately.
1636 gen_goto_tb(s
, 0, s
->pc
);
1640 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1641 goto do_unallocated
;
1644 * TODO: There is no speculation barrier opcode for TCG;
1645 * MB and end the TB instead.
1647 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1648 gen_goto_tb(s
, 0, s
->pc
);
1653 unallocated_encoding(s
);
1658 static void gen_xaflag(void)
1660 TCGv_i32 z
= tcg_temp_new_i32();
1662 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1671 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1672 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1675 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1676 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1678 /* (!C & Z) << 31 -> -(Z & ~C) */
1679 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1680 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1683 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1685 tcg_temp_free_i32(z
);
1688 static void gen_axflag(void)
1690 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1691 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1693 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1694 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1696 tcg_gen_movi_i32(cpu_NF
, 0);
1697 tcg_gen_movi_i32(cpu_VF
, 0);
1700 /* MSR (immediate) - move immediate to processor state field */
1701 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1702 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1705 int op
= op1
<< 3 | op2
;
1707 /* End the TB by default, chaining is ok. */
1708 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1711 case 0x00: /* CFINV */
1712 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1713 goto do_unallocated
;
1715 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1716 s
->base
.is_jmp
= DISAS_NEXT
;
1719 case 0x01: /* XAFlag */
1720 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1721 goto do_unallocated
;
1724 s
->base
.is_jmp
= DISAS_NEXT
;
1727 case 0x02: /* AXFlag */
1728 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1729 goto do_unallocated
;
1732 s
->base
.is_jmp
= DISAS_NEXT
;
1735 case 0x05: /* SPSel */
1736 if (s
->current_el
== 0) {
1737 goto do_unallocated
;
1739 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1740 gen_helper_msr_i_spsel(cpu_env
, t1
);
1741 tcg_temp_free_i32(t1
);
1744 case 0x1e: /* DAIFSet */
1745 t1
= tcg_const_i32(crm
);
1746 gen_helper_msr_i_daifset(cpu_env
, t1
);
1747 tcg_temp_free_i32(t1
);
1750 case 0x1f: /* DAIFClear */
1751 t1
= tcg_const_i32(crm
);
1752 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1753 tcg_temp_free_i32(t1
);
1754 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1755 s
->base
.is_jmp
= DISAS_UPDATE
;
1760 unallocated_encoding(s
);
1765 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1767 TCGv_i32 tmp
= tcg_temp_new_i32();
1768 TCGv_i32 nzcv
= tcg_temp_new_i32();
1770 /* build bit 31, N */
1771 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1772 /* build bit 30, Z */
1773 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1774 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1775 /* build bit 29, C */
1776 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1777 /* build bit 28, V */
1778 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1779 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1780 /* generate result */
1781 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1783 tcg_temp_free_i32(nzcv
);
1784 tcg_temp_free_i32(tmp
);
1787 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1789 TCGv_i32 nzcv
= tcg_temp_new_i32();
1791 /* take NZCV from R[t] */
1792 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1795 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1797 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1798 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1800 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1801 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1803 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1804 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1805 tcg_temp_free_i32(nzcv
);
1808 /* MRS - move from system register
1809 * MSR (register) - move to system register
1812 * These are all essentially the same insn in 'read' and 'write'
1813 * versions, with varying op0 fields.
1815 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1816 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1817 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1819 const ARMCPRegInfo
*ri
;
1822 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1823 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1824 crn
, crm
, op0
, op1
, op2
));
1827 /* Unknown register; this might be a guest error or a QEMU
1828 * unimplemented feature.
1830 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1831 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1832 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1833 unallocated_encoding(s
);
1837 /* Check access permissions */
1838 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1839 unallocated_encoding(s
);
1844 /* Emit code to perform further access permissions checks at
1845 * runtime; this may result in an exception.
1848 TCGv_i32 tcg_syn
, tcg_isread
;
1851 gen_a64_set_pc_im(s
->pc
- 4);
1852 tmpptr
= tcg_const_ptr(ri
);
1853 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1854 tcg_syn
= tcg_const_i32(syndrome
);
1855 tcg_isread
= tcg_const_i32(isread
);
1856 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1857 tcg_temp_free_ptr(tmpptr
);
1858 tcg_temp_free_i32(tcg_syn
);
1859 tcg_temp_free_i32(tcg_isread
);
1862 /* Handle special cases first */
1863 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1867 tcg_rt
= cpu_reg(s
, rt
);
1869 gen_get_nzcv(tcg_rt
);
1871 gen_set_nzcv(tcg_rt
);
1874 case ARM_CP_CURRENTEL
:
1875 /* Reads as current EL value from pstate, which is
1876 * guaranteed to be constant by the tb flags.
1878 tcg_rt
= cpu_reg(s
, rt
);
1879 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1882 /* Writes clear the aligned block of memory which rt points into. */
1883 tcg_rt
= cpu_reg(s
, rt
);
1884 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1889 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1891 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1895 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1899 tcg_rt
= cpu_reg(s
, rt
);
1902 if (ri
->type
& ARM_CP_CONST
) {
1903 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1904 } else if (ri
->readfn
) {
1906 tmpptr
= tcg_const_ptr(ri
);
1907 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1908 tcg_temp_free_ptr(tmpptr
);
1910 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1913 if (ri
->type
& ARM_CP_CONST
) {
1914 /* If not forbidden by access permissions, treat as WI */
1916 } else if (ri
->writefn
) {
1918 tmpptr
= tcg_const_ptr(ri
);
1919 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1920 tcg_temp_free_ptr(tmpptr
);
1922 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1926 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1927 /* I/O operations must end the TB here (whether read or write) */
1929 s
->base
.is_jmp
= DISAS_UPDATE
;
1930 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1931 /* We default to ending the TB on a coprocessor register write,
1932 * but allow this to be suppressed by the register definition
1933 * (usually only necessary to work around guest bugs).
1935 s
->base
.is_jmp
= DISAS_UPDATE
;
1940 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1941 * +---------------------+---+-----+-----+-------+-------+-----+------+
1942 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1943 * +---------------------+---+-----+-----+-------+-------+-----+------+
1945 static void disas_system(DisasContext
*s
, uint32_t insn
)
1947 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1948 l
= extract32(insn
, 21, 1);
1949 op0
= extract32(insn
, 19, 2);
1950 op1
= extract32(insn
, 16, 3);
1951 crn
= extract32(insn
, 12, 4);
1952 crm
= extract32(insn
, 8, 4);
1953 op2
= extract32(insn
, 5, 3);
1954 rt
= extract32(insn
, 0, 5);
1957 if (l
|| rt
!= 31) {
1958 unallocated_encoding(s
);
1962 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1963 handle_hint(s
, insn
, op1
, op2
, crm
);
1965 case 3: /* CLREX, DSB, DMB, ISB */
1966 handle_sync(s
, insn
, op1
, op2
, crm
);
1968 case 4: /* MSR (immediate) */
1969 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1972 unallocated_encoding(s
);
1977 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1980 /* Exception generation
1982 * 31 24 23 21 20 5 4 2 1 0
1983 * +-----------------+-----+------------------------+-----+----+
1984 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1985 * +-----------------------+------------------------+----------+
1987 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1989 int opc
= extract32(insn
, 21, 3);
1990 int op2_ll
= extract32(insn
, 0, 5);
1991 int imm16
= extract32(insn
, 5, 16);
1996 /* For SVC, HVC and SMC we advance the single-step state
1997 * machine before taking the exception. This is architecturally
1998 * mandated, to ensure that single-stepping a system call
1999 * instruction works properly.
2004 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
2005 default_exception_el(s
));
2008 if (s
->current_el
== 0) {
2009 unallocated_encoding(s
);
2012 /* The pre HVC helper handles cases when HVC gets trapped
2013 * as an undefined insn by runtime configuration.
2015 gen_a64_set_pc_im(s
->pc
- 4);
2016 gen_helper_pre_hvc(cpu_env
);
2018 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
2021 if (s
->current_el
== 0) {
2022 unallocated_encoding(s
);
2025 gen_a64_set_pc_im(s
->pc
- 4);
2026 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
2027 gen_helper_pre_smc(cpu_env
, tmp
);
2028 tcg_temp_free_i32(tmp
);
2030 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
2033 unallocated_encoding(s
);
2039 unallocated_encoding(s
);
2043 gen_exception_bkpt_insn(s
, 4, syn_aa64_bkpt(imm16
));
2047 unallocated_encoding(s
);
2050 /* HLT. This has two purposes.
2051 * Architecturally, it is an external halting debug instruction.
2052 * Since QEMU doesn't implement external debug, we treat this as
2053 * it is required for halting debug disabled: it will UNDEF.
2054 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
2056 if (semihosting_enabled() && imm16
== 0xf000) {
2057 #ifndef CONFIG_USER_ONLY
2058 /* In system mode, don't allow userspace access to semihosting,
2059 * to provide some semblance of security (and for consistency
2060 * with our 32-bit semihosting).
2062 if (s
->current_el
== 0) {
2063 unsupported_encoding(s
, insn
);
2067 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
2069 unsupported_encoding(s
, insn
);
2073 if (op2_ll
< 1 || op2_ll
> 3) {
2074 unallocated_encoding(s
);
2077 /* DCPS1, DCPS2, DCPS3 */
2078 unsupported_encoding(s
, insn
);
2081 unallocated_encoding(s
);
2086 /* Unconditional branch (register)
2087 * 31 25 24 21 20 16 15 10 9 5 4 0
2088 * +---------------+-------+-------+-------+------+-------+
2089 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2090 * +---------------+-------+-------+-------+------+-------+
2092 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2094 unsigned int opc
, op2
, op3
, rn
, op4
;
2095 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2099 opc
= extract32(insn
, 21, 4);
2100 op2
= extract32(insn
, 16, 5);
2101 op3
= extract32(insn
, 10, 6);
2102 rn
= extract32(insn
, 5, 5);
2103 op4
= extract32(insn
, 0, 5);
2106 goto do_unallocated
;
2118 goto do_unallocated
;
2120 dst
= cpu_reg(s
, rn
);
2125 if (!dc_isar_feature(aa64_pauth
, s
)) {
2126 goto do_unallocated
;
2130 if (rn
!= 0x1f || op4
!= 0x1f) {
2131 goto do_unallocated
;
2134 modifier
= cpu_X
[31];
2136 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2138 goto do_unallocated
;
2140 modifier
= new_tmp_a64_zero(s
);
2142 if (s
->pauth_active
) {
2143 dst
= new_tmp_a64(s
);
2145 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2147 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2150 dst
= cpu_reg(s
, rn
);
2155 goto do_unallocated
;
2157 gen_a64_set_pc(s
, dst
);
2158 /* BLR also needs to load return address */
2160 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2166 if (!dc_isar_feature(aa64_pauth
, s
)) {
2167 goto do_unallocated
;
2169 if ((op3
& ~1) != 2) {
2170 goto do_unallocated
;
2172 btype_mod
= opc
& 1;
2173 if (s
->pauth_active
) {
2174 dst
= new_tmp_a64(s
);
2175 modifier
= cpu_reg_sp(s
, op4
);
2177 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2179 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2182 dst
= cpu_reg(s
, rn
);
2184 gen_a64_set_pc(s
, dst
);
2185 /* BLRAA also needs to load return address */
2187 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2192 if (s
->current_el
== 0) {
2193 goto do_unallocated
;
2198 goto do_unallocated
;
2200 dst
= tcg_temp_new_i64();
2201 tcg_gen_ld_i64(dst
, cpu_env
,
2202 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2205 case 2: /* ERETAA */
2206 case 3: /* ERETAB */
2207 if (!dc_isar_feature(aa64_pauth
, s
)) {
2208 goto do_unallocated
;
2210 if (rn
!= 0x1f || op4
!= 0x1f) {
2211 goto do_unallocated
;
2213 dst
= tcg_temp_new_i64();
2214 tcg_gen_ld_i64(dst
, cpu_env
,
2215 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2216 if (s
->pauth_active
) {
2217 modifier
= cpu_X
[31];
2219 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2221 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2227 goto do_unallocated
;
2229 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2233 gen_helper_exception_return(cpu_env
, dst
);
2234 tcg_temp_free_i64(dst
);
2235 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2238 /* Must exit loop to check un-masked IRQs */
2239 s
->base
.is_jmp
= DISAS_EXIT
;
2243 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2244 goto do_unallocated
;
2246 unsupported_encoding(s
, insn
);
2252 unallocated_encoding(s
);
2256 switch (btype_mod
) {
2258 if (dc_isar_feature(aa64_bti
, s
)) {
2259 /* BR to {x16,x17} or !guard -> 1, else 3. */
2260 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2265 if (dc_isar_feature(aa64_bti
, s
)) {
2266 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2271 default: /* RET or none of the above. */
2272 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2276 s
->base
.is_jmp
= DISAS_JUMP
;
2279 /* Branches, exception generating and system instructions */
2280 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2282 switch (extract32(insn
, 25, 7)) {
2283 case 0x0a: case 0x0b:
2284 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2285 disas_uncond_b_imm(s
, insn
);
2287 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2288 disas_comp_b_imm(s
, insn
);
2290 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2291 disas_test_b_imm(s
, insn
);
2293 case 0x2a: /* Conditional branch (immediate) */
2294 disas_cond_b_imm(s
, insn
);
2296 case 0x6a: /* Exception generation / System */
2297 if (insn
& (1 << 24)) {
2298 if (extract32(insn
, 22, 2) == 0) {
2299 disas_system(s
, insn
);
2301 unallocated_encoding(s
);
2307 case 0x6b: /* Unconditional branch (register) */
2308 disas_uncond_b_reg(s
, insn
);
2311 unallocated_encoding(s
);
2317 * Load/Store exclusive instructions are implemented by remembering
2318 * the value/address loaded, and seeing if these are the same
2319 * when the store is performed. This is not actually the architecturally
2320 * mandated semantics, but it works for typical guest code sequences
2321 * and avoids having to monitor regular stores.
2323 * The store exclusive uses the atomic cmpxchg primitives to avoid
2324 * races in multi-threaded linux-user and when MTTCG softmmu is
2327 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2328 TCGv_i64 addr
, int size
, bool is_pair
)
2330 int idx
= get_mem_index(s
);
2331 TCGMemOp memop
= s
->be_data
;
2333 g_assert(size
<= 3);
2335 g_assert(size
>= 2);
2337 /* The pair must be single-copy atomic for the doubleword. */
2338 memop
|= MO_64
| MO_ALIGN
;
2339 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2340 if (s
->be_data
== MO_LE
) {
2341 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2342 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2344 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2345 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2348 /* The pair must be single-copy atomic for *each* doubleword, not
2349 the entire quadword, however it must be quadword aligned. */
2351 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2352 memop
| MO_ALIGN_16
);
2354 TCGv_i64 addr2
= tcg_temp_new_i64();
2355 tcg_gen_addi_i64(addr2
, addr
, 8);
2356 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2357 tcg_temp_free_i64(addr2
);
2359 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2360 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2363 memop
|= size
| MO_ALIGN
;
2364 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2365 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2367 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2370 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2371 TCGv_i64 addr
, int size
, int is_pair
)
2373 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2374 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2377 * [addr + datasize] = {Rt2};
2383 * env->exclusive_addr = -1;
2385 TCGLabel
*fail_label
= gen_new_label();
2386 TCGLabel
*done_label
= gen_new_label();
2389 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2391 tmp
= tcg_temp_new_i64();
2394 if (s
->be_data
== MO_LE
) {
2395 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2397 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2399 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2400 cpu_exclusive_val
, tmp
,
2402 MO_64
| MO_ALIGN
| s
->be_data
);
2403 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2404 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2405 if (!HAVE_CMPXCHG128
) {
2406 gen_helper_exit_atomic(cpu_env
);
2407 s
->base
.is_jmp
= DISAS_NORETURN
;
2408 } else if (s
->be_data
== MO_LE
) {
2409 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2414 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2419 } else if (s
->be_data
== MO_LE
) {
2420 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2421 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2423 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2424 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2427 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2428 cpu_reg(s
, rt
), get_mem_index(s
),
2429 size
| MO_ALIGN
| s
->be_data
);
2430 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2432 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2433 tcg_temp_free_i64(tmp
);
2434 tcg_gen_br(done_label
);
2436 gen_set_label(fail_label
);
2437 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2438 gen_set_label(done_label
);
2439 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2442 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2445 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2446 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2447 int memidx
= get_mem_index(s
);
2448 TCGv_i64 clean_addr
;
2451 gen_check_sp_alignment(s
);
2453 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2454 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2455 size
| MO_ALIGN
| s
->be_data
);
2458 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2461 TCGv_i64 s1
= cpu_reg(s
, rs
);
2462 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2463 TCGv_i64 t1
= cpu_reg(s
, rt
);
2464 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2465 TCGv_i64 clean_addr
;
2466 int memidx
= get_mem_index(s
);
2469 gen_check_sp_alignment(s
);
2471 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2474 TCGv_i64 cmp
= tcg_temp_new_i64();
2475 TCGv_i64 val
= tcg_temp_new_i64();
2477 if (s
->be_data
== MO_LE
) {
2478 tcg_gen_concat32_i64(val
, t1
, t2
);
2479 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2481 tcg_gen_concat32_i64(val
, t2
, t1
);
2482 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2485 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2486 MO_64
| MO_ALIGN
| s
->be_data
);
2487 tcg_temp_free_i64(val
);
2489 if (s
->be_data
== MO_LE
) {
2490 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2492 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2494 tcg_temp_free_i64(cmp
);
2495 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2496 if (HAVE_CMPXCHG128
) {
2497 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2498 if (s
->be_data
== MO_LE
) {
2499 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2500 clean_addr
, t1
, t2
);
2502 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2503 clean_addr
, t1
, t2
);
2505 tcg_temp_free_i32(tcg_rs
);
2507 gen_helper_exit_atomic(cpu_env
);
2508 s
->base
.is_jmp
= DISAS_NORETURN
;
2511 TCGv_i64 d1
= tcg_temp_new_i64();
2512 TCGv_i64 d2
= tcg_temp_new_i64();
2513 TCGv_i64 a2
= tcg_temp_new_i64();
2514 TCGv_i64 c1
= tcg_temp_new_i64();
2515 TCGv_i64 c2
= tcg_temp_new_i64();
2516 TCGv_i64 zero
= tcg_const_i64(0);
2518 /* Load the two words, in memory order. */
2519 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2520 MO_64
| MO_ALIGN_16
| s
->be_data
);
2521 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2522 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2524 /* Compare the two words, also in memory order. */
2525 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2526 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2527 tcg_gen_and_i64(c2
, c2
, c1
);
2529 /* If compare equal, write back new data, else write back old data. */
2530 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2531 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2532 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2533 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2534 tcg_temp_free_i64(a2
);
2535 tcg_temp_free_i64(c1
);
2536 tcg_temp_free_i64(c2
);
2537 tcg_temp_free_i64(zero
);
2539 /* Write back the data from memory to Rs. */
2540 tcg_gen_mov_i64(s1
, d1
);
2541 tcg_gen_mov_i64(s2
, d2
);
2542 tcg_temp_free_i64(d1
);
2543 tcg_temp_free_i64(d2
);
2547 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2548 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2550 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2552 int opc0
= extract32(opc
, 0, 1);
2556 regsize
= opc0
? 32 : 64;
2558 regsize
= size
== 3 ? 64 : 32;
2560 return regsize
== 64;
2563 /* Load/store exclusive
2565 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2566 * +-----+-------------+----+---+----+------+----+-------+------+------+
2567 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2568 * +-----+-------------+----+---+----+------+----+-------+------+------+
2570 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2571 * L: 0 -> store, 1 -> load
2572 * o2: 0 -> exclusive, 1 -> not
2573 * o1: 0 -> single register, 1 -> register pair
2574 * o0: 1 -> load-acquire/store-release, 0 -> not
2576 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2578 int rt
= extract32(insn
, 0, 5);
2579 int rn
= extract32(insn
, 5, 5);
2580 int rt2
= extract32(insn
, 10, 5);
2581 int rs
= extract32(insn
, 16, 5);
2582 int is_lasr
= extract32(insn
, 15, 1);
2583 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2584 int size
= extract32(insn
, 30, 2);
2585 TCGv_i64 clean_addr
;
2587 switch (o2_L_o1_o0
) {
2588 case 0x0: /* STXR */
2589 case 0x1: /* STLXR */
2591 gen_check_sp_alignment(s
);
2594 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2596 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2597 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2600 case 0x4: /* LDXR */
2601 case 0x5: /* LDAXR */
2603 gen_check_sp_alignment(s
);
2605 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2607 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2609 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2613 case 0x8: /* STLLR */
2614 if (!dc_isar_feature(aa64_lor
, s
)) {
2617 /* StoreLORelease is the same as Store-Release for QEMU. */
2619 case 0x9: /* STLR */
2620 /* Generate ISS for non-exclusive accesses including LASR. */
2622 gen_check_sp_alignment(s
);
2624 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2625 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2626 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2627 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2630 case 0xc: /* LDLAR */
2631 if (!dc_isar_feature(aa64_lor
, s
)) {
2634 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2636 case 0xd: /* LDAR */
2637 /* Generate ISS for non-exclusive accesses including LASR. */
2639 gen_check_sp_alignment(s
);
2641 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2642 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2643 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2644 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2647 case 0x2: case 0x3: /* CASP / STXP */
2648 if (size
& 2) { /* STXP / STLXP */
2650 gen_check_sp_alignment(s
);
2653 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2655 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2656 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2660 && ((rt
| rs
) & 1) == 0
2661 && dc_isar_feature(aa64_atomics
, s
)) {
2663 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2668 case 0x6: case 0x7: /* CASPA / LDXP */
2669 if (size
& 2) { /* LDXP / LDAXP */
2671 gen_check_sp_alignment(s
);
2673 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2675 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2677 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2682 && ((rt
| rs
) & 1) == 0
2683 && dc_isar_feature(aa64_atomics
, s
)) {
2684 /* CASPA / CASPAL */
2685 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2691 case 0xb: /* CASL */
2692 case 0xe: /* CASA */
2693 case 0xf: /* CASAL */
2694 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2695 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2700 unallocated_encoding(s
);
2704 * Load register (literal)
2706 * 31 30 29 27 26 25 24 23 5 4 0
2707 * +-----+-------+---+-----+-------------------+-------+
2708 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2709 * +-----+-------+---+-----+-------------------+-------+
2711 * V: 1 -> vector (simd/fp)
2712 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2713 * 10-> 32 bit signed, 11 -> prefetch
2714 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2716 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2718 int rt
= extract32(insn
, 0, 5);
2719 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2720 bool is_vector
= extract32(insn
, 26, 1);
2721 int opc
= extract32(insn
, 30, 2);
2722 bool is_signed
= false;
2724 TCGv_i64 tcg_rt
, clean_addr
;
2728 unallocated_encoding(s
);
2732 if (!fp_access_check(s
)) {
2737 /* PRFM (literal) : prefetch */
2740 size
= 2 + extract32(opc
, 0, 1);
2741 is_signed
= extract32(opc
, 1, 1);
2744 tcg_rt
= cpu_reg(s
, rt
);
2746 clean_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2748 do_fp_ld(s
, rt
, clean_addr
, size
);
2750 /* Only unsigned 32bit loads target 32bit registers. */
2751 bool iss_sf
= opc
!= 0;
2753 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2754 true, rt
, iss_sf
, false);
2756 tcg_temp_free_i64(clean_addr
);
2760 * LDNP (Load Pair - non-temporal hint)
2761 * LDP (Load Pair - non vector)
2762 * LDPSW (Load Pair Signed Word - non vector)
2763 * STNP (Store Pair - non-temporal hint)
2764 * STP (Store Pair - non vector)
2765 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2766 * LDP (Load Pair of SIMD&FP)
2767 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2768 * STP (Store Pair of SIMD&FP)
2770 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2771 * +-----+-------+---+---+-------+---+-----------------------------+
2772 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2773 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2775 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2777 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2778 * V: 0 -> GPR, 1 -> Vector
2779 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2780 * 10 -> signed offset, 11 -> pre-index
2781 * L: 0 -> Store 1 -> Load
2783 * Rt, Rt2 = GPR or SIMD registers to be stored
2784 * Rn = general purpose register containing address
2785 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2787 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2789 int rt
= extract32(insn
, 0, 5);
2790 int rn
= extract32(insn
, 5, 5);
2791 int rt2
= extract32(insn
, 10, 5);
2792 uint64_t offset
= sextract64(insn
, 15, 7);
2793 int index
= extract32(insn
, 23, 2);
2794 bool is_vector
= extract32(insn
, 26, 1);
2795 bool is_load
= extract32(insn
, 22, 1);
2796 int opc
= extract32(insn
, 30, 2);
2798 bool is_signed
= false;
2799 bool postindex
= false;
2802 TCGv_i64 clean_addr
, dirty_addr
;
2807 unallocated_encoding(s
);
2814 size
= 2 + extract32(opc
, 1, 1);
2815 is_signed
= extract32(opc
, 0, 1);
2816 if (!is_load
&& is_signed
) {
2817 unallocated_encoding(s
);
2823 case 1: /* post-index */
2828 /* signed offset with "non-temporal" hint. Since we don't emulate
2829 * caches we don't care about hints to the cache system about
2830 * data access patterns, and handle this identically to plain
2834 /* There is no non-temporal-hint version of LDPSW */
2835 unallocated_encoding(s
);
2840 case 2: /* signed offset, rn not updated */
2843 case 3: /* pre-index */
2849 if (is_vector
&& !fp_access_check(s
)) {
2856 gen_check_sp_alignment(s
);
2859 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2861 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2863 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2867 do_fp_ld(s
, rt
, clean_addr
, size
);
2869 do_fp_st(s
, rt
, clean_addr
, size
);
2871 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2873 do_fp_ld(s
, rt2
, clean_addr
, size
);
2875 do_fp_st(s
, rt2
, clean_addr
, size
);
2878 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2879 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2882 TCGv_i64 tmp
= tcg_temp_new_i64();
2884 /* Do not modify tcg_rt before recognizing any exception
2885 * from the second load.
2887 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2888 false, 0, false, false);
2889 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2890 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2891 false, 0, false, false);
2893 tcg_gen_mov_i64(tcg_rt
, tmp
);
2894 tcg_temp_free_i64(tmp
);
2896 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2897 false, 0, false, false);
2898 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2899 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2900 false, 0, false, false);
2906 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2908 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2913 * Load/store (immediate post-indexed)
2914 * Load/store (immediate pre-indexed)
2915 * Load/store (unscaled immediate)
2917 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2918 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2919 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2920 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2922 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2924 * V = 0 -> non-vector
2925 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2926 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2928 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2934 int rn
= extract32(insn
, 5, 5);
2935 int imm9
= sextract32(insn
, 12, 9);
2936 int idx
= extract32(insn
, 10, 2);
2937 bool is_signed
= false;
2938 bool is_store
= false;
2939 bool is_extended
= false;
2940 bool is_unpriv
= (idx
== 2);
2941 bool iss_valid
= !is_vector
;
2945 TCGv_i64 clean_addr
, dirty_addr
;
2948 size
|= (opc
& 2) << 1;
2949 if (size
> 4 || is_unpriv
) {
2950 unallocated_encoding(s
);
2953 is_store
= ((opc
& 1) == 0);
2954 if (!fp_access_check(s
)) {
2958 if (size
== 3 && opc
== 2) {
2959 /* PRFM - prefetch */
2961 unallocated_encoding(s
);
2966 if (opc
== 3 && size
> 1) {
2967 unallocated_encoding(s
);
2970 is_store
= (opc
== 0);
2971 is_signed
= extract32(opc
, 1, 1);
2972 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2990 g_assert_not_reached();
2994 gen_check_sp_alignment(s
);
2997 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2999 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3001 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3005 do_fp_st(s
, rt
, clean_addr
, size
);
3007 do_fp_ld(s
, rt
, clean_addr
, size
);
3010 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3011 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
3012 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3015 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
3016 iss_valid
, rt
, iss_sf
, false);
3018 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
3019 is_signed
, is_extended
, memidx
,
3020 iss_valid
, rt
, iss_sf
, false);
3025 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3027 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3029 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
3034 * Load/store (register offset)
3036 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3037 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3038 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
3039 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3042 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3043 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3045 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3046 * opc<0>: 0 -> store, 1 -> load
3047 * V: 1 -> vector/simd
3048 * opt: extend encoding (see DecodeRegExtend)
3049 * S: if S=1 then scale (essentially index by sizeof(size))
3050 * Rt: register to transfer into/out of
3051 * Rn: address register or SP for base
3052 * Rm: offset register or ZR for offset
3054 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
3060 int rn
= extract32(insn
, 5, 5);
3061 int shift
= extract32(insn
, 12, 1);
3062 int rm
= extract32(insn
, 16, 5);
3063 int opt
= extract32(insn
, 13, 3);
3064 bool is_signed
= false;
3065 bool is_store
= false;
3066 bool is_extended
= false;
3068 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
3070 if (extract32(opt
, 1, 1) == 0) {
3071 unallocated_encoding(s
);
3076 size
|= (opc
& 2) << 1;
3078 unallocated_encoding(s
);
3081 is_store
= !extract32(opc
, 0, 1);
3082 if (!fp_access_check(s
)) {
3086 if (size
== 3 && opc
== 2) {
3087 /* PRFM - prefetch */
3090 if (opc
== 3 && size
> 1) {
3091 unallocated_encoding(s
);
3094 is_store
= (opc
== 0);
3095 is_signed
= extract32(opc
, 1, 1);
3096 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3100 gen_check_sp_alignment(s
);
3102 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3104 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3105 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3107 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3108 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3112 do_fp_st(s
, rt
, clean_addr
, size
);
3114 do_fp_ld(s
, rt
, clean_addr
, size
);
3117 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3118 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3120 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3121 true, rt
, iss_sf
, false);
3123 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3124 is_signed
, is_extended
,
3125 true, rt
, iss_sf
, false);
3131 * Load/store (unsigned immediate)
3133 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3134 * +----+-------+---+-----+-----+------------+-------+------+
3135 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3136 * +----+-------+---+-----+-----+------------+-------+------+
3139 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3140 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3142 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3143 * opc<0>: 0 -> store, 1 -> load
3144 * Rn: base address register (inc SP)
3145 * Rt: target register
3147 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3153 int rn
= extract32(insn
, 5, 5);
3154 unsigned int imm12
= extract32(insn
, 10, 12);
3155 unsigned int offset
;
3157 TCGv_i64 clean_addr
, dirty_addr
;
3160 bool is_signed
= false;
3161 bool is_extended
= false;
3164 size
|= (opc
& 2) << 1;
3166 unallocated_encoding(s
);
3169 is_store
= !extract32(opc
, 0, 1);
3170 if (!fp_access_check(s
)) {
3174 if (size
== 3 && opc
== 2) {
3175 /* PRFM - prefetch */
3178 if (opc
== 3 && size
> 1) {
3179 unallocated_encoding(s
);
3182 is_store
= (opc
== 0);
3183 is_signed
= extract32(opc
, 1, 1);
3184 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3188 gen_check_sp_alignment(s
);
3190 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3191 offset
= imm12
<< size
;
3192 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3193 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3197 do_fp_st(s
, rt
, clean_addr
, size
);
3199 do_fp_ld(s
, rt
, clean_addr
, size
);
3202 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3203 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3205 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3206 true, rt
, iss_sf
, false);
3208 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3209 true, rt
, iss_sf
, false);
3214 /* Atomic memory operations
3216 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3217 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3218 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3219 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3221 * Rt: the result register
3222 * Rn: base address or SP
3223 * Rs: the source register for the operation
3224 * V: vector flag (always 0 as of v8.3)
3228 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3229 int size
, int rt
, bool is_vector
)
3231 int rs
= extract32(insn
, 16, 5);
3232 int rn
= extract32(insn
, 5, 5);
3233 int o3_opc
= extract32(insn
, 12, 4);
3234 TCGv_i64 tcg_rs
, clean_addr
;
3235 AtomicThreeOpFn
*fn
;
3237 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3238 unallocated_encoding(s
);
3242 case 000: /* LDADD */
3243 fn
= tcg_gen_atomic_fetch_add_i64
;
3245 case 001: /* LDCLR */
3246 fn
= tcg_gen_atomic_fetch_and_i64
;
3248 case 002: /* LDEOR */
3249 fn
= tcg_gen_atomic_fetch_xor_i64
;
3251 case 003: /* LDSET */
3252 fn
= tcg_gen_atomic_fetch_or_i64
;
3254 case 004: /* LDSMAX */
3255 fn
= tcg_gen_atomic_fetch_smax_i64
;
3257 case 005: /* LDSMIN */
3258 fn
= tcg_gen_atomic_fetch_smin_i64
;
3260 case 006: /* LDUMAX */
3261 fn
= tcg_gen_atomic_fetch_umax_i64
;
3263 case 007: /* LDUMIN */
3264 fn
= tcg_gen_atomic_fetch_umin_i64
;
3267 fn
= tcg_gen_atomic_xchg_i64
;
3270 unallocated_encoding(s
);
3275 gen_check_sp_alignment(s
);
3277 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
3278 tcg_rs
= read_cpu_reg(s
, rs
, true);
3280 if (o3_opc
== 1) { /* LDCLR */
3281 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3284 /* The tcg atomic primitives are all full barriers. Therefore we
3285 * can ignore the Acquire and Release bits of this instruction.
3287 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3288 s
->be_data
| size
| MO_ALIGN
);
3292 * PAC memory operations
3294 * 31 30 27 26 24 22 21 12 11 10 5 0
3295 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3296 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3297 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3299 * Rt: the result register
3300 * Rn: base address or SP
3301 * V: vector flag (always 0 as of v8.3)
3302 * M: clear for key DA, set for key DB
3303 * W: pre-indexing flag
3306 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3307 int size
, int rt
, bool is_vector
)
3309 int rn
= extract32(insn
, 5, 5);
3310 bool is_wback
= extract32(insn
, 11, 1);
3311 bool use_key_a
= !extract32(insn
, 23, 1);
3313 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3315 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3316 unallocated_encoding(s
);
3321 gen_check_sp_alignment(s
);
3323 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3325 if (s
->pauth_active
) {
3327 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3329 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3333 /* Form the 10-bit signed, scaled offset. */
3334 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3335 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3336 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3338 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3339 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3341 tcg_rt
= cpu_reg(s
, rt
);
3342 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3343 /* extend */ false, /* iss_valid */ !is_wback
,
3344 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3347 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3351 /* Load/store register (all forms) */
3352 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3354 int rt
= extract32(insn
, 0, 5);
3355 int opc
= extract32(insn
, 22, 2);
3356 bool is_vector
= extract32(insn
, 26, 1);
3357 int size
= extract32(insn
, 30, 2);
3359 switch (extract32(insn
, 24, 2)) {
3361 if (extract32(insn
, 21, 1) == 0) {
3362 /* Load/store register (unscaled immediate)
3363 * Load/store immediate pre/post-indexed
3364 * Load/store register unprivileged
3366 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3369 switch (extract32(insn
, 10, 2)) {
3371 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3374 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3377 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3382 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3385 unallocated_encoding(s
);
3388 /* AdvSIMD load/store multiple structures
3390 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3391 * +---+---+---------------+---+-------------+--------+------+------+------+
3392 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3393 * +---+---+---------------+---+-------------+--------+------+------+------+
3395 * AdvSIMD load/store multiple structures (post-indexed)
3397 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3398 * +---+---+---------------+---+---+---------+--------+------+------+------+
3399 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3400 * +---+---+---------------+---+---+---------+--------+------+------+------+
3402 * Rt: first (or only) SIMD&FP register to be transferred
3403 * Rn: base address or SP
3404 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3406 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3408 int rt
= extract32(insn
, 0, 5);
3409 int rn
= extract32(insn
, 5, 5);
3410 int rm
= extract32(insn
, 16, 5);
3411 int size
= extract32(insn
, 10, 2);
3412 int opcode
= extract32(insn
, 12, 4);
3413 bool is_store
= !extract32(insn
, 22, 1);
3414 bool is_postidx
= extract32(insn
, 23, 1);
3415 bool is_q
= extract32(insn
, 30, 1);
3416 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3417 TCGMemOp endian
= s
->be_data
;
3419 int ebytes
; /* bytes per element */
3420 int elements
; /* elements per vector */
3421 int rpt
; /* num iterations */
3422 int selem
; /* structure elements */
3425 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3426 unallocated_encoding(s
);
3430 if (!is_postidx
&& rm
!= 0) {
3431 unallocated_encoding(s
);
3435 /* From the shared decode logic */
3466 unallocated_encoding(s
);
3470 if (size
== 3 && !is_q
&& selem
!= 1) {
3472 unallocated_encoding(s
);
3476 if (!fp_access_check(s
)) {
3481 gen_check_sp_alignment(s
);
3484 /* For our purposes, bytes are always little-endian. */
3489 /* Consecutive little-endian elements from a single register
3490 * can be promoted to a larger little-endian operation.
3492 if (selem
== 1 && endian
== MO_LE
) {
3496 elements
= (is_q
? 16 : 8) / ebytes
;
3498 tcg_rn
= cpu_reg_sp(s
, rn
);
3499 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3500 tcg_ebytes
= tcg_const_i64(ebytes
);
3502 for (r
= 0; r
< rpt
; r
++) {
3504 for (e
= 0; e
< elements
; e
++) {
3506 for (xs
= 0; xs
< selem
; xs
++) {
3507 int tt
= (rt
+ r
+ xs
) % 32;
3509 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3511 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3513 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3517 tcg_temp_free_i64(tcg_ebytes
);
3520 /* For non-quad operations, setting a slice of the low
3521 * 64 bits of the register clears the high 64 bits (in
3522 * the ARM ARM pseudocode this is implicit in the fact
3523 * that 'rval' is a 64 bit wide variable).
3524 * For quad operations, we might still need to zero the
3527 for (r
= 0; r
< rpt
* selem
; r
++) {
3528 int tt
= (rt
+ r
) % 32;
3529 clear_vec_high(s
, is_q
, tt
);
3535 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, rpt
* elements
* selem
* ebytes
);
3537 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3542 /* AdvSIMD load/store single structure
3544 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3545 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3546 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3547 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3549 * AdvSIMD load/store single structure (post-indexed)
3551 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3552 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3553 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3554 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3556 * Rt: first (or only) SIMD&FP register to be transferred
3557 * Rn: base address or SP
3558 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3559 * index = encoded in Q:S:size dependent on size
3561 * lane_size = encoded in R, opc
3562 * transfer width = encoded in opc, S, size
3564 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3566 int rt
= extract32(insn
, 0, 5);
3567 int rn
= extract32(insn
, 5, 5);
3568 int rm
= extract32(insn
, 16, 5);
3569 int size
= extract32(insn
, 10, 2);
3570 int S
= extract32(insn
, 12, 1);
3571 int opc
= extract32(insn
, 13, 3);
3572 int R
= extract32(insn
, 21, 1);
3573 int is_load
= extract32(insn
, 22, 1);
3574 int is_postidx
= extract32(insn
, 23, 1);
3575 int is_q
= extract32(insn
, 30, 1);
3577 int scale
= extract32(opc
, 1, 2);
3578 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3579 bool replicate
= false;
3580 int index
= is_q
<< 3 | S
<< 2 | size
;
3582 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3584 if (extract32(insn
, 31, 1)) {
3585 unallocated_encoding(s
);
3588 if (!is_postidx
&& rm
!= 0) {
3589 unallocated_encoding(s
);
3595 if (!is_load
|| S
) {
3596 unallocated_encoding(s
);
3605 if (extract32(size
, 0, 1)) {
3606 unallocated_encoding(s
);
3612 if (extract32(size
, 1, 1)) {
3613 unallocated_encoding(s
);
3616 if (!extract32(size
, 0, 1)) {
3620 unallocated_encoding(s
);
3628 g_assert_not_reached();
3631 if (!fp_access_check(s
)) {
3635 ebytes
= 1 << scale
;
3638 gen_check_sp_alignment(s
);
3641 tcg_rn
= cpu_reg_sp(s
, rn
);
3642 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3643 tcg_ebytes
= tcg_const_i64(ebytes
);
3645 for (xs
= 0; xs
< selem
; xs
++) {
3647 /* Load and replicate to all elements */
3648 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3650 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3651 get_mem_index(s
), s
->be_data
+ scale
);
3652 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3653 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3655 tcg_temp_free_i64(tcg_tmp
);
3657 /* Load/store one element per register */
3659 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3661 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3664 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3667 tcg_temp_free_i64(tcg_ebytes
);
3671 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, selem
* ebytes
);
3673 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3678 /* Loads and stores */
3679 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3681 switch (extract32(insn
, 24, 6)) {
3682 case 0x08: /* Load/store exclusive */
3683 disas_ldst_excl(s
, insn
);
3685 case 0x18: case 0x1c: /* Load register (literal) */
3686 disas_ld_lit(s
, insn
);
3688 case 0x28: case 0x29:
3689 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3690 disas_ldst_pair(s
, insn
);
3692 case 0x38: case 0x39:
3693 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3694 disas_ldst_reg(s
, insn
);
3696 case 0x0c: /* AdvSIMD load/store multiple structures */
3697 disas_ldst_multiple_struct(s
, insn
);
3699 case 0x0d: /* AdvSIMD load/store single structure */
3700 disas_ldst_single_struct(s
, insn
);
3703 unallocated_encoding(s
);
3708 /* PC-rel. addressing
3709 * 31 30 29 28 24 23 5 4 0
3710 * +----+-------+-----------+-------------------+------+
3711 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3712 * +----+-------+-----------+-------------------+------+
3714 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3716 unsigned int page
, rd
;
3720 page
= extract32(insn
, 31, 1);
3721 /* SignExtend(immhi:immlo) -> offset */
3722 offset
= sextract64(insn
, 5, 19);
3723 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3724 rd
= extract32(insn
, 0, 5);
3728 /* ADRP (page based) */
3733 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3737 * Add/subtract (immediate)
3739 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3740 * +--+--+--+-----------+-----+-------------+-----+-----+
3741 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3742 * +--+--+--+-----------+-----+-------------+-----+-----+
3744 * sf: 0 -> 32bit, 1 -> 64bit
3745 * op: 0 -> add , 1 -> sub
3747 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3749 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3751 int rd
= extract32(insn
, 0, 5);
3752 int rn
= extract32(insn
, 5, 5);
3753 uint64_t imm
= extract32(insn
, 10, 12);
3754 int shift
= extract32(insn
, 22, 2);
3755 bool setflags
= extract32(insn
, 29, 1);
3756 bool sub_op
= extract32(insn
, 30, 1);
3757 bool is_64bit
= extract32(insn
, 31, 1);
3759 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3760 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3761 TCGv_i64 tcg_result
;
3770 unallocated_encoding(s
);
3774 tcg_result
= tcg_temp_new_i64();
3777 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3779 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3782 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3784 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3786 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3788 tcg_temp_free_i64(tcg_imm
);
3792 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3794 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3797 tcg_temp_free_i64(tcg_result
);
3800 /* The input should be a value in the bottom e bits (with higher
3801 * bits zero); returns that value replicated into every element
3802 * of size e in a 64 bit integer.
3804 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3814 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3815 static inline uint64_t bitmask64(unsigned int length
)
3817 assert(length
> 0 && length
<= 64);
3818 return ~0ULL >> (64 - length
);
3821 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3822 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3823 * value (ie should cause a guest UNDEF exception), and true if they are
3824 * valid, in which case the decoded bit pattern is written to result.
3826 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3827 unsigned int imms
, unsigned int immr
)
3830 unsigned e
, levels
, s
, r
;
3833 assert(immn
< 2 && imms
< 64 && immr
< 64);
3835 /* The bit patterns we create here are 64 bit patterns which
3836 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3837 * 64 bits each. Each element contains the same value: a run
3838 * of between 1 and e-1 non-zero bits, rotated within the
3839 * element by between 0 and e-1 bits.
3841 * The element size and run length are encoded into immn (1 bit)
3842 * and imms (6 bits) as follows:
3843 * 64 bit elements: immn = 1, imms = <length of run - 1>
3844 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3845 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3846 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3847 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3848 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3849 * Notice that immn = 0, imms = 11111x is the only combination
3850 * not covered by one of the above options; this is reserved.
3851 * Further, <length of run - 1> all-ones is a reserved pattern.
3853 * In all cases the rotation is by immr % e (and immr is 6 bits).
3856 /* First determine the element size */
3857 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3859 /* This is the immn == 0, imms == 0x11111x case */
3869 /* <length of run - 1> mustn't be all-ones. */
3873 /* Create the value of one element: s+1 set bits rotated
3874 * by r within the element (which is e bits wide)...
3876 mask
= bitmask64(s
+ 1);
3878 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3879 mask
&= bitmask64(e
);
3881 /* ...then replicate the element over the whole 64 bit value */
3882 mask
= bitfield_replicate(mask
, e
);
3887 /* Logical (immediate)
3888 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3889 * +----+-----+-------------+---+------+------+------+------+
3890 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3891 * +----+-----+-------------+---+------+------+------+------+
3893 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3895 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3896 TCGv_i64 tcg_rd
, tcg_rn
;
3898 bool is_and
= false;
3900 sf
= extract32(insn
, 31, 1);
3901 opc
= extract32(insn
, 29, 2);
3902 is_n
= extract32(insn
, 22, 1);
3903 immr
= extract32(insn
, 16, 6);
3904 imms
= extract32(insn
, 10, 6);
3905 rn
= extract32(insn
, 5, 5);
3906 rd
= extract32(insn
, 0, 5);
3909 unallocated_encoding(s
);
3913 if (opc
== 0x3) { /* ANDS */
3914 tcg_rd
= cpu_reg(s
, rd
);
3916 tcg_rd
= cpu_reg_sp(s
, rd
);
3918 tcg_rn
= cpu_reg(s
, rn
);
3920 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3921 /* some immediate field values are reserved */
3922 unallocated_encoding(s
);
3927 wmask
&= 0xffffffff;
3931 case 0x3: /* ANDS */
3933 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3937 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3940 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3943 assert(FALSE
); /* must handle all above */
3947 if (!sf
&& !is_and
) {
3948 /* zero extend final result; we know we can skip this for AND
3949 * since the immediate had the high 32 bits clear.
3951 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3954 if (opc
== 3) { /* ANDS */
3955 gen_logic_CC(sf
, tcg_rd
);
3960 * Move wide (immediate)
3962 * 31 30 29 28 23 22 21 20 5 4 0
3963 * +--+-----+-------------+-----+----------------+------+
3964 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3965 * +--+-----+-------------+-----+----------------+------+
3967 * sf: 0 -> 32 bit, 1 -> 64 bit
3968 * opc: 00 -> N, 10 -> Z, 11 -> K
3969 * hw: shift/16 (0,16, and sf only 32, 48)
3971 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3973 int rd
= extract32(insn
, 0, 5);
3974 uint64_t imm
= extract32(insn
, 5, 16);
3975 int sf
= extract32(insn
, 31, 1);
3976 int opc
= extract32(insn
, 29, 2);
3977 int pos
= extract32(insn
, 21, 2) << 4;
3978 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3981 if (!sf
&& (pos
>= 32)) {
3982 unallocated_encoding(s
);
3996 tcg_gen_movi_i64(tcg_rd
, imm
);
3999 tcg_imm
= tcg_const_i64(imm
);
4000 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
4001 tcg_temp_free_i64(tcg_imm
);
4003 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4007 unallocated_encoding(s
);
4013 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4014 * +----+-----+-------------+---+------+------+------+------+
4015 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4016 * +----+-----+-------------+---+------+------+------+------+
4018 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4020 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4021 TCGv_i64 tcg_rd
, tcg_tmp
;
4023 sf
= extract32(insn
, 31, 1);
4024 opc
= extract32(insn
, 29, 2);
4025 n
= extract32(insn
, 22, 1);
4026 ri
= extract32(insn
, 16, 6);
4027 si
= extract32(insn
, 10, 6);
4028 rn
= extract32(insn
, 5, 5);
4029 rd
= extract32(insn
, 0, 5);
4030 bitsize
= sf
? 64 : 32;
4032 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4033 unallocated_encoding(s
);
4037 tcg_rd
= cpu_reg(s
, rd
);
4039 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4040 to be smaller than bitsize, we'll never reference data outside the
4041 low 32-bits anyway. */
4042 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4044 /* Recognize simple(r) extractions. */
4046 /* Wd<s-r:0> = Wn<s:r> */
4047 len
= (si
- ri
) + 1;
4048 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4049 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4051 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4052 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4055 /* opc == 1, BFXIL fall through to deposit */
4056 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4059 /* Handle the ri > si case with a deposit
4060 * Wd<32+s-r,32-r> = Wn<s:0>
4063 pos
= (bitsize
- ri
) & (bitsize
- 1);
4066 if (opc
== 0 && len
< ri
) {
4067 /* SBFM: sign extend the destination field from len to fill
4068 the balance of the word. Let the deposit below insert all
4069 of those sign bits. */
4070 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4074 if (opc
== 1) { /* BFM, BFXIL */
4075 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4077 /* SBFM or UBFM: We start with zero, and we haven't modified
4078 any bits outside bitsize, therefore the zero-extension
4079 below is unneeded. */
4080 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4085 if (!sf
) { /* zero extend final result */
4086 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4091 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4092 * +----+------+-------------+---+----+------+--------+------+------+
4093 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4094 * +----+------+-------------+---+----+------+--------+------+------+
4096 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4098 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4100 sf
= extract32(insn
, 31, 1);
4101 n
= extract32(insn
, 22, 1);
4102 rm
= extract32(insn
, 16, 5);
4103 imm
= extract32(insn
, 10, 6);
4104 rn
= extract32(insn
, 5, 5);
4105 rd
= extract32(insn
, 0, 5);
4106 op21
= extract32(insn
, 29, 2);
4107 op0
= extract32(insn
, 21, 1);
4108 bitsize
= sf
? 64 : 32;
4110 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4111 unallocated_encoding(s
);
4113 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4115 tcg_rd
= cpu_reg(s
, rd
);
4117 if (unlikely(imm
== 0)) {
4118 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4119 * so an extract from bit 0 is a special case.
4122 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4124 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4127 tcg_rm
= cpu_reg(s
, rm
);
4128 tcg_rn
= cpu_reg(s
, rn
);
4131 /* Specialization to ROR happens in EXTRACT2. */
4132 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4134 TCGv_i32 t0
= tcg_temp_new_i32();
4136 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4138 tcg_gen_rotri_i32(t0
, t0
, imm
);
4140 TCGv_i32 t1
= tcg_temp_new_i32();
4141 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4142 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4143 tcg_temp_free_i32(t1
);
4145 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4146 tcg_temp_free_i32(t0
);
4152 /* Data processing - immediate */
4153 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4155 switch (extract32(insn
, 23, 6)) {
4156 case 0x20: case 0x21: /* PC-rel. addressing */
4157 disas_pc_rel_adr(s
, insn
);
4159 case 0x22: case 0x23: /* Add/subtract (immediate) */
4160 disas_add_sub_imm(s
, insn
);
4162 case 0x24: /* Logical (immediate) */
4163 disas_logic_imm(s
, insn
);
4165 case 0x25: /* Move wide (immediate) */
4166 disas_movw_imm(s
, insn
);
4168 case 0x26: /* Bitfield */
4169 disas_bitfield(s
, insn
);
4171 case 0x27: /* Extract */
4172 disas_extract(s
, insn
);
4175 unallocated_encoding(s
);
4180 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4181 * Note that it is the caller's responsibility to ensure that the
4182 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4183 * mandated semantics for out of range shifts.
4185 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4186 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4188 switch (shift_type
) {
4189 case A64_SHIFT_TYPE_LSL
:
4190 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4192 case A64_SHIFT_TYPE_LSR
:
4193 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4195 case A64_SHIFT_TYPE_ASR
:
4197 tcg_gen_ext32s_i64(dst
, src
);
4199 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4201 case A64_SHIFT_TYPE_ROR
:
4203 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4206 t0
= tcg_temp_new_i32();
4207 t1
= tcg_temp_new_i32();
4208 tcg_gen_extrl_i64_i32(t0
, src
);
4209 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4210 tcg_gen_rotr_i32(t0
, t0
, t1
);
4211 tcg_gen_extu_i32_i64(dst
, t0
);
4212 tcg_temp_free_i32(t0
);
4213 tcg_temp_free_i32(t1
);
4217 assert(FALSE
); /* all shift types should be handled */
4221 if (!sf
) { /* zero extend final result */
4222 tcg_gen_ext32u_i64(dst
, dst
);
4226 /* Shift a TCGv src by immediate, put result in dst.
4227 * The shift amount must be in range (this should always be true as the
4228 * relevant instructions will UNDEF on bad shift immediates).
4230 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4231 enum a64_shift_type shift_type
, unsigned int shift_i
)
4233 assert(shift_i
< (sf
? 64 : 32));
4236 tcg_gen_mov_i64(dst
, src
);
4238 TCGv_i64 shift_const
;
4240 shift_const
= tcg_const_i64(shift_i
);
4241 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4242 tcg_temp_free_i64(shift_const
);
4246 /* Logical (shifted register)
4247 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4248 * +----+-----+-----------+-------+---+------+--------+------+------+
4249 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4250 * +----+-----+-----------+-------+---+------+--------+------+------+
4252 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4254 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4255 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4257 sf
= extract32(insn
, 31, 1);
4258 opc
= extract32(insn
, 29, 2);
4259 shift_type
= extract32(insn
, 22, 2);
4260 invert
= extract32(insn
, 21, 1);
4261 rm
= extract32(insn
, 16, 5);
4262 shift_amount
= extract32(insn
, 10, 6);
4263 rn
= extract32(insn
, 5, 5);
4264 rd
= extract32(insn
, 0, 5);
4266 if (!sf
&& (shift_amount
& (1 << 5))) {
4267 unallocated_encoding(s
);
4271 tcg_rd
= cpu_reg(s
, rd
);
4273 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4274 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4275 * register-register MOV and MVN, so it is worth special casing.
4277 tcg_rm
= cpu_reg(s
, rm
);
4279 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4281 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4285 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4287 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4293 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4296 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4299 tcg_rn
= cpu_reg(s
, rn
);
4301 switch (opc
| (invert
<< 2)) {
4304 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4307 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4310 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4314 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4317 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4320 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4328 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4332 gen_logic_CC(sf
, tcg_rd
);
4337 * Add/subtract (extended register)
4339 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4340 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4341 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4342 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4344 * sf: 0 -> 32bit, 1 -> 64bit
4345 * op: 0 -> add , 1 -> sub
4348 * option: extension type (see DecodeRegExtend)
4349 * imm3: optional shift to Rm
4351 * Rd = Rn + LSL(extend(Rm), amount)
4353 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4355 int rd
= extract32(insn
, 0, 5);
4356 int rn
= extract32(insn
, 5, 5);
4357 int imm3
= extract32(insn
, 10, 3);
4358 int option
= extract32(insn
, 13, 3);
4359 int rm
= extract32(insn
, 16, 5);
4360 int opt
= extract32(insn
, 22, 2);
4361 bool setflags
= extract32(insn
, 29, 1);
4362 bool sub_op
= extract32(insn
, 30, 1);
4363 bool sf
= extract32(insn
, 31, 1);
4365 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4367 TCGv_i64 tcg_result
;
4369 if (imm3
> 4 || opt
!= 0) {
4370 unallocated_encoding(s
);
4374 /* non-flag setting ops may use SP */
4376 tcg_rd
= cpu_reg_sp(s
, rd
);
4378 tcg_rd
= cpu_reg(s
, rd
);
4380 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4382 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4383 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4385 tcg_result
= tcg_temp_new_i64();
4389 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4391 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4395 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4397 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4402 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4404 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4407 tcg_temp_free_i64(tcg_result
);
4411 * Add/subtract (shifted register)
4413 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4414 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4415 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4416 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4418 * sf: 0 -> 32bit, 1 -> 64bit
4419 * op: 0 -> add , 1 -> sub
4421 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4422 * imm6: Shift amount to apply to Rm before the add/sub
4424 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4426 int rd
= extract32(insn
, 0, 5);
4427 int rn
= extract32(insn
, 5, 5);
4428 int imm6
= extract32(insn
, 10, 6);
4429 int rm
= extract32(insn
, 16, 5);
4430 int shift_type
= extract32(insn
, 22, 2);
4431 bool setflags
= extract32(insn
, 29, 1);
4432 bool sub_op
= extract32(insn
, 30, 1);
4433 bool sf
= extract32(insn
, 31, 1);
4435 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4436 TCGv_i64 tcg_rn
, tcg_rm
;
4437 TCGv_i64 tcg_result
;
4439 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4440 unallocated_encoding(s
);
4444 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4445 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4447 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4449 tcg_result
= tcg_temp_new_i64();
4453 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4455 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4459 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4461 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4466 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4468 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4471 tcg_temp_free_i64(tcg_result
);
4474 /* Data-processing (3 source)
4476 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4477 * +--+------+-----------+------+------+----+------+------+------+
4478 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4479 * +--+------+-----------+------+------+----+------+------+------+
4481 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4483 int rd
= extract32(insn
, 0, 5);
4484 int rn
= extract32(insn
, 5, 5);
4485 int ra
= extract32(insn
, 10, 5);
4486 int rm
= extract32(insn
, 16, 5);
4487 int op_id
= (extract32(insn
, 29, 3) << 4) |
4488 (extract32(insn
, 21, 3) << 1) |
4489 extract32(insn
, 15, 1);
4490 bool sf
= extract32(insn
, 31, 1);
4491 bool is_sub
= extract32(op_id
, 0, 1);
4492 bool is_high
= extract32(op_id
, 2, 1);
4493 bool is_signed
= false;
4498 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4500 case 0x42: /* SMADDL */
4501 case 0x43: /* SMSUBL */
4502 case 0x44: /* SMULH */
4505 case 0x0: /* MADD (32bit) */
4506 case 0x1: /* MSUB (32bit) */
4507 case 0x40: /* MADD (64bit) */
4508 case 0x41: /* MSUB (64bit) */
4509 case 0x4a: /* UMADDL */
4510 case 0x4b: /* UMSUBL */
4511 case 0x4c: /* UMULH */
4514 unallocated_encoding(s
);
4519 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4520 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4521 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4522 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4525 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4527 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4530 tcg_temp_free_i64(low_bits
);
4534 tcg_op1
= tcg_temp_new_i64();
4535 tcg_op2
= tcg_temp_new_i64();
4536 tcg_tmp
= tcg_temp_new_i64();
4539 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4540 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4543 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4544 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4546 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4547 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4551 if (ra
== 31 && !is_sub
) {
4552 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4553 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4555 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4557 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4559 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4564 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4567 tcg_temp_free_i64(tcg_op1
);
4568 tcg_temp_free_i64(tcg_op2
);
4569 tcg_temp_free_i64(tcg_tmp
);
4572 /* Add/subtract (with carry)
4573 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4574 * +--+--+--+------------------------+------+-------------+------+-----+
4575 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
4576 * +--+--+--+------------------------+------+-------------+------+-----+
4579 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4581 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4582 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4584 sf
= extract32(insn
, 31, 1);
4585 op
= extract32(insn
, 30, 1);
4586 setflags
= extract32(insn
, 29, 1);
4587 rm
= extract32(insn
, 16, 5);
4588 rn
= extract32(insn
, 5, 5);
4589 rd
= extract32(insn
, 0, 5);
4591 tcg_rd
= cpu_reg(s
, rd
);
4592 tcg_rn
= cpu_reg(s
, rn
);
4595 tcg_y
= new_tmp_a64(s
);
4596 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4598 tcg_y
= cpu_reg(s
, rm
);
4602 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4604 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4609 * Rotate right into flags
4610 * 31 30 29 21 15 10 5 4 0
4611 * +--+--+--+-----------------+--------+-----------+------+--+------+
4612 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
4613 * +--+--+--+-----------------+--------+-----------+------+--+------+
4615 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
4617 int mask
= extract32(insn
, 0, 4);
4618 int o2
= extract32(insn
, 4, 1);
4619 int rn
= extract32(insn
, 5, 5);
4620 int imm6
= extract32(insn
, 15, 6);
4621 int sf_op_s
= extract32(insn
, 29, 3);
4625 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
4626 unallocated_encoding(s
);
4630 tcg_rn
= read_cpu_reg(s
, rn
, 1);
4631 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
4633 nzcv
= tcg_temp_new_i32();
4634 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
4636 if (mask
& 8) { /* N */
4637 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
4639 if (mask
& 4) { /* Z */
4640 tcg_gen_not_i32(cpu_ZF
, nzcv
);
4641 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
4643 if (mask
& 2) { /* C */
4644 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
4646 if (mask
& 1) { /* V */
4647 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
4650 tcg_temp_free_i32(nzcv
);
4654 * Evaluate into flags
4655 * 31 30 29 21 15 14 10 5 4 0
4656 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4657 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
4658 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4660 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
4662 int o3_mask
= extract32(insn
, 0, 5);
4663 int rn
= extract32(insn
, 5, 5);
4664 int o2
= extract32(insn
, 15, 6);
4665 int sz
= extract32(insn
, 14, 1);
4666 int sf_op_s
= extract32(insn
, 29, 3);
4670 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
4671 !dc_isar_feature(aa64_condm_4
, s
)) {
4672 unallocated_encoding(s
);
4675 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
4677 tmp
= tcg_temp_new_i32();
4678 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
4679 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
4680 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
4681 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
4682 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
4683 tcg_temp_free_i32(tmp
);
4686 /* Conditional compare (immediate / register)
4687 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4688 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4689 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4690 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4693 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4695 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4696 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4697 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4700 if (!extract32(insn
, 29, 1)) {
4701 unallocated_encoding(s
);
4704 if (insn
& (1 << 10 | 1 << 4)) {
4705 unallocated_encoding(s
);
4708 sf
= extract32(insn
, 31, 1);
4709 op
= extract32(insn
, 30, 1);
4710 is_imm
= extract32(insn
, 11, 1);
4711 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4712 cond
= extract32(insn
, 12, 4);
4713 rn
= extract32(insn
, 5, 5);
4714 nzcv
= extract32(insn
, 0, 4);
4716 /* Set T0 = !COND. */
4717 tcg_t0
= tcg_temp_new_i32();
4718 arm_test_cc(&c
, cond
);
4719 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4722 /* Load the arguments for the new comparison. */
4724 tcg_y
= new_tmp_a64(s
);
4725 tcg_gen_movi_i64(tcg_y
, y
);
4727 tcg_y
= cpu_reg(s
, y
);
4729 tcg_rn
= cpu_reg(s
, rn
);
4731 /* Set the flags for the new comparison. */
4732 tcg_tmp
= tcg_temp_new_i64();
4734 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4736 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4738 tcg_temp_free_i64(tcg_tmp
);
4740 /* If COND was false, force the flags to #nzcv. Compute two masks
4741 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4742 * For tcg hosts that support ANDC, we can make do with just T1.
4743 * In either case, allow the tcg optimizer to delete any unused mask.
4745 tcg_t1
= tcg_temp_new_i32();
4746 tcg_t2
= tcg_temp_new_i32();
4747 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4748 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4750 if (nzcv
& 8) { /* N */
4751 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4753 if (TCG_TARGET_HAS_andc_i32
) {
4754 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4756 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4759 if (nzcv
& 4) { /* Z */
4760 if (TCG_TARGET_HAS_andc_i32
) {
4761 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4763 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4766 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4768 if (nzcv
& 2) { /* C */
4769 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4771 if (TCG_TARGET_HAS_andc_i32
) {
4772 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4774 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4777 if (nzcv
& 1) { /* V */
4778 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4780 if (TCG_TARGET_HAS_andc_i32
) {
4781 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4783 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4786 tcg_temp_free_i32(tcg_t0
);
4787 tcg_temp_free_i32(tcg_t1
);
4788 tcg_temp_free_i32(tcg_t2
);
4791 /* Conditional select
4792 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4793 * +----+----+---+-----------------+------+------+-----+------+------+
4794 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4795 * +----+----+---+-----------------+------+------+-----+------+------+
4797 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4799 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4800 TCGv_i64 tcg_rd
, zero
;
4803 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4804 /* S == 1 or op2<1> == 1 */
4805 unallocated_encoding(s
);
4808 sf
= extract32(insn
, 31, 1);
4809 else_inv
= extract32(insn
, 30, 1);
4810 rm
= extract32(insn
, 16, 5);
4811 cond
= extract32(insn
, 12, 4);
4812 else_inc
= extract32(insn
, 10, 1);
4813 rn
= extract32(insn
, 5, 5);
4814 rd
= extract32(insn
, 0, 5);
4816 tcg_rd
= cpu_reg(s
, rd
);
4818 a64_test_cc(&c
, cond
);
4819 zero
= tcg_const_i64(0);
4821 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4823 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4825 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4828 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4829 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4830 if (else_inv
&& else_inc
) {
4831 tcg_gen_neg_i64(t_false
, t_false
);
4832 } else if (else_inv
) {
4833 tcg_gen_not_i64(t_false
, t_false
);
4834 } else if (else_inc
) {
4835 tcg_gen_addi_i64(t_false
, t_false
, 1);
4837 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4840 tcg_temp_free_i64(zero
);
4844 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4848 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4849 unsigned int rn
, unsigned int rd
)
4851 TCGv_i64 tcg_rd
, tcg_rn
;
4852 tcg_rd
= cpu_reg(s
, rd
);
4853 tcg_rn
= cpu_reg(s
, rn
);
4856 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4858 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4859 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4860 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4861 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4862 tcg_temp_free_i32(tcg_tmp32
);
4866 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4867 unsigned int rn
, unsigned int rd
)
4869 TCGv_i64 tcg_rd
, tcg_rn
;
4870 tcg_rd
= cpu_reg(s
, rd
);
4871 tcg_rn
= cpu_reg(s
, rn
);
4874 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4876 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4877 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4878 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4879 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4880 tcg_temp_free_i32(tcg_tmp32
);
4884 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4885 unsigned int rn
, unsigned int rd
)
4887 TCGv_i64 tcg_rd
, tcg_rn
;
4888 tcg_rd
= cpu_reg(s
, rd
);
4889 tcg_rn
= cpu_reg(s
, rn
);
4892 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4894 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4895 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4896 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4897 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4898 tcg_temp_free_i32(tcg_tmp32
);
4902 /* REV with sf==1, opcode==3 ("REV64") */
4903 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4904 unsigned int rn
, unsigned int rd
)
4907 unallocated_encoding(s
);
4910 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4913 /* REV with sf==0, opcode==2
4914 * REV32 (sf==1, opcode==2)
4916 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4917 unsigned int rn
, unsigned int rd
)
4919 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4922 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4923 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4925 /* bswap32_i64 requires zero high word */
4926 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4927 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4928 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4929 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4930 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4932 tcg_temp_free_i64(tcg_tmp
);
4934 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4935 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4939 /* REV16 (opcode==1) */
4940 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4941 unsigned int rn
, unsigned int rd
)
4943 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4944 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4945 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4946 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4948 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4949 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4950 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4951 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4952 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4954 tcg_temp_free_i64(mask
);
4955 tcg_temp_free_i64(tcg_tmp
);
4958 /* Data-processing (1 source)
4959 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4960 * +----+---+---+-----------------+---------+--------+------+------+
4961 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4962 * +----+---+---+-----------------+---------+--------+------+------+
4964 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4966 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
4969 if (extract32(insn
, 29, 1)) {
4970 unallocated_encoding(s
);
4974 sf
= extract32(insn
, 31, 1);
4975 opcode
= extract32(insn
, 10, 6);
4976 opcode2
= extract32(insn
, 16, 5);
4977 rn
= extract32(insn
, 5, 5);
4978 rd
= extract32(insn
, 0, 5);
4980 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
4982 switch (MAP(sf
, opcode2
, opcode
)) {
4983 case MAP(0, 0x00, 0x00): /* RBIT */
4984 case MAP(1, 0x00, 0x00):
4985 handle_rbit(s
, sf
, rn
, rd
);
4987 case MAP(0, 0x00, 0x01): /* REV16 */
4988 case MAP(1, 0x00, 0x01):
4989 handle_rev16(s
, sf
, rn
, rd
);
4991 case MAP(0, 0x00, 0x02): /* REV/REV32 */
4992 case MAP(1, 0x00, 0x02):
4993 handle_rev32(s
, sf
, rn
, rd
);
4995 case MAP(1, 0x00, 0x03): /* REV64 */
4996 handle_rev64(s
, sf
, rn
, rd
);
4998 case MAP(0, 0x00, 0x04): /* CLZ */
4999 case MAP(1, 0x00, 0x04):
5000 handle_clz(s
, sf
, rn
, rd
);
5002 case MAP(0, 0x00, 0x05): /* CLS */
5003 case MAP(1, 0x00, 0x05):
5004 handle_cls(s
, sf
, rn
, rd
);
5006 case MAP(1, 0x01, 0x00): /* PACIA */
5007 if (s
->pauth_active
) {
5008 tcg_rd
= cpu_reg(s
, rd
);
5009 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5010 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5011 goto do_unallocated
;
5014 case MAP(1, 0x01, 0x01): /* PACIB */
5015 if (s
->pauth_active
) {
5016 tcg_rd
= cpu_reg(s
, rd
);
5017 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5018 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5019 goto do_unallocated
;
5022 case MAP(1, 0x01, 0x02): /* PACDA */
5023 if (s
->pauth_active
) {
5024 tcg_rd
= cpu_reg(s
, rd
);
5025 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5026 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5027 goto do_unallocated
;
5030 case MAP(1, 0x01, 0x03): /* PACDB */
5031 if (s
->pauth_active
) {
5032 tcg_rd
= cpu_reg(s
, rd
);
5033 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5034 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5035 goto do_unallocated
;
5038 case MAP(1, 0x01, 0x04): /* AUTIA */
5039 if (s
->pauth_active
) {
5040 tcg_rd
= cpu_reg(s
, rd
);
5041 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5042 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5043 goto do_unallocated
;
5046 case MAP(1, 0x01, 0x05): /* AUTIB */
5047 if (s
->pauth_active
) {
5048 tcg_rd
= cpu_reg(s
, rd
);
5049 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5050 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5051 goto do_unallocated
;
5054 case MAP(1, 0x01, 0x06): /* AUTDA */
5055 if (s
->pauth_active
) {
5056 tcg_rd
= cpu_reg(s
, rd
);
5057 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5058 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5059 goto do_unallocated
;
5062 case MAP(1, 0x01, 0x07): /* AUTDB */
5063 if (s
->pauth_active
) {
5064 tcg_rd
= cpu_reg(s
, rd
);
5065 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5066 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5067 goto do_unallocated
;
5070 case MAP(1, 0x01, 0x08): /* PACIZA */
5071 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5072 goto do_unallocated
;
5073 } else if (s
->pauth_active
) {
5074 tcg_rd
= cpu_reg(s
, rd
);
5075 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5078 case MAP(1, 0x01, 0x09): /* PACIZB */
5079 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5080 goto do_unallocated
;
5081 } else if (s
->pauth_active
) {
5082 tcg_rd
= cpu_reg(s
, rd
);
5083 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5086 case MAP(1, 0x01, 0x0a): /* PACDZA */
5087 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5088 goto do_unallocated
;
5089 } else if (s
->pauth_active
) {
5090 tcg_rd
= cpu_reg(s
, rd
);
5091 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5094 case MAP(1, 0x01, 0x0b): /* PACDZB */
5095 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5096 goto do_unallocated
;
5097 } else if (s
->pauth_active
) {
5098 tcg_rd
= cpu_reg(s
, rd
);
5099 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5102 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5103 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5104 goto do_unallocated
;
5105 } else if (s
->pauth_active
) {
5106 tcg_rd
= cpu_reg(s
, rd
);
5107 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5110 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5111 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5112 goto do_unallocated
;
5113 } else if (s
->pauth_active
) {
5114 tcg_rd
= cpu_reg(s
, rd
);
5115 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5118 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5119 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5120 goto do_unallocated
;
5121 } else if (s
->pauth_active
) {
5122 tcg_rd
= cpu_reg(s
, rd
);
5123 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5126 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5127 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5128 goto do_unallocated
;
5129 } else if (s
->pauth_active
) {
5130 tcg_rd
= cpu_reg(s
, rd
);
5131 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5134 case MAP(1, 0x01, 0x10): /* XPACI */
5135 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5136 goto do_unallocated
;
5137 } else if (s
->pauth_active
) {
5138 tcg_rd
= cpu_reg(s
, rd
);
5139 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5142 case MAP(1, 0x01, 0x11): /* XPACD */
5143 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5144 goto do_unallocated
;
5145 } else if (s
->pauth_active
) {
5146 tcg_rd
= cpu_reg(s
, rd
);
5147 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5152 unallocated_encoding(s
);
5159 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5160 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5162 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5163 tcg_rd
= cpu_reg(s
, rd
);
5165 if (!sf
&& is_signed
) {
5166 tcg_n
= new_tmp_a64(s
);
5167 tcg_m
= new_tmp_a64(s
);
5168 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5169 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5171 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5172 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5176 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5178 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5181 if (!sf
) { /* zero extend final result */
5182 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5186 /* LSLV, LSRV, ASRV, RORV */
5187 static void handle_shift_reg(DisasContext
*s
,
5188 enum a64_shift_type shift_type
, unsigned int sf
,
5189 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5191 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5192 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5193 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5195 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5196 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5197 tcg_temp_free_i64(tcg_shift
);
5200 /* CRC32[BHWX], CRC32C[BHWX] */
5201 static void handle_crc32(DisasContext
*s
,
5202 unsigned int sf
, unsigned int sz
, bool crc32c
,
5203 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5205 TCGv_i64 tcg_acc
, tcg_val
;
5208 if (!dc_isar_feature(aa64_crc32
, s
)
5209 || (sf
== 1 && sz
!= 3)
5210 || (sf
== 0 && sz
== 3)) {
5211 unallocated_encoding(s
);
5216 tcg_val
= cpu_reg(s
, rm
);
5230 g_assert_not_reached();
5232 tcg_val
= new_tmp_a64(s
);
5233 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5236 tcg_acc
= cpu_reg(s
, rn
);
5237 tcg_bytes
= tcg_const_i32(1 << sz
);
5240 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5242 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5245 tcg_temp_free_i32(tcg_bytes
);
5248 /* Data-processing (2 source)
5249 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5250 * +----+---+---+-----------------+------+--------+------+------+
5251 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5252 * +----+---+---+-----------------+------+--------+------+------+
5254 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5256 unsigned int sf
, rm
, opcode
, rn
, rd
;
5257 sf
= extract32(insn
, 31, 1);
5258 rm
= extract32(insn
, 16, 5);
5259 opcode
= extract32(insn
, 10, 6);
5260 rn
= extract32(insn
, 5, 5);
5261 rd
= extract32(insn
, 0, 5);
5263 if (extract32(insn
, 29, 1)) {
5264 unallocated_encoding(s
);
5270 handle_div(s
, false, sf
, rm
, rn
, rd
);
5273 handle_div(s
, true, sf
, rm
, rn
, rd
);
5276 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5279 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5282 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5285 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5287 case 12: /* PACGA */
5288 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5289 goto do_unallocated
;
5291 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5292 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5301 case 23: /* CRC32 */
5303 int sz
= extract32(opcode
, 0, 2);
5304 bool crc32c
= extract32(opcode
, 2, 1);
5305 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5310 unallocated_encoding(s
);
5316 * Data processing - register
5317 * 31 30 29 28 25 21 20 16 10 0
5318 * +--+---+--+---+-------+-----+-------+-------+---------+
5319 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5320 * +--+---+--+---+-------+-----+-------+-------+---------+
5322 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5324 int op0
= extract32(insn
, 30, 1);
5325 int op1
= extract32(insn
, 28, 1);
5326 int op2
= extract32(insn
, 21, 4);
5327 int op3
= extract32(insn
, 10, 6);
5332 /* Add/sub (extended register) */
5333 disas_add_sub_ext_reg(s
, insn
);
5335 /* Add/sub (shifted register) */
5336 disas_add_sub_reg(s
, insn
);
5339 /* Logical (shifted register) */
5340 disas_logic_reg(s
, insn
);
5348 case 0x00: /* Add/subtract (with carry) */
5349 disas_adc_sbc(s
, insn
);
5352 case 0x01: /* Rotate right into flags */
5354 disas_rotate_right_into_flags(s
, insn
);
5357 case 0x02: /* Evaluate into flags */
5361 disas_evaluate_into_flags(s
, insn
);
5365 goto do_unallocated
;
5369 case 0x2: /* Conditional compare */
5370 disas_cc(s
, insn
); /* both imm and reg forms */
5373 case 0x4: /* Conditional select */
5374 disas_cond_select(s
, insn
);
5377 case 0x6: /* Data-processing */
5378 if (op0
) { /* (1 source) */
5379 disas_data_proc_1src(s
, insn
);
5380 } else { /* (2 source) */
5381 disas_data_proc_2src(s
, insn
);
5384 case 0x8 ... 0xf: /* (3 source) */
5385 disas_data_proc_3src(s
, insn
);
5390 unallocated_encoding(s
);
5395 static void handle_fp_compare(DisasContext
*s
, int size
,
5396 unsigned int rn
, unsigned int rm
,
5397 bool cmp_with_zero
, bool signal_all_nans
)
5399 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5400 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5402 if (size
== MO_64
) {
5403 TCGv_i64 tcg_vn
, tcg_vm
;
5405 tcg_vn
= read_fp_dreg(s
, rn
);
5406 if (cmp_with_zero
) {
5407 tcg_vm
= tcg_const_i64(0);
5409 tcg_vm
= read_fp_dreg(s
, rm
);
5411 if (signal_all_nans
) {
5412 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5414 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5416 tcg_temp_free_i64(tcg_vn
);
5417 tcg_temp_free_i64(tcg_vm
);
5419 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5420 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5422 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5423 if (cmp_with_zero
) {
5424 tcg_gen_movi_i32(tcg_vm
, 0);
5426 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5431 if (signal_all_nans
) {
5432 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5434 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5438 if (signal_all_nans
) {
5439 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5441 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5445 g_assert_not_reached();
5448 tcg_temp_free_i32(tcg_vn
);
5449 tcg_temp_free_i32(tcg_vm
);
5452 tcg_temp_free_ptr(fpst
);
5454 gen_set_nzcv(tcg_flags
);
5456 tcg_temp_free_i64(tcg_flags
);
5459 /* Floating point compare
5460 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5461 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5462 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5463 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5465 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5467 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5470 mos
= extract32(insn
, 29, 3);
5471 type
= extract32(insn
, 22, 2);
5472 rm
= extract32(insn
, 16, 5);
5473 op
= extract32(insn
, 14, 2);
5474 rn
= extract32(insn
, 5, 5);
5475 opc
= extract32(insn
, 3, 2);
5476 op2r
= extract32(insn
, 0, 3);
5478 if (mos
|| op
|| op2r
) {
5479 unallocated_encoding(s
);
5492 if (dc_isar_feature(aa64_fp16
, s
)) {
5497 unallocated_encoding(s
);
5501 if (!fp_access_check(s
)) {
5505 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5508 /* Floating point conditional compare
5509 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5510 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5511 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5512 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5514 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5516 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5518 TCGLabel
*label_continue
= NULL
;
5521 mos
= extract32(insn
, 29, 3);
5522 type
= extract32(insn
, 22, 2);
5523 rm
= extract32(insn
, 16, 5);
5524 cond
= extract32(insn
, 12, 4);
5525 rn
= extract32(insn
, 5, 5);
5526 op
= extract32(insn
, 4, 1);
5527 nzcv
= extract32(insn
, 0, 4);
5530 unallocated_encoding(s
);
5543 if (dc_isar_feature(aa64_fp16
, s
)) {
5548 unallocated_encoding(s
);
5552 if (!fp_access_check(s
)) {
5556 if (cond
< 0x0e) { /* not always */
5557 TCGLabel
*label_match
= gen_new_label();
5558 label_continue
= gen_new_label();
5559 arm_gen_test_cc(cond
, label_match
);
5561 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5562 gen_set_nzcv(tcg_flags
);
5563 tcg_temp_free_i64(tcg_flags
);
5564 tcg_gen_br(label_continue
);
5565 gen_set_label(label_match
);
5568 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5571 gen_set_label(label_continue
);
5575 /* Floating point conditional select
5576 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5577 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5578 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5579 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5581 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5583 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5584 TCGv_i64 t_true
, t_false
, t_zero
;
5588 mos
= extract32(insn
, 29, 3);
5589 type
= extract32(insn
, 22, 2);
5590 rm
= extract32(insn
, 16, 5);
5591 cond
= extract32(insn
, 12, 4);
5592 rn
= extract32(insn
, 5, 5);
5593 rd
= extract32(insn
, 0, 5);
5596 unallocated_encoding(s
);
5609 if (dc_isar_feature(aa64_fp16
, s
)) {
5614 unallocated_encoding(s
);
5618 if (!fp_access_check(s
)) {
5622 /* Zero extend sreg & hreg inputs to 64 bits now. */
5623 t_true
= tcg_temp_new_i64();
5624 t_false
= tcg_temp_new_i64();
5625 read_vec_element(s
, t_true
, rn
, 0, sz
);
5626 read_vec_element(s
, t_false
, rm
, 0, sz
);
5628 a64_test_cc(&c
, cond
);
5629 t_zero
= tcg_const_i64(0);
5630 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5631 tcg_temp_free_i64(t_zero
);
5632 tcg_temp_free_i64(t_false
);
5635 /* Note that sregs & hregs write back zeros to the high bits,
5636 and we've already done the zero-extension. */
5637 write_fp_dreg(s
, rd
, t_true
);
5638 tcg_temp_free_i64(t_true
);
5641 /* Floating-point data-processing (1 source) - half precision */
5642 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5644 TCGv_ptr fpst
= NULL
;
5645 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5646 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5649 case 0x0: /* FMOV */
5650 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5652 case 0x1: /* FABS */
5653 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5655 case 0x2: /* FNEG */
5656 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5658 case 0x3: /* FSQRT */
5659 fpst
= get_fpstatus_ptr(true);
5660 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5662 case 0x8: /* FRINTN */
5663 case 0x9: /* FRINTP */
5664 case 0xa: /* FRINTM */
5665 case 0xb: /* FRINTZ */
5666 case 0xc: /* FRINTA */
5668 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5669 fpst
= get_fpstatus_ptr(true);
5671 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5672 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5674 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5675 tcg_temp_free_i32(tcg_rmode
);
5678 case 0xe: /* FRINTX */
5679 fpst
= get_fpstatus_ptr(true);
5680 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5682 case 0xf: /* FRINTI */
5683 fpst
= get_fpstatus_ptr(true);
5684 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5690 write_fp_sreg(s
, rd
, tcg_res
);
5693 tcg_temp_free_ptr(fpst
);
5695 tcg_temp_free_i32(tcg_op
);
5696 tcg_temp_free_i32(tcg_res
);
5699 /* Floating-point data-processing (1 source) - single precision */
5700 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5702 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
5703 TCGv_i32 tcg_op
, tcg_res
;
5707 tcg_op
= read_fp_sreg(s
, rn
);
5708 tcg_res
= tcg_temp_new_i32();
5711 case 0x0: /* FMOV */
5712 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5714 case 0x1: /* FABS */
5715 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5717 case 0x2: /* FNEG */
5718 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5720 case 0x3: /* FSQRT */
5721 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5723 case 0x8: /* FRINTN */
5724 case 0x9: /* FRINTP */
5725 case 0xa: /* FRINTM */
5726 case 0xb: /* FRINTZ */
5727 case 0xc: /* FRINTA */
5728 rmode
= arm_rmode_to_sf(opcode
& 7);
5729 gen_fpst
= gen_helper_rints
;
5731 case 0xe: /* FRINTX */
5732 gen_fpst
= gen_helper_rints_exact
;
5734 case 0xf: /* FRINTI */
5735 gen_fpst
= gen_helper_rints
;
5737 case 0x10: /* FRINT32Z */
5738 rmode
= float_round_to_zero
;
5739 gen_fpst
= gen_helper_frint32_s
;
5741 case 0x11: /* FRINT32X */
5742 gen_fpst
= gen_helper_frint32_s
;
5744 case 0x12: /* FRINT64Z */
5745 rmode
= float_round_to_zero
;
5746 gen_fpst
= gen_helper_frint64_s
;
5748 case 0x13: /* FRINT64X */
5749 gen_fpst
= gen_helper_frint64_s
;
5752 g_assert_not_reached();
5755 fpst
= get_fpstatus_ptr(false);
5757 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5758 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5759 gen_fpst(tcg_res
, tcg_op
, fpst
);
5760 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5761 tcg_temp_free_i32(tcg_rmode
);
5763 gen_fpst(tcg_res
, tcg_op
, fpst
);
5765 tcg_temp_free_ptr(fpst
);
5768 write_fp_sreg(s
, rd
, tcg_res
);
5769 tcg_temp_free_i32(tcg_op
);
5770 tcg_temp_free_i32(tcg_res
);
5773 /* Floating-point data-processing (1 source) - double precision */
5774 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5776 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
5777 TCGv_i64 tcg_op
, tcg_res
;
5782 case 0x0: /* FMOV */
5783 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5787 tcg_op
= read_fp_dreg(s
, rn
);
5788 tcg_res
= tcg_temp_new_i64();
5791 case 0x1: /* FABS */
5792 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5794 case 0x2: /* FNEG */
5795 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5797 case 0x3: /* FSQRT */
5798 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5800 case 0x8: /* FRINTN */
5801 case 0x9: /* FRINTP */
5802 case 0xa: /* FRINTM */
5803 case 0xb: /* FRINTZ */
5804 case 0xc: /* FRINTA */
5805 rmode
= arm_rmode_to_sf(opcode
& 7);
5806 gen_fpst
= gen_helper_rintd
;
5808 case 0xe: /* FRINTX */
5809 gen_fpst
= gen_helper_rintd_exact
;
5811 case 0xf: /* FRINTI */
5812 gen_fpst
= gen_helper_rintd
;
5814 case 0x10: /* FRINT32Z */
5815 rmode
= float_round_to_zero
;
5816 gen_fpst
= gen_helper_frint32_d
;
5818 case 0x11: /* FRINT32X */
5819 gen_fpst
= gen_helper_frint32_d
;
5821 case 0x12: /* FRINT64Z */
5822 rmode
= float_round_to_zero
;
5823 gen_fpst
= gen_helper_frint64_d
;
5825 case 0x13: /* FRINT64X */
5826 gen_fpst
= gen_helper_frint64_d
;
5829 g_assert_not_reached();
5832 fpst
= get_fpstatus_ptr(false);
5834 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5835 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5836 gen_fpst(tcg_res
, tcg_op
, fpst
);
5837 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5838 tcg_temp_free_i32(tcg_rmode
);
5840 gen_fpst(tcg_res
, tcg_op
, fpst
);
5842 tcg_temp_free_ptr(fpst
);
5845 write_fp_dreg(s
, rd
, tcg_res
);
5846 tcg_temp_free_i64(tcg_op
);
5847 tcg_temp_free_i64(tcg_res
);
5850 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5851 int rd
, int rn
, int dtype
, int ntype
)
5856 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5858 /* Single to double */
5859 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5860 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5861 write_fp_dreg(s
, rd
, tcg_rd
);
5862 tcg_temp_free_i64(tcg_rd
);
5864 /* Single to half */
5865 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5866 TCGv_i32 ahp
= get_ahp_flag();
5867 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5869 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5870 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5871 write_fp_sreg(s
, rd
, tcg_rd
);
5872 tcg_temp_free_i32(tcg_rd
);
5873 tcg_temp_free_i32(ahp
);
5874 tcg_temp_free_ptr(fpst
);
5876 tcg_temp_free_i32(tcg_rn
);
5881 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5882 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5884 /* Double to single */
5885 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5887 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5888 TCGv_i32 ahp
= get_ahp_flag();
5889 /* Double to half */
5890 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5891 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5892 tcg_temp_free_ptr(fpst
);
5893 tcg_temp_free_i32(ahp
);
5895 write_fp_sreg(s
, rd
, tcg_rd
);
5896 tcg_temp_free_i32(tcg_rd
);
5897 tcg_temp_free_i64(tcg_rn
);
5902 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5903 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5904 TCGv_i32 tcg_ahp
= get_ahp_flag();
5905 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5907 /* Half to single */
5908 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5909 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5910 write_fp_sreg(s
, rd
, tcg_rd
);
5911 tcg_temp_free_ptr(tcg_fpst
);
5912 tcg_temp_free_i32(tcg_ahp
);
5913 tcg_temp_free_i32(tcg_rd
);
5915 /* Half to double */
5916 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5917 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5918 write_fp_dreg(s
, rd
, tcg_rd
);
5919 tcg_temp_free_i64(tcg_rd
);
5921 tcg_temp_free_i32(tcg_rn
);
5929 /* Floating point data-processing (1 source)
5930 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5931 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5932 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5933 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5935 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5937 int mos
= extract32(insn
, 29, 3);
5938 int type
= extract32(insn
, 22, 2);
5939 int opcode
= extract32(insn
, 15, 6);
5940 int rn
= extract32(insn
, 5, 5);
5941 int rd
= extract32(insn
, 0, 5);
5944 unallocated_encoding(s
);
5949 case 0x4: case 0x5: case 0x7:
5951 /* FCVT between half, single and double precision */
5952 int dtype
= extract32(opcode
, 0, 2);
5953 if (type
== 2 || dtype
== type
) {
5954 unallocated_encoding(s
);
5957 if (!fp_access_check(s
)) {
5961 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5965 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
5966 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
5967 unallocated_encoding(s
);
5974 /* 32-to-32 and 64-to-64 ops */
5977 if (!fp_access_check(s
)) {
5980 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5983 if (!fp_access_check(s
)) {
5986 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5989 if (!dc_isar_feature(aa64_fp16
, s
)) {
5990 unallocated_encoding(s
);
5994 if (!fp_access_check(s
)) {
5997 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6000 unallocated_encoding(s
);
6005 unallocated_encoding(s
);
6010 /* Floating-point data-processing (2 source) - single precision */
6011 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6012 int rd
, int rn
, int rm
)
6019 tcg_res
= tcg_temp_new_i32();
6020 fpst
= get_fpstatus_ptr(false);
6021 tcg_op1
= read_fp_sreg(s
, rn
);
6022 tcg_op2
= read_fp_sreg(s
, rm
);
6025 case 0x0: /* FMUL */
6026 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6028 case 0x1: /* FDIV */
6029 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6031 case 0x2: /* FADD */
6032 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6034 case 0x3: /* FSUB */
6035 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6037 case 0x4: /* FMAX */
6038 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6040 case 0x5: /* FMIN */
6041 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6043 case 0x6: /* FMAXNM */
6044 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6046 case 0x7: /* FMINNM */
6047 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6049 case 0x8: /* FNMUL */
6050 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6051 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6055 write_fp_sreg(s
, rd
, tcg_res
);
6057 tcg_temp_free_ptr(fpst
);
6058 tcg_temp_free_i32(tcg_op1
);
6059 tcg_temp_free_i32(tcg_op2
);
6060 tcg_temp_free_i32(tcg_res
);
6063 /* Floating-point data-processing (2 source) - double precision */
6064 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6065 int rd
, int rn
, int rm
)
6072 tcg_res
= tcg_temp_new_i64();
6073 fpst
= get_fpstatus_ptr(false);
6074 tcg_op1
= read_fp_dreg(s
, rn
);
6075 tcg_op2
= read_fp_dreg(s
, rm
);
6078 case 0x0: /* FMUL */
6079 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6081 case 0x1: /* FDIV */
6082 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6084 case 0x2: /* FADD */
6085 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6087 case 0x3: /* FSUB */
6088 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6090 case 0x4: /* FMAX */
6091 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6093 case 0x5: /* FMIN */
6094 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6096 case 0x6: /* FMAXNM */
6097 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6099 case 0x7: /* FMINNM */
6100 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6102 case 0x8: /* FNMUL */
6103 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6104 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6108 write_fp_dreg(s
, rd
, tcg_res
);
6110 tcg_temp_free_ptr(fpst
);
6111 tcg_temp_free_i64(tcg_op1
);
6112 tcg_temp_free_i64(tcg_op2
);
6113 tcg_temp_free_i64(tcg_res
);
6116 /* Floating-point data-processing (2 source) - half precision */
6117 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6118 int rd
, int rn
, int rm
)
6125 tcg_res
= tcg_temp_new_i32();
6126 fpst
= get_fpstatus_ptr(true);
6127 tcg_op1
= read_fp_hreg(s
, rn
);
6128 tcg_op2
= read_fp_hreg(s
, rm
);
6131 case 0x0: /* FMUL */
6132 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6134 case 0x1: /* FDIV */
6135 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6137 case 0x2: /* FADD */
6138 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6140 case 0x3: /* FSUB */
6141 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6143 case 0x4: /* FMAX */
6144 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6146 case 0x5: /* FMIN */
6147 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6149 case 0x6: /* FMAXNM */
6150 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6152 case 0x7: /* FMINNM */
6153 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6155 case 0x8: /* FNMUL */
6156 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6157 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6160 g_assert_not_reached();
6163 write_fp_sreg(s
, rd
, tcg_res
);
6165 tcg_temp_free_ptr(fpst
);
6166 tcg_temp_free_i32(tcg_op1
);
6167 tcg_temp_free_i32(tcg_op2
);
6168 tcg_temp_free_i32(tcg_res
);
6171 /* Floating point data-processing (2 source)
6172 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6173 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6174 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6175 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6177 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6179 int mos
= extract32(insn
, 29, 3);
6180 int type
= extract32(insn
, 22, 2);
6181 int rd
= extract32(insn
, 0, 5);
6182 int rn
= extract32(insn
, 5, 5);
6183 int rm
= extract32(insn
, 16, 5);
6184 int opcode
= extract32(insn
, 12, 4);
6186 if (opcode
> 8 || mos
) {
6187 unallocated_encoding(s
);
6193 if (!fp_access_check(s
)) {
6196 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6199 if (!fp_access_check(s
)) {
6202 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6205 if (!dc_isar_feature(aa64_fp16
, s
)) {
6206 unallocated_encoding(s
);
6209 if (!fp_access_check(s
)) {
6212 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6215 unallocated_encoding(s
);
6219 /* Floating-point data-processing (3 source) - single precision */
6220 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6221 int rd
, int rn
, int rm
, int ra
)
6223 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6224 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6225 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6227 tcg_op1
= read_fp_sreg(s
, rn
);
6228 tcg_op2
= read_fp_sreg(s
, rm
);
6229 tcg_op3
= read_fp_sreg(s
, ra
);
6231 /* These are fused multiply-add, and must be done as one
6232 * floating point operation with no rounding between the
6233 * multiplication and addition steps.
6234 * NB that doing the negations here as separate steps is
6235 * correct : an input NaN should come out with its sign bit
6236 * flipped if it is a negated-input.
6239 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6243 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6246 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6248 write_fp_sreg(s
, rd
, tcg_res
);
6250 tcg_temp_free_ptr(fpst
);
6251 tcg_temp_free_i32(tcg_op1
);
6252 tcg_temp_free_i32(tcg_op2
);
6253 tcg_temp_free_i32(tcg_op3
);
6254 tcg_temp_free_i32(tcg_res
);
6257 /* Floating-point data-processing (3 source) - double precision */
6258 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6259 int rd
, int rn
, int rm
, int ra
)
6261 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6262 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6263 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6265 tcg_op1
= read_fp_dreg(s
, rn
);
6266 tcg_op2
= read_fp_dreg(s
, rm
);
6267 tcg_op3
= read_fp_dreg(s
, ra
);
6269 /* These are fused multiply-add, and must be done as one
6270 * floating point operation with no rounding between the
6271 * multiplication and addition steps.
6272 * NB that doing the negations here as separate steps is
6273 * correct : an input NaN should come out with its sign bit
6274 * flipped if it is a negated-input.
6277 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6281 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6284 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6286 write_fp_dreg(s
, rd
, tcg_res
);
6288 tcg_temp_free_ptr(fpst
);
6289 tcg_temp_free_i64(tcg_op1
);
6290 tcg_temp_free_i64(tcg_op2
);
6291 tcg_temp_free_i64(tcg_op3
);
6292 tcg_temp_free_i64(tcg_res
);
6295 /* Floating-point data-processing (3 source) - half precision */
6296 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6297 int rd
, int rn
, int rm
, int ra
)
6299 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6300 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6301 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6303 tcg_op1
= read_fp_hreg(s
, rn
);
6304 tcg_op2
= read_fp_hreg(s
, rm
);
6305 tcg_op3
= read_fp_hreg(s
, ra
);
6307 /* These are fused multiply-add, and must be done as one
6308 * floating point operation with no rounding between the
6309 * multiplication and addition steps.
6310 * NB that doing the negations here as separate steps is
6311 * correct : an input NaN should come out with its sign bit
6312 * flipped if it is a negated-input.
6315 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6319 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6322 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6324 write_fp_sreg(s
, rd
, tcg_res
);
6326 tcg_temp_free_ptr(fpst
);
6327 tcg_temp_free_i32(tcg_op1
);
6328 tcg_temp_free_i32(tcg_op2
);
6329 tcg_temp_free_i32(tcg_op3
);
6330 tcg_temp_free_i32(tcg_res
);
6333 /* Floating point data-processing (3 source)
6334 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6335 * +---+---+---+-----------+------+----+------+----+------+------+------+
6336 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6337 * +---+---+---+-----------+------+----+------+----+------+------+------+
6339 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6341 int mos
= extract32(insn
, 29, 3);
6342 int type
= extract32(insn
, 22, 2);
6343 int rd
= extract32(insn
, 0, 5);
6344 int rn
= extract32(insn
, 5, 5);
6345 int ra
= extract32(insn
, 10, 5);
6346 int rm
= extract32(insn
, 16, 5);
6347 bool o0
= extract32(insn
, 15, 1);
6348 bool o1
= extract32(insn
, 21, 1);
6351 unallocated_encoding(s
);
6357 if (!fp_access_check(s
)) {
6360 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6363 if (!fp_access_check(s
)) {
6366 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6369 if (!dc_isar_feature(aa64_fp16
, s
)) {
6370 unallocated_encoding(s
);
6373 if (!fp_access_check(s
)) {
6376 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6379 unallocated_encoding(s
);
6383 /* The imm8 encodes the sign bit, enough bits to represent an exponent in
6384 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
6385 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
6387 uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
6393 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6394 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
6395 extract32(imm8
, 0, 6);
6399 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6400 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
6401 (extract32(imm8
, 0, 6) << 3);
6405 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6406 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
6407 (extract32(imm8
, 0, 6) << 6);
6410 g_assert_not_reached();
6415 /* Floating point immediate
6416 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6417 * +---+---+---+-----------+------+---+------------+-------+------+------+
6418 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6419 * +---+---+---+-----------+------+---+------------+-------+------+------+
6421 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6423 int rd
= extract32(insn
, 0, 5);
6424 int imm5
= extract32(insn
, 5, 5);
6425 int imm8
= extract32(insn
, 13, 8);
6426 int type
= extract32(insn
, 22, 2);
6427 int mos
= extract32(insn
, 29, 3);
6433 unallocated_encoding(s
);
6446 if (dc_isar_feature(aa64_fp16
, s
)) {
6451 unallocated_encoding(s
);
6455 if (!fp_access_check(s
)) {
6459 imm
= vfp_expand_imm(sz
, imm8
);
6461 tcg_res
= tcg_const_i64(imm
);
6462 write_fp_dreg(s
, rd
, tcg_res
);
6463 tcg_temp_free_i64(tcg_res
);
6466 /* Handle floating point <=> fixed point conversions. Note that we can
6467 * also deal with fp <=> integer conversions as a special case (scale == 64)
6468 * OPTME: consider handling that special case specially or at least skipping
6469 * the call to scalbn in the helpers for zero shifts.
6471 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6472 bool itof
, int rmode
, int scale
, int sf
, int type
)
6474 bool is_signed
= !(opcode
& 1);
6475 TCGv_ptr tcg_fpstatus
;
6476 TCGv_i32 tcg_shift
, tcg_single
;
6477 TCGv_i64 tcg_double
;
6479 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6481 tcg_shift
= tcg_const_i32(64 - scale
);
6484 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6486 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6489 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6491 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6494 tcg_int
= tcg_extend
;
6498 case 1: /* float64 */
6499 tcg_double
= tcg_temp_new_i64();
6501 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6502 tcg_shift
, tcg_fpstatus
);
6504 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6505 tcg_shift
, tcg_fpstatus
);
6507 write_fp_dreg(s
, rd
, tcg_double
);
6508 tcg_temp_free_i64(tcg_double
);
6511 case 0: /* float32 */
6512 tcg_single
= tcg_temp_new_i32();
6514 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6515 tcg_shift
, tcg_fpstatus
);
6517 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6518 tcg_shift
, tcg_fpstatus
);
6520 write_fp_sreg(s
, rd
, tcg_single
);
6521 tcg_temp_free_i32(tcg_single
);
6524 case 3: /* float16 */
6525 tcg_single
= tcg_temp_new_i32();
6527 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6528 tcg_shift
, tcg_fpstatus
);
6530 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6531 tcg_shift
, tcg_fpstatus
);
6533 write_fp_sreg(s
, rd
, tcg_single
);
6534 tcg_temp_free_i32(tcg_single
);
6538 g_assert_not_reached();
6541 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6544 if (extract32(opcode
, 2, 1)) {
6545 /* There are too many rounding modes to all fit into rmode,
6546 * so FCVTA[US] is a special case.
6548 rmode
= FPROUNDING_TIEAWAY
;
6551 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6553 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6556 case 1: /* float64 */
6557 tcg_double
= read_fp_dreg(s
, rn
);
6560 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6561 tcg_shift
, tcg_fpstatus
);
6563 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6564 tcg_shift
, tcg_fpstatus
);
6568 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6569 tcg_shift
, tcg_fpstatus
);
6571 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6572 tcg_shift
, tcg_fpstatus
);
6576 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6578 tcg_temp_free_i64(tcg_double
);
6581 case 0: /* float32 */
6582 tcg_single
= read_fp_sreg(s
, rn
);
6585 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6586 tcg_shift
, tcg_fpstatus
);
6588 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6589 tcg_shift
, tcg_fpstatus
);
6592 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6594 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6595 tcg_shift
, tcg_fpstatus
);
6597 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6598 tcg_shift
, tcg_fpstatus
);
6600 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6601 tcg_temp_free_i32(tcg_dest
);
6603 tcg_temp_free_i32(tcg_single
);
6606 case 3: /* float16 */
6607 tcg_single
= read_fp_sreg(s
, rn
);
6610 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6611 tcg_shift
, tcg_fpstatus
);
6613 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6614 tcg_shift
, tcg_fpstatus
);
6617 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6619 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6620 tcg_shift
, tcg_fpstatus
);
6622 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6623 tcg_shift
, tcg_fpstatus
);
6625 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6626 tcg_temp_free_i32(tcg_dest
);
6628 tcg_temp_free_i32(tcg_single
);
6632 g_assert_not_reached();
6635 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6636 tcg_temp_free_i32(tcg_rmode
);
6639 tcg_temp_free_ptr(tcg_fpstatus
);
6640 tcg_temp_free_i32(tcg_shift
);
6643 /* Floating point <-> fixed point conversions
6644 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6645 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6646 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6647 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6649 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6651 int rd
= extract32(insn
, 0, 5);
6652 int rn
= extract32(insn
, 5, 5);
6653 int scale
= extract32(insn
, 10, 6);
6654 int opcode
= extract32(insn
, 16, 3);
6655 int rmode
= extract32(insn
, 19, 2);
6656 int type
= extract32(insn
, 22, 2);
6657 bool sbit
= extract32(insn
, 29, 1);
6658 bool sf
= extract32(insn
, 31, 1);
6661 if (sbit
|| (!sf
&& scale
< 32)) {
6662 unallocated_encoding(s
);
6667 case 0: /* float32 */
6668 case 1: /* float64 */
6670 case 3: /* float16 */
6671 if (dc_isar_feature(aa64_fp16
, s
)) {
6676 unallocated_encoding(s
);
6680 switch ((rmode
<< 3) | opcode
) {
6681 case 0x2: /* SCVTF */
6682 case 0x3: /* UCVTF */
6685 case 0x18: /* FCVTZS */
6686 case 0x19: /* FCVTZU */
6690 unallocated_encoding(s
);
6694 if (!fp_access_check(s
)) {
6698 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6701 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6703 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6704 * without conversion.
6708 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6714 tmp
= tcg_temp_new_i64();
6715 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6716 write_fp_dreg(s
, rd
, tmp
);
6717 tcg_temp_free_i64(tmp
);
6721 write_fp_dreg(s
, rd
, tcg_rn
);
6724 /* 64 bit to top half. */
6725 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6726 clear_vec_high(s
, true, rd
);
6730 tmp
= tcg_temp_new_i64();
6731 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6732 write_fp_dreg(s
, rd
, tmp
);
6733 tcg_temp_free_i64(tmp
);
6736 g_assert_not_reached();
6739 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6744 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6748 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6751 /* 64 bits from top half */
6752 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6756 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6759 g_assert_not_reached();
6764 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
6766 TCGv_i64 t
= read_fp_dreg(s
, rn
);
6767 TCGv_ptr fpstatus
= get_fpstatus_ptr(false);
6769 gen_helper_fjcvtzs(t
, t
, fpstatus
);
6771 tcg_temp_free_ptr(fpstatus
);
6773 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
6774 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
6775 tcg_gen_movi_i32(cpu_CF
, 0);
6776 tcg_gen_movi_i32(cpu_NF
, 0);
6777 tcg_gen_movi_i32(cpu_VF
, 0);
6779 tcg_temp_free_i64(t
);
6782 /* Floating point <-> integer conversions
6783 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6784 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6785 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6786 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6788 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6790 int rd
= extract32(insn
, 0, 5);
6791 int rn
= extract32(insn
, 5, 5);
6792 int opcode
= extract32(insn
, 16, 3);
6793 int rmode
= extract32(insn
, 19, 2);
6794 int type
= extract32(insn
, 22, 2);
6795 bool sbit
= extract32(insn
, 29, 1);
6796 bool sf
= extract32(insn
, 31, 1);
6800 goto do_unallocated
;
6808 case 4: /* FCVTAS */
6809 case 5: /* FCVTAU */
6811 goto do_unallocated
;
6814 case 0: /* FCVT[NPMZ]S */
6815 case 1: /* FCVT[NPMZ]U */
6817 case 0: /* float32 */
6818 case 1: /* float64 */
6820 case 3: /* float16 */
6821 if (!dc_isar_feature(aa64_fp16
, s
)) {
6822 goto do_unallocated
;
6826 goto do_unallocated
;
6828 if (!fp_access_check(s
)) {
6831 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6835 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
6836 case 0b01100110: /* FMOV half <-> 32-bit int */
6838 case 0b11100110: /* FMOV half <-> 64-bit int */
6840 if (!dc_isar_feature(aa64_fp16
, s
)) {
6841 goto do_unallocated
;
6844 case 0b00000110: /* FMOV 32-bit */
6846 case 0b10100110: /* FMOV 64-bit */
6848 case 0b11001110: /* FMOV top half of 128-bit */
6850 if (!fp_access_check(s
)) {
6854 handle_fmov(s
, rd
, rn
, type
, itof
);
6857 case 0b00111110: /* FJCVTZS */
6858 if (!dc_isar_feature(aa64_jscvt
, s
)) {
6859 goto do_unallocated
;
6860 } else if (fp_access_check(s
)) {
6861 handle_fjcvtzs(s
, rd
, rn
);
6867 unallocated_encoding(s
);
6874 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6875 * 31 30 29 28 25 24 0
6876 * +---+---+---+---------+-----------------------------+
6877 * | | 0 | | 1 1 1 1 | |
6878 * +---+---+---+---------+-----------------------------+
6880 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6882 if (extract32(insn
, 24, 1)) {
6883 /* Floating point data-processing (3 source) */
6884 disas_fp_3src(s
, insn
);
6885 } else if (extract32(insn
, 21, 1) == 0) {
6886 /* Floating point to fixed point conversions */
6887 disas_fp_fixed_conv(s
, insn
);
6889 switch (extract32(insn
, 10, 2)) {
6891 /* Floating point conditional compare */
6892 disas_fp_ccomp(s
, insn
);
6895 /* Floating point data-processing (2 source) */
6896 disas_fp_2src(s
, insn
);
6899 /* Floating point conditional select */
6900 disas_fp_csel(s
, insn
);
6903 switch (ctz32(extract32(insn
, 12, 4))) {
6904 case 0: /* [15:12] == xxx1 */
6905 /* Floating point immediate */
6906 disas_fp_imm(s
, insn
);
6908 case 1: /* [15:12] == xx10 */
6909 /* Floating point compare */
6910 disas_fp_compare(s
, insn
);
6912 case 2: /* [15:12] == x100 */
6913 /* Floating point data-processing (1 source) */
6914 disas_fp_1src(s
, insn
);
6916 case 3: /* [15:12] == 1000 */
6917 unallocated_encoding(s
);
6919 default: /* [15:12] == 0000 */
6920 /* Floating point <-> integer conversions */
6921 disas_fp_int_conv(s
, insn
);
6929 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6932 /* Extract 64 bits from the middle of two concatenated 64 bit
6933 * vector register slices left:right. The extracted bits start
6934 * at 'pos' bits into the right (least significant) side.
6935 * We return the result in tcg_right, and guarantee not to
6938 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6939 assert(pos
> 0 && pos
< 64);
6941 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6942 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6943 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6945 tcg_temp_free_i64(tcg_tmp
);
6949 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6950 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6951 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6952 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6954 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6956 int is_q
= extract32(insn
, 30, 1);
6957 int op2
= extract32(insn
, 22, 2);
6958 int imm4
= extract32(insn
, 11, 4);
6959 int rm
= extract32(insn
, 16, 5);
6960 int rn
= extract32(insn
, 5, 5);
6961 int rd
= extract32(insn
, 0, 5);
6962 int pos
= imm4
<< 3;
6963 TCGv_i64 tcg_resl
, tcg_resh
;
6965 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6966 unallocated_encoding(s
);
6970 if (!fp_access_check(s
)) {
6974 tcg_resh
= tcg_temp_new_i64();
6975 tcg_resl
= tcg_temp_new_i64();
6977 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6978 * either extracting 128 bits from a 128:128 concatenation, or
6979 * extracting 64 bits from a 64:64 concatenation.
6982 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6984 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6985 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6987 tcg_gen_movi_i64(tcg_resh
, 0);
6994 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6995 EltPosns
*elt
= eltposns
;
7002 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
7004 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
7007 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7008 tcg_hh
= tcg_temp_new_i64();
7009 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7010 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7011 tcg_temp_free_i64(tcg_hh
);
7015 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7016 tcg_temp_free_i64(tcg_resl
);
7017 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7018 tcg_temp_free_i64(tcg_resh
);
7022 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7023 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7024 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7025 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7027 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7029 int op2
= extract32(insn
, 22, 2);
7030 int is_q
= extract32(insn
, 30, 1);
7031 int rm
= extract32(insn
, 16, 5);
7032 int rn
= extract32(insn
, 5, 5);
7033 int rd
= extract32(insn
, 0, 5);
7034 int is_tblx
= extract32(insn
, 12, 1);
7035 int len
= extract32(insn
, 13, 2);
7036 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
7037 TCGv_i32 tcg_regno
, tcg_numregs
;
7040 unallocated_encoding(s
);
7044 if (!fp_access_check(s
)) {
7048 /* This does a table lookup: for every byte element in the input
7049 * we index into a table formed from up to four vector registers,
7050 * and then the output is the result of the lookups. Our helper
7051 * function does the lookup operation for a single 64 bit part of
7054 tcg_resl
= tcg_temp_new_i64();
7055 tcg_resh
= tcg_temp_new_i64();
7058 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7060 tcg_gen_movi_i64(tcg_resl
, 0);
7062 if (is_tblx
&& is_q
) {
7063 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7065 tcg_gen_movi_i64(tcg_resh
, 0);
7068 tcg_idx
= tcg_temp_new_i64();
7069 tcg_regno
= tcg_const_i32(rn
);
7070 tcg_numregs
= tcg_const_i32(len
+ 1);
7071 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
7072 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
7073 tcg_regno
, tcg_numregs
);
7075 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
7076 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
7077 tcg_regno
, tcg_numregs
);
7079 tcg_temp_free_i64(tcg_idx
);
7080 tcg_temp_free_i32(tcg_regno
);
7081 tcg_temp_free_i32(tcg_numregs
);
7083 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7084 tcg_temp_free_i64(tcg_resl
);
7085 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7086 tcg_temp_free_i64(tcg_resh
);
7090 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7091 * +---+---+-------------+------+---+------+---+------------------+------+
7092 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7093 * +---+---+-------------+------+---+------+---+------------------+------+
7095 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7097 int rd
= extract32(insn
, 0, 5);
7098 int rn
= extract32(insn
, 5, 5);
7099 int rm
= extract32(insn
, 16, 5);
7100 int size
= extract32(insn
, 22, 2);
7101 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7102 * bit 2 indicates 1 vs 2 variant of the insn.
7104 int opcode
= extract32(insn
, 12, 2);
7105 bool part
= extract32(insn
, 14, 1);
7106 bool is_q
= extract32(insn
, 30, 1);
7107 int esize
= 8 << size
;
7109 int datasize
= is_q
? 128 : 64;
7110 int elements
= datasize
/ esize
;
7111 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7113 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7114 unallocated_encoding(s
);
7118 if (!fp_access_check(s
)) {
7122 tcg_resl
= tcg_const_i64(0);
7123 tcg_resh
= tcg_const_i64(0);
7124 tcg_res
= tcg_temp_new_i64();
7126 for (i
= 0; i
< elements
; i
++) {
7128 case 1: /* UZP1/2 */
7130 int midpoint
= elements
/ 2;
7132 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7134 read_vec_element(s
, tcg_res
, rm
,
7135 2 * (i
- midpoint
) + part
, size
);
7139 case 2: /* TRN1/2 */
7141 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7143 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7146 case 3: /* ZIP1/2 */
7148 int base
= part
* elements
/ 2;
7150 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7152 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7157 g_assert_not_reached();
7162 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7163 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7165 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7166 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7170 tcg_temp_free_i64(tcg_res
);
7172 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7173 tcg_temp_free_i64(tcg_resl
);
7174 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7175 tcg_temp_free_i64(tcg_resh
);
7179 * do_reduction_op helper
7181 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7182 * important for correct NaN propagation that we do these
7183 * operations in exactly the order specified by the pseudocode.
7185 * This is a recursive function, TCG temps should be freed by the
7186 * calling function once it is done with the values.
7188 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7189 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7191 if (esize
== size
) {
7193 TCGMemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7196 /* We should have one register left here */
7197 assert(ctpop8(vmap
) == 1);
7198 element
= ctz32(vmap
);
7199 assert(element
< 8);
7201 tcg_elem
= tcg_temp_new_i32();
7202 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7205 int bits
= size
/ 2;
7206 int shift
= ctpop8(vmap
) / 2;
7207 int vmap_lo
= (vmap
>> shift
) & vmap
;
7208 int vmap_hi
= (vmap
& ~vmap_lo
);
7209 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7211 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7212 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7213 tcg_res
= tcg_temp_new_i32();
7216 case 0x0c: /* fmaxnmv half-precision */
7217 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7219 case 0x0f: /* fmaxv half-precision */
7220 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7222 case 0x1c: /* fminnmv half-precision */
7223 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7225 case 0x1f: /* fminv half-precision */
7226 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7228 case 0x2c: /* fmaxnmv */
7229 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7231 case 0x2f: /* fmaxv */
7232 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7234 case 0x3c: /* fminnmv */
7235 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7237 case 0x3f: /* fminv */
7238 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7241 g_assert_not_reached();
7244 tcg_temp_free_i32(tcg_hi
);
7245 tcg_temp_free_i32(tcg_lo
);
7250 /* AdvSIMD across lanes
7251 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7252 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7253 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7254 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7256 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7258 int rd
= extract32(insn
, 0, 5);
7259 int rn
= extract32(insn
, 5, 5);
7260 int size
= extract32(insn
, 22, 2);
7261 int opcode
= extract32(insn
, 12, 5);
7262 bool is_q
= extract32(insn
, 30, 1);
7263 bool is_u
= extract32(insn
, 29, 1);
7265 bool is_min
= false;
7269 TCGv_i64 tcg_res
, tcg_elt
;
7272 case 0x1b: /* ADDV */
7274 unallocated_encoding(s
);
7278 case 0x3: /* SADDLV, UADDLV */
7279 case 0xa: /* SMAXV, UMAXV */
7280 case 0x1a: /* SMINV, UMINV */
7281 if (size
== 3 || (size
== 2 && !is_q
)) {
7282 unallocated_encoding(s
);
7286 case 0xc: /* FMAXNMV, FMINNMV */
7287 case 0xf: /* FMAXV, FMINV */
7288 /* Bit 1 of size field encodes min vs max and the actual size
7289 * depends on the encoding of the U bit. If not set (and FP16
7290 * enabled) then we do half-precision float instead of single
7293 is_min
= extract32(size
, 1, 1);
7295 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7297 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7298 unallocated_encoding(s
);
7305 unallocated_encoding(s
);
7309 if (!fp_access_check(s
)) {
7314 elements
= (is_q
? 128 : 64) / esize
;
7316 tcg_res
= tcg_temp_new_i64();
7317 tcg_elt
= tcg_temp_new_i64();
7319 /* These instructions operate across all lanes of a vector
7320 * to produce a single result. We can guarantee that a 64
7321 * bit intermediate is sufficient:
7322 * + for [US]ADDLV the maximum element size is 32 bits, and
7323 * the result type is 64 bits
7324 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7325 * same as the element size, which is 32 bits at most
7326 * For the integer operations we can choose to work at 64
7327 * or 32 bits and truncate at the end; for simplicity
7328 * we use 64 bits always. The floating point
7329 * ops do require 32 bit intermediates, though.
7332 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7334 for (i
= 1; i
< elements
; i
++) {
7335 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7338 case 0x03: /* SADDLV / UADDLV */
7339 case 0x1b: /* ADDV */
7340 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7342 case 0x0a: /* SMAXV / UMAXV */
7344 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7346 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7349 case 0x1a: /* SMINV / UMINV */
7351 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7353 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7357 g_assert_not_reached();
7362 /* Floating point vector reduction ops which work across 32
7363 * bit (single) or 16 bit (half-precision) intermediates.
7364 * Note that correct NaN propagation requires that we do these
7365 * operations in exactly the order specified by the pseudocode.
7367 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7368 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7369 int vmap
= (1 << elements
) - 1;
7370 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7371 (is_q
? 128 : 64), vmap
, fpst
);
7372 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7373 tcg_temp_free_i32(tcg_res32
);
7374 tcg_temp_free_ptr(fpst
);
7377 tcg_temp_free_i64(tcg_elt
);
7379 /* Now truncate the result to the width required for the final output */
7380 if (opcode
== 0x03) {
7381 /* SADDLV, UADDLV: result is 2*esize */
7387 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7390 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7393 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7398 g_assert_not_reached();
7401 write_fp_dreg(s
, rd
, tcg_res
);
7402 tcg_temp_free_i64(tcg_res
);
7405 /* DUP (Element, Vector)
7407 * 31 30 29 21 20 16 15 10 9 5 4 0
7408 * +---+---+-------------------+--------+-------------+------+------+
7409 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7410 * +---+---+-------------------+--------+-------------+------+------+
7412 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7414 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7417 int size
= ctz32(imm5
);
7418 int index
= imm5
>> (size
+ 1);
7420 if (size
> 3 || (size
== 3 && !is_q
)) {
7421 unallocated_encoding(s
);
7425 if (!fp_access_check(s
)) {
7429 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7430 vec_reg_offset(s
, rn
, index
, size
),
7431 is_q
? 16 : 8, vec_full_reg_size(s
));
7434 /* DUP (element, scalar)
7435 * 31 21 20 16 15 10 9 5 4 0
7436 * +-----------------------+--------+-------------+------+------+
7437 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7438 * +-----------------------+--------+-------------+------+------+
7440 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7443 int size
= ctz32(imm5
);
7448 unallocated_encoding(s
);
7452 if (!fp_access_check(s
)) {
7456 index
= imm5
>> (size
+ 1);
7458 /* This instruction just extracts the specified element and
7459 * zero-extends it into the bottom of the destination register.
7461 tmp
= tcg_temp_new_i64();
7462 read_vec_element(s
, tmp
, rn
, index
, size
);
7463 write_fp_dreg(s
, rd
, tmp
);
7464 tcg_temp_free_i64(tmp
);
7469 * 31 30 29 21 20 16 15 10 9 5 4 0
7470 * +---+---+-------------------+--------+-------------+------+------+
7471 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7472 * +---+---+-------------------+--------+-------------+------+------+
7474 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7476 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7479 int size
= ctz32(imm5
);
7480 uint32_t dofs
, oprsz
, maxsz
;
7482 if (size
> 3 || ((size
== 3) && !is_q
)) {
7483 unallocated_encoding(s
);
7487 if (!fp_access_check(s
)) {
7491 dofs
= vec_full_reg_offset(s
, rd
);
7492 oprsz
= is_q
? 16 : 8;
7493 maxsz
= vec_full_reg_size(s
);
7495 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7500 * 31 21 20 16 15 14 11 10 9 5 4 0
7501 * +-----------------------+--------+------------+---+------+------+
7502 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7503 * +-----------------------+--------+------------+---+------+------+
7505 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7506 * index: encoded in imm5<4:size+1>
7508 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7511 int size
= ctz32(imm5
);
7512 int src_index
, dst_index
;
7516 unallocated_encoding(s
);
7520 if (!fp_access_check(s
)) {
7524 dst_index
= extract32(imm5
, 1+size
, 5);
7525 src_index
= extract32(imm4
, size
, 4);
7527 tmp
= tcg_temp_new_i64();
7529 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7530 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7532 tcg_temp_free_i64(tmp
);
7538 * 31 21 20 16 15 10 9 5 4 0
7539 * +-----------------------+--------+-------------+------+------+
7540 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7541 * +-----------------------+--------+-------------+------+------+
7543 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7544 * index: encoded in imm5<4:size+1>
7546 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7548 int size
= ctz32(imm5
);
7552 unallocated_encoding(s
);
7556 if (!fp_access_check(s
)) {
7560 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7561 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7568 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7569 * +---+---+-------------------+--------+-------------+------+------+
7570 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7571 * +---+---+-------------------+--------+-------------+------+------+
7573 * U: unsigned when set
7574 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7576 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7577 int rn
, int rd
, int imm5
)
7579 int size
= ctz32(imm5
);
7583 /* Check for UnallocatedEncodings */
7585 if (size
> 2 || (size
== 2 && !is_q
)) {
7586 unallocated_encoding(s
);
7591 || (size
< 3 && is_q
)
7592 || (size
== 3 && !is_q
)) {
7593 unallocated_encoding(s
);
7598 if (!fp_access_check(s
)) {
7602 element
= extract32(imm5
, 1+size
, 4);
7604 tcg_rd
= cpu_reg(s
, rd
);
7605 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7606 if (is_signed
&& !is_q
) {
7607 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7612 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7613 * +---+---+----+-----------------+------+---+------+---+------+------+
7614 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7615 * +---+---+----+-----------------+------+---+------+---+------+------+
7617 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7619 int rd
= extract32(insn
, 0, 5);
7620 int rn
= extract32(insn
, 5, 5);
7621 int imm4
= extract32(insn
, 11, 4);
7622 int op
= extract32(insn
, 29, 1);
7623 int is_q
= extract32(insn
, 30, 1);
7624 int imm5
= extract32(insn
, 16, 5);
7629 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7631 unallocated_encoding(s
);
7636 /* DUP (element - vector) */
7637 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7641 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7646 handle_simd_insg(s
, rd
, rn
, imm5
);
7648 unallocated_encoding(s
);
7653 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7654 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7657 unallocated_encoding(s
);
7663 /* AdvSIMD modified immediate
7664 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7665 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7666 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7667 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7669 * There are a number of operations that can be carried out here:
7670 * MOVI - move (shifted) imm into register
7671 * MVNI - move inverted (shifted) imm into register
7672 * ORR - bitwise OR of (shifted) imm with register
7673 * BIC - bitwise clear of (shifted) imm with register
7674 * With ARMv8.2 we also have:
7675 * FMOV half-precision
7677 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7679 int rd
= extract32(insn
, 0, 5);
7680 int cmode
= extract32(insn
, 12, 4);
7681 int cmode_3_1
= extract32(cmode
, 1, 3);
7682 int cmode_0
= extract32(cmode
, 0, 1);
7683 int o2
= extract32(insn
, 11, 1);
7684 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7685 bool is_neg
= extract32(insn
, 29, 1);
7686 bool is_q
= extract32(insn
, 30, 1);
7689 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7690 /* Check for FMOV (vector, immediate) - half-precision */
7691 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7692 unallocated_encoding(s
);
7697 if (!fp_access_check(s
)) {
7701 /* See AdvSIMDExpandImm() in ARM ARM */
7702 switch (cmode_3_1
) {
7703 case 0: /* Replicate(Zeros(24):imm8, 2) */
7704 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7705 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7706 case 3: /* Replicate(imm8:Zeros(24), 2) */
7708 int shift
= cmode_3_1
* 8;
7709 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7712 case 4: /* Replicate(Zeros(8):imm8, 4) */
7713 case 5: /* Replicate(imm8:Zeros(8), 4) */
7715 int shift
= (cmode_3_1
& 0x1) * 8;
7716 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7721 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7722 imm
= (abcdefgh
<< 16) | 0xffff;
7724 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7725 imm
= (abcdefgh
<< 8) | 0xff;
7727 imm
= bitfield_replicate(imm
, 32);
7730 if (!cmode_0
&& !is_neg
) {
7731 imm
= bitfield_replicate(abcdefgh
, 8);
7732 } else if (!cmode_0
&& is_neg
) {
7735 for (i
= 0; i
< 8; i
++) {
7736 if ((abcdefgh
) & (1 << i
)) {
7737 imm
|= 0xffULL
<< (i
* 8);
7740 } else if (cmode_0
) {
7742 imm
= (abcdefgh
& 0x3f) << 48;
7743 if (abcdefgh
& 0x80) {
7744 imm
|= 0x8000000000000000ULL
;
7746 if (abcdefgh
& 0x40) {
7747 imm
|= 0x3fc0000000000000ULL
;
7749 imm
|= 0x4000000000000000ULL
;
7753 /* FMOV (vector, immediate) - half-precision */
7754 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7755 /* now duplicate across the lanes */
7756 imm
= bitfield_replicate(imm
, 16);
7758 imm
= (abcdefgh
& 0x3f) << 19;
7759 if (abcdefgh
& 0x80) {
7762 if (abcdefgh
& 0x40) {
7773 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7774 g_assert_not_reached();
7777 if (cmode_3_1
!= 7 && is_neg
) {
7781 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7782 /* MOVI or MVNI, with MVNI negation handled above. */
7783 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7784 vec_full_reg_size(s
), imm
);
7786 /* ORR or BIC, with BIC negation to AND handled above. */
7788 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7790 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7795 /* AdvSIMD scalar copy
7796 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7797 * +-----+----+-----------------+------+---+------+---+------+------+
7798 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7799 * +-----+----+-----------------+------+---+------+---+------+------+
7801 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7803 int rd
= extract32(insn
, 0, 5);
7804 int rn
= extract32(insn
, 5, 5);
7805 int imm4
= extract32(insn
, 11, 4);
7806 int imm5
= extract32(insn
, 16, 5);
7807 int op
= extract32(insn
, 29, 1);
7809 if (op
!= 0 || imm4
!= 0) {
7810 unallocated_encoding(s
);
7814 /* DUP (element, scalar) */
7815 handle_simd_dupes(s
, rd
, rn
, imm5
);
7818 /* AdvSIMD scalar pairwise
7819 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7820 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7821 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7822 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7824 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7826 int u
= extract32(insn
, 29, 1);
7827 int size
= extract32(insn
, 22, 2);
7828 int opcode
= extract32(insn
, 12, 5);
7829 int rn
= extract32(insn
, 5, 5);
7830 int rd
= extract32(insn
, 0, 5);
7833 /* For some ops (the FP ones), size[1] is part of the encoding.
7834 * For ADDP strictly it is not but size[1] is always 1 for valid
7837 opcode
|= (extract32(size
, 1, 1) << 5);
7840 case 0x3b: /* ADDP */
7841 if (u
|| size
!= 3) {
7842 unallocated_encoding(s
);
7845 if (!fp_access_check(s
)) {
7851 case 0xc: /* FMAXNMP */
7852 case 0xd: /* FADDP */
7853 case 0xf: /* FMAXP */
7854 case 0x2c: /* FMINNMP */
7855 case 0x2f: /* FMINP */
7856 /* FP op, size[0] is 32 or 64 bit*/
7858 if (!dc_isar_feature(aa64_fp16
, s
)) {
7859 unallocated_encoding(s
);
7865 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7868 if (!fp_access_check(s
)) {
7872 fpst
= get_fpstatus_ptr(size
== MO_16
);
7875 unallocated_encoding(s
);
7879 if (size
== MO_64
) {
7880 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7881 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7882 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7884 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7885 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7888 case 0x3b: /* ADDP */
7889 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7891 case 0xc: /* FMAXNMP */
7892 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7894 case 0xd: /* FADDP */
7895 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7897 case 0xf: /* FMAXP */
7898 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7900 case 0x2c: /* FMINNMP */
7901 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7903 case 0x2f: /* FMINP */
7904 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7907 g_assert_not_reached();
7910 write_fp_dreg(s
, rd
, tcg_res
);
7912 tcg_temp_free_i64(tcg_op1
);
7913 tcg_temp_free_i64(tcg_op2
);
7914 tcg_temp_free_i64(tcg_res
);
7916 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7917 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7918 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7920 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7921 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7923 if (size
== MO_16
) {
7925 case 0xc: /* FMAXNMP */
7926 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7928 case 0xd: /* FADDP */
7929 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7931 case 0xf: /* FMAXP */
7932 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7934 case 0x2c: /* FMINNMP */
7935 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7937 case 0x2f: /* FMINP */
7938 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7941 g_assert_not_reached();
7945 case 0xc: /* FMAXNMP */
7946 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7948 case 0xd: /* FADDP */
7949 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7951 case 0xf: /* FMAXP */
7952 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7954 case 0x2c: /* FMINNMP */
7955 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7957 case 0x2f: /* FMINP */
7958 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7961 g_assert_not_reached();
7965 write_fp_sreg(s
, rd
, tcg_res
);
7967 tcg_temp_free_i32(tcg_op1
);
7968 tcg_temp_free_i32(tcg_op2
);
7969 tcg_temp_free_i32(tcg_res
);
7973 tcg_temp_free_ptr(fpst
);
7978 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7980 * This code is handles the common shifting code and is used by both
7981 * the vector and scalar code.
7983 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7984 TCGv_i64 tcg_rnd
, bool accumulate
,
7985 bool is_u
, int size
, int shift
)
7987 bool extended_result
= false;
7988 bool round
= tcg_rnd
!= NULL
;
7990 TCGv_i64 tcg_src_hi
;
7992 if (round
&& size
== 3) {
7993 extended_result
= true;
7994 ext_lshift
= 64 - shift
;
7995 tcg_src_hi
= tcg_temp_new_i64();
7996 } else if (shift
== 64) {
7997 if (!accumulate
&& is_u
) {
7998 /* result is zero */
7999 tcg_gen_movi_i64(tcg_res
, 0);
8004 /* Deal with the rounding step */
8006 if (extended_result
) {
8007 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8009 /* take care of sign extending tcg_res */
8010 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8011 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8012 tcg_src
, tcg_src_hi
,
8015 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8019 tcg_temp_free_i64(tcg_zero
);
8021 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8025 /* Now do the shift right */
8026 if (round
&& extended_result
) {
8027 /* extended case, >64 bit precision required */
8028 if (ext_lshift
== 0) {
8029 /* special case, only high bits matter */
8030 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8032 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8033 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8034 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8039 /* essentially shifting in 64 zeros */
8040 tcg_gen_movi_i64(tcg_src
, 0);
8042 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8046 /* effectively extending the sign-bit */
8047 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8049 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8055 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8057 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8060 if (extended_result
) {
8061 tcg_temp_free_i64(tcg_src_hi
);
8065 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8066 static void handle_scalar_simd_shri(DisasContext
*s
,
8067 bool is_u
, int immh
, int immb
,
8068 int opcode
, int rn
, int rd
)
8071 int immhb
= immh
<< 3 | immb
;
8072 int shift
= 2 * (8 << size
) - immhb
;
8073 bool accumulate
= false;
8075 bool insert
= false;
8080 if (!extract32(immh
, 3, 1)) {
8081 unallocated_encoding(s
);
8085 if (!fp_access_check(s
)) {
8090 case 0x02: /* SSRA / USRA (accumulate) */
8093 case 0x04: /* SRSHR / URSHR (rounding) */
8096 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8097 accumulate
= round
= true;
8099 case 0x08: /* SRI */
8105 uint64_t round_const
= 1ULL << (shift
- 1);
8106 tcg_round
= tcg_const_i64(round_const
);
8111 tcg_rn
= read_fp_dreg(s
, rn
);
8112 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8115 /* shift count same as element size is valid but does nothing;
8116 * special case to avoid potential shift by 64.
8118 int esize
= 8 << size
;
8119 if (shift
!= esize
) {
8120 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8121 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8124 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8125 accumulate
, is_u
, size
, shift
);
8128 write_fp_dreg(s
, rd
, tcg_rd
);
8130 tcg_temp_free_i64(tcg_rn
);
8131 tcg_temp_free_i64(tcg_rd
);
8133 tcg_temp_free_i64(tcg_round
);
8137 /* SHL/SLI - Scalar shift left */
8138 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8139 int immh
, int immb
, int opcode
,
8142 int size
= 32 - clz32(immh
) - 1;
8143 int immhb
= immh
<< 3 | immb
;
8144 int shift
= immhb
- (8 << size
);
8145 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8146 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8148 if (!extract32(immh
, 3, 1)) {
8149 unallocated_encoding(s
);
8153 if (!fp_access_check(s
)) {
8157 tcg_rn
= read_fp_dreg(s
, rn
);
8158 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8161 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8163 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8166 write_fp_dreg(s
, rd
, tcg_rd
);
8168 tcg_temp_free_i64(tcg_rn
);
8169 tcg_temp_free_i64(tcg_rd
);
8172 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8173 * (signed/unsigned) narrowing */
8174 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8175 bool is_u_shift
, bool is_u_narrow
,
8176 int immh
, int immb
, int opcode
,
8179 int immhb
= immh
<< 3 | immb
;
8180 int size
= 32 - clz32(immh
) - 1;
8181 int esize
= 8 << size
;
8182 int shift
= (2 * esize
) - immhb
;
8183 int elements
= is_scalar
? 1 : (64 / esize
);
8184 bool round
= extract32(opcode
, 0, 1);
8185 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8186 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8187 TCGv_i32 tcg_rd_narrowed
;
8190 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8191 { gen_helper_neon_narrow_sat_s8
,
8192 gen_helper_neon_unarrow_sat8
},
8193 { gen_helper_neon_narrow_sat_s16
,
8194 gen_helper_neon_unarrow_sat16
},
8195 { gen_helper_neon_narrow_sat_s32
,
8196 gen_helper_neon_unarrow_sat32
},
8199 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8200 gen_helper_neon_narrow_sat_u8
,
8201 gen_helper_neon_narrow_sat_u16
,
8202 gen_helper_neon_narrow_sat_u32
,
8205 NeonGenNarrowEnvFn
*narrowfn
;
8211 if (extract32(immh
, 3, 1)) {
8212 unallocated_encoding(s
);
8216 if (!fp_access_check(s
)) {
8221 narrowfn
= unsigned_narrow_fns
[size
];
8223 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8226 tcg_rn
= tcg_temp_new_i64();
8227 tcg_rd
= tcg_temp_new_i64();
8228 tcg_rd_narrowed
= tcg_temp_new_i32();
8229 tcg_final
= tcg_const_i64(0);
8232 uint64_t round_const
= 1ULL << (shift
- 1);
8233 tcg_round
= tcg_const_i64(round_const
);
8238 for (i
= 0; i
< elements
; i
++) {
8239 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8240 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8241 false, is_u_shift
, size
+1, shift
);
8242 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8243 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8244 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8248 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8250 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8254 tcg_temp_free_i64(tcg_round
);
8256 tcg_temp_free_i64(tcg_rn
);
8257 tcg_temp_free_i64(tcg_rd
);
8258 tcg_temp_free_i32(tcg_rd_narrowed
);
8259 tcg_temp_free_i64(tcg_final
);
8261 clear_vec_high(s
, is_q
, rd
);
8264 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8265 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8266 bool src_unsigned
, bool dst_unsigned
,
8267 int immh
, int immb
, int rn
, int rd
)
8269 int immhb
= immh
<< 3 | immb
;
8270 int size
= 32 - clz32(immh
) - 1;
8271 int shift
= immhb
- (8 << size
);
8275 assert(!(scalar
&& is_q
));
8278 if (!is_q
&& extract32(immh
, 3, 1)) {
8279 unallocated_encoding(s
);
8283 /* Since we use the variable-shift helpers we must
8284 * replicate the shift count into each element of
8285 * the tcg_shift value.
8289 shift
|= shift
<< 8;
8292 shift
|= shift
<< 16;
8298 g_assert_not_reached();
8302 if (!fp_access_check(s
)) {
8307 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8308 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8309 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8310 { NULL
, gen_helper_neon_qshl_u64
},
8312 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8313 int maxpass
= is_q
? 2 : 1;
8315 for (pass
= 0; pass
< maxpass
; pass
++) {
8316 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8318 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8319 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8320 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8322 tcg_temp_free_i64(tcg_op
);
8324 tcg_temp_free_i64(tcg_shift
);
8325 clear_vec_high(s
, is_q
, rd
);
8327 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8328 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8330 { gen_helper_neon_qshl_s8
,
8331 gen_helper_neon_qshl_s16
,
8332 gen_helper_neon_qshl_s32
},
8333 { gen_helper_neon_qshlu_s8
,
8334 gen_helper_neon_qshlu_s16
,
8335 gen_helper_neon_qshlu_s32
}
8337 { NULL
, NULL
, NULL
},
8338 { gen_helper_neon_qshl_u8
,
8339 gen_helper_neon_qshl_u16
,
8340 gen_helper_neon_qshl_u32
}
8343 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8344 TCGMemOp memop
= scalar
? size
: MO_32
;
8345 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8347 for (pass
= 0; pass
< maxpass
; pass
++) {
8348 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8350 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8351 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8355 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8358 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8363 g_assert_not_reached();
8365 write_fp_sreg(s
, rd
, tcg_op
);
8367 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8370 tcg_temp_free_i32(tcg_op
);
8372 tcg_temp_free_i32(tcg_shift
);
8375 clear_vec_high(s
, is_q
, rd
);
8380 /* Common vector code for handling integer to FP conversion */
8381 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8382 int elements
, int is_signed
,
8383 int fracbits
, int size
)
8385 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8386 TCGv_i32 tcg_shift
= NULL
;
8388 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8391 if (fracbits
|| size
== MO_64
) {
8392 tcg_shift
= tcg_const_i32(fracbits
);
8395 if (size
== MO_64
) {
8396 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8397 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8399 for (pass
= 0; pass
< elements
; pass
++) {
8400 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8403 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8404 tcg_shift
, tcg_fpst
);
8406 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8407 tcg_shift
, tcg_fpst
);
8409 if (elements
== 1) {
8410 write_fp_dreg(s
, rd
, tcg_double
);
8412 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8416 tcg_temp_free_i64(tcg_int64
);
8417 tcg_temp_free_i64(tcg_double
);
8420 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8421 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8423 for (pass
= 0; pass
< elements
; pass
++) {
8424 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8430 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8431 tcg_shift
, tcg_fpst
);
8433 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8434 tcg_shift
, tcg_fpst
);
8438 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8440 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8447 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8448 tcg_shift
, tcg_fpst
);
8450 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8451 tcg_shift
, tcg_fpst
);
8455 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8457 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8462 g_assert_not_reached();
8465 if (elements
== 1) {
8466 write_fp_sreg(s
, rd
, tcg_float
);
8468 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8472 tcg_temp_free_i32(tcg_int32
);
8473 tcg_temp_free_i32(tcg_float
);
8476 tcg_temp_free_ptr(tcg_fpst
);
8478 tcg_temp_free_i32(tcg_shift
);
8481 clear_vec_high(s
, elements
<< size
== 16, rd
);
8484 /* UCVTF/SCVTF - Integer to FP conversion */
8485 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8486 bool is_q
, bool is_u
,
8487 int immh
, int immb
, int opcode
,
8490 int size
, elements
, fracbits
;
8491 int immhb
= immh
<< 3 | immb
;
8495 if (!is_scalar
&& !is_q
) {
8496 unallocated_encoding(s
);
8499 } else if (immh
& 4) {
8501 } else if (immh
& 2) {
8503 if (!dc_isar_feature(aa64_fp16
, s
)) {
8504 unallocated_encoding(s
);
8508 /* immh == 0 would be a failure of the decode logic */
8509 g_assert(immh
== 1);
8510 unallocated_encoding(s
);
8517 elements
= (8 << is_q
) >> size
;
8519 fracbits
= (16 << size
) - immhb
;
8521 if (!fp_access_check(s
)) {
8525 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8528 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8529 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8530 bool is_q
, bool is_u
,
8531 int immh
, int immb
, int rn
, int rd
)
8533 int immhb
= immh
<< 3 | immb
;
8534 int pass
, size
, fracbits
;
8535 TCGv_ptr tcg_fpstatus
;
8536 TCGv_i32 tcg_rmode
, tcg_shift
;
8540 if (!is_scalar
&& !is_q
) {
8541 unallocated_encoding(s
);
8544 } else if (immh
& 0x4) {
8546 } else if (immh
& 0x2) {
8548 if (!dc_isar_feature(aa64_fp16
, s
)) {
8549 unallocated_encoding(s
);
8553 /* Should have split out AdvSIMD modified immediate earlier. */
8555 unallocated_encoding(s
);
8559 if (!fp_access_check(s
)) {
8563 assert(!(is_scalar
&& is_q
));
8565 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8566 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8567 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8568 fracbits
= (16 << size
) - immhb
;
8569 tcg_shift
= tcg_const_i32(fracbits
);
8571 if (size
== MO_64
) {
8572 int maxpass
= is_scalar
? 1 : 2;
8574 for (pass
= 0; pass
< maxpass
; pass
++) {
8575 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8577 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8579 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8581 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8583 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8584 tcg_temp_free_i64(tcg_op
);
8586 clear_vec_high(s
, is_q
, rd
);
8588 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8589 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8594 fn
= gen_helper_vfp_touhh
;
8596 fn
= gen_helper_vfp_toshh
;
8601 fn
= gen_helper_vfp_touls
;
8603 fn
= gen_helper_vfp_tosls
;
8607 g_assert_not_reached();
8610 for (pass
= 0; pass
< maxpass
; pass
++) {
8611 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8613 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8614 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8616 write_fp_sreg(s
, rd
, tcg_op
);
8618 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8620 tcg_temp_free_i32(tcg_op
);
8623 clear_vec_high(s
, is_q
, rd
);
8627 tcg_temp_free_ptr(tcg_fpstatus
);
8628 tcg_temp_free_i32(tcg_shift
);
8629 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8630 tcg_temp_free_i32(tcg_rmode
);
8633 /* AdvSIMD scalar shift by immediate
8634 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8635 * +-----+---+-------------+------+------+--------+---+------+------+
8636 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8637 * +-----+---+-------------+------+------+--------+---+------+------+
8639 * This is the scalar version so it works on a fixed sized registers
8641 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8643 int rd
= extract32(insn
, 0, 5);
8644 int rn
= extract32(insn
, 5, 5);
8645 int opcode
= extract32(insn
, 11, 5);
8646 int immb
= extract32(insn
, 16, 3);
8647 int immh
= extract32(insn
, 19, 4);
8648 bool is_u
= extract32(insn
, 29, 1);
8651 unallocated_encoding(s
);
8656 case 0x08: /* SRI */
8658 unallocated_encoding(s
);
8662 case 0x00: /* SSHR / USHR */
8663 case 0x02: /* SSRA / USRA */
8664 case 0x04: /* SRSHR / URSHR */
8665 case 0x06: /* SRSRA / URSRA */
8666 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8668 case 0x0a: /* SHL / SLI */
8669 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8671 case 0x1c: /* SCVTF, UCVTF */
8672 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8675 case 0x10: /* SQSHRUN, SQSHRUN2 */
8676 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8678 unallocated_encoding(s
);
8681 handle_vec_simd_sqshrn(s
, true, false, false, true,
8682 immh
, immb
, opcode
, rn
, rd
);
8684 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8685 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8686 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8687 immh
, immb
, opcode
, rn
, rd
);
8689 case 0xc: /* SQSHLU */
8691 unallocated_encoding(s
);
8694 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8696 case 0xe: /* SQSHL, UQSHL */
8697 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8699 case 0x1f: /* FCVTZS, FCVTZU */
8700 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8703 unallocated_encoding(s
);
8708 /* AdvSIMD scalar three different
8709 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8710 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8711 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8712 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8714 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8716 bool is_u
= extract32(insn
, 29, 1);
8717 int size
= extract32(insn
, 22, 2);
8718 int opcode
= extract32(insn
, 12, 4);
8719 int rm
= extract32(insn
, 16, 5);
8720 int rn
= extract32(insn
, 5, 5);
8721 int rd
= extract32(insn
, 0, 5);
8724 unallocated_encoding(s
);
8729 case 0x9: /* SQDMLAL, SQDMLAL2 */
8730 case 0xb: /* SQDMLSL, SQDMLSL2 */
8731 case 0xd: /* SQDMULL, SQDMULL2 */
8732 if (size
== 0 || size
== 3) {
8733 unallocated_encoding(s
);
8738 unallocated_encoding(s
);
8742 if (!fp_access_check(s
)) {
8747 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8748 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8749 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8751 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8752 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8754 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8755 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8758 case 0xd: /* SQDMULL, SQDMULL2 */
8760 case 0xb: /* SQDMLSL, SQDMLSL2 */
8761 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8763 case 0x9: /* SQDMLAL, SQDMLAL2 */
8764 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8765 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8769 g_assert_not_reached();
8772 write_fp_dreg(s
, rd
, tcg_res
);
8774 tcg_temp_free_i64(tcg_op1
);
8775 tcg_temp_free_i64(tcg_op2
);
8776 tcg_temp_free_i64(tcg_res
);
8778 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8779 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8780 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8782 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8783 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8786 case 0xd: /* SQDMULL, SQDMULL2 */
8788 case 0xb: /* SQDMLSL, SQDMLSL2 */
8789 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8791 case 0x9: /* SQDMLAL, SQDMLAL2 */
8793 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8794 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8795 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8797 tcg_temp_free_i64(tcg_op3
);
8801 g_assert_not_reached();
8804 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8805 write_fp_dreg(s
, rd
, tcg_res
);
8807 tcg_temp_free_i32(tcg_op1
);
8808 tcg_temp_free_i32(tcg_op2
);
8809 tcg_temp_free_i64(tcg_res
);
8813 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8814 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8816 /* Handle 64x64->64 opcodes which are shared between the scalar
8817 * and vector 3-same groups. We cover every opcode where size == 3
8818 * is valid in either the three-reg-same (integer, not pairwise)
8819 * or scalar-three-reg-same groups.
8824 case 0x1: /* SQADD */
8826 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8828 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8831 case 0x5: /* SQSUB */
8833 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8835 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8838 case 0x6: /* CMGT, CMHI */
8839 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8840 * We implement this using setcond (test) and then negating.
8842 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8844 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8845 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8847 case 0x7: /* CMGE, CMHS */
8848 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8850 case 0x11: /* CMTST, CMEQ */
8855 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8857 case 0x8: /* SSHL, USHL */
8859 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8861 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8864 case 0x9: /* SQSHL, UQSHL */
8866 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8868 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8871 case 0xa: /* SRSHL, URSHL */
8873 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8875 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8878 case 0xb: /* SQRSHL, UQRSHL */
8880 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8882 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8885 case 0x10: /* ADD, SUB */
8887 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8889 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8893 g_assert_not_reached();
8897 /* Handle the 3-same-operands float operations; shared by the scalar
8898 * and vector encodings. The caller must filter out any encodings
8899 * not allocated for the encoding it is dealing with.
8901 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8902 int fpopcode
, int rd
, int rn
, int rm
)
8905 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8907 for (pass
= 0; pass
< elements
; pass
++) {
8910 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8911 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8912 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8914 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8915 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8918 case 0x39: /* FMLS */
8919 /* As usual for ARM, separate negation for fused multiply-add */
8920 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8922 case 0x19: /* FMLA */
8923 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8924 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8927 case 0x18: /* FMAXNM */
8928 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8930 case 0x1a: /* FADD */
8931 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8933 case 0x1b: /* FMULX */
8934 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8936 case 0x1c: /* FCMEQ */
8937 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8939 case 0x1e: /* FMAX */
8940 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8942 case 0x1f: /* FRECPS */
8943 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8945 case 0x38: /* FMINNM */
8946 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8948 case 0x3a: /* FSUB */
8949 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8951 case 0x3e: /* FMIN */
8952 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8954 case 0x3f: /* FRSQRTS */
8955 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8957 case 0x5b: /* FMUL */
8958 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8960 case 0x5c: /* FCMGE */
8961 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8963 case 0x5d: /* FACGE */
8964 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8966 case 0x5f: /* FDIV */
8967 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8969 case 0x7a: /* FABD */
8970 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8971 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8973 case 0x7c: /* FCMGT */
8974 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8976 case 0x7d: /* FACGT */
8977 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8980 g_assert_not_reached();
8983 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8985 tcg_temp_free_i64(tcg_res
);
8986 tcg_temp_free_i64(tcg_op1
);
8987 tcg_temp_free_i64(tcg_op2
);
8990 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8991 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8992 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8994 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8995 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8998 case 0x39: /* FMLS */
8999 /* As usual for ARM, separate negation for fused multiply-add */
9000 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9002 case 0x19: /* FMLA */
9003 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9004 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9007 case 0x1a: /* FADD */
9008 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9010 case 0x1b: /* FMULX */
9011 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9013 case 0x1c: /* FCMEQ */
9014 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9016 case 0x1e: /* FMAX */
9017 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9019 case 0x1f: /* FRECPS */
9020 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9022 case 0x18: /* FMAXNM */
9023 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9025 case 0x38: /* FMINNM */
9026 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9028 case 0x3a: /* FSUB */
9029 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9031 case 0x3e: /* FMIN */
9032 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9034 case 0x3f: /* FRSQRTS */
9035 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9037 case 0x5b: /* FMUL */
9038 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9040 case 0x5c: /* FCMGE */
9041 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9043 case 0x5d: /* FACGE */
9044 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9046 case 0x5f: /* FDIV */
9047 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9049 case 0x7a: /* FABD */
9050 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9051 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9053 case 0x7c: /* FCMGT */
9054 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9056 case 0x7d: /* FACGT */
9057 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9060 g_assert_not_reached();
9063 if (elements
== 1) {
9064 /* scalar single so clear high part */
9065 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9067 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9068 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9069 tcg_temp_free_i64(tcg_tmp
);
9071 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9074 tcg_temp_free_i32(tcg_res
);
9075 tcg_temp_free_i32(tcg_op1
);
9076 tcg_temp_free_i32(tcg_op2
);
9080 tcg_temp_free_ptr(fpst
);
9082 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9085 /* AdvSIMD scalar three same
9086 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9087 * +-----+---+-----------+------+---+------+--------+---+------+------+
9088 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9089 * +-----+---+-----------+------+---+------+--------+---+------+------+
9091 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9093 int rd
= extract32(insn
, 0, 5);
9094 int rn
= extract32(insn
, 5, 5);
9095 int opcode
= extract32(insn
, 11, 5);
9096 int rm
= extract32(insn
, 16, 5);
9097 int size
= extract32(insn
, 22, 2);
9098 bool u
= extract32(insn
, 29, 1);
9101 if (opcode
>= 0x18) {
9102 /* Floating point: U, size[1] and opcode indicate operation */
9103 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9105 case 0x1b: /* FMULX */
9106 case 0x1f: /* FRECPS */
9107 case 0x3f: /* FRSQRTS */
9108 case 0x5d: /* FACGE */
9109 case 0x7d: /* FACGT */
9110 case 0x1c: /* FCMEQ */
9111 case 0x5c: /* FCMGE */
9112 case 0x7c: /* FCMGT */
9113 case 0x7a: /* FABD */
9116 unallocated_encoding(s
);
9120 if (!fp_access_check(s
)) {
9124 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9129 case 0x1: /* SQADD, UQADD */
9130 case 0x5: /* SQSUB, UQSUB */
9131 case 0x9: /* SQSHL, UQSHL */
9132 case 0xb: /* SQRSHL, UQRSHL */
9134 case 0x8: /* SSHL, USHL */
9135 case 0xa: /* SRSHL, URSHL */
9136 case 0x6: /* CMGT, CMHI */
9137 case 0x7: /* CMGE, CMHS */
9138 case 0x11: /* CMTST, CMEQ */
9139 case 0x10: /* ADD, SUB (vector) */
9141 unallocated_encoding(s
);
9145 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9146 if (size
!= 1 && size
!= 2) {
9147 unallocated_encoding(s
);
9152 unallocated_encoding(s
);
9156 if (!fp_access_check(s
)) {
9160 tcg_rd
= tcg_temp_new_i64();
9163 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9164 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9166 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9167 tcg_temp_free_i64(tcg_rn
);
9168 tcg_temp_free_i64(tcg_rm
);
9170 /* Do a single operation on the lowest element in the vector.
9171 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9172 * no side effects for all these operations.
9173 * OPTME: special-purpose helpers would avoid doing some
9174 * unnecessary work in the helper for the 8 and 16 bit cases.
9176 NeonGenTwoOpEnvFn
*genenvfn
;
9177 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9178 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9179 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9181 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9182 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9185 case 0x1: /* SQADD, UQADD */
9187 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9188 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9189 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9190 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9192 genenvfn
= fns
[size
][u
];
9195 case 0x5: /* SQSUB, UQSUB */
9197 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9198 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9199 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9200 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9202 genenvfn
= fns
[size
][u
];
9205 case 0x9: /* SQSHL, UQSHL */
9207 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9208 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9209 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9210 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9212 genenvfn
= fns
[size
][u
];
9215 case 0xb: /* SQRSHL, UQRSHL */
9217 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9218 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9219 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9220 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9222 genenvfn
= fns
[size
][u
];
9225 case 0x16: /* SQDMULH, SQRDMULH */
9227 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9228 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9229 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9231 assert(size
== 1 || size
== 2);
9232 genenvfn
= fns
[size
- 1][u
];
9236 g_assert_not_reached();
9239 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9240 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9241 tcg_temp_free_i32(tcg_rd32
);
9242 tcg_temp_free_i32(tcg_rn
);
9243 tcg_temp_free_i32(tcg_rm
);
9246 write_fp_dreg(s
, rd
, tcg_rd
);
9248 tcg_temp_free_i64(tcg_rd
);
9251 /* AdvSIMD scalar three same FP16
9252 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9253 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9254 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9255 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9256 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9257 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9259 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9262 int rd
= extract32(insn
, 0, 5);
9263 int rn
= extract32(insn
, 5, 5);
9264 int opcode
= extract32(insn
, 11, 3);
9265 int rm
= extract32(insn
, 16, 5);
9266 bool u
= extract32(insn
, 29, 1);
9267 bool a
= extract32(insn
, 23, 1);
9268 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9275 case 0x03: /* FMULX */
9276 case 0x04: /* FCMEQ (reg) */
9277 case 0x07: /* FRECPS */
9278 case 0x0f: /* FRSQRTS */
9279 case 0x14: /* FCMGE (reg) */
9280 case 0x15: /* FACGE */
9281 case 0x1a: /* FABD */
9282 case 0x1c: /* FCMGT (reg) */
9283 case 0x1d: /* FACGT */
9286 unallocated_encoding(s
);
9290 if (!dc_isar_feature(aa64_fp16
, s
)) {
9291 unallocated_encoding(s
);
9294 if (!fp_access_check(s
)) {
9298 fpst
= get_fpstatus_ptr(true);
9300 tcg_op1
= read_fp_hreg(s
, rn
);
9301 tcg_op2
= read_fp_hreg(s
, rm
);
9302 tcg_res
= tcg_temp_new_i32();
9305 case 0x03: /* FMULX */
9306 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9308 case 0x04: /* FCMEQ (reg) */
9309 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9311 case 0x07: /* FRECPS */
9312 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9314 case 0x0f: /* FRSQRTS */
9315 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9317 case 0x14: /* FCMGE (reg) */
9318 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9320 case 0x15: /* FACGE */
9321 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9323 case 0x1a: /* FABD */
9324 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9325 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9327 case 0x1c: /* FCMGT (reg) */
9328 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9330 case 0x1d: /* FACGT */
9331 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9334 g_assert_not_reached();
9337 write_fp_sreg(s
, rd
, tcg_res
);
9340 tcg_temp_free_i32(tcg_res
);
9341 tcg_temp_free_i32(tcg_op1
);
9342 tcg_temp_free_i32(tcg_op2
);
9343 tcg_temp_free_ptr(fpst
);
9346 /* AdvSIMD scalar three same extra
9347 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9348 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9349 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9350 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9352 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9355 int rd
= extract32(insn
, 0, 5);
9356 int rn
= extract32(insn
, 5, 5);
9357 int opcode
= extract32(insn
, 11, 4);
9358 int rm
= extract32(insn
, 16, 5);
9359 int size
= extract32(insn
, 22, 2);
9360 bool u
= extract32(insn
, 29, 1);
9361 TCGv_i32 ele1
, ele2
, ele3
;
9365 switch (u
* 16 + opcode
) {
9366 case 0x10: /* SQRDMLAH (vector) */
9367 case 0x11: /* SQRDMLSH (vector) */
9368 if (size
!= 1 && size
!= 2) {
9369 unallocated_encoding(s
);
9372 feature
= dc_isar_feature(aa64_rdm
, s
);
9375 unallocated_encoding(s
);
9379 unallocated_encoding(s
);
9382 if (!fp_access_check(s
)) {
9386 /* Do a single operation on the lowest element in the vector.
9387 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9388 * with no side effects for all these operations.
9389 * OPTME: special-purpose helpers would avoid doing some
9390 * unnecessary work in the helper for the 16 bit cases.
9392 ele1
= tcg_temp_new_i32();
9393 ele2
= tcg_temp_new_i32();
9394 ele3
= tcg_temp_new_i32();
9396 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9397 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9398 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9401 case 0x0: /* SQRDMLAH */
9403 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9405 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9408 case 0x1: /* SQRDMLSH */
9410 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9412 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9416 g_assert_not_reached();
9418 tcg_temp_free_i32(ele1
);
9419 tcg_temp_free_i32(ele2
);
9421 res
= tcg_temp_new_i64();
9422 tcg_gen_extu_i32_i64(res
, ele3
);
9423 tcg_temp_free_i32(ele3
);
9425 write_fp_dreg(s
, rd
, res
);
9426 tcg_temp_free_i64(res
);
9429 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9430 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9431 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9433 /* Handle 64->64 opcodes which are shared between the scalar and
9434 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9435 * is valid in either group and also the double-precision fp ops.
9436 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9442 case 0x4: /* CLS, CLZ */
9444 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9446 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9450 /* This opcode is shared with CNT and RBIT but we have earlier
9451 * enforced that size == 3 if and only if this is the NOT insn.
9453 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9455 case 0x7: /* SQABS, SQNEG */
9457 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9459 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9462 case 0xa: /* CMLT */
9463 /* 64 bit integer comparison against zero, result is
9464 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9469 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9470 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9472 case 0x8: /* CMGT, CMGE */
9473 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9475 case 0x9: /* CMEQ, CMLE */
9476 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9478 case 0xb: /* ABS, NEG */
9480 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9482 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9485 case 0x2f: /* FABS */
9486 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9488 case 0x6f: /* FNEG */
9489 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9491 case 0x7f: /* FSQRT */
9492 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9494 case 0x1a: /* FCVTNS */
9495 case 0x1b: /* FCVTMS */
9496 case 0x1c: /* FCVTAS */
9497 case 0x3a: /* FCVTPS */
9498 case 0x3b: /* FCVTZS */
9500 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9501 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9502 tcg_temp_free_i32(tcg_shift
);
9505 case 0x5a: /* FCVTNU */
9506 case 0x5b: /* FCVTMU */
9507 case 0x5c: /* FCVTAU */
9508 case 0x7a: /* FCVTPU */
9509 case 0x7b: /* FCVTZU */
9511 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9512 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9513 tcg_temp_free_i32(tcg_shift
);
9516 case 0x18: /* FRINTN */
9517 case 0x19: /* FRINTM */
9518 case 0x38: /* FRINTP */
9519 case 0x39: /* FRINTZ */
9520 case 0x58: /* FRINTA */
9521 case 0x79: /* FRINTI */
9522 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9524 case 0x59: /* FRINTX */
9525 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9527 case 0x1e: /* FRINT32Z */
9528 case 0x5e: /* FRINT32X */
9529 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9531 case 0x1f: /* FRINT64Z */
9532 case 0x5f: /* FRINT64X */
9533 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9536 g_assert_not_reached();
9540 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9541 bool is_scalar
, bool is_u
, bool is_q
,
9542 int size
, int rn
, int rd
)
9544 bool is_double
= (size
== MO_64
);
9547 if (!fp_access_check(s
)) {
9551 fpst
= get_fpstatus_ptr(size
== MO_16
);
9554 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9555 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9556 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9557 NeonGenTwoDoubleOPFn
*genfn
;
9562 case 0x2e: /* FCMLT (zero) */
9565 case 0x2c: /* FCMGT (zero) */
9566 genfn
= gen_helper_neon_cgt_f64
;
9568 case 0x2d: /* FCMEQ (zero) */
9569 genfn
= gen_helper_neon_ceq_f64
;
9571 case 0x6d: /* FCMLE (zero) */
9574 case 0x6c: /* FCMGE (zero) */
9575 genfn
= gen_helper_neon_cge_f64
;
9578 g_assert_not_reached();
9581 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9582 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9584 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9586 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9588 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9590 tcg_temp_free_i64(tcg_res
);
9591 tcg_temp_free_i64(tcg_zero
);
9592 tcg_temp_free_i64(tcg_op
);
9594 clear_vec_high(s
, !is_scalar
, rd
);
9596 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9597 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9598 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9599 NeonGenTwoSingleOPFn
*genfn
;
9601 int pass
, maxpasses
;
9603 if (size
== MO_16
) {
9605 case 0x2e: /* FCMLT (zero) */
9608 case 0x2c: /* FCMGT (zero) */
9609 genfn
= gen_helper_advsimd_cgt_f16
;
9611 case 0x2d: /* FCMEQ (zero) */
9612 genfn
= gen_helper_advsimd_ceq_f16
;
9614 case 0x6d: /* FCMLE (zero) */
9617 case 0x6c: /* FCMGE (zero) */
9618 genfn
= gen_helper_advsimd_cge_f16
;
9621 g_assert_not_reached();
9625 case 0x2e: /* FCMLT (zero) */
9628 case 0x2c: /* FCMGT (zero) */
9629 genfn
= gen_helper_neon_cgt_f32
;
9631 case 0x2d: /* FCMEQ (zero) */
9632 genfn
= gen_helper_neon_ceq_f32
;
9634 case 0x6d: /* FCMLE (zero) */
9637 case 0x6c: /* FCMGE (zero) */
9638 genfn
= gen_helper_neon_cge_f32
;
9641 g_assert_not_reached();
9648 int vector_size
= 8 << is_q
;
9649 maxpasses
= vector_size
>> size
;
9652 for (pass
= 0; pass
< maxpasses
; pass
++) {
9653 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9655 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9657 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9660 write_fp_sreg(s
, rd
, tcg_res
);
9662 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9665 tcg_temp_free_i32(tcg_res
);
9666 tcg_temp_free_i32(tcg_zero
);
9667 tcg_temp_free_i32(tcg_op
);
9669 clear_vec_high(s
, is_q
, rd
);
9673 tcg_temp_free_ptr(fpst
);
9676 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9677 bool is_scalar
, bool is_u
, bool is_q
,
9678 int size
, int rn
, int rd
)
9680 bool is_double
= (size
== 3);
9681 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9684 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9685 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9688 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9689 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9691 case 0x3d: /* FRECPE */
9692 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9694 case 0x3f: /* FRECPX */
9695 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9697 case 0x7d: /* FRSQRTE */
9698 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9701 g_assert_not_reached();
9703 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9705 tcg_temp_free_i64(tcg_res
);
9706 tcg_temp_free_i64(tcg_op
);
9707 clear_vec_high(s
, !is_scalar
, rd
);
9709 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9710 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9711 int pass
, maxpasses
;
9716 maxpasses
= is_q
? 4 : 2;
9719 for (pass
= 0; pass
< maxpasses
; pass
++) {
9720 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9723 case 0x3c: /* URECPE */
9724 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
9726 case 0x3d: /* FRECPE */
9727 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9729 case 0x3f: /* FRECPX */
9730 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9732 case 0x7d: /* FRSQRTE */
9733 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9736 g_assert_not_reached();
9740 write_fp_sreg(s
, rd
, tcg_res
);
9742 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9745 tcg_temp_free_i32(tcg_res
);
9746 tcg_temp_free_i32(tcg_op
);
9748 clear_vec_high(s
, is_q
, rd
);
9751 tcg_temp_free_ptr(fpst
);
9754 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9755 int opcode
, bool u
, bool is_q
,
9756 int size
, int rn
, int rd
)
9758 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9759 * in the source becomes a size element in the destination).
9762 TCGv_i32 tcg_res
[2];
9763 int destelt
= is_q
? 2 : 0;
9764 int passes
= scalar
? 1 : 2;
9767 tcg_res
[1] = tcg_const_i32(0);
9770 for (pass
= 0; pass
< passes
; pass
++) {
9771 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9772 NeonGenNarrowFn
*genfn
= NULL
;
9773 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9776 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9778 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9780 tcg_res
[pass
] = tcg_temp_new_i32();
9783 case 0x12: /* XTN, SQXTUN */
9785 static NeonGenNarrowFn
* const xtnfns
[3] = {
9786 gen_helper_neon_narrow_u8
,
9787 gen_helper_neon_narrow_u16
,
9788 tcg_gen_extrl_i64_i32
,
9790 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9791 gen_helper_neon_unarrow_sat8
,
9792 gen_helper_neon_unarrow_sat16
,
9793 gen_helper_neon_unarrow_sat32
,
9796 genenvfn
= sqxtunfns
[size
];
9798 genfn
= xtnfns
[size
];
9802 case 0x14: /* SQXTN, UQXTN */
9804 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9805 { gen_helper_neon_narrow_sat_s8
,
9806 gen_helper_neon_narrow_sat_u8
},
9807 { gen_helper_neon_narrow_sat_s16
,
9808 gen_helper_neon_narrow_sat_u16
},
9809 { gen_helper_neon_narrow_sat_s32
,
9810 gen_helper_neon_narrow_sat_u32
},
9812 genenvfn
= fns
[size
][u
];
9815 case 0x16: /* FCVTN, FCVTN2 */
9816 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9818 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9820 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9821 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9822 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9823 TCGv_i32 ahp
= get_ahp_flag();
9825 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9826 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9827 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9828 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9829 tcg_temp_free_i32(tcg_lo
);
9830 tcg_temp_free_i32(tcg_hi
);
9831 tcg_temp_free_ptr(fpst
);
9832 tcg_temp_free_i32(ahp
);
9835 case 0x56: /* FCVTXN, FCVTXN2 */
9836 /* 64 bit to 32 bit float conversion
9837 * with von Neumann rounding (round to odd)
9840 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9843 g_assert_not_reached();
9847 genfn(tcg_res
[pass
], tcg_op
);
9848 } else if (genenvfn
) {
9849 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9852 tcg_temp_free_i64(tcg_op
);
9855 for (pass
= 0; pass
< 2; pass
++) {
9856 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9857 tcg_temp_free_i32(tcg_res
[pass
]);
9859 clear_vec_high(s
, is_q
, rd
);
9862 /* Remaining saturating accumulating ops */
9863 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9864 bool is_q
, int size
, int rn
, int rd
)
9866 bool is_double
= (size
== 3);
9869 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9870 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9873 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9874 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9875 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9877 if (is_u
) { /* USQADD */
9878 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9879 } else { /* SUQADD */
9880 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9882 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9884 tcg_temp_free_i64(tcg_rd
);
9885 tcg_temp_free_i64(tcg_rn
);
9886 clear_vec_high(s
, !is_scalar
, rd
);
9888 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9889 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9890 int pass
, maxpasses
;
9895 maxpasses
= is_q
? 4 : 2;
9898 for (pass
= 0; pass
< maxpasses
; pass
++) {
9900 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9901 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9903 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9904 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9907 if (is_u
) { /* USQADD */
9910 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9913 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9916 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9919 g_assert_not_reached();
9921 } else { /* SUQADD */
9924 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9927 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9930 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9933 g_assert_not_reached();
9938 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9939 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9940 tcg_temp_free_i64(tcg_zero
);
9942 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9944 tcg_temp_free_i32(tcg_rd
);
9945 tcg_temp_free_i32(tcg_rn
);
9946 clear_vec_high(s
, is_q
, rd
);
9950 /* AdvSIMD scalar two reg misc
9951 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9952 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9953 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9954 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9956 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9958 int rd
= extract32(insn
, 0, 5);
9959 int rn
= extract32(insn
, 5, 5);
9960 int opcode
= extract32(insn
, 12, 5);
9961 int size
= extract32(insn
, 22, 2);
9962 bool u
= extract32(insn
, 29, 1);
9963 bool is_fcvt
= false;
9966 TCGv_ptr tcg_fpstatus
;
9969 case 0x3: /* USQADD / SUQADD*/
9970 if (!fp_access_check(s
)) {
9973 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9975 case 0x7: /* SQABS / SQNEG */
9977 case 0xa: /* CMLT */
9979 unallocated_encoding(s
);
9983 case 0x8: /* CMGT, CMGE */
9984 case 0x9: /* CMEQ, CMLE */
9985 case 0xb: /* ABS, NEG */
9987 unallocated_encoding(s
);
9991 case 0x12: /* SQXTUN */
9993 unallocated_encoding(s
);
9997 case 0x14: /* SQXTN, UQXTN */
9999 unallocated_encoding(s
);
10002 if (!fp_access_check(s
)) {
10005 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10008 case 0x16 ... 0x1d:
10010 /* Floating point: U, size[1] and opcode indicate operation;
10011 * size[0] indicates single or double precision.
10013 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10014 size
= extract32(size
, 0, 1) ? 3 : 2;
10016 case 0x2c: /* FCMGT (zero) */
10017 case 0x2d: /* FCMEQ (zero) */
10018 case 0x2e: /* FCMLT (zero) */
10019 case 0x6c: /* FCMGE (zero) */
10020 case 0x6d: /* FCMLE (zero) */
10021 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10023 case 0x1d: /* SCVTF */
10024 case 0x5d: /* UCVTF */
10026 bool is_signed
= (opcode
== 0x1d);
10027 if (!fp_access_check(s
)) {
10030 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10033 case 0x3d: /* FRECPE */
10034 case 0x3f: /* FRECPX */
10035 case 0x7d: /* FRSQRTE */
10036 if (!fp_access_check(s
)) {
10039 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10041 case 0x1a: /* FCVTNS */
10042 case 0x1b: /* FCVTMS */
10043 case 0x3a: /* FCVTPS */
10044 case 0x3b: /* FCVTZS */
10045 case 0x5a: /* FCVTNU */
10046 case 0x5b: /* FCVTMU */
10047 case 0x7a: /* FCVTPU */
10048 case 0x7b: /* FCVTZU */
10050 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10052 case 0x1c: /* FCVTAS */
10053 case 0x5c: /* FCVTAU */
10054 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10056 rmode
= FPROUNDING_TIEAWAY
;
10058 case 0x56: /* FCVTXN, FCVTXN2 */
10060 unallocated_encoding(s
);
10063 if (!fp_access_check(s
)) {
10066 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10069 unallocated_encoding(s
);
10074 unallocated_encoding(s
);
10078 if (!fp_access_check(s
)) {
10083 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10084 tcg_fpstatus
= get_fpstatus_ptr(false);
10085 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10088 tcg_fpstatus
= NULL
;
10092 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10093 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10095 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10096 write_fp_dreg(s
, rd
, tcg_rd
);
10097 tcg_temp_free_i64(tcg_rd
);
10098 tcg_temp_free_i64(tcg_rn
);
10100 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10101 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10103 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10106 case 0x7: /* SQABS, SQNEG */
10108 NeonGenOneOpEnvFn
*genfn
;
10109 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10110 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10111 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10112 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10114 genfn
= fns
[size
][u
];
10115 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10118 case 0x1a: /* FCVTNS */
10119 case 0x1b: /* FCVTMS */
10120 case 0x1c: /* FCVTAS */
10121 case 0x3a: /* FCVTPS */
10122 case 0x3b: /* FCVTZS */
10124 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10125 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10126 tcg_temp_free_i32(tcg_shift
);
10129 case 0x5a: /* FCVTNU */
10130 case 0x5b: /* FCVTMU */
10131 case 0x5c: /* FCVTAU */
10132 case 0x7a: /* FCVTPU */
10133 case 0x7b: /* FCVTZU */
10135 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10136 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10137 tcg_temp_free_i32(tcg_shift
);
10141 g_assert_not_reached();
10144 write_fp_sreg(s
, rd
, tcg_rd
);
10145 tcg_temp_free_i32(tcg_rd
);
10146 tcg_temp_free_i32(tcg_rn
);
10150 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10151 tcg_temp_free_i32(tcg_rmode
);
10152 tcg_temp_free_ptr(tcg_fpstatus
);
10156 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10157 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10158 int immh
, int immb
, int opcode
, int rn
, int rd
)
10160 int size
= 32 - clz32(immh
) - 1;
10161 int immhb
= immh
<< 3 | immb
;
10162 int shift
= 2 * (8 << size
) - immhb
;
10163 bool accumulate
= false;
10164 int dsize
= is_q
? 128 : 64;
10165 int esize
= 8 << size
;
10166 int elements
= dsize
/esize
;
10167 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
10168 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10169 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10170 TCGv_i64 tcg_round
;
10171 uint64_t round_const
;
10174 if (extract32(immh
, 3, 1) && !is_q
) {
10175 unallocated_encoding(s
);
10178 tcg_debug_assert(size
<= 3);
10180 if (!fp_access_check(s
)) {
10185 case 0x02: /* SSRA / USRA (accumulate) */
10187 /* Shift count same as element size produces zero to add. */
10188 if (shift
== 8 << size
) {
10191 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
10193 /* Shift count same as element size produces all sign to add. */
10194 if (shift
== 8 << size
) {
10197 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
10200 case 0x08: /* SRI */
10201 /* Shift count same as element size is valid but does nothing. */
10202 if (shift
== 8 << size
) {
10205 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
10208 case 0x00: /* SSHR / USHR */
10210 if (shift
== 8 << size
) {
10211 /* Shift count the same size as element size produces zero. */
10212 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
10213 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10215 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
10218 /* Shift count the same size as element size produces all sign. */
10219 if (shift
== 8 << size
) {
10222 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
10226 case 0x04: /* SRSHR / URSHR (rounding) */
10228 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10232 g_assert_not_reached();
10235 round_const
= 1ULL << (shift
- 1);
10236 tcg_round
= tcg_const_i64(round_const
);
10238 for (i
= 0; i
< elements
; i
++) {
10239 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
10241 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
10244 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10245 accumulate
, is_u
, size
, shift
);
10247 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
10249 tcg_temp_free_i64(tcg_round
);
10252 clear_vec_high(s
, is_q
, rd
);
10255 /* SHL/SLI - Vector shift left */
10256 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10257 int immh
, int immb
, int opcode
, int rn
, int rd
)
10259 int size
= 32 - clz32(immh
) - 1;
10260 int immhb
= immh
<< 3 | immb
;
10261 int shift
= immhb
- (8 << size
);
10263 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10264 assert(size
>= 0 && size
<= 3);
10266 if (extract32(immh
, 3, 1) && !is_q
) {
10267 unallocated_encoding(s
);
10271 if (!fp_access_check(s
)) {
10276 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sli_op
[size
]);
10278 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10282 /* USHLL/SHLL - Vector shift left with widening */
10283 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10284 int immh
, int immb
, int opcode
, int rn
, int rd
)
10286 int size
= 32 - clz32(immh
) - 1;
10287 int immhb
= immh
<< 3 | immb
;
10288 int shift
= immhb
- (8 << size
);
10290 int esize
= 8 << size
;
10291 int elements
= dsize
/esize
;
10292 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10293 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10297 unallocated_encoding(s
);
10301 if (!fp_access_check(s
)) {
10305 /* For the LL variants the store is larger than the load,
10306 * so if rd == rn we would overwrite parts of our input.
10307 * So load everything right now and use shifts in the main loop.
10309 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10311 for (i
= 0; i
< elements
; i
++) {
10312 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10313 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10314 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10315 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10319 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10320 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10321 int immh
, int immb
, int opcode
, int rn
, int rd
)
10323 int immhb
= immh
<< 3 | immb
;
10324 int size
= 32 - clz32(immh
) - 1;
10326 int esize
= 8 << size
;
10327 int elements
= dsize
/esize
;
10328 int shift
= (2 * esize
) - immhb
;
10329 bool round
= extract32(opcode
, 0, 1);
10330 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10331 TCGv_i64 tcg_round
;
10334 if (extract32(immh
, 3, 1)) {
10335 unallocated_encoding(s
);
10339 if (!fp_access_check(s
)) {
10343 tcg_rn
= tcg_temp_new_i64();
10344 tcg_rd
= tcg_temp_new_i64();
10345 tcg_final
= tcg_temp_new_i64();
10346 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10349 uint64_t round_const
= 1ULL << (shift
- 1);
10350 tcg_round
= tcg_const_i64(round_const
);
10355 for (i
= 0; i
< elements
; i
++) {
10356 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10357 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10358 false, true, size
+1, shift
);
10360 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10364 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10366 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10369 tcg_temp_free_i64(tcg_round
);
10371 tcg_temp_free_i64(tcg_rn
);
10372 tcg_temp_free_i64(tcg_rd
);
10373 tcg_temp_free_i64(tcg_final
);
10375 clear_vec_high(s
, is_q
, rd
);
10379 /* AdvSIMD shift by immediate
10380 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10381 * +---+---+---+-------------+------+------+--------+---+------+------+
10382 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10383 * +---+---+---+-------------+------+------+--------+---+------+------+
10385 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10387 int rd
= extract32(insn
, 0, 5);
10388 int rn
= extract32(insn
, 5, 5);
10389 int opcode
= extract32(insn
, 11, 5);
10390 int immb
= extract32(insn
, 16, 3);
10391 int immh
= extract32(insn
, 19, 4);
10392 bool is_u
= extract32(insn
, 29, 1);
10393 bool is_q
= extract32(insn
, 30, 1);
10396 case 0x08: /* SRI */
10398 unallocated_encoding(s
);
10402 case 0x00: /* SSHR / USHR */
10403 case 0x02: /* SSRA / USRA (accumulate) */
10404 case 0x04: /* SRSHR / URSHR (rounding) */
10405 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10406 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10408 case 0x0a: /* SHL / SLI */
10409 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10411 case 0x10: /* SHRN */
10412 case 0x11: /* RSHRN / SQRSHRUN */
10414 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10417 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10420 case 0x12: /* SQSHRN / UQSHRN */
10421 case 0x13: /* SQRSHRN / UQRSHRN */
10422 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10425 case 0x14: /* SSHLL / USHLL */
10426 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10428 case 0x1c: /* SCVTF / UCVTF */
10429 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10432 case 0xc: /* SQSHLU */
10434 unallocated_encoding(s
);
10437 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10439 case 0xe: /* SQSHL, UQSHL */
10440 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10442 case 0x1f: /* FCVTZS/ FCVTZU */
10443 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10446 unallocated_encoding(s
);
10451 /* Generate code to do a "long" addition or subtraction, ie one done in
10452 * TCGv_i64 on vector lanes twice the width specified by size.
10454 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10455 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10457 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10458 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10459 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10460 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10462 NeonGenTwo64OpFn
*genfn
;
10465 genfn
= fns
[size
][is_sub
];
10466 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10469 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10470 int opcode
, int rd
, int rn
, int rm
)
10472 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10473 TCGv_i64 tcg_res
[2];
10476 tcg_res
[0] = tcg_temp_new_i64();
10477 tcg_res
[1] = tcg_temp_new_i64();
10479 /* Does this op do an adding accumulate, a subtracting accumulate,
10480 * or no accumulate at all?
10498 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10499 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10502 /* size == 2 means two 32x32->64 operations; this is worth special
10503 * casing because we can generally handle it inline.
10506 for (pass
= 0; pass
< 2; pass
++) {
10507 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10508 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10509 TCGv_i64 tcg_passres
;
10510 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10512 int elt
= pass
+ is_q
* 2;
10514 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10515 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10518 tcg_passres
= tcg_res
[pass
];
10520 tcg_passres
= tcg_temp_new_i64();
10524 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10525 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10527 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10528 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10530 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10531 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10533 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10534 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10536 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10537 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10538 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10540 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10541 tcg_temp_free_i64(tcg_tmp1
);
10542 tcg_temp_free_i64(tcg_tmp2
);
10545 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10546 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10547 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10548 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10550 case 9: /* SQDMLAL, SQDMLAL2 */
10551 case 11: /* SQDMLSL, SQDMLSL2 */
10552 case 13: /* SQDMULL, SQDMULL2 */
10553 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10554 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10555 tcg_passres
, tcg_passres
);
10558 g_assert_not_reached();
10561 if (opcode
== 9 || opcode
== 11) {
10562 /* saturating accumulate ops */
10564 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10566 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10567 tcg_res
[pass
], tcg_passres
);
10568 } else if (accop
> 0) {
10569 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10570 } else if (accop
< 0) {
10571 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10575 tcg_temp_free_i64(tcg_passres
);
10578 tcg_temp_free_i64(tcg_op1
);
10579 tcg_temp_free_i64(tcg_op2
);
10582 /* size 0 or 1, generally helper functions */
10583 for (pass
= 0; pass
< 2; pass
++) {
10584 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10585 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10586 TCGv_i64 tcg_passres
;
10587 int elt
= pass
+ is_q
* 2;
10589 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10590 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10593 tcg_passres
= tcg_res
[pass
];
10595 tcg_passres
= tcg_temp_new_i64();
10599 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10600 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10602 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10603 static NeonGenWidenFn
* const widenfns
[2][2] = {
10604 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10605 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10607 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10609 widenfn(tcg_op2_64
, tcg_op2
);
10610 widenfn(tcg_passres
, tcg_op1
);
10611 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10612 tcg_passres
, tcg_op2_64
);
10613 tcg_temp_free_i64(tcg_op2_64
);
10616 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10617 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10620 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10622 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10626 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10628 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10632 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10633 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10634 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10637 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10639 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10643 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10645 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10649 case 9: /* SQDMLAL, SQDMLAL2 */
10650 case 11: /* SQDMLSL, SQDMLSL2 */
10651 case 13: /* SQDMULL, SQDMULL2 */
10653 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10654 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10655 tcg_passres
, tcg_passres
);
10657 case 14: /* PMULL */
10659 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
10662 g_assert_not_reached();
10664 tcg_temp_free_i32(tcg_op1
);
10665 tcg_temp_free_i32(tcg_op2
);
10668 if (opcode
== 9 || opcode
== 11) {
10669 /* saturating accumulate ops */
10671 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10673 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10677 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10678 tcg_res
[pass
], tcg_passres
);
10680 tcg_temp_free_i64(tcg_passres
);
10685 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10686 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10687 tcg_temp_free_i64(tcg_res
[0]);
10688 tcg_temp_free_i64(tcg_res
[1]);
10691 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10692 int opcode
, int rd
, int rn
, int rm
)
10694 TCGv_i64 tcg_res
[2];
10695 int part
= is_q
? 2 : 0;
10698 for (pass
= 0; pass
< 2; pass
++) {
10699 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10700 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10701 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10702 static NeonGenWidenFn
* const widenfns
[3][2] = {
10703 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10704 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10705 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10707 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10709 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10710 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10711 widenfn(tcg_op2_wide
, tcg_op2
);
10712 tcg_temp_free_i32(tcg_op2
);
10713 tcg_res
[pass
] = tcg_temp_new_i64();
10714 gen_neon_addl(size
, (opcode
== 3),
10715 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10716 tcg_temp_free_i64(tcg_op1
);
10717 tcg_temp_free_i64(tcg_op2_wide
);
10720 for (pass
= 0; pass
< 2; pass
++) {
10721 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10722 tcg_temp_free_i64(tcg_res
[pass
]);
10726 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10728 tcg_gen_addi_i64(in
, in
, 1U << 31);
10729 tcg_gen_extrh_i64_i32(res
, in
);
10732 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10733 int opcode
, int rd
, int rn
, int rm
)
10735 TCGv_i32 tcg_res
[2];
10736 int part
= is_q
? 2 : 0;
10739 for (pass
= 0; pass
< 2; pass
++) {
10740 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10741 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10742 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10743 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10744 { gen_helper_neon_narrow_high_u8
,
10745 gen_helper_neon_narrow_round_high_u8
},
10746 { gen_helper_neon_narrow_high_u16
,
10747 gen_helper_neon_narrow_round_high_u16
},
10748 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10750 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10752 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10753 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10755 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10757 tcg_temp_free_i64(tcg_op1
);
10758 tcg_temp_free_i64(tcg_op2
);
10760 tcg_res
[pass
] = tcg_temp_new_i32();
10761 gennarrow(tcg_res
[pass
], tcg_wideres
);
10762 tcg_temp_free_i64(tcg_wideres
);
10765 for (pass
= 0; pass
< 2; pass
++) {
10766 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10767 tcg_temp_free_i32(tcg_res
[pass
]);
10769 clear_vec_high(s
, is_q
, rd
);
10772 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
10774 /* PMULL of 64 x 64 -> 128 is an odd special case because it
10775 * is the only three-reg-diff instruction which produces a
10776 * 128-bit wide result from a single operation. However since
10777 * it's possible to calculate the two halves more or less
10778 * separately we just use two helper calls.
10780 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10781 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10782 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10784 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
10785 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
10786 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
10787 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
10788 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
10789 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
10791 tcg_temp_free_i64(tcg_op1
);
10792 tcg_temp_free_i64(tcg_op2
);
10793 tcg_temp_free_i64(tcg_res
);
10796 /* AdvSIMD three different
10797 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10798 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10799 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10800 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10802 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10804 /* Instructions in this group fall into three basic classes
10805 * (in each case with the operation working on each element in
10806 * the input vectors):
10807 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10809 * (2) wide 64 x 128 -> 128
10810 * (3) narrowing 128 x 128 -> 64
10811 * Here we do initial decode, catch unallocated cases and
10812 * dispatch to separate functions for each class.
10814 int is_q
= extract32(insn
, 30, 1);
10815 int is_u
= extract32(insn
, 29, 1);
10816 int size
= extract32(insn
, 22, 2);
10817 int opcode
= extract32(insn
, 12, 4);
10818 int rm
= extract32(insn
, 16, 5);
10819 int rn
= extract32(insn
, 5, 5);
10820 int rd
= extract32(insn
, 0, 5);
10823 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10824 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10825 /* 64 x 128 -> 128 */
10827 unallocated_encoding(s
);
10830 if (!fp_access_check(s
)) {
10833 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10835 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10836 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10837 /* 128 x 128 -> 64 */
10839 unallocated_encoding(s
);
10842 if (!fp_access_check(s
)) {
10845 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10847 case 14: /* PMULL, PMULL2 */
10848 if (is_u
|| size
== 1 || size
== 2) {
10849 unallocated_encoding(s
);
10853 if (!dc_isar_feature(aa64_pmull
, s
)) {
10854 unallocated_encoding(s
);
10857 if (!fp_access_check(s
)) {
10860 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
10864 case 9: /* SQDMLAL, SQDMLAL2 */
10865 case 11: /* SQDMLSL, SQDMLSL2 */
10866 case 13: /* SQDMULL, SQDMULL2 */
10867 if (is_u
|| size
== 0) {
10868 unallocated_encoding(s
);
10872 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10873 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10874 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10875 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10876 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10877 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10878 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10879 /* 64 x 64 -> 128 */
10881 unallocated_encoding(s
);
10885 if (!fp_access_check(s
)) {
10889 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10892 /* opcode 15 not allocated */
10893 unallocated_encoding(s
);
10898 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10899 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10901 int rd
= extract32(insn
, 0, 5);
10902 int rn
= extract32(insn
, 5, 5);
10903 int rm
= extract32(insn
, 16, 5);
10904 int size
= extract32(insn
, 22, 2);
10905 bool is_u
= extract32(insn
, 29, 1);
10906 bool is_q
= extract32(insn
, 30, 1);
10908 if (!fp_access_check(s
)) {
10912 switch (size
+ 4 * is_u
) {
10914 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10917 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10920 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10923 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10926 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10929 case 5: /* BSL bitwise select */
10930 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
10932 case 6: /* BIT, bitwise insert if true */
10933 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
10935 case 7: /* BIF, bitwise insert if false */
10936 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
10940 g_assert_not_reached();
10944 /* Pairwise op subgroup of C3.6.16.
10946 * This is called directly or via the handle_3same_float for float pairwise
10947 * operations where the opcode and size are calculated differently.
10949 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10950 int size
, int rn
, int rm
, int rd
)
10955 /* Floating point operations need fpst */
10956 if (opcode
>= 0x58) {
10957 fpst
= get_fpstatus_ptr(false);
10962 if (!fp_access_check(s
)) {
10966 /* These operations work on the concatenated rm:rn, with each pair of
10967 * adjacent elements being operated on to produce an element in the result.
10970 TCGv_i64 tcg_res
[2];
10972 for (pass
= 0; pass
< 2; pass
++) {
10973 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10974 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10975 int passreg
= (pass
== 0) ? rn
: rm
;
10977 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10978 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10979 tcg_res
[pass
] = tcg_temp_new_i64();
10982 case 0x17: /* ADDP */
10983 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10985 case 0x58: /* FMAXNMP */
10986 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10988 case 0x5a: /* FADDP */
10989 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10991 case 0x5e: /* FMAXP */
10992 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10994 case 0x78: /* FMINNMP */
10995 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10997 case 0x7e: /* FMINP */
10998 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11001 g_assert_not_reached();
11004 tcg_temp_free_i64(tcg_op1
);
11005 tcg_temp_free_i64(tcg_op2
);
11008 for (pass
= 0; pass
< 2; pass
++) {
11009 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11010 tcg_temp_free_i64(tcg_res
[pass
]);
11013 int maxpass
= is_q
? 4 : 2;
11014 TCGv_i32 tcg_res
[4];
11016 for (pass
= 0; pass
< maxpass
; pass
++) {
11017 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11018 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11019 NeonGenTwoOpFn
*genfn
= NULL
;
11020 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11021 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
11023 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
11024 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
11025 tcg_res
[pass
] = tcg_temp_new_i32();
11028 case 0x17: /* ADDP */
11030 static NeonGenTwoOpFn
* const fns
[3] = {
11031 gen_helper_neon_padd_u8
,
11032 gen_helper_neon_padd_u16
,
11038 case 0x14: /* SMAXP, UMAXP */
11040 static NeonGenTwoOpFn
* const fns
[3][2] = {
11041 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11042 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11043 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11045 genfn
= fns
[size
][u
];
11048 case 0x15: /* SMINP, UMINP */
11050 static NeonGenTwoOpFn
* const fns
[3][2] = {
11051 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11052 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11053 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11055 genfn
= fns
[size
][u
];
11058 /* The FP operations are all on single floats (32 bit) */
11059 case 0x58: /* FMAXNMP */
11060 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11062 case 0x5a: /* FADDP */
11063 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11065 case 0x5e: /* FMAXP */
11066 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11068 case 0x78: /* FMINNMP */
11069 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11071 case 0x7e: /* FMINP */
11072 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11075 g_assert_not_reached();
11078 /* FP ops called directly, otherwise call now */
11080 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11083 tcg_temp_free_i32(tcg_op1
);
11084 tcg_temp_free_i32(tcg_op2
);
11087 for (pass
= 0; pass
< maxpass
; pass
++) {
11088 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11089 tcg_temp_free_i32(tcg_res
[pass
]);
11091 clear_vec_high(s
, is_q
, rd
);
11095 tcg_temp_free_ptr(fpst
);
11099 /* Floating point op subgroup of C3.6.16. */
11100 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11102 /* For floating point ops, the U, size[1] and opcode bits
11103 * together indicate the operation. size[0] indicates single
11106 int fpopcode
= extract32(insn
, 11, 5)
11107 | (extract32(insn
, 23, 1) << 5)
11108 | (extract32(insn
, 29, 1) << 6);
11109 int is_q
= extract32(insn
, 30, 1);
11110 int size
= extract32(insn
, 22, 1);
11111 int rm
= extract32(insn
, 16, 5);
11112 int rn
= extract32(insn
, 5, 5);
11113 int rd
= extract32(insn
, 0, 5);
11115 int datasize
= is_q
? 128 : 64;
11116 int esize
= 32 << size
;
11117 int elements
= datasize
/ esize
;
11119 if (size
== 1 && !is_q
) {
11120 unallocated_encoding(s
);
11124 switch (fpopcode
) {
11125 case 0x58: /* FMAXNMP */
11126 case 0x5a: /* FADDP */
11127 case 0x5e: /* FMAXP */
11128 case 0x78: /* FMINNMP */
11129 case 0x7e: /* FMINP */
11130 if (size
&& !is_q
) {
11131 unallocated_encoding(s
);
11134 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11137 case 0x1b: /* FMULX */
11138 case 0x1f: /* FRECPS */
11139 case 0x3f: /* FRSQRTS */
11140 case 0x5d: /* FACGE */
11141 case 0x7d: /* FACGT */
11142 case 0x19: /* FMLA */
11143 case 0x39: /* FMLS */
11144 case 0x18: /* FMAXNM */
11145 case 0x1a: /* FADD */
11146 case 0x1c: /* FCMEQ */
11147 case 0x1e: /* FMAX */
11148 case 0x38: /* FMINNM */
11149 case 0x3a: /* FSUB */
11150 case 0x3e: /* FMIN */
11151 case 0x5b: /* FMUL */
11152 case 0x5c: /* FCMGE */
11153 case 0x5f: /* FDIV */
11154 case 0x7a: /* FABD */
11155 case 0x7c: /* FCMGT */
11156 if (!fp_access_check(s
)) {
11159 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11162 case 0x1d: /* FMLAL */
11163 case 0x3d: /* FMLSL */
11164 case 0x59: /* FMLAL2 */
11165 case 0x79: /* FMLSL2 */
11166 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11167 unallocated_encoding(s
);
11170 if (fp_access_check(s
)) {
11171 int is_s
= extract32(insn
, 23, 1);
11172 int is_2
= extract32(insn
, 29, 1);
11173 int data
= (is_2
<< 1) | is_s
;
11174 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11175 vec_full_reg_offset(s
, rn
),
11176 vec_full_reg_offset(s
, rm
), cpu_env
,
11177 is_q
? 16 : 8, vec_full_reg_size(s
),
11178 data
, gen_helper_gvec_fmlal_a64
);
11183 unallocated_encoding(s
);
11188 /* Integer op subgroup of C3.6.16. */
11189 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11191 int is_q
= extract32(insn
, 30, 1);
11192 int u
= extract32(insn
, 29, 1);
11193 int size
= extract32(insn
, 22, 2);
11194 int opcode
= extract32(insn
, 11, 5);
11195 int rm
= extract32(insn
, 16, 5);
11196 int rn
= extract32(insn
, 5, 5);
11197 int rd
= extract32(insn
, 0, 5);
11202 case 0x13: /* MUL, PMUL */
11203 if (u
&& size
!= 0) {
11204 unallocated_encoding(s
);
11208 case 0x0: /* SHADD, UHADD */
11209 case 0x2: /* SRHADD, URHADD */
11210 case 0x4: /* SHSUB, UHSUB */
11211 case 0xc: /* SMAX, UMAX */
11212 case 0xd: /* SMIN, UMIN */
11213 case 0xe: /* SABD, UABD */
11214 case 0xf: /* SABA, UABA */
11215 case 0x12: /* MLA, MLS */
11217 unallocated_encoding(s
);
11221 case 0x16: /* SQDMULH, SQRDMULH */
11222 if (size
== 0 || size
== 3) {
11223 unallocated_encoding(s
);
11228 if (size
== 3 && !is_q
) {
11229 unallocated_encoding(s
);
11235 if (!fp_access_check(s
)) {
11240 case 0x01: /* SQADD, UQADD */
11241 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11242 offsetof(CPUARMState
, vfp
.qc
),
11243 vec_full_reg_offset(s
, rn
),
11244 vec_full_reg_offset(s
, rm
),
11245 is_q
? 16 : 8, vec_full_reg_size(s
),
11246 (u
? uqadd_op
: sqadd_op
) + size
);
11248 case 0x05: /* SQSUB, UQSUB */
11249 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11250 offsetof(CPUARMState
, vfp
.qc
),
11251 vec_full_reg_offset(s
, rn
),
11252 vec_full_reg_offset(s
, rm
),
11253 is_q
? 16 : 8, vec_full_reg_size(s
),
11254 (u
? uqsub_op
: sqsub_op
) + size
);
11256 case 0x0c: /* SMAX, UMAX */
11258 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11260 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11263 case 0x0d: /* SMIN, UMIN */
11265 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11267 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11270 case 0x10: /* ADD, SUB */
11272 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11274 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11277 case 0x13: /* MUL, PMUL */
11278 if (!u
) { /* MUL */
11279 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11283 case 0x12: /* MLA, MLS */
11285 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
11287 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
11291 if (!u
) { /* CMTST */
11292 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
11296 cond
= TCG_COND_EQ
;
11298 case 0x06: /* CMGT, CMHI */
11299 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11301 case 0x07: /* CMGE, CMHS */
11302 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11304 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11305 vec_full_reg_offset(s
, rn
),
11306 vec_full_reg_offset(s
, rm
),
11307 is_q
? 16 : 8, vec_full_reg_size(s
));
11313 for (pass
= 0; pass
< 2; pass
++) {
11314 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11315 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11316 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11318 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11319 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11321 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11323 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11325 tcg_temp_free_i64(tcg_res
);
11326 tcg_temp_free_i64(tcg_op1
);
11327 tcg_temp_free_i64(tcg_op2
);
11330 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11331 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11332 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11333 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11334 NeonGenTwoOpFn
*genfn
= NULL
;
11335 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11337 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11338 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11341 case 0x0: /* SHADD, UHADD */
11343 static NeonGenTwoOpFn
* const fns
[3][2] = {
11344 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11345 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11346 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11348 genfn
= fns
[size
][u
];
11351 case 0x2: /* SRHADD, URHADD */
11353 static NeonGenTwoOpFn
* const fns
[3][2] = {
11354 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11355 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11356 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11358 genfn
= fns
[size
][u
];
11361 case 0x4: /* SHSUB, UHSUB */
11363 static NeonGenTwoOpFn
* const fns
[3][2] = {
11364 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11365 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11366 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11368 genfn
= fns
[size
][u
];
11371 case 0x8: /* SSHL, USHL */
11373 static NeonGenTwoOpFn
* const fns
[3][2] = {
11374 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
11375 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
11376 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
11378 genfn
= fns
[size
][u
];
11381 case 0x9: /* SQSHL, UQSHL */
11383 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11384 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11385 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11386 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11388 genenvfn
= fns
[size
][u
];
11391 case 0xa: /* SRSHL, URSHL */
11393 static NeonGenTwoOpFn
* const fns
[3][2] = {
11394 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11395 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11396 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11398 genfn
= fns
[size
][u
];
11401 case 0xb: /* SQRSHL, UQRSHL */
11403 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11404 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11405 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11406 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11408 genenvfn
= fns
[size
][u
];
11411 case 0xe: /* SABD, UABD */
11412 case 0xf: /* SABA, UABA */
11414 static NeonGenTwoOpFn
* const fns
[3][2] = {
11415 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
11416 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
11417 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
11419 genfn
= fns
[size
][u
];
11422 case 0x13: /* MUL, PMUL */
11423 assert(u
); /* PMUL */
11425 genfn
= gen_helper_neon_mul_p8
;
11427 case 0x16: /* SQDMULH, SQRDMULH */
11429 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11430 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11431 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11433 assert(size
== 1 || size
== 2);
11434 genenvfn
= fns
[size
- 1][u
];
11438 g_assert_not_reached();
11442 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11444 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11447 if (opcode
== 0xf) {
11448 /* SABA, UABA: accumulating ops */
11449 static NeonGenTwoOpFn
* const fns
[3] = {
11450 gen_helper_neon_add_u8
,
11451 gen_helper_neon_add_u16
,
11455 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11456 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11459 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11461 tcg_temp_free_i32(tcg_res
);
11462 tcg_temp_free_i32(tcg_op1
);
11463 tcg_temp_free_i32(tcg_op2
);
11466 clear_vec_high(s
, is_q
, rd
);
11469 /* AdvSIMD three same
11470 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11471 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11472 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11473 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11475 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11477 int opcode
= extract32(insn
, 11, 5);
11480 case 0x3: /* logic ops */
11481 disas_simd_3same_logic(s
, insn
);
11483 case 0x17: /* ADDP */
11484 case 0x14: /* SMAXP, UMAXP */
11485 case 0x15: /* SMINP, UMINP */
11487 /* Pairwise operations */
11488 int is_q
= extract32(insn
, 30, 1);
11489 int u
= extract32(insn
, 29, 1);
11490 int size
= extract32(insn
, 22, 2);
11491 int rm
= extract32(insn
, 16, 5);
11492 int rn
= extract32(insn
, 5, 5);
11493 int rd
= extract32(insn
, 0, 5);
11494 if (opcode
== 0x17) {
11495 if (u
|| (size
== 3 && !is_q
)) {
11496 unallocated_encoding(s
);
11501 unallocated_encoding(s
);
11505 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11508 case 0x18 ... 0x31:
11509 /* floating point ops, sz[1] and U are part of opcode */
11510 disas_simd_3same_float(s
, insn
);
11513 disas_simd_3same_int(s
, insn
);
11519 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11521 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11522 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11523 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11524 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11526 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11527 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11530 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11532 int opcode
, fpopcode
;
11533 int is_q
, u
, a
, rm
, rn
, rd
;
11534 int datasize
, elements
;
11537 bool pairwise
= false;
11539 if (!dc_isar_feature(aa64_fp16
, s
)) {
11540 unallocated_encoding(s
);
11544 if (!fp_access_check(s
)) {
11548 /* For these floating point ops, the U, a and opcode bits
11549 * together indicate the operation.
11551 opcode
= extract32(insn
, 11, 3);
11552 u
= extract32(insn
, 29, 1);
11553 a
= extract32(insn
, 23, 1);
11554 is_q
= extract32(insn
, 30, 1);
11555 rm
= extract32(insn
, 16, 5);
11556 rn
= extract32(insn
, 5, 5);
11557 rd
= extract32(insn
, 0, 5);
11559 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11560 datasize
= is_q
? 128 : 64;
11561 elements
= datasize
/ 16;
11563 switch (fpopcode
) {
11564 case 0x10: /* FMAXNMP */
11565 case 0x12: /* FADDP */
11566 case 0x16: /* FMAXP */
11567 case 0x18: /* FMINNMP */
11568 case 0x1e: /* FMINP */
11573 fpst
= get_fpstatus_ptr(true);
11576 int maxpass
= is_q
? 8 : 4;
11577 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11578 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11579 TCGv_i32 tcg_res
[8];
11581 for (pass
= 0; pass
< maxpass
; pass
++) {
11582 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11583 int passelt
= (pass
<< 1) & (maxpass
- 1);
11585 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11586 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11587 tcg_res
[pass
] = tcg_temp_new_i32();
11589 switch (fpopcode
) {
11590 case 0x10: /* FMAXNMP */
11591 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11594 case 0x12: /* FADDP */
11595 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11597 case 0x16: /* FMAXP */
11598 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11600 case 0x18: /* FMINNMP */
11601 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11604 case 0x1e: /* FMINP */
11605 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11608 g_assert_not_reached();
11612 for (pass
= 0; pass
< maxpass
; pass
++) {
11613 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11614 tcg_temp_free_i32(tcg_res
[pass
]);
11617 tcg_temp_free_i32(tcg_op1
);
11618 tcg_temp_free_i32(tcg_op2
);
11621 for (pass
= 0; pass
< elements
; pass
++) {
11622 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11623 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11624 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11626 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11627 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11629 switch (fpopcode
) {
11630 case 0x0: /* FMAXNM */
11631 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11633 case 0x1: /* FMLA */
11634 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11635 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11638 case 0x2: /* FADD */
11639 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11641 case 0x3: /* FMULX */
11642 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11644 case 0x4: /* FCMEQ */
11645 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11647 case 0x6: /* FMAX */
11648 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11650 case 0x7: /* FRECPS */
11651 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11653 case 0x8: /* FMINNM */
11654 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11656 case 0x9: /* FMLS */
11657 /* As usual for ARM, separate negation for fused multiply-add */
11658 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11659 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11660 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11663 case 0xa: /* FSUB */
11664 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11666 case 0xe: /* FMIN */
11667 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11669 case 0xf: /* FRSQRTS */
11670 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11672 case 0x13: /* FMUL */
11673 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11675 case 0x14: /* FCMGE */
11676 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11678 case 0x15: /* FACGE */
11679 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11681 case 0x17: /* FDIV */
11682 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11684 case 0x1a: /* FABD */
11685 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11686 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11688 case 0x1c: /* FCMGT */
11689 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11691 case 0x1d: /* FACGT */
11692 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11695 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11696 __func__
, insn
, fpopcode
, s
->pc
);
11697 g_assert_not_reached();
11700 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11701 tcg_temp_free_i32(tcg_res
);
11702 tcg_temp_free_i32(tcg_op1
);
11703 tcg_temp_free_i32(tcg_op2
);
11707 tcg_temp_free_ptr(fpst
);
11709 clear_vec_high(s
, is_q
, rd
);
11712 /* AdvSIMD three same extra
11713 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11714 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11715 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11716 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11718 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11720 int rd
= extract32(insn
, 0, 5);
11721 int rn
= extract32(insn
, 5, 5);
11722 int opcode
= extract32(insn
, 11, 4);
11723 int rm
= extract32(insn
, 16, 5);
11724 int size
= extract32(insn
, 22, 2);
11725 bool u
= extract32(insn
, 29, 1);
11726 bool is_q
= extract32(insn
, 30, 1);
11730 switch (u
* 16 + opcode
) {
11731 case 0x10: /* SQRDMLAH (vector) */
11732 case 0x11: /* SQRDMLSH (vector) */
11733 if (size
!= 1 && size
!= 2) {
11734 unallocated_encoding(s
);
11737 feature
= dc_isar_feature(aa64_rdm
, s
);
11739 case 0x02: /* SDOT (vector) */
11740 case 0x12: /* UDOT (vector) */
11741 if (size
!= MO_32
) {
11742 unallocated_encoding(s
);
11745 feature
= dc_isar_feature(aa64_dp
, s
);
11747 case 0x18: /* FCMLA, #0 */
11748 case 0x19: /* FCMLA, #90 */
11749 case 0x1a: /* FCMLA, #180 */
11750 case 0x1b: /* FCMLA, #270 */
11751 case 0x1c: /* FCADD, #90 */
11752 case 0x1e: /* FCADD, #270 */
11754 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11755 || (size
== 3 && !is_q
)) {
11756 unallocated_encoding(s
);
11759 feature
= dc_isar_feature(aa64_fcma
, s
);
11762 unallocated_encoding(s
);
11766 unallocated_encoding(s
);
11769 if (!fp_access_check(s
)) {
11774 case 0x0: /* SQRDMLAH (vector) */
11777 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11780 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11783 g_assert_not_reached();
11787 case 0x1: /* SQRDMLSH (vector) */
11790 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11793 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11796 g_assert_not_reached();
11800 case 0x2: /* SDOT / UDOT */
11801 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11802 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11805 case 0x8: /* FCMLA, #0 */
11806 case 0x9: /* FCMLA, #90 */
11807 case 0xa: /* FCMLA, #180 */
11808 case 0xb: /* FCMLA, #270 */
11809 rot
= extract32(opcode
, 0, 2);
11812 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11813 gen_helper_gvec_fcmlah
);
11816 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11817 gen_helper_gvec_fcmlas
);
11820 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11821 gen_helper_gvec_fcmlad
);
11824 g_assert_not_reached();
11828 case 0xc: /* FCADD, #90 */
11829 case 0xe: /* FCADD, #270 */
11830 rot
= extract32(opcode
, 1, 1);
11833 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11834 gen_helper_gvec_fcaddh
);
11837 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11838 gen_helper_gvec_fcadds
);
11841 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11842 gen_helper_gvec_fcaddd
);
11845 g_assert_not_reached();
11850 g_assert_not_reached();
11854 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11855 int size
, int rn
, int rd
)
11857 /* Handle 2-reg-misc ops which are widening (so each size element
11858 * in the source becomes a 2*size element in the destination.
11859 * The only instruction like this is FCVTL.
11864 /* 32 -> 64 bit fp conversion */
11865 TCGv_i64 tcg_res
[2];
11866 int srcelt
= is_q
? 2 : 0;
11868 for (pass
= 0; pass
< 2; pass
++) {
11869 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11870 tcg_res
[pass
] = tcg_temp_new_i64();
11872 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11873 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11874 tcg_temp_free_i32(tcg_op
);
11876 for (pass
= 0; pass
< 2; pass
++) {
11877 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11878 tcg_temp_free_i64(tcg_res
[pass
]);
11881 /* 16 -> 32 bit fp conversion */
11882 int srcelt
= is_q
? 4 : 0;
11883 TCGv_i32 tcg_res
[4];
11884 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11885 TCGv_i32 ahp
= get_ahp_flag();
11887 for (pass
= 0; pass
< 4; pass
++) {
11888 tcg_res
[pass
] = tcg_temp_new_i32();
11890 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11891 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11894 for (pass
= 0; pass
< 4; pass
++) {
11895 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11896 tcg_temp_free_i32(tcg_res
[pass
]);
11899 tcg_temp_free_ptr(fpst
);
11900 tcg_temp_free_i32(ahp
);
11904 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11905 bool is_q
, int size
, int rn
, int rd
)
11907 int op
= (opcode
<< 1) | u
;
11908 int opsz
= op
+ size
;
11909 int grp_size
= 3 - opsz
;
11910 int dsize
= is_q
? 128 : 64;
11914 unallocated_encoding(s
);
11918 if (!fp_access_check(s
)) {
11923 /* Special case bytes, use bswap op on each group of elements */
11924 int groups
= dsize
/ (8 << grp_size
);
11926 for (i
= 0; i
< groups
; i
++) {
11927 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11929 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11930 switch (grp_size
) {
11932 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11935 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11938 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11941 g_assert_not_reached();
11943 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11944 tcg_temp_free_i64(tcg_tmp
);
11946 clear_vec_high(s
, is_q
, rd
);
11948 int revmask
= (1 << grp_size
) - 1;
11949 int esize
= 8 << size
;
11950 int elements
= dsize
/ esize
;
11951 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11952 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11953 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11955 for (i
= 0; i
< elements
; i
++) {
11956 int e_rev
= (i
& 0xf) ^ revmask
;
11957 int off
= e_rev
* esize
;
11958 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11960 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11961 tcg_rn
, off
- 64, esize
);
11963 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11966 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11967 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11969 tcg_temp_free_i64(tcg_rd_hi
);
11970 tcg_temp_free_i64(tcg_rd
);
11971 tcg_temp_free_i64(tcg_rn
);
11975 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11976 bool is_q
, int size
, int rn
, int rd
)
11978 /* Implement the pairwise operations from 2-misc:
11979 * SADDLP, UADDLP, SADALP, UADALP.
11980 * These all add pairs of elements in the input to produce a
11981 * double-width result element in the output (possibly accumulating).
11983 bool accum
= (opcode
== 0x6);
11984 int maxpass
= is_q
? 2 : 1;
11986 TCGv_i64 tcg_res
[2];
11989 /* 32 + 32 -> 64 op */
11990 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11992 for (pass
= 0; pass
< maxpass
; pass
++) {
11993 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11994 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11996 tcg_res
[pass
] = tcg_temp_new_i64();
11998 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11999 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
12000 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
12002 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
12003 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
12006 tcg_temp_free_i64(tcg_op1
);
12007 tcg_temp_free_i64(tcg_op2
);
12010 for (pass
= 0; pass
< maxpass
; pass
++) {
12011 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12012 NeonGenOneOpFn
*genfn
;
12013 static NeonGenOneOpFn
* const fns
[2][2] = {
12014 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
12015 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
12018 genfn
= fns
[size
][u
];
12020 tcg_res
[pass
] = tcg_temp_new_i64();
12022 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12023 genfn(tcg_res
[pass
], tcg_op
);
12026 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
12028 gen_helper_neon_addl_u16(tcg_res
[pass
],
12029 tcg_res
[pass
], tcg_op
);
12031 gen_helper_neon_addl_u32(tcg_res
[pass
],
12032 tcg_res
[pass
], tcg_op
);
12035 tcg_temp_free_i64(tcg_op
);
12039 tcg_res
[1] = tcg_const_i64(0);
12041 for (pass
= 0; pass
< 2; pass
++) {
12042 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12043 tcg_temp_free_i64(tcg_res
[pass
]);
12047 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
12049 /* Implement SHLL and SHLL2 */
12051 int part
= is_q
? 2 : 0;
12052 TCGv_i64 tcg_res
[2];
12054 for (pass
= 0; pass
< 2; pass
++) {
12055 static NeonGenWidenFn
* const widenfns
[3] = {
12056 gen_helper_neon_widen_u8
,
12057 gen_helper_neon_widen_u16
,
12058 tcg_gen_extu_i32_i64
,
12060 NeonGenWidenFn
*widenfn
= widenfns
[size
];
12061 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12063 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
12064 tcg_res
[pass
] = tcg_temp_new_i64();
12065 widenfn(tcg_res
[pass
], tcg_op
);
12066 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
12068 tcg_temp_free_i32(tcg_op
);
12071 for (pass
= 0; pass
< 2; pass
++) {
12072 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12073 tcg_temp_free_i64(tcg_res
[pass
]);
12077 /* AdvSIMD two reg misc
12078 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12079 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12080 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12081 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12083 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12085 int size
= extract32(insn
, 22, 2);
12086 int opcode
= extract32(insn
, 12, 5);
12087 bool u
= extract32(insn
, 29, 1);
12088 bool is_q
= extract32(insn
, 30, 1);
12089 int rn
= extract32(insn
, 5, 5);
12090 int rd
= extract32(insn
, 0, 5);
12091 bool need_fpstatus
= false;
12092 bool need_rmode
= false;
12094 TCGv_i32 tcg_rmode
;
12095 TCGv_ptr tcg_fpstatus
;
12098 case 0x0: /* REV64, REV32 */
12099 case 0x1: /* REV16 */
12100 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12102 case 0x5: /* CNT, NOT, RBIT */
12103 if (u
&& size
== 0) {
12106 } else if (u
&& size
== 1) {
12109 } else if (!u
&& size
== 0) {
12113 unallocated_encoding(s
);
12115 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12116 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12118 unallocated_encoding(s
);
12121 if (!fp_access_check(s
)) {
12125 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12127 case 0x4: /* CLS, CLZ */
12129 unallocated_encoding(s
);
12133 case 0x2: /* SADDLP, UADDLP */
12134 case 0x6: /* SADALP, UADALP */
12136 unallocated_encoding(s
);
12139 if (!fp_access_check(s
)) {
12142 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12144 case 0x13: /* SHLL, SHLL2 */
12145 if (u
== 0 || size
== 3) {
12146 unallocated_encoding(s
);
12149 if (!fp_access_check(s
)) {
12152 handle_shll(s
, is_q
, size
, rn
, rd
);
12154 case 0xa: /* CMLT */
12156 unallocated_encoding(s
);
12160 case 0x8: /* CMGT, CMGE */
12161 case 0x9: /* CMEQ, CMLE */
12162 case 0xb: /* ABS, NEG */
12163 if (size
== 3 && !is_q
) {
12164 unallocated_encoding(s
);
12168 case 0x3: /* SUQADD, USQADD */
12169 if (size
== 3 && !is_q
) {
12170 unallocated_encoding(s
);
12173 if (!fp_access_check(s
)) {
12176 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12178 case 0x7: /* SQABS, SQNEG */
12179 if (size
== 3 && !is_q
) {
12180 unallocated_encoding(s
);
12185 case 0x16 ... 0x1f:
12187 /* Floating point: U, size[1] and opcode indicate operation;
12188 * size[0] indicates single or double precision.
12190 int is_double
= extract32(size
, 0, 1);
12191 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12192 size
= is_double
? 3 : 2;
12194 case 0x2f: /* FABS */
12195 case 0x6f: /* FNEG */
12196 if (size
== 3 && !is_q
) {
12197 unallocated_encoding(s
);
12201 case 0x1d: /* SCVTF */
12202 case 0x5d: /* UCVTF */
12204 bool is_signed
= (opcode
== 0x1d) ? true : false;
12205 int elements
= is_double
? 2 : is_q
? 4 : 2;
12206 if (is_double
&& !is_q
) {
12207 unallocated_encoding(s
);
12210 if (!fp_access_check(s
)) {
12213 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12216 case 0x2c: /* FCMGT (zero) */
12217 case 0x2d: /* FCMEQ (zero) */
12218 case 0x2e: /* FCMLT (zero) */
12219 case 0x6c: /* FCMGE (zero) */
12220 case 0x6d: /* FCMLE (zero) */
12221 if (size
== 3 && !is_q
) {
12222 unallocated_encoding(s
);
12225 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12227 case 0x7f: /* FSQRT */
12228 if (size
== 3 && !is_q
) {
12229 unallocated_encoding(s
);
12233 case 0x1a: /* FCVTNS */
12234 case 0x1b: /* FCVTMS */
12235 case 0x3a: /* FCVTPS */
12236 case 0x3b: /* FCVTZS */
12237 case 0x5a: /* FCVTNU */
12238 case 0x5b: /* FCVTMU */
12239 case 0x7a: /* FCVTPU */
12240 case 0x7b: /* FCVTZU */
12241 need_fpstatus
= true;
12243 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12244 if (size
== 3 && !is_q
) {
12245 unallocated_encoding(s
);
12249 case 0x5c: /* FCVTAU */
12250 case 0x1c: /* FCVTAS */
12251 need_fpstatus
= true;
12253 rmode
= FPROUNDING_TIEAWAY
;
12254 if (size
== 3 && !is_q
) {
12255 unallocated_encoding(s
);
12259 case 0x3c: /* URECPE */
12261 unallocated_encoding(s
);
12265 case 0x3d: /* FRECPE */
12266 case 0x7d: /* FRSQRTE */
12267 if (size
== 3 && !is_q
) {
12268 unallocated_encoding(s
);
12271 if (!fp_access_check(s
)) {
12274 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12276 case 0x56: /* FCVTXN, FCVTXN2 */
12278 unallocated_encoding(s
);
12282 case 0x16: /* FCVTN, FCVTN2 */
12283 /* handle_2misc_narrow does a 2*size -> size operation, but these
12284 * instructions encode the source size rather than dest size.
12286 if (!fp_access_check(s
)) {
12289 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12291 case 0x17: /* FCVTL, FCVTL2 */
12292 if (!fp_access_check(s
)) {
12295 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12297 case 0x18: /* FRINTN */
12298 case 0x19: /* FRINTM */
12299 case 0x38: /* FRINTP */
12300 case 0x39: /* FRINTZ */
12302 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12304 case 0x59: /* FRINTX */
12305 case 0x79: /* FRINTI */
12306 need_fpstatus
= true;
12307 if (size
== 3 && !is_q
) {
12308 unallocated_encoding(s
);
12312 case 0x58: /* FRINTA */
12314 rmode
= FPROUNDING_TIEAWAY
;
12315 need_fpstatus
= true;
12316 if (size
== 3 && !is_q
) {
12317 unallocated_encoding(s
);
12321 case 0x7c: /* URSQRTE */
12323 unallocated_encoding(s
);
12326 need_fpstatus
= true;
12328 case 0x1e: /* FRINT32Z */
12329 case 0x1f: /* FRINT64Z */
12331 rmode
= FPROUNDING_ZERO
;
12333 case 0x5e: /* FRINT32X */
12334 case 0x5f: /* FRINT64X */
12335 need_fpstatus
= true;
12336 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12337 unallocated_encoding(s
);
12342 unallocated_encoding(s
);
12348 unallocated_encoding(s
);
12352 if (!fp_access_check(s
)) {
12356 if (need_fpstatus
|| need_rmode
) {
12357 tcg_fpstatus
= get_fpstatus_ptr(false);
12359 tcg_fpstatus
= NULL
;
12362 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12363 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12370 if (u
&& size
== 0) { /* NOT */
12371 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12376 if (u
) { /* ABS, NEG */
12377 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12379 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12385 /* All 64-bit element operations can be shared with scalar 2misc */
12388 /* Coverity claims (size == 3 && !is_q) has been eliminated
12389 * from all paths leading to here.
12391 tcg_debug_assert(is_q
);
12392 for (pass
= 0; pass
< 2; pass
++) {
12393 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12394 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12396 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12398 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12399 tcg_rmode
, tcg_fpstatus
);
12401 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12403 tcg_temp_free_i64(tcg_res
);
12404 tcg_temp_free_i64(tcg_op
);
12409 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12410 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12411 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12414 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12417 /* Special cases for 32 bit elements */
12419 case 0xa: /* CMLT */
12420 /* 32 bit integer comparison against zero, result is
12421 * test ? (2^32 - 1) : 0. We implement via setcond(test)
12424 cond
= TCG_COND_LT
;
12426 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
12427 tcg_gen_neg_i32(tcg_res
, tcg_res
);
12429 case 0x8: /* CMGT, CMGE */
12430 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
12432 case 0x9: /* CMEQ, CMLE */
12433 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
12435 case 0x4: /* CLS */
12437 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12439 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12442 case 0x7: /* SQABS, SQNEG */
12444 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12446 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12449 case 0x2f: /* FABS */
12450 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12452 case 0x6f: /* FNEG */
12453 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12455 case 0x7f: /* FSQRT */
12456 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12458 case 0x1a: /* FCVTNS */
12459 case 0x1b: /* FCVTMS */
12460 case 0x1c: /* FCVTAS */
12461 case 0x3a: /* FCVTPS */
12462 case 0x3b: /* FCVTZS */
12464 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12465 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12466 tcg_shift
, tcg_fpstatus
);
12467 tcg_temp_free_i32(tcg_shift
);
12470 case 0x5a: /* FCVTNU */
12471 case 0x5b: /* FCVTMU */
12472 case 0x5c: /* FCVTAU */
12473 case 0x7a: /* FCVTPU */
12474 case 0x7b: /* FCVTZU */
12476 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12477 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12478 tcg_shift
, tcg_fpstatus
);
12479 tcg_temp_free_i32(tcg_shift
);
12482 case 0x18: /* FRINTN */
12483 case 0x19: /* FRINTM */
12484 case 0x38: /* FRINTP */
12485 case 0x39: /* FRINTZ */
12486 case 0x58: /* FRINTA */
12487 case 0x79: /* FRINTI */
12488 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12490 case 0x59: /* FRINTX */
12491 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12493 case 0x7c: /* URSQRTE */
12494 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
12496 case 0x1e: /* FRINT32Z */
12497 case 0x5e: /* FRINT32X */
12498 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12500 case 0x1f: /* FRINT64Z */
12501 case 0x5f: /* FRINT64X */
12502 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12505 g_assert_not_reached();
12508 /* Use helpers for 8 and 16 bit elements */
12510 case 0x5: /* CNT, RBIT */
12511 /* For these two insns size is part of the opcode specifier
12512 * (handled earlier); they always operate on byte elements.
12515 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12517 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12520 case 0x7: /* SQABS, SQNEG */
12522 NeonGenOneOpEnvFn
*genfn
;
12523 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12524 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12525 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12527 genfn
= fns
[size
][u
];
12528 genfn(tcg_res
, cpu_env
, tcg_op
);
12531 case 0x8: /* CMGT, CMGE */
12532 case 0x9: /* CMEQ, CMLE */
12533 case 0xa: /* CMLT */
12535 static NeonGenTwoOpFn
* const fns
[3][2] = {
12536 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
12537 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
12538 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
12540 NeonGenTwoOpFn
*genfn
;
12543 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12545 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
12546 comp
= (opcode
- 0x8) * 2 + u
;
12547 /* ...but LE, LT are implemented as reverse GE, GT */
12548 reverse
= (comp
> 2);
12552 genfn
= fns
[comp
][size
];
12554 genfn(tcg_res
, tcg_zero
, tcg_op
);
12556 genfn(tcg_res
, tcg_op
, tcg_zero
);
12558 tcg_temp_free_i32(tcg_zero
);
12561 case 0x4: /* CLS, CLZ */
12564 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12566 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12570 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12572 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12577 g_assert_not_reached();
12581 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12583 tcg_temp_free_i32(tcg_res
);
12584 tcg_temp_free_i32(tcg_op
);
12587 clear_vec_high(s
, is_q
, rd
);
12590 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12591 tcg_temp_free_i32(tcg_rmode
);
12593 if (need_fpstatus
) {
12594 tcg_temp_free_ptr(tcg_fpstatus
);
12598 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12600 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12601 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12602 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12603 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12604 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12605 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12607 * This actually covers two groups where scalar access is governed by
12608 * bit 28. A bunch of the instructions (float to integral) only exist
12609 * in the vector form and are un-allocated for the scalar decode. Also
12610 * in the scalar decode Q is always 1.
12612 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12614 int fpop
, opcode
, a
, u
;
12618 bool only_in_vector
= false;
12621 TCGv_i32 tcg_rmode
= NULL
;
12622 TCGv_ptr tcg_fpstatus
= NULL
;
12623 bool need_rmode
= false;
12624 bool need_fpst
= true;
12627 if (!dc_isar_feature(aa64_fp16
, s
)) {
12628 unallocated_encoding(s
);
12632 rd
= extract32(insn
, 0, 5);
12633 rn
= extract32(insn
, 5, 5);
12635 a
= extract32(insn
, 23, 1);
12636 u
= extract32(insn
, 29, 1);
12637 is_scalar
= extract32(insn
, 28, 1);
12638 is_q
= extract32(insn
, 30, 1);
12640 opcode
= extract32(insn
, 12, 5);
12641 fpop
= deposit32(opcode
, 5, 1, a
);
12642 fpop
= deposit32(fpop
, 6, 1, u
);
12644 rd
= extract32(insn
, 0, 5);
12645 rn
= extract32(insn
, 5, 5);
12648 case 0x1d: /* SCVTF */
12649 case 0x5d: /* UCVTF */
12656 elements
= (is_q
? 8 : 4);
12659 if (!fp_access_check(s
)) {
12662 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12666 case 0x2c: /* FCMGT (zero) */
12667 case 0x2d: /* FCMEQ (zero) */
12668 case 0x2e: /* FCMLT (zero) */
12669 case 0x6c: /* FCMGE (zero) */
12670 case 0x6d: /* FCMLE (zero) */
12671 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12673 case 0x3d: /* FRECPE */
12674 case 0x3f: /* FRECPX */
12676 case 0x18: /* FRINTN */
12678 only_in_vector
= true;
12679 rmode
= FPROUNDING_TIEEVEN
;
12681 case 0x19: /* FRINTM */
12683 only_in_vector
= true;
12684 rmode
= FPROUNDING_NEGINF
;
12686 case 0x38: /* FRINTP */
12688 only_in_vector
= true;
12689 rmode
= FPROUNDING_POSINF
;
12691 case 0x39: /* FRINTZ */
12693 only_in_vector
= true;
12694 rmode
= FPROUNDING_ZERO
;
12696 case 0x58: /* FRINTA */
12698 only_in_vector
= true;
12699 rmode
= FPROUNDING_TIEAWAY
;
12701 case 0x59: /* FRINTX */
12702 case 0x79: /* FRINTI */
12703 only_in_vector
= true;
12704 /* current rounding mode */
12706 case 0x1a: /* FCVTNS */
12708 rmode
= FPROUNDING_TIEEVEN
;
12710 case 0x1b: /* FCVTMS */
12712 rmode
= FPROUNDING_NEGINF
;
12714 case 0x1c: /* FCVTAS */
12716 rmode
= FPROUNDING_TIEAWAY
;
12718 case 0x3a: /* FCVTPS */
12720 rmode
= FPROUNDING_POSINF
;
12722 case 0x3b: /* FCVTZS */
12724 rmode
= FPROUNDING_ZERO
;
12726 case 0x5a: /* FCVTNU */
12728 rmode
= FPROUNDING_TIEEVEN
;
12730 case 0x5b: /* FCVTMU */
12732 rmode
= FPROUNDING_NEGINF
;
12734 case 0x5c: /* FCVTAU */
12736 rmode
= FPROUNDING_TIEAWAY
;
12738 case 0x7a: /* FCVTPU */
12740 rmode
= FPROUNDING_POSINF
;
12742 case 0x7b: /* FCVTZU */
12744 rmode
= FPROUNDING_ZERO
;
12746 case 0x2f: /* FABS */
12747 case 0x6f: /* FNEG */
12750 case 0x7d: /* FRSQRTE */
12751 case 0x7f: /* FSQRT (vector) */
12754 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12755 g_assert_not_reached();
12759 /* Check additional constraints for the scalar encoding */
12762 unallocated_encoding(s
);
12765 /* FRINTxx is only in the vector form */
12766 if (only_in_vector
) {
12767 unallocated_encoding(s
);
12772 if (!fp_access_check(s
)) {
12776 if (need_rmode
|| need_fpst
) {
12777 tcg_fpstatus
= get_fpstatus_ptr(true);
12781 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12782 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12786 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12787 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12790 case 0x1a: /* FCVTNS */
12791 case 0x1b: /* FCVTMS */
12792 case 0x1c: /* FCVTAS */
12793 case 0x3a: /* FCVTPS */
12794 case 0x3b: /* FCVTZS */
12795 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12797 case 0x3d: /* FRECPE */
12798 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12800 case 0x3f: /* FRECPX */
12801 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12803 case 0x5a: /* FCVTNU */
12804 case 0x5b: /* FCVTMU */
12805 case 0x5c: /* FCVTAU */
12806 case 0x7a: /* FCVTPU */
12807 case 0x7b: /* FCVTZU */
12808 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12810 case 0x6f: /* FNEG */
12811 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12813 case 0x7d: /* FRSQRTE */
12814 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12817 g_assert_not_reached();
12820 /* limit any sign extension going on */
12821 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12822 write_fp_sreg(s
, rd
, tcg_res
);
12824 tcg_temp_free_i32(tcg_res
);
12825 tcg_temp_free_i32(tcg_op
);
12827 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12828 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12829 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12831 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12834 case 0x1a: /* FCVTNS */
12835 case 0x1b: /* FCVTMS */
12836 case 0x1c: /* FCVTAS */
12837 case 0x3a: /* FCVTPS */
12838 case 0x3b: /* FCVTZS */
12839 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12841 case 0x3d: /* FRECPE */
12842 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12844 case 0x5a: /* FCVTNU */
12845 case 0x5b: /* FCVTMU */
12846 case 0x5c: /* FCVTAU */
12847 case 0x7a: /* FCVTPU */
12848 case 0x7b: /* FCVTZU */
12849 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12851 case 0x18: /* FRINTN */
12852 case 0x19: /* FRINTM */
12853 case 0x38: /* FRINTP */
12854 case 0x39: /* FRINTZ */
12855 case 0x58: /* FRINTA */
12856 case 0x79: /* FRINTI */
12857 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12859 case 0x59: /* FRINTX */
12860 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12862 case 0x2f: /* FABS */
12863 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12865 case 0x6f: /* FNEG */
12866 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12868 case 0x7d: /* FRSQRTE */
12869 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12871 case 0x7f: /* FSQRT */
12872 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12875 g_assert_not_reached();
12878 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12880 tcg_temp_free_i32(tcg_res
);
12881 tcg_temp_free_i32(tcg_op
);
12884 clear_vec_high(s
, is_q
, rd
);
12888 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12889 tcg_temp_free_i32(tcg_rmode
);
12892 if (tcg_fpstatus
) {
12893 tcg_temp_free_ptr(tcg_fpstatus
);
12897 /* AdvSIMD scalar x indexed element
12898 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12899 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12900 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12901 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12902 * AdvSIMD vector x indexed element
12903 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12904 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12905 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12906 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12908 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12910 /* This encoding has two kinds of instruction:
12911 * normal, where we perform elt x idxelt => elt for each
12912 * element in the vector
12913 * long, where we perform elt x idxelt and generate a result of
12914 * double the width of the input element
12915 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12917 bool is_scalar
= extract32(insn
, 28, 1);
12918 bool is_q
= extract32(insn
, 30, 1);
12919 bool u
= extract32(insn
, 29, 1);
12920 int size
= extract32(insn
, 22, 2);
12921 int l
= extract32(insn
, 21, 1);
12922 int m
= extract32(insn
, 20, 1);
12923 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12924 int rm
= extract32(insn
, 16, 4);
12925 int opcode
= extract32(insn
, 12, 4);
12926 int h
= extract32(insn
, 11, 1);
12927 int rn
= extract32(insn
, 5, 5);
12928 int rd
= extract32(insn
, 0, 5);
12929 bool is_long
= false;
12931 bool is_fp16
= false;
12935 switch (16 * u
+ opcode
) {
12936 case 0x08: /* MUL */
12937 case 0x10: /* MLA */
12938 case 0x14: /* MLS */
12940 unallocated_encoding(s
);
12944 case 0x02: /* SMLAL, SMLAL2 */
12945 case 0x12: /* UMLAL, UMLAL2 */
12946 case 0x06: /* SMLSL, SMLSL2 */
12947 case 0x16: /* UMLSL, UMLSL2 */
12948 case 0x0a: /* SMULL, SMULL2 */
12949 case 0x1a: /* UMULL, UMULL2 */
12951 unallocated_encoding(s
);
12956 case 0x03: /* SQDMLAL, SQDMLAL2 */
12957 case 0x07: /* SQDMLSL, SQDMLSL2 */
12958 case 0x0b: /* SQDMULL, SQDMULL2 */
12961 case 0x0c: /* SQDMULH */
12962 case 0x0d: /* SQRDMULH */
12964 case 0x01: /* FMLA */
12965 case 0x05: /* FMLS */
12966 case 0x09: /* FMUL */
12967 case 0x19: /* FMULX */
12970 case 0x1d: /* SQRDMLAH */
12971 case 0x1f: /* SQRDMLSH */
12972 if (!dc_isar_feature(aa64_rdm
, s
)) {
12973 unallocated_encoding(s
);
12977 case 0x0e: /* SDOT */
12978 case 0x1e: /* UDOT */
12979 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12980 unallocated_encoding(s
);
12984 case 0x11: /* FCMLA #0 */
12985 case 0x13: /* FCMLA #90 */
12986 case 0x15: /* FCMLA #180 */
12987 case 0x17: /* FCMLA #270 */
12988 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12989 unallocated_encoding(s
);
12994 case 0x00: /* FMLAL */
12995 case 0x04: /* FMLSL */
12996 case 0x18: /* FMLAL2 */
12997 case 0x1c: /* FMLSL2 */
12998 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
12999 unallocated_encoding(s
);
13003 /* is_fp, but we pass cpu_env not fp_status. */
13006 unallocated_encoding(s
);
13011 case 1: /* normal fp */
13012 /* convert insn encoded size to TCGMemOp size */
13014 case 0: /* half-precision */
13018 case MO_32
: /* single precision */
13019 case MO_64
: /* double precision */
13022 unallocated_encoding(s
);
13027 case 2: /* complex fp */
13028 /* Each indexable element is a complex pair. */
13033 unallocated_encoding(s
);
13041 unallocated_encoding(s
);
13046 default: /* integer */
13050 unallocated_encoding(s
);
13055 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
13056 unallocated_encoding(s
);
13060 /* Given TCGMemOp size, adjust register and indexing. */
13063 index
= h
<< 2 | l
<< 1 | m
;
13066 index
= h
<< 1 | l
;
13071 unallocated_encoding(s
);
13078 g_assert_not_reached();
13081 if (!fp_access_check(s
)) {
13086 fpst
= get_fpstatus_ptr(is_fp16
);
13091 switch (16 * u
+ opcode
) {
13092 case 0x0e: /* SDOT */
13093 case 0x1e: /* UDOT */
13094 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
13095 u
? gen_helper_gvec_udot_idx_b
13096 : gen_helper_gvec_sdot_idx_b
);
13098 case 0x11: /* FCMLA #0 */
13099 case 0x13: /* FCMLA #90 */
13100 case 0x15: /* FCMLA #180 */
13101 case 0x17: /* FCMLA #270 */
13103 int rot
= extract32(insn
, 13, 2);
13104 int data
= (index
<< 2) | rot
;
13105 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13106 vec_full_reg_offset(s
, rn
),
13107 vec_full_reg_offset(s
, rm
), fpst
,
13108 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13110 ? gen_helper_gvec_fcmlas_idx
13111 : gen_helper_gvec_fcmlah_idx
);
13112 tcg_temp_free_ptr(fpst
);
13116 case 0x00: /* FMLAL */
13117 case 0x04: /* FMLSL */
13118 case 0x18: /* FMLAL2 */
13119 case 0x1c: /* FMLSL2 */
13121 int is_s
= extract32(opcode
, 2, 1);
13123 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13124 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13125 vec_full_reg_offset(s
, rn
),
13126 vec_full_reg_offset(s
, rm
), cpu_env
,
13127 is_q
? 16 : 8, vec_full_reg_size(s
),
13128 data
, gen_helper_gvec_fmlal_idx_a64
);
13134 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13137 assert(is_fp
&& is_q
&& !is_long
);
13139 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13141 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13142 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13143 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13145 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13147 switch (16 * u
+ opcode
) {
13148 case 0x05: /* FMLS */
13149 /* As usual for ARM, separate negation for fused multiply-add */
13150 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13152 case 0x01: /* FMLA */
13153 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13154 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13156 case 0x09: /* FMUL */
13157 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13159 case 0x19: /* FMULX */
13160 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13163 g_assert_not_reached();
13166 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13167 tcg_temp_free_i64(tcg_op
);
13168 tcg_temp_free_i64(tcg_res
);
13171 tcg_temp_free_i64(tcg_idx
);
13172 clear_vec_high(s
, !is_scalar
, rd
);
13173 } else if (!is_long
) {
13174 /* 32 bit floating point, or 16 or 32 bit integer.
13175 * For the 16 bit scalar case we use the usual Neon helpers and
13176 * rely on the fact that 0 op 0 == 0 with no side effects.
13178 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13179 int pass
, maxpasses
;
13184 maxpasses
= is_q
? 4 : 2;
13187 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13189 if (size
== 1 && !is_scalar
) {
13190 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13191 * the index into both halves of the 32 bit tcg_idx and then use
13192 * the usual Neon helpers.
13194 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13197 for (pass
= 0; pass
< maxpasses
; pass
++) {
13198 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13199 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13201 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13203 switch (16 * u
+ opcode
) {
13204 case 0x08: /* MUL */
13205 case 0x10: /* MLA */
13206 case 0x14: /* MLS */
13208 static NeonGenTwoOpFn
* const fns
[2][2] = {
13209 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13210 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13212 NeonGenTwoOpFn
*genfn
;
13213 bool is_sub
= opcode
== 0x4;
13216 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13218 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13220 if (opcode
== 0x8) {
13223 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13224 genfn
= fns
[size
- 1][is_sub
];
13225 genfn(tcg_res
, tcg_op
, tcg_res
);
13228 case 0x05: /* FMLS */
13229 case 0x01: /* FMLA */
13230 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13231 is_scalar
? size
: MO_32
);
13234 if (opcode
== 0x5) {
13235 /* As usual for ARM, separate negation for fused
13237 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13240 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13243 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13248 if (opcode
== 0x5) {
13249 /* As usual for ARM, separate negation for
13250 * fused multiply-add */
13251 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13253 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13257 g_assert_not_reached();
13260 case 0x09: /* FMUL */
13264 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13267 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13272 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13275 g_assert_not_reached();
13278 case 0x19: /* FMULX */
13282 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13285 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13290 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13293 g_assert_not_reached();
13296 case 0x0c: /* SQDMULH */
13298 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13301 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13305 case 0x0d: /* SQRDMULH */
13307 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13310 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13314 case 0x1d: /* SQRDMLAH */
13315 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13316 is_scalar
? size
: MO_32
);
13318 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13319 tcg_op
, tcg_idx
, tcg_res
);
13321 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13322 tcg_op
, tcg_idx
, tcg_res
);
13325 case 0x1f: /* SQRDMLSH */
13326 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13327 is_scalar
? size
: MO_32
);
13329 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13330 tcg_op
, tcg_idx
, tcg_res
);
13332 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13333 tcg_op
, tcg_idx
, tcg_res
);
13337 g_assert_not_reached();
13341 write_fp_sreg(s
, rd
, tcg_res
);
13343 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13346 tcg_temp_free_i32(tcg_op
);
13347 tcg_temp_free_i32(tcg_res
);
13350 tcg_temp_free_i32(tcg_idx
);
13351 clear_vec_high(s
, is_q
, rd
);
13353 /* long ops: 16x16->32 or 32x32->64 */
13354 TCGv_i64 tcg_res
[2];
13356 bool satop
= extract32(opcode
, 0, 1);
13357 TCGMemOp memop
= MO_32
;
13364 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13366 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13368 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13369 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13370 TCGv_i64 tcg_passres
;
13376 passelt
= pass
+ (is_q
* 2);
13379 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13381 tcg_res
[pass
] = tcg_temp_new_i64();
13383 if (opcode
== 0xa || opcode
== 0xb) {
13384 /* Non-accumulating ops */
13385 tcg_passres
= tcg_res
[pass
];
13387 tcg_passres
= tcg_temp_new_i64();
13390 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13391 tcg_temp_free_i64(tcg_op
);
13394 /* saturating, doubling */
13395 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13396 tcg_passres
, tcg_passres
);
13399 if (opcode
== 0xa || opcode
== 0xb) {
13403 /* Accumulating op: handle accumulate step */
13404 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13407 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13408 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13410 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13411 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13413 case 0x7: /* SQDMLSL, SQDMLSL2 */
13414 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13416 case 0x3: /* SQDMLAL, SQDMLAL2 */
13417 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13422 g_assert_not_reached();
13424 tcg_temp_free_i64(tcg_passres
);
13426 tcg_temp_free_i64(tcg_idx
);
13428 clear_vec_high(s
, !is_scalar
, rd
);
13430 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13433 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13436 /* The simplest way to handle the 16x16 indexed ops is to
13437 * duplicate the index into both halves of the 32 bit tcg_idx
13438 * and then use the usual Neon helpers.
13440 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13443 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13444 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13445 TCGv_i64 tcg_passres
;
13448 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13450 read_vec_element_i32(s
, tcg_op
, rn
,
13451 pass
+ (is_q
* 2), MO_32
);
13454 tcg_res
[pass
] = tcg_temp_new_i64();
13456 if (opcode
== 0xa || opcode
== 0xb) {
13457 /* Non-accumulating ops */
13458 tcg_passres
= tcg_res
[pass
];
13460 tcg_passres
= tcg_temp_new_i64();
13463 if (memop
& MO_SIGN
) {
13464 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13466 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13469 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13470 tcg_passres
, tcg_passres
);
13472 tcg_temp_free_i32(tcg_op
);
13474 if (opcode
== 0xa || opcode
== 0xb) {
13478 /* Accumulating op: handle accumulate step */
13479 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13482 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13483 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13486 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13487 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13490 case 0x7: /* SQDMLSL, SQDMLSL2 */
13491 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13493 case 0x3: /* SQDMLAL, SQDMLAL2 */
13494 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13499 g_assert_not_reached();
13501 tcg_temp_free_i64(tcg_passres
);
13503 tcg_temp_free_i32(tcg_idx
);
13506 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13511 tcg_res
[1] = tcg_const_i64(0);
13514 for (pass
= 0; pass
< 2; pass
++) {
13515 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13516 tcg_temp_free_i64(tcg_res
[pass
]);
13521 tcg_temp_free_ptr(fpst
);
13526 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13527 * +-----------------+------+-----------+--------+-----+------+------+
13528 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13529 * +-----------------+------+-----------+--------+-----+------+------+
13531 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13533 int size
= extract32(insn
, 22, 2);
13534 int opcode
= extract32(insn
, 12, 5);
13535 int rn
= extract32(insn
, 5, 5);
13536 int rd
= extract32(insn
, 0, 5);
13538 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13539 TCGv_i32 tcg_decrypt
;
13540 CryptoThreeOpIntFn
*genfn
;
13542 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13543 unallocated_encoding(s
);
13548 case 0x4: /* AESE */
13550 genfn
= gen_helper_crypto_aese
;
13552 case 0x6: /* AESMC */
13554 genfn
= gen_helper_crypto_aesmc
;
13556 case 0x5: /* AESD */
13558 genfn
= gen_helper_crypto_aese
;
13560 case 0x7: /* AESIMC */
13562 genfn
= gen_helper_crypto_aesmc
;
13565 unallocated_encoding(s
);
13569 if (!fp_access_check(s
)) {
13573 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13574 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13575 tcg_decrypt
= tcg_const_i32(decrypt
);
13577 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
13579 tcg_temp_free_ptr(tcg_rd_ptr
);
13580 tcg_temp_free_ptr(tcg_rn_ptr
);
13581 tcg_temp_free_i32(tcg_decrypt
);
13584 /* Crypto three-reg SHA
13585 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13586 * +-----------------+------+---+------+---+--------+-----+------+------+
13587 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13588 * +-----------------+------+---+------+---+--------+-----+------+------+
13590 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13592 int size
= extract32(insn
, 22, 2);
13593 int opcode
= extract32(insn
, 12, 3);
13594 int rm
= extract32(insn
, 16, 5);
13595 int rn
= extract32(insn
, 5, 5);
13596 int rd
= extract32(insn
, 0, 5);
13597 CryptoThreeOpFn
*genfn
;
13598 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13602 unallocated_encoding(s
);
13607 case 0: /* SHA1C */
13608 case 1: /* SHA1P */
13609 case 2: /* SHA1M */
13610 case 3: /* SHA1SU0 */
13612 feature
= dc_isar_feature(aa64_sha1
, s
);
13614 case 4: /* SHA256H */
13615 genfn
= gen_helper_crypto_sha256h
;
13616 feature
= dc_isar_feature(aa64_sha256
, s
);
13618 case 5: /* SHA256H2 */
13619 genfn
= gen_helper_crypto_sha256h2
;
13620 feature
= dc_isar_feature(aa64_sha256
, s
);
13622 case 6: /* SHA256SU1 */
13623 genfn
= gen_helper_crypto_sha256su1
;
13624 feature
= dc_isar_feature(aa64_sha256
, s
);
13627 unallocated_encoding(s
);
13632 unallocated_encoding(s
);
13636 if (!fp_access_check(s
)) {
13640 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13641 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13642 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13645 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13647 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13649 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13650 tcg_rm_ptr
, tcg_opcode
);
13651 tcg_temp_free_i32(tcg_opcode
);
13654 tcg_temp_free_ptr(tcg_rd_ptr
);
13655 tcg_temp_free_ptr(tcg_rn_ptr
);
13656 tcg_temp_free_ptr(tcg_rm_ptr
);
13659 /* Crypto two-reg SHA
13660 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13661 * +-----------------+------+-----------+--------+-----+------+------+
13662 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13663 * +-----------------+------+-----------+--------+-----+------+------+
13665 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13667 int size
= extract32(insn
, 22, 2);
13668 int opcode
= extract32(insn
, 12, 5);
13669 int rn
= extract32(insn
, 5, 5);
13670 int rd
= extract32(insn
, 0, 5);
13671 CryptoTwoOpFn
*genfn
;
13673 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13676 unallocated_encoding(s
);
13681 case 0: /* SHA1H */
13682 feature
= dc_isar_feature(aa64_sha1
, s
);
13683 genfn
= gen_helper_crypto_sha1h
;
13685 case 1: /* SHA1SU1 */
13686 feature
= dc_isar_feature(aa64_sha1
, s
);
13687 genfn
= gen_helper_crypto_sha1su1
;
13689 case 2: /* SHA256SU0 */
13690 feature
= dc_isar_feature(aa64_sha256
, s
);
13691 genfn
= gen_helper_crypto_sha256su0
;
13694 unallocated_encoding(s
);
13699 unallocated_encoding(s
);
13703 if (!fp_access_check(s
)) {
13707 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13708 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13710 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13712 tcg_temp_free_ptr(tcg_rd_ptr
);
13713 tcg_temp_free_ptr(tcg_rn_ptr
);
13716 /* Crypto three-reg SHA512
13717 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13718 * +-----------------------+------+---+---+-----+--------+------+------+
13719 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13720 * +-----------------------+------+---+---+-----+--------+------+------+
13722 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13724 int opcode
= extract32(insn
, 10, 2);
13725 int o
= extract32(insn
, 14, 1);
13726 int rm
= extract32(insn
, 16, 5);
13727 int rn
= extract32(insn
, 5, 5);
13728 int rd
= extract32(insn
, 0, 5);
13730 CryptoThreeOpFn
*genfn
;
13734 case 0: /* SHA512H */
13735 feature
= dc_isar_feature(aa64_sha512
, s
);
13736 genfn
= gen_helper_crypto_sha512h
;
13738 case 1: /* SHA512H2 */
13739 feature
= dc_isar_feature(aa64_sha512
, s
);
13740 genfn
= gen_helper_crypto_sha512h2
;
13742 case 2: /* SHA512SU1 */
13743 feature
= dc_isar_feature(aa64_sha512
, s
);
13744 genfn
= gen_helper_crypto_sha512su1
;
13747 feature
= dc_isar_feature(aa64_sha3
, s
);
13753 case 0: /* SM3PARTW1 */
13754 feature
= dc_isar_feature(aa64_sm3
, s
);
13755 genfn
= gen_helper_crypto_sm3partw1
;
13757 case 1: /* SM3PARTW2 */
13758 feature
= dc_isar_feature(aa64_sm3
, s
);
13759 genfn
= gen_helper_crypto_sm3partw2
;
13761 case 2: /* SM4EKEY */
13762 feature
= dc_isar_feature(aa64_sm4
, s
);
13763 genfn
= gen_helper_crypto_sm4ekey
;
13766 unallocated_encoding(s
);
13772 unallocated_encoding(s
);
13776 if (!fp_access_check(s
)) {
13781 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13783 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13784 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13785 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13787 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13789 tcg_temp_free_ptr(tcg_rd_ptr
);
13790 tcg_temp_free_ptr(tcg_rn_ptr
);
13791 tcg_temp_free_ptr(tcg_rm_ptr
);
13793 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13796 tcg_op1
= tcg_temp_new_i64();
13797 tcg_op2
= tcg_temp_new_i64();
13798 tcg_res
[0] = tcg_temp_new_i64();
13799 tcg_res
[1] = tcg_temp_new_i64();
13801 for (pass
= 0; pass
< 2; pass
++) {
13802 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13803 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13805 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13806 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13808 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13809 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13811 tcg_temp_free_i64(tcg_op1
);
13812 tcg_temp_free_i64(tcg_op2
);
13813 tcg_temp_free_i64(tcg_res
[0]);
13814 tcg_temp_free_i64(tcg_res
[1]);
13818 /* Crypto two-reg SHA512
13819 * 31 12 11 10 9 5 4 0
13820 * +-----------------------------------------+--------+------+------+
13821 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13822 * +-----------------------------------------+--------+------+------+
13824 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13826 int opcode
= extract32(insn
, 10, 2);
13827 int rn
= extract32(insn
, 5, 5);
13828 int rd
= extract32(insn
, 0, 5);
13829 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13831 CryptoTwoOpFn
*genfn
;
13834 case 0: /* SHA512SU0 */
13835 feature
= dc_isar_feature(aa64_sha512
, s
);
13836 genfn
= gen_helper_crypto_sha512su0
;
13839 feature
= dc_isar_feature(aa64_sm4
, s
);
13840 genfn
= gen_helper_crypto_sm4e
;
13843 unallocated_encoding(s
);
13848 unallocated_encoding(s
);
13852 if (!fp_access_check(s
)) {
13856 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13857 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13859 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13861 tcg_temp_free_ptr(tcg_rd_ptr
);
13862 tcg_temp_free_ptr(tcg_rn_ptr
);
13865 /* Crypto four-register
13866 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13867 * +-------------------+-----+------+---+------+------+------+
13868 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13869 * +-------------------+-----+------+---+------+------+------+
13871 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13873 int op0
= extract32(insn
, 21, 2);
13874 int rm
= extract32(insn
, 16, 5);
13875 int ra
= extract32(insn
, 10, 5);
13876 int rn
= extract32(insn
, 5, 5);
13877 int rd
= extract32(insn
, 0, 5);
13883 feature
= dc_isar_feature(aa64_sha3
, s
);
13885 case 2: /* SM3SS1 */
13886 feature
= dc_isar_feature(aa64_sm3
, s
);
13889 unallocated_encoding(s
);
13894 unallocated_encoding(s
);
13898 if (!fp_access_check(s
)) {
13903 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13906 tcg_op1
= tcg_temp_new_i64();
13907 tcg_op2
= tcg_temp_new_i64();
13908 tcg_op3
= tcg_temp_new_i64();
13909 tcg_res
[0] = tcg_temp_new_i64();
13910 tcg_res
[1] = tcg_temp_new_i64();
13912 for (pass
= 0; pass
< 2; pass
++) {
13913 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13914 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13915 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13919 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13922 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13924 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13926 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13927 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13929 tcg_temp_free_i64(tcg_op1
);
13930 tcg_temp_free_i64(tcg_op2
);
13931 tcg_temp_free_i64(tcg_op3
);
13932 tcg_temp_free_i64(tcg_res
[0]);
13933 tcg_temp_free_i64(tcg_res
[1]);
13935 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13937 tcg_op1
= tcg_temp_new_i32();
13938 tcg_op2
= tcg_temp_new_i32();
13939 tcg_op3
= tcg_temp_new_i32();
13940 tcg_res
= tcg_temp_new_i32();
13941 tcg_zero
= tcg_const_i32(0);
13943 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13944 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13945 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13947 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13948 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13949 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13950 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13952 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13953 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13954 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13955 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13957 tcg_temp_free_i32(tcg_op1
);
13958 tcg_temp_free_i32(tcg_op2
);
13959 tcg_temp_free_i32(tcg_op3
);
13960 tcg_temp_free_i32(tcg_res
);
13961 tcg_temp_free_i32(tcg_zero
);
13966 * 31 21 20 16 15 10 9 5 4 0
13967 * +-----------------------+------+--------+------+------+
13968 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13969 * +-----------------------+------+--------+------+------+
13971 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13973 int rm
= extract32(insn
, 16, 5);
13974 int imm6
= extract32(insn
, 10, 6);
13975 int rn
= extract32(insn
, 5, 5);
13976 int rd
= extract32(insn
, 0, 5);
13977 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13980 if (!dc_isar_feature(aa64_sha3
, s
)) {
13981 unallocated_encoding(s
);
13985 if (!fp_access_check(s
)) {
13989 tcg_op1
= tcg_temp_new_i64();
13990 tcg_op2
= tcg_temp_new_i64();
13991 tcg_res
[0] = tcg_temp_new_i64();
13992 tcg_res
[1] = tcg_temp_new_i64();
13994 for (pass
= 0; pass
< 2; pass
++) {
13995 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13996 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13998 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13999 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
14001 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
14002 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
14004 tcg_temp_free_i64(tcg_op1
);
14005 tcg_temp_free_i64(tcg_op2
);
14006 tcg_temp_free_i64(tcg_res
[0]);
14007 tcg_temp_free_i64(tcg_res
[1]);
14010 /* Crypto three-reg imm2
14011 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14012 * +-----------------------+------+-----+------+--------+------+------+
14013 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
14014 * +-----------------------+------+-----+------+--------+------+------+
14016 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
14018 int opcode
= extract32(insn
, 10, 2);
14019 int imm2
= extract32(insn
, 12, 2);
14020 int rm
= extract32(insn
, 16, 5);
14021 int rn
= extract32(insn
, 5, 5);
14022 int rd
= extract32(insn
, 0, 5);
14023 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
14024 TCGv_i32 tcg_imm2
, tcg_opcode
;
14026 if (!dc_isar_feature(aa64_sm3
, s
)) {
14027 unallocated_encoding(s
);
14031 if (!fp_access_check(s
)) {
14035 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
14036 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
14037 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
14038 tcg_imm2
= tcg_const_i32(imm2
);
14039 tcg_opcode
= tcg_const_i32(opcode
);
14041 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
14044 tcg_temp_free_ptr(tcg_rd_ptr
);
14045 tcg_temp_free_ptr(tcg_rn_ptr
);
14046 tcg_temp_free_ptr(tcg_rm_ptr
);
14047 tcg_temp_free_i32(tcg_imm2
);
14048 tcg_temp_free_i32(tcg_opcode
);
14051 /* C3.6 Data processing - SIMD, inc Crypto
14053 * As the decode gets a little complex we are using a table based
14054 * approach for this part of the decode.
14056 static const AArch64DecodeTable data_proc_simd
[] = {
14057 /* pattern , mask , fn */
14058 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
14059 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
14060 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
14061 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
14062 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
14063 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
14064 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
14065 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
14066 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
14067 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
14068 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
14069 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
14070 { 0x2e000000, 0xbf208400, disas_simd_ext
},
14071 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
14072 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
14073 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
14074 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
14075 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
14076 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
14077 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
14078 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
14079 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
14080 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
14081 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
14082 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
14083 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
14084 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
14085 { 0xce800000, 0xffe00000, disas_crypto_xar
},
14086 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
14087 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
14088 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
14089 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
14090 { 0x00000000, 0x00000000, NULL
}
14093 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
14095 /* Note that this is called with all non-FP cases from
14096 * table C3-6 so it must UNDEF for entries not specifically
14097 * allocated to instructions in that table.
14099 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
14103 unallocated_encoding(s
);
14107 /* C3.6 Data processing - SIMD and floating point */
14108 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
14110 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
14111 disas_data_proc_fp(s
, insn
);
14113 /* SIMD, including crypto */
14114 disas_data_proc_simd(s
, insn
);
14120 * @env: The cpu environment
14121 * @s: The DisasContext
14123 * Return true if the page is guarded.
14125 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
14127 #ifdef CONFIG_USER_ONLY
14128 return false; /* FIXME */
14130 uint64_t addr
= s
->base
.pc_first
;
14131 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14132 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
14133 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
14136 * We test this immediately after reading an insn, which means
14137 * that any normal page must be in the TLB. The only exception
14138 * would be for executing from flash or device memory, which
14139 * does not retain the TLB entry.
14141 * FIXME: Assume false for those, for now. We could use
14142 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14143 * table entry even for that case.
14145 return (tlb_hit(entry
->addr_code
, addr
) &&
14146 env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
.target_tlb_bit0
);
14151 * btype_destination_ok:
14152 * @insn: The instruction at the branch destination
14153 * @bt: SCTLR_ELx.BT
14154 * @btype: PSTATE.BTYPE, and is non-zero
14156 * On a guarded page, there are a limited number of insns
14157 * that may be present at the branch target:
14158 * - branch target identifiers,
14159 * - paciasp, pacibsp,
14162 * Anything else causes a Branch Target Exception.
14164 * Return true if the branch is compatible, false to raise BTITRAP.
14166 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14168 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14170 switch (extract32(insn
, 5, 7)) {
14171 case 0b011001: /* PACIASP */
14172 case 0b011011: /* PACIBSP */
14174 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14175 * with btype == 3. Otherwise all btype are ok.
14177 return !bt
|| btype
!= 3;
14178 case 0b100000: /* BTI */
14179 /* Not compatible with any btype. */
14181 case 0b100010: /* BTI c */
14182 /* Not compatible with btype == 3 */
14184 case 0b100100: /* BTI j */
14185 /* Not compatible with btype == 2 */
14187 case 0b100110: /* BTI jc */
14188 /* Compatible with any btype. */
14192 switch (insn
& 0xffe0001fu
) {
14193 case 0xd4200000u
: /* BRK */
14194 case 0xd4400000u
: /* HLT */
14195 /* Give priority to the breakpoint exception. */
14202 /* C3.1 A64 instruction index by encoding */
14203 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14207 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
14211 s
->fp_access_checked
= false;
14213 if (dc_isar_feature(aa64_bti
, s
)) {
14214 if (s
->base
.num_insns
== 1) {
14216 * At the first insn of the TB, compute s->guarded_page.
14217 * We delayed computing this until successfully reading
14218 * the first insn of the TB, above. This (mostly) ensures
14219 * that the softmmu tlb entry has been populated, and the
14220 * page table GP bit is available.
14222 * Note that we need to compute this even if btype == 0,
14223 * because this value is used for BR instructions later
14224 * where ENV is not available.
14226 s
->guarded_page
= is_guarded_page(env
, s
);
14228 /* First insn can have btype set to non-zero. */
14229 tcg_debug_assert(s
->btype
>= 0);
14232 * Note that the Branch Target Exception has fairly high
14233 * priority -- below debugging exceptions but above most
14234 * everything else. This allows us to handle this now
14235 * instead of waiting until the insn is otherwise decoded.
14239 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14240 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_btitrap(s
->btype
),
14241 default_exception_el(s
));
14245 /* Not the first insn: btype must be 0. */
14246 tcg_debug_assert(s
->btype
== 0);
14250 switch (extract32(insn
, 25, 4)) {
14251 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14252 unallocated_encoding(s
);
14255 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14256 unallocated_encoding(s
);
14259 case 0x8: case 0x9: /* Data processing - immediate */
14260 disas_data_proc_imm(s
, insn
);
14262 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14263 disas_b_exc_sys(s
, insn
);
14268 case 0xe: /* Loads and stores */
14269 disas_ldst(s
, insn
);
14272 case 0xd: /* Data processing - register */
14273 disas_data_proc_reg(s
, insn
);
14276 case 0xf: /* Data processing - SIMD and floating point */
14277 disas_data_proc_simd_fp(s
, insn
);
14280 assert(FALSE
); /* all 15 cases should be handled above */
14284 /* if we allocated any temporaries, free them here */
14288 * After execution of most insns, btype is reset to 0.
14289 * Note that we set btype == -1 when the insn sets btype.
14291 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14296 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14299 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14300 CPUARMState
*env
= cpu
->env_ptr
;
14301 ARMCPU
*arm_cpu
= env_archcpu(env
);
14302 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14303 int bound
, core_mmu_idx
;
14305 dc
->isar
= &arm_cpu
->isar
;
14306 dc
->pc
= dc
->base
.pc_first
;
14310 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14311 * there is no secure EL1, so we route exceptions to EL3.
14313 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14314 !arm_el_is_aa64(env
, 3);
14317 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14318 dc
->condexec_mask
= 0;
14319 dc
->condexec_cond
= 0;
14320 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14321 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, core_mmu_idx
);
14322 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14323 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14324 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14325 #if !defined(CONFIG_USER_ONLY)
14326 dc
->user
= (dc
->current_el
== 0);
14328 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14329 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14330 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14331 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14332 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14333 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14335 dc
->vec_stride
= 0;
14336 dc
->cp_regs
= arm_cpu
->cp_regs
;
14337 dc
->features
= env
->features
;
14339 /* Single step state. The code-generation logic here is:
14341 * generate code with no special handling for single-stepping (except
14342 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14343 * this happens anyway because those changes are all system register or
14345 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14346 * emit code for one insn
14347 * emit code to clear PSTATE.SS
14348 * emit code to generate software step exception for completed step
14349 * end TB (as usual for having generated an exception)
14350 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14351 * emit code to generate a software step exception
14354 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14355 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14356 dc
->is_ldex
= false;
14357 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
14359 /* Bound the number of insns to execute to those left on the page. */
14360 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14362 /* If architectural single step active, limit to 1. */
14363 if (dc
->ss_active
) {
14366 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14368 init_tmp_a64_array(dc
);
14371 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14375 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14377 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14379 tcg_gen_insn_start(dc
->pc
, 0, 0);
14380 dc
->insn_start
= tcg_last_op();
14383 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14384 const CPUBreakpoint
*bp
)
14386 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14388 if (bp
->flags
& BP_CPU
) {
14389 gen_a64_set_pc_im(dc
->pc
);
14390 gen_helper_check_breakpoints(cpu_env
);
14391 /* End the TB early; it likely won't be executed */
14392 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14394 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
14395 /* The address covered by the breakpoint must be
14396 included in [tb->pc, tb->pc + tb->size) in order
14397 to for it to be properly cleared -- thus we
14398 increment the PC here so that the logic setting
14399 tb->size below does the right thing. */
14401 dc
->base
.is_jmp
= DISAS_NORETURN
;
14407 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14409 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14410 CPUARMState
*env
= cpu
->env_ptr
;
14412 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14413 /* Singlestep state is Active-pending.
14414 * If we're in this state at the start of a TB then either
14415 * a) we just took an exception to an EL which is being debugged
14416 * and this is the first insn in the exception handler
14417 * b) debug exceptions were masked and we just unmasked them
14418 * without changing EL (eg by clearing PSTATE.D)
14419 * In either case we're going to take a swstep exception in the
14420 * "did not step an insn" case, and so the syndrome ISV and EX
14421 * bits should be zero.
14423 assert(dc
->base
.num_insns
== 1);
14424 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
14425 default_exception_el(dc
));
14426 dc
->base
.is_jmp
= DISAS_NORETURN
;
14428 disas_a64_insn(env
, dc
);
14431 dc
->base
.pc_next
= dc
->pc
;
14432 translator_loop_temp_check(&dc
->base
);
14435 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14437 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14439 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14440 /* Note that this means single stepping WFI doesn't halt the CPU.
14441 * For conditional branch insns this is harmless unreachable code as
14442 * gen_goto_tb() has already handled emitting the debug exception
14443 * (and thus a tb-jump is not possible when singlestepping).
14445 switch (dc
->base
.is_jmp
) {
14447 gen_a64_set_pc_im(dc
->pc
);
14451 if (dc
->base
.singlestep_enabled
) {
14452 gen_exception_internal(EXCP_DEBUG
);
14454 gen_step_complete_exception(dc
);
14457 case DISAS_NORETURN
:
14461 switch (dc
->base
.is_jmp
) {
14463 case DISAS_TOO_MANY
:
14464 gen_goto_tb(dc
, 1, dc
->pc
);
14468 gen_a64_set_pc_im(dc
->pc
);
14471 tcg_gen_exit_tb(NULL
, 0);
14474 tcg_gen_lookup_and_goto_ptr();
14476 case DISAS_NORETURN
:
14480 gen_a64_set_pc_im(dc
->pc
);
14481 gen_helper_wfe(cpu_env
);
14484 gen_a64_set_pc_im(dc
->pc
);
14485 gen_helper_yield(cpu_env
);
14489 /* This is a special case because we don't want to just halt the CPU
14490 * if trying to debug across a WFI.
14492 TCGv_i32 tmp
= tcg_const_i32(4);
14494 gen_a64_set_pc_im(dc
->pc
);
14495 gen_helper_wfi(cpu_env
, tmp
);
14496 tcg_temp_free_i32(tmp
);
14497 /* The helper doesn't necessarily throw an exception, but we
14498 * must go back to the main loop to check for interrupts anyway.
14500 tcg_gen_exit_tb(NULL
, 0);
14506 /* Functions above can change dc->pc, so re-align db->pc_next */
14507 dc
->base
.pc_next
= dc
->pc
;
14510 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14513 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14515 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14516 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14519 const TranslatorOps aarch64_translator_ops
= {
14520 .init_disas_context
= aarch64_tr_init_disas_context
,
14521 .tb_start
= aarch64_tr_tb_start
,
14522 .insn_start
= aarch64_tr_insn_start
,
14523 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14524 .translate_insn
= aarch64_tr_translate_insn
,
14525 .tb_stop
= aarch64_tr_tb_stop
,
14526 .disas_log
= aarch64_tr_disas_log
,