target-lm32/helper.c

   1 /*
   2  *  LatticeMico32 helper routines.
   3  *
   4  *  Copyright (c) 2010-2014 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "qemu/host-utils.h"
  23 #include "sysemu/sysemu.h"
  24 #include "exec/semihost.h"
  25
  26 int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  27                               int mmu_idx)
  28 {
  29     LM32CPU *cpu = LM32_CPU(cs);
  30     CPULM32State *env = &cpu->env;
  31     int prot;
  32
  33     address &= TARGET_PAGE_MASK;
  34     prot = PAGE_BITS;
  35     if (env->flags & LM32_FLAG_IGNORE_MSB) {
  36         tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx,
  37                      TARGET_PAGE_SIZE);
  38     } else {
  39         tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
  40     }
  41
  42     return 0;
  43 }
  44
  45 hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
  46 {
  47     LM32CPU *cpu = LM32_CPU(cs);
  48
  49     addr &= TARGET_PAGE_MASK;
  50     if (cpu->env.flags & LM32_FLAG_IGNORE_MSB) {
  51         return addr & 0x7fffffff;
  52     } else {
  53         return addr;
  54     }
  55 }
  56
  57 void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address)
  58 {
  59     LM32CPU *cpu = lm32_env_get_cpu(env);
  60
  61     cpu_breakpoint_insert(CPU(cpu), address, BP_CPU,
  62                           &env->cpu_breakpoint[idx]);
  63 }
  64
  65 void lm32_breakpoint_remove(CPULM32State *env, int idx)
  66 {
  67     LM32CPU *cpu = lm32_env_get_cpu(env);
  68
  69     if (!env->cpu_breakpoint[idx]) {
  70         return;
  71     }
  72
  73     cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[idx]);
  74     env->cpu_breakpoint[idx] = NULL;
  75 }
  76
  77 void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
  78                             lm32_wp_t wp_type)
  79 {
  80     LM32CPU *cpu = lm32_env_get_cpu(env);
  81     int flags = 0;
  82
  83     switch (wp_type) {
  84     case LM32_WP_DISABLED:
  85         /* nothing to do */
  86         break;
  87     case LM32_WP_READ:
  88         flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_READ;
  89         break;
  90     case LM32_WP_WRITE:
  91         flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_WRITE;
  92         break;
  93     case LM32_WP_READ_WRITE:
  94         flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_ACCESS;
  95         break;
  96     }
  97
  98     if (flags != 0) {
  99         cpu_watchpoint_insert(CPU(cpu), address, 1, flags,
 100                 &env->cpu_watchpoint[idx]);
 101     }
 102 }
 103
 104 void lm32_watchpoint_remove(CPULM32State *env, int idx)
 105 {
 106     LM32CPU *cpu = lm32_env_get_cpu(env);
 107
 108     if (!env->cpu_watchpoint[idx]) {
 109         return;
 110     }
 111
 112     cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[idx]);
 113     env->cpu_watchpoint[idx] = NULL;
 114 }
 115
 116 static bool check_watchpoints(CPULM32State *env)
 117 {
 118     LM32CPU *cpu = lm32_env_get_cpu(env);
 119     int i;
 120
 121     for (i = 0; i < cpu->num_watchpoints; i++) {
 122         if (env->cpu_watchpoint[i] &&
 123                 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
 124             return true;
 125         }
 126     }
 127     return false;
 128 }
 129
 130 void lm32_debug_excp_handler(CPUState *cs)
 131 {
 132     LM32CPU *cpu = LM32_CPU(cs);
 133     CPULM32State *env = &cpu->env;
 134     CPUBreakpoint *bp;
 135
 136     if (cs->watchpoint_hit) {
 137         if (cs->watchpoint_hit->flags & BP_CPU) {
 138             cs->watchpoint_hit = NULL;
 139             if (check_watchpoints(env)) {
 140                 raise_exception(env, EXCP_WATCHPOINT);
 141             } else {
 142                 cpu_resume_from_signal(cs, NULL);
 143             }
 144         }
 145     } else {
 146         QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
 147             if (bp->pc == env->pc) {
 148                 if (bp->flags & BP_CPU) {
 149                     raise_exception(env, EXCP_BREAKPOINT);
 150                 }
 151                 break;
 152             }
 153         }
 154     }
 155 }
 156
 157 void lm32_cpu_do_interrupt(CPUState *cs)
 158 {
 159     LM32CPU *cpu = LM32_CPU(cs);
 160     CPULM32State *env = &cpu->env;
 161
 162     qemu_log_mask(CPU_LOG_INT,
 163             "exception at pc=%x type=%x\n", env->pc, cs->exception_index);
 164
 165     switch (cs->exception_index) {
 166     case EXCP_SYSTEMCALL:
 167         if (unlikely(semihosting_enabled())) {
 168             /* do_semicall() returns true if call was handled. Otherwise
 169              * do the normal exception handling. */
 170             if (lm32_cpu_do_semihosting(cs)) {
 171                 env->pc += 4;
 172                 break;
 173             }
 174         }
 175         /* fall through */
 176     case EXCP_INSN_BUS_ERROR:
 177     case EXCP_DATA_BUS_ERROR:
 178     case EXCP_DIVIDE_BY_ZERO:
 179     case EXCP_IRQ:
 180         /* non-debug exceptions */
 181         env->regs[R_EA] = env->pc;
 182         env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
 183         env->ie &= ~IE_IE;
 184         if (env->dc & DC_RE) {
 185             env->pc = env->deba + (cs->exception_index * 32);
 186         } else {
 187             env->pc = env->eba + (cs->exception_index * 32);
 188         }
 189         log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 190         break;
 191     case EXCP_BREAKPOINT:
 192     case EXCP_WATCHPOINT:
 193         /* debug exceptions */
 194         env->regs[R_BA] = env->pc;
 195         env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
 196         env->ie &= ~IE_IE;
 197         env->pc = env->deba + (cs->exception_index * 32);
 198         log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 199         break;
 200     default:
 201         cpu_abort(cs, "unhandled exception type=%d\n",
 202                   cs->exception_index);
 203         break;
 204     }
 205 }
 206
 207 bool lm32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 208 {
 209     LM32CPU *cpu = LM32_CPU(cs);
 210     CPULM32State *env = &cpu->env;
 211
 212     if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->ie & IE_IE)) {
 213         cs->exception_index = EXCP_IRQ;
 214         lm32_cpu_do_interrupt(cs);
 215         return true;
 216     }
 217     return false;
 218 }
 219
 220 LM32CPU *cpu_lm32_init(const char *cpu_model)
 221 {
 222     return LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));
 223 }
 224
 225 /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
 226  * area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
 227  * 0x80000000-0xffffffff is not cached and used to access IO devices. */
 228 void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
 229 {
 230     if (value) {
 231         env->flags |= LM32_FLAG_IGNORE_MSB;
 232     } else {
 233         env->flags &= ~LM32_FLAG_IGNORE_MSB;
 234     }
 235 }