hw/intc/arm_gicv2m.c

   1 /*
   2  *  GICv2m extension for MSI/MSI-x support with a GICv2-based system
   3  *
   4  * Copyright (C) 2015 Linaro, All rights reserved.
   5  *
   6  * Author: Christoffer Dall <christoffer.dall@linaro.org>
   7  *
   8  * This library is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU Lesser General Public
  10  * License as published by the Free Software Foundation; either
  11  * version 2 of the License, or (at your option) any later version.
  12  *
  13  * This library is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * Lesser General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 /* This file implements an emulated GICv2m widget as described in the ARM
  23  * Server Base System Architecture (SBSA) specification Version 2.2
  24  * (ARM-DEN-0029 v2.2) pages 35-39 without any optional implementation defined
  25  * identification registers and with a single non-secure MSI register frame.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "hw/sysbus.h"
  31 #include "hw/pci/msi.h"
  32 #include "sysemu/kvm.h"
  33 #include "qemu/log.h"
  34
  35 #define TYPE_ARM_GICV2M "arm-gicv2m"
  36 #define ARM_GICV2M(obj) OBJECT_CHECK(ARMGICv2mState, (obj), TYPE_ARM_GICV2M)
  37
  38 #define GICV2M_NUM_SPI_MAX 128
  39
  40 #define V2M_MSI_TYPER           0x008
  41 #define V2M_MSI_SETSPI_NS       0x040
  42 #define V2M_MSI_IIDR            0xFCC
  43 #define V2M_IIDR0               0xFD0
  44 #define V2M_IIDR11              0xFFC
  45
  46 #define PRODUCT_ID_QEMU         0x51 /* ASCII code Q */
  47
  48 typedef struct ARMGICv2mState {
  49     SysBusDevice parent_obj;
  50
  51     MemoryRegion iomem;
  52     qemu_irq spi[GICV2M_NUM_SPI_MAX];
  53
  54     uint32_t base_spi;
  55     uint32_t num_spi;
  56 } ARMGICv2mState;
  57
  58 static void gicv2m_set_irq(void *opaque, int irq)
  59 {
  60     ARMGICv2mState *s = (ARMGICv2mState *)opaque;
  61
  62     qemu_irq_pulse(s->spi[irq]);
  63 }
  64
  65 static uint64_t gicv2m_read(void *opaque, hwaddr offset,
  66                             unsigned size)
  67 {
  68     ARMGICv2mState *s = (ARMGICv2mState *)opaque;
  69     uint32_t val;
  70
  71     if (size != 4) {
  72         qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_read: bad size %u\n", size);
  73         return 0;
  74     }
  75
  76     switch (offset) {
  77     case V2M_MSI_TYPER:
  78         val = (s->base_spi + 32) << 16;
  79         val |= s->num_spi;
  80         return val;
  81     case V2M_MSI_IIDR:
  82         /* We don't have any valid implementor so we leave that field as zero
  83          * and we return 0 in the arch revision as per the spec.
  84          */
  85         return (PRODUCT_ID_QEMU << 20);
  86     case V2M_IIDR0 ... V2M_IIDR11:
  87         /* We do not implement any optional identification registers and the
  88          * mandatory MSI_PIDR2 register reads as 0x0, so we capture all
  89          * implementation defined registers here.
  90          */
  91         return 0;
  92     default:
  93         qemu_log_mask(LOG_GUEST_ERROR,
  94                       "gicv2m_read: Bad offset %x\n", (int)offset);
  95         return 0;
  96     }
  97 }
  98
  99 static void gicv2m_write(void *opaque, hwaddr offset,
 100                         uint64_t value, unsigned size)
 101 {
 102     ARMGICv2mState *s = (ARMGICv2mState *)opaque;
 103
 104     if (size != 2 && size != 4) {
 105         qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_write: bad size %u\n", size);
 106         return;
 107     }
 108
 109     switch (offset) {
 110     case V2M_MSI_SETSPI_NS: {
 111         int spi;
 112
 113         spi = (value & 0x3ff) - (s->base_spi + 32);
 114         if (spi >= 0 && spi < s->num_spi) {
 115             gicv2m_set_irq(s, spi);
 116         }
 117         return;
 118     }
 119     default:
 120         qemu_log_mask(LOG_GUEST_ERROR,
 121                       "gicv2m_write: Bad offset %x\n", (int)offset);
 122     }
 123 }
 124
 125 static const MemoryRegionOps gicv2m_ops = {
 126     .read = gicv2m_read,
 127     .write = gicv2m_write,
 128     .endianness = DEVICE_LITTLE_ENDIAN,
 129 };
 130
 131 static void gicv2m_realize(DeviceState *dev, Error **errp)
 132 {
 133     ARMGICv2mState *s = ARM_GICV2M(dev);
 134     int i;
 135
 136     if (s->num_spi > GICV2M_NUM_SPI_MAX) {
 137         error_setg(errp,
 138                    "requested %u SPIs exceeds GICv2m frame maximum %d",
 139                    s->num_spi, GICV2M_NUM_SPI_MAX);
 140         return;
 141     }
 142
 143     if (s->base_spi + 32 > 1020 - s->num_spi) {
 144         error_setg(errp,
 145                    "requested base SPI %u+%u exceeds max. number 1020",
 146                    s->base_spi + 32, s->num_spi);
 147         return;
 148     }
 149
 150     for (i = 0; i < s->num_spi; i++) {
 151         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->spi[i]);
 152     }
 153
 154     msi_nonbroken = true;
 155     kvm_gsi_direct_mapping = true;
 156     kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();
 157 }
 158
 159 static void gicv2m_init(Object *obj)
 160 {
 161     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 162     ARMGICv2mState *s = ARM_GICV2M(obj);
 163
 164     memory_region_init_io(&s->iomem, OBJECT(s), &gicv2m_ops, s,
 165                           "gicv2m", 0x1000);
 166     sysbus_init_mmio(sbd, &s->iomem);
 167 }
 168
 169 static Property gicv2m_properties[] = {
 170     DEFINE_PROP_UINT32("base-spi", ARMGICv2mState, base_spi, 0),
 171     DEFINE_PROP_UINT32("num-spi", ARMGICv2mState, num_spi, 64),
 172     DEFINE_PROP_END_OF_LIST(),
 173 };
 174
 175 static void gicv2m_class_init(ObjectClass *klass, void *data)
 176 {
 177     DeviceClass *dc = DEVICE_CLASS(klass);
 178
 179     dc->props = gicv2m_properties;
 180     dc->realize = gicv2m_realize;
 181 }
 182
 183 static const TypeInfo gicv2m_info = {
 184     .name          = TYPE_ARM_GICV2M,
 185     .parent        = TYPE_SYS_BUS_DEVICE,
 186     .instance_size = sizeof(ARMGICv2mState),
 187     .instance_init = gicv2m_init,
 188     .class_init    = gicv2m_class_init,
 189 };
 190
 191 static void gicv2m_register_types(void)
 192 {
 193     type_register_static(&gicv2m_info);
 194 }
 195
 196 type_init(gicv2m_register_types)