target-arm/op_helper.c

   1 /*
   2  *  ARM helper routines
   3  *
   4  *  Copyright (c) 2005-2007 CodeSourcery, LLC
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "internals.h"
  23 #include "exec/cpu_ldst.h"
  24
  25 #define SIGNBIT (uint32_t)0x80000000
  26 #define SIGNBIT64 ((uint64_t)1 << 63)
  27
  28 static void raise_exception(CPUARMState *env, uint32_t excp,
  29                             uint32_t syndrome, uint32_t target_el)
  30 {
  31     CPUState *cs = CPU(arm_env_get_cpu(env));
  32
  33     assert(!excp_is_internal(excp));
  34     cs->exception_index = excp;
  35     env->exception.syndrome = syndrome;
  36     env->exception.target_el = target_el;
  37     cpu_loop_exit(cs);
  38 }
  39
  40 static int exception_target_el(CPUARMState *env)
  41 {
  42     int target_el = MAX(1, arm_current_el(env));
  43
  44     /* No such thing as secure EL1 if EL3 is aarch32, so update the target EL
  45      * to EL3 in this case.
  46      */
  47     if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {
  48         target_el = 3;
  49     }
  50
  51     return target_el;
  52 }
  53
  54 uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
  55                           uint32_t rn, uint32_t maxindex)
  56 {
  57     uint32_t val;
  58     uint32_t tmp;
  59     int index;
  60     int shift;
  61     uint64_t *table;
  62     table = (uint64_t *)&env->vfp.regs[rn];
  63     val = 0;
  64     for (shift = 0; shift < 32; shift += 8) {
  65         index = (ireg >> shift) & 0xff;
  66         if (index < maxindex) {
  67             tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
  68             val |= tmp << shift;
  69         } else {
  70             val |= def & (0xff << shift);
  71         }
  72     }
  73     return val;
  74 }
  75
  76 #if !defined(CONFIG_USER_ONLY)
  77
  78 /* try to fill the TLB and return an exception if error. If retaddr is
  79  * NULL, it means that the function was called in C code (i.e. not
  80  * from generated code or from helper.c)
  81  */
  82 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
  83               uintptr_t retaddr)
  84 {
  85     bool ret;
  86     uint32_t fsr = 0;
  87     ARMMMUFaultInfo fi = {};
  88
  89     ret = arm_tlb_fill(cs, addr, is_write, mmu_idx, &fsr, &fi);
  90     if (unlikely(ret)) {
  91         ARMCPU *cpu = ARM_CPU(cs);
  92         CPUARMState *env = &cpu->env;
  93         uint32_t syn, exc;
  94         unsigned int target_el;
  95         bool same_el;
  96
  97         if (retaddr) {
  98             /* now we have a real cpu fault */
  99             cpu_restore_state(cs, retaddr);
 100         }
 101
 102         target_el = exception_target_el(env);
 103         if (fi.stage2) {
 104             target_el = 2;
 105             env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
 106         }
 107         same_el = arm_current_el(env) == target_el;
 108         /* AArch64 syndrome does not have an LPAE bit */
 109         syn = fsr & ~(1 << 9);
 110
 111         /* For insn and data aborts we assume there is no instruction syndrome
 112          * information; this is always true for exceptions reported to EL1.
 113          */
 114         if (is_write == 2) {
 115             syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn);
 116             exc = EXCP_PREFETCH_ABORT;
 117         } else {
 118             syn = syn_data_abort(same_el, 0, 0, fi.s1ptw, is_write == 1, syn);
 119             if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) {
 120                 fsr |= (1 << 11);
 121             }
 122             exc = EXCP_DATA_ABORT;
 123         }
 124
 125         env->exception.vaddress = addr;
 126         env->exception.fsr = fsr;
 127         raise_exception(env, exc, syn, target_el);
 128     }
 129 }
 130
 131 /* Raise a data fault alignment exception for the specified virtual address */
 132 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write,
 133                                  int is_user, uintptr_t retaddr)
 134 {
 135     ARMCPU *cpu = ARM_CPU(cs);
 136     CPUARMState *env = &cpu->env;
 137     int target_el;
 138     bool same_el;
 139
 140     if (retaddr) {
 141         /* now we have a real cpu fault */
 142         cpu_restore_state(cs, retaddr);
 143     }
 144
 145     target_el = exception_target_el(env);
 146     same_el = (arm_current_el(env) == target_el);
 147
 148     env->exception.vaddress = vaddr;
 149
 150     /* the DFSR for an alignment fault depends on whether we're using
 151      * the LPAE long descriptor format, or the short descriptor format
 152      */
 153     if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) {
 154         env->exception.fsr = 0x21;
 155     } else {
 156         env->exception.fsr = 0x1;
 157     }
 158
 159     if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) {
 160         env->exception.fsr |= (1 << 11);
 161     }
 162
 163     raise_exception(env, EXCP_DATA_ABORT,
 164                     syn_data_abort(same_el, 0, 0, 0, is_write == 1, 0x21),
 165                     target_el);
 166 }
 167
 168 #endif /* !defined(CONFIG_USER_ONLY) */
 169
 170 uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
 171 {
 172     uint32_t res = a + b;
 173     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
 174         env->QF = 1;
 175     return res;
 176 }
 177
 178 uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
 179 {
 180     uint32_t res = a + b;
 181     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
 182         env->QF = 1;
 183         res = ~(((int32_t)a >> 31) ^ SIGNBIT);
 184     }
 185     return res;
 186 }
 187
 188 uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
 189 {
 190     uint32_t res = a - b;
 191     if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
 192         env->QF = 1;
 193         res = ~(((int32_t)a >> 31) ^ SIGNBIT);
 194     }
 195     return res;
 196 }
 197
 198 uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
 199 {
 200     uint32_t res;
 201     if (val >= 0x40000000) {
 202         res = ~SIGNBIT;
 203         env->QF = 1;
 204     } else if (val <= (int32_t)0xc0000000) {
 205         res = SIGNBIT;
 206         env->QF = 1;
 207     } else {
 208         res = val << 1;
 209     }
 210     return res;
 211 }
 212
 213 uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 214 {
 215     uint32_t res = a + b;
 216     if (res < a) {
 217         env->QF = 1;
 218         res = ~0;
 219     }
 220     return res;
 221 }
 222
 223 uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 224 {
 225     uint32_t res = a - b;
 226     if (res > a) {
 227         env->QF = 1;
 228         res = 0;
 229     }
 230     return res;
 231 }
 232
 233 /* Signed saturation.  */
 234 static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
 235 {
 236     int32_t top;
 237     uint32_t mask;
 238
 239     top = val >> shift;
 240     mask = (1u << shift) - 1;
 241     if (top > 0) {
 242         env->QF = 1;
 243         return mask;
 244     } else if (top < -1) {
 245         env->QF = 1;
 246         return ~mask;
 247     }
 248     return val;
 249 }
 250
 251 /* Unsigned saturation.  */
 252 static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
 253 {
 254     uint32_t max;
 255
 256     max = (1u << shift) - 1;
 257     if (val < 0) {
 258         env->QF = 1;
 259         return 0;
 260     } else if (val > max) {
 261         env->QF = 1;
 262         return max;
 263     }
 264     return val;
 265 }
 266
 267 /* Signed saturate.  */
 268 uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
 269 {
 270     return do_ssat(env, x, shift);
 271 }
 272
 273 /* Dual halfword signed saturate.  */
 274 uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 275 {
 276     uint32_t res;
 277
 278     res = (uint16_t)do_ssat(env, (int16_t)x, shift);
 279     res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
 280     return res;
 281 }
 282
 283 /* Unsigned saturate.  */
 284 uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
 285 {
 286     return do_usat(env, x, shift);
 287 }
 288
 289 /* Dual halfword unsigned saturate.  */
 290 uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 291 {
 292     uint32_t res;
 293
 294     res = (uint16_t)do_usat(env, (int16_t)x, shift);
 295     res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
 296     return res;
 297 }
 298
 299 /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
 300  * The function returns the target EL (1-3) if the instruction is to be trapped;
 301  * otherwise it returns 0 indicating it is not trapped.
 302  */
 303 static inline int check_wfx_trap(CPUARMState *env, bool is_wfe)
 304 {
 305     int cur_el = arm_current_el(env);
 306     uint64_t mask;
 307
 308     /* If we are currently in EL0 then we need to check if SCTLR is set up for
 309      * WFx instructions being trapped to EL1. These trap bits don't exist in v7.
 310      */
 311     if (cur_el < 1 && arm_feature(env, ARM_FEATURE_V8)) {
 312         int target_el;
 313
 314         mask = is_wfe ? SCTLR_nTWE : SCTLR_nTWI;
 315         if (arm_is_secure_below_el3(env) && !arm_el_is_aa64(env, 3)) {
 316             /* Secure EL0 and Secure PL1 is at EL3 */
 317             target_el = 3;
 318         } else {
 319             target_el = 1;
 320         }
 321
 322         if (!(env->cp15.sctlr_el[target_el] & mask)) {
 323             return target_el;
 324         }
 325     }
 326
 327     /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
 328      * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
 329      * bits will be zero indicating no trap.
 330      */
 331     if (cur_el < 2 && !arm_is_secure(env)) {
 332         mask = (is_wfe) ? HCR_TWE : HCR_TWI;
 333         if (env->cp15.hcr_el2 & mask) {
 334             return 2;
 335         }
 336     }
 337
 338     /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
 339     if (cur_el < 3) {
 340         mask = (is_wfe) ? SCR_TWE : SCR_TWI;
 341         if (env->cp15.scr_el3 & mask) {
 342             return 3;
 343         }
 344     }
 345
 346     return 0;
 347 }
 348
 349 void HELPER(wfi)(CPUARMState *env)
 350 {
 351     CPUState *cs = CPU(arm_env_get_cpu(env));
 352     int target_el = check_wfx_trap(env, false);
 353
 354     if (cpu_has_work(cs)) {
 355         /* Don't bother to go into our "low power state" if
 356          * we would just wake up immediately.
 357          */
 358         return;
 359     }
 360
 361     if (target_el) {
 362         env->pc -= 4;
 363         raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0), target_el);
 364     }
 365
 366     cs->exception_index = EXCP_HLT;
 367     cs->halted = 1;
 368     cpu_loop_exit(cs);
 369 }
 370
 371 void HELPER(wfe)(CPUARMState *env)
 372 {
 373     /* This is a hint instruction that is semantically different
 374      * from YIELD even though we currently implement it identically.
 375      * Don't actually halt the CPU, just yield back to top
 376      * level loop. This is not going into a "low power state"
 377      * (ie halting until some event occurs), so we never take
 378      * a configurable trap to a different exception level.
 379      */
 380     HELPER(yield)(env);
 381 }
 382
 383 void HELPER(yield)(CPUARMState *env)
 384 {
 385     ARMCPU *cpu = arm_env_get_cpu(env);
 386     CPUState *cs = CPU(cpu);
 387
 388     /* This is a non-trappable hint instruction that generally indicates
 389      * that the guest is currently busy-looping. Yield control back to the
 390      * top level loop so that a more deserving VCPU has a chance to run.
 391      */
 392     cs->exception_index = EXCP_YIELD;
 393     cpu_loop_exit(cs);
 394 }
 395
 396 /* Raise an internal-to-QEMU exception. This is limited to only
 397  * those EXCP values which are special cases for QEMU to interrupt
 398  * execution and not to be used for exceptions which are passed to
 399  * the guest (those must all have syndrome information and thus should
 400  * use exception_with_syndrome).
 401  */
 402 void HELPER(exception_internal)(CPUARMState *env, uint32_t excp)
 403 {
 404     CPUState *cs = CPU(arm_env_get_cpu(env));
 405
 406     assert(excp_is_internal(excp));
 407     cs->exception_index = excp;
 408     cpu_loop_exit(cs);
 409 }
 410
 411 /* Raise an exception with the specified syndrome register value */
 412 void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
 413                                      uint32_t syndrome, uint32_t target_el)
 414 {
 415     raise_exception(env, excp, syndrome, target_el);
 416 }
 417
 418 uint32_t HELPER(cpsr_read)(CPUARMState *env)
 419 {
 420     return cpsr_read(env) & ~(CPSR_EXEC | CPSR_RESERVED);
 421 }
 422
 423 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
 424 {
 425     cpsr_write(env, val, mask, CPSRWriteByInstr);
 426 }
 427
 428 /* Write the CPSR for a 32-bit exception return */
 429 void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val)
 430 {
 431     cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn);
 432 }
 433
 434 /* Access to user mode registers from privileged modes.  */
 435 uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
 436 {
 437     uint32_t val;
 438
 439     if (regno == 13) {
 440         val = env->banked_r13[BANK_USRSYS];
 441     } else if (regno == 14) {
 442         val = env->banked_r14[BANK_USRSYS];
 443     } else if (regno >= 8
 444                && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
 445         val = env->usr_regs[regno - 8];
 446     } else {
 447         val = env->regs[regno];
 448     }
 449     return val;
 450 }
 451
 452 void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
 453 {
 454     if (regno == 13) {
 455         env->banked_r13[BANK_USRSYS] = val;
 456     } else if (regno == 14) {
 457         env->banked_r14[BANK_USRSYS] = val;
 458     } else if (regno >= 8
 459                && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
 460         env->usr_regs[regno - 8] = val;
 461     } else {
 462         env->regs[regno] = val;
 463     }
 464 }
 465
 466 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
 467 {
 468     if ((env->uncached_cpsr & CPSR_M) == mode) {
 469         env->regs[13] = val;
 470     } else {
 471         env->banked_r13[bank_number(mode)] = val;
 472     }
 473 }
 474
 475 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
 476 {
 477     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) {
 478         /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
 479          * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
 480          */
 481         raise_exception(env, EXCP_UDEF, syn_uncategorized(),
 482                         exception_target_el(env));
 483     }
 484
 485     if ((env->uncached_cpsr & CPSR_M) == mode) {
 486         return env->regs[13];
 487     } else {
 488         return env->banked_r13[bank_number(mode)];
 489     }
 490 }
 491
 492 void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
 493                                  uint32_t isread)
 494 {
 495     const ARMCPRegInfo *ri = rip;
 496     int target_el;
 497
 498     if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
 499         && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
 500         raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
 501     }
 502
 503     if (!ri->accessfn) {
 504         return;
 505     }
 506
 507     switch (ri->accessfn(env, ri, isread)) {
 508     case CP_ACCESS_OK:
 509         return;
 510     case CP_ACCESS_TRAP:
 511         target_el = exception_target_el(env);
 512         break;
 513     case CP_ACCESS_TRAP_EL2:
 514         /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
 515          * a bug in the access function.
 516          */
 517         assert(!arm_is_secure(env) && arm_current_el(env) != 3);
 518         target_el = 2;
 519         break;
 520     case CP_ACCESS_TRAP_EL3:
 521         target_el = 3;
 522         break;
 523     case CP_ACCESS_TRAP_UNCATEGORIZED:
 524         target_el = exception_target_el(env);
 525         syndrome = syn_uncategorized();
 526         break;
 527     case CP_ACCESS_TRAP_UNCATEGORIZED_EL2:
 528         target_el = 2;
 529         syndrome = syn_uncategorized();
 530         break;
 531     case CP_ACCESS_TRAP_UNCATEGORIZED_EL3:
 532         target_el = 3;
 533         syndrome = syn_uncategorized();
 534         break;
 535     case CP_ACCESS_TRAP_FP_EL2:
 536         target_el = 2;
 537         /* Since we are an implementation that takes exceptions on a trapped
 538          * conditional insn only if the insn has passed its condition code
 539          * check, we take the IMPDEF choice to always report CV=1 COND=0xe
 540          * (which is also the required value for AArch64 traps).
 541          */
 542         syndrome = syn_fp_access_trap(1, 0xe, false);
 543         break;
 544     case CP_ACCESS_TRAP_FP_EL3:
 545         target_el = 3;
 546         syndrome = syn_fp_access_trap(1, 0xe, false);
 547         break;
 548     default:
 549         g_assert_not_reached();
 550     }
 551
 552     raise_exception(env, EXCP_UDEF, syndrome, target_el);
 553 }
 554
 555 void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
 556 {
 557     const ARMCPRegInfo *ri = rip;
 558
 559     ri->writefn(env, ri, value);
 560 }
 561
 562 uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
 563 {
 564     const ARMCPRegInfo *ri = rip;
 565
 566     return ri->readfn(env, ri);
 567 }
 568
 569 void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
 570 {
 571     const ARMCPRegInfo *ri = rip;
 572
 573     ri->writefn(env, ri, value);
 574 }
 575
 576 uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
 577 {
 578     const ARMCPRegInfo *ri = rip;
 579
 580     return ri->readfn(env, ri);
 581 }
 582
 583 void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)
 584 {
 585     /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
 586      * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
 587      * to catch that case at translate time.
 588      */
 589     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
 590         uint32_t syndrome = syn_aa64_sysregtrap(0, extract32(op, 0, 3),
 591                                                 extract32(op, 3, 3), 4,
 592                                                 imm, 0x1f, 0);
 593         raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
 594     }
 595
 596     switch (op) {
 597     case 0x05: /* SPSel */
 598         update_spsel(env, imm);
 599         break;
 600     case 0x1e: /* DAIFSet */
 601         env->daif |= (imm << 6) & PSTATE_DAIF;
 602         break;
 603     case 0x1f: /* DAIFClear */
 604         env->daif &= ~((imm << 6) & PSTATE_DAIF);
 605         break;
 606     default:
 607         g_assert_not_reached();
 608     }
 609 }
 610
 611 void HELPER(clear_pstate_ss)(CPUARMState *env)
 612 {
 613     env->pstate &= ~PSTATE_SS;
 614 }
 615
 616 void HELPER(pre_hvc)(CPUARMState *env)
 617 {
 618     ARMCPU *cpu = arm_env_get_cpu(env);
 619     int cur_el = arm_current_el(env);
 620     /* FIXME: Use actual secure state.  */
 621     bool secure = false;
 622     bool undef;
 623
 624     if (arm_is_psci_call(cpu, EXCP_HVC)) {
 625         /* If PSCI is enabled and this looks like a valid PSCI call then
 626          * that overrides the architecturally mandated HVC behaviour.
 627          */
 628         return;
 629     }
 630
 631     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 632         /* If EL2 doesn't exist, HVC always UNDEFs */
 633         undef = true;
 634     } else if (arm_feature(env, ARM_FEATURE_EL3)) {
 635         /* EL3.HCE has priority over EL2.HCD. */
 636         undef = !(env->cp15.scr_el3 & SCR_HCE);
 637     } else {
 638         undef = env->cp15.hcr_el2 & HCR_HCD;
 639     }
 640
 641     /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
 642      * For ARMv8/AArch64, HVC is allowed in EL3.
 643      * Note that we've already trapped HVC from EL0 at translation
 644      * time.
 645      */
 646     if (secure && (!is_a64(env) || cur_el == 1)) {
 647         undef = true;
 648     }
 649
 650     if (undef) {
 651         raise_exception(env, EXCP_UDEF, syn_uncategorized(),
 652                         exception_target_el(env));
 653     }
 654 }
 655
 656 void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
 657 {
 658     ARMCPU *cpu = arm_env_get_cpu(env);
 659     int cur_el = arm_current_el(env);
 660     bool secure = arm_is_secure(env);
 661     bool smd = env->cp15.scr_el3 & SCR_SMD;
 662     /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
 663      * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
 664      *  extensions, SMD only applies to NS state.
 665      * On ARMv7 without the Virtualization extensions, the SMD bit
 666      * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
 667      * so we need not special case this here.
 668      */
 669     bool undef = arm_feature(env, ARM_FEATURE_AARCH64) ? smd : smd && !secure;
 670
 671     if (arm_is_psci_call(cpu, EXCP_SMC)) {
 672         /* If PSCI is enabled and this looks like a valid PSCI call then
 673          * that overrides the architecturally mandated SMC behaviour.
 674          */
 675         return;
 676     }
 677
 678     if (!arm_feature(env, ARM_FEATURE_EL3)) {
 679         /* If we have no EL3 then SMC always UNDEFs */
 680         undef = true;
 681     } else if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
 682         /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. */
 683         raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
 684     }
 685
 686     if (undef) {
 687         raise_exception(env, EXCP_UDEF, syn_uncategorized(),
 688                         exception_target_el(env));
 689     }
 690 }
 691
 692 static int el_from_spsr(uint32_t spsr)
 693 {
 694     /* Return the exception level that this SPSR is requesting a return to,
 695      * or -1 if it is invalid (an illegal return)
 696      */
 697     if (spsr & PSTATE_nRW) {
 698         switch (spsr & CPSR_M) {
 699         case ARM_CPU_MODE_USR:
 700             return 0;
 701         case ARM_CPU_MODE_HYP:
 702             return 2;
 703         case ARM_CPU_MODE_FIQ:
 704         case ARM_CPU_MODE_IRQ:
 705         case ARM_CPU_MODE_SVC:
 706         case ARM_CPU_MODE_ABT:
 707         case ARM_CPU_MODE_UND:
 708         case ARM_CPU_MODE_SYS:
 709             return 1;
 710         case ARM_CPU_MODE_MON:
 711             /* Returning to Mon from AArch64 is never possible,
 712              * so this is an illegal return.
 713              */
 714         default:
 715             return -1;
 716         }
 717     } else {
 718         if (extract32(spsr, 1, 1)) {
 719             /* Return with reserved M[1] bit set */
 720             return -1;
 721         }
 722         if (extract32(spsr, 0, 4) == 1) {
 723             /* return to EL0 with M[0] bit set */
 724             return -1;
 725         }
 726         return extract32(spsr, 2, 2);
 727     }
 728 }
 729
 730 void HELPER(exception_return)(CPUARMState *env)
 731 {
 732     int cur_el = arm_current_el(env);
 733     unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
 734     uint32_t spsr = env->banked_spsr[spsr_idx];
 735     int new_el;
 736     bool return_to_aa64 = (spsr & PSTATE_nRW) == 0;
 737
 738     aarch64_save_sp(env, cur_el);
 739
 740     env->exclusive_addr = -1;
 741
 742     /* We must squash the PSTATE.SS bit to zero unless both of the
 743      * following hold:
 744      *  1. debug exceptions are currently disabled
 745      *  2. singlestep will be active in the EL we return to
 746      * We check 1 here and 2 after we've done the pstate/cpsr write() to
 747      * transition to the EL we're going to.
 748      */
 749     if (arm_generate_debug_exceptions(env)) {
 750         spsr &= ~PSTATE_SS;
 751     }
 752
 753     new_el = el_from_spsr(spsr);
 754     if (new_el == -1) {
 755         goto illegal_return;
 756     }
 757     if (new_el > cur_el
 758         || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) {
 759         /* Disallow return to an EL which is unimplemented or higher
 760          * than the current one.
 761          */
 762         goto illegal_return;
 763     }
 764
 765     if (new_el != 0 && arm_el_is_aa64(env, new_el) != return_to_aa64) {
 766         /* Return to an EL which is configured for a different register width */
 767         goto illegal_return;
 768     }
 769
 770     if (new_el == 2 && arm_is_secure_below_el3(env)) {
 771         /* Return to the non-existent secure-EL2 */
 772         goto illegal_return;
 773     }
 774
 775     if (new_el == 1 && (env->cp15.hcr_el2 & HCR_TGE)
 776         && !arm_is_secure_below_el3(env)) {
 777         goto illegal_return;
 778     }
 779
 780     if (!return_to_aa64) {
 781         env->aarch64 = 0;
 782         /* We do a raw CPSR write because aarch64_sync_64_to_32()
 783          * will sort the register banks out for us, and we've already
 784          * caught all the bad-mode cases in el_from_spsr().
 785          */
 786         cpsr_write(env, spsr, ~0, CPSRWriteRaw);
 787         if (!arm_singlestep_active(env)) {
 788             env->uncached_cpsr &= ~PSTATE_SS;
 789         }
 790         aarch64_sync_64_to_32(env);
 791
 792         if (spsr & CPSR_T) {
 793             env->regs[15] = env->elr_el[cur_el] & ~0x1;
 794         } else {
 795             env->regs[15] = env->elr_el[cur_el] & ~0x3;
 796         }
 797     } else {
 798         env->aarch64 = 1;
 799         pstate_write(env, spsr);
 800         if (!arm_singlestep_active(env)) {
 801             env->pstate &= ~PSTATE_SS;
 802         }
 803         aarch64_restore_sp(env, new_el);
 804         env->pc = env->elr_el[cur_el];
 805     }
 806
 807     return;
 808
 809 illegal_return:
 810     /* Illegal return events of various kinds have architecturally
 811      * mandated behaviour:
 812      * restore NZCV and DAIF from SPSR_ELx
 813      * set PSTATE.IL
 814      * restore PC from ELR_ELx
 815      * no change to exception level, execution state or stack pointer
 816      */
 817     env->pstate |= PSTATE_IL;
 818     env->pc = env->elr_el[cur_el];
 819     spsr &= PSTATE_NZCV | PSTATE_DAIF;
 820     spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);
 821     pstate_write(env, spsr);
 822     if (!arm_singlestep_active(env)) {
 823         env->pstate &= ~PSTATE_SS;
 824     }
 825 }
 826
 827 /* Return true if the linked breakpoint entry lbn passes its checks */
 828 static bool linked_bp_matches(ARMCPU *cpu, int lbn)
 829 {
 830     CPUARMState *env = &cpu->env;
 831     uint64_t bcr = env->cp15.dbgbcr[lbn];
 832     int brps = extract32(cpu->dbgdidr, 24, 4);
 833     int ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
 834     int bt;
 835     uint32_t contextidr;
 836
 837     /* Links to unimplemented or non-context aware breakpoints are
 838      * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
 839      * as if linked to an UNKNOWN context-aware breakpoint (in which
 840      * case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
 841      * We choose the former.
 842      */
 843     if (lbn > brps || lbn < (brps - ctx_cmps)) {
 844         return false;
 845     }
 846
 847     bcr = env->cp15.dbgbcr[lbn];
 848
 849     if (extract64(bcr, 0, 1) == 0) {
 850         /* Linked breakpoint disabled : generate no events */
 851         return false;
 852     }
 853
 854     bt = extract64(bcr, 20, 4);
 855
 856     /* We match the whole register even if this is AArch32 using the
 857      * short descriptor format (in which case it holds both PROCID and ASID),
 858      * since we don't implement the optional v7 context ID masking.
 859      */
 860     contextidr = extract64(env->cp15.contextidr_el[1], 0, 32);
 861
 862     switch (bt) {
 863     case 3: /* linked context ID match */
 864         if (arm_current_el(env) > 1) {
 865             /* Context matches never fire in EL2 or (AArch64) EL3 */
 866             return false;
 867         }
 868         return (contextidr == extract64(env->cp15.dbgbvr[lbn], 0, 32));
 869     case 5: /* linked address mismatch (reserved in AArch64) */
 870     case 9: /* linked VMID match (reserved if no EL2) */
 871     case 11: /* linked context ID and VMID match (reserved if no EL2) */
 872     default:
 873         /* Links to Unlinked context breakpoints must generate no
 874          * events; we choose to do the same for reserved values too.
 875          */
 876         return false;
 877     }
 878
 879     return false;
 880 }
 881
 882 static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
 883 {
 884     CPUARMState *env = &cpu->env;
 885     uint64_t cr;
 886     int pac, hmc, ssc, wt, lbn;
 887     /* Note that for watchpoints the check is against the CPU security
 888      * state, not the S/NS attribute on the offending data access.
 889      */
 890     bool is_secure = arm_is_secure(env);
 891     int access_el = arm_current_el(env);
 892
 893     if (is_wp) {
 894         CPUWatchpoint *wp = env->cpu_watchpoint[n];
 895
 896         if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) {
 897             return false;
 898         }
 899         cr = env->cp15.dbgwcr[n];
 900         if (wp->hitattrs.user) {
 901             /* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
 902              * match watchpoints as if they were accesses done at EL0, even if
 903              * the CPU is at EL1 or higher.
 904              */
 905             access_el = 0;
 906         }
 907     } else {
 908         uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
 909
 910         if (!env->cpu_breakpoint[n] || env->cpu_breakpoint[n]->pc != pc) {
 911             return false;
 912         }
 913         cr = env->cp15.dbgbcr[n];
 914     }
 915     /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
 916      * enabled and that the address and access type match; for breakpoints
 917      * we know the address matched; check the remaining fields, including
 918      * linked breakpoints. We rely on WCR and BCR having the same layout
 919      * for the LBN, SSC, HMC, PAC/PMC and is-linked fields.
 920      * Note that some combinations of {PAC, HMC, SSC} are reserved and
 921      * must act either like some valid combination or as if the watchpoint
 922      * were disabled. We choose the former, and use this together with
 923      * the fact that EL3 must always be Secure and EL2 must always be
 924      * Non-Secure to simplify the code slightly compared to the full
 925      * table in the ARM ARM.
 926      */
 927     pac = extract64(cr, 1, 2);
 928     hmc = extract64(cr, 13, 1);
 929     ssc = extract64(cr, 14, 2);
 930
 931     switch (ssc) {
 932     case 0:
 933         break;
 934     case 1:
 935     case 3:
 936         if (is_secure) {
 937             return false;
 938         }
 939         break;
 940     case 2:
 941         if (!is_secure) {
 942             return false;
 943         }
 944         break;
 945     }
 946
 947     switch (access_el) {
 948     case 3:
 949     case 2:
 950         if (!hmc) {
 951             return false;
 952         }
 953         break;
 954     case 1:
 955         if (extract32(pac, 0, 1) == 0) {
 956             return false;
 957         }
 958         break;
 959     case 0:
 960         if (extract32(pac, 1, 1) == 0) {
 961             return false;
 962         }
 963         break;
 964     default:
 965         g_assert_not_reached();
 966     }
 967
 968     wt = extract64(cr, 20, 1);
 969     lbn = extract64(cr, 16, 4);
 970
 971     if (wt && !linked_bp_matches(cpu, lbn)) {
 972         return false;
 973     }
 974
 975     return true;
 976 }
 977
 978 static bool check_watchpoints(ARMCPU *cpu)
 979 {
 980     CPUARMState *env = &cpu->env;
 981     int n;
 982
 983     /* If watchpoints are disabled globally or we can't take debug
 984      * exceptions here then watchpoint firings are ignored.
 985      */
 986     if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
 987         || !arm_generate_debug_exceptions(env)) {
 988         return false;
 989     }
 990
 991     for (n = 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) {
 992         if (bp_wp_matches(cpu, n, true)) {
 993             return true;
 994         }
 995     }
 996     return false;
 997 }
 998
 999 static bool check_breakpoints(ARMCPU *cpu)
1000 {
1001     CPUARMState *env = &cpu->env;
1002     int n;
1003
1004     /* If breakpoints are disabled globally or we can't take debug
1005      * exceptions here then breakpoint firings are ignored.
1006      */
1007     if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
1008         || !arm_generate_debug_exceptions(env)) {
1009         return false;
1010     }
1011
1012     for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
1013         if (bp_wp_matches(cpu, n, false)) {
1014             return true;
1015         }
1016     }
1017     return false;
1018 }
1019
1020 void HELPER(check_breakpoints)(CPUARMState *env)
1021 {
1022     ARMCPU *cpu = arm_env_get_cpu(env);
1023
1024     if (check_breakpoints(cpu)) {
1025         HELPER(exception_internal(env, EXCP_DEBUG));
1026     }
1027 }
1028
1029 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
1030 {
1031     /* Called by core code when a CPU watchpoint fires; need to check if this
1032      * is also an architectural watchpoint match.
1033      */
1034     ARMCPU *cpu = ARM_CPU(cs);
1035
1036     return check_watchpoints(cpu);
1037 }
1038
1039 void arm_debug_excp_handler(CPUState *cs)
1040 {
1041     /* Called by core code when a watchpoint or breakpoint fires;
1042      * need to check which one and raise the appropriate exception.
1043      */
1044     ARMCPU *cpu = ARM_CPU(cs);
1045     CPUARMState *env = &cpu->env;
1046     CPUWatchpoint *wp_hit = cs->watchpoint_hit;
1047
1048     if (wp_hit) {
1049         if (wp_hit->flags & BP_CPU) {
1050             bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
1051             bool same_el = arm_debug_target_el(env) == arm_current_el(env);
1052
1053             cs->watchpoint_hit = NULL;
1054
1055             if (extended_addresses_enabled(env)) {
1056                 env->exception.fsr = (1 << 9) | 0x22;
1057             } else {
1058                 env->exception.fsr = 0x2;
1059             }
1060             env->exception.vaddress = wp_hit->hitaddr;
1061             raise_exception(env, EXCP_DATA_ABORT,
1062                     syn_watchpoint(same_el, 0, wnr),
1063                     arm_debug_target_el(env));
1064         }
1065     } else {
1066         uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
1067         bool same_el = (arm_debug_target_el(env) == arm_current_el(env));
1068
1069         /* (1) GDB breakpoints should be handled first.
1070          * (2) Do not raise a CPU exception if no CPU breakpoint has fired,
1071          * since singlestep is also done by generating a debug internal
1072          * exception.
1073          */
1074         if (cpu_breakpoint_test(cs, pc, BP_GDB)
1075             || !cpu_breakpoint_test(cs, pc, BP_CPU)) {
1076             return;
1077         }
1078
1079         if (extended_addresses_enabled(env)) {
1080             env->exception.fsr = (1 << 9) | 0x22;
1081         } else {
1082             env->exception.fsr = 0x2;
1083         }
1084         /* FAR is UNKNOWN, so doesn't need setting */
1085         raise_exception(env, EXCP_PREFETCH_ABORT,
1086                         syn_breakpoint(same_el),
1087                         arm_debug_target_el(env));
1088     }
1089 }
1090
1091 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
1092    The only way to do that in TCG is a conditional branch, which clobbers
1093    all our temporaries.  For now implement these as helper functions.  */
1094
1095 /* Similarly for variable shift instructions.  */
1096
1097 uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
1098 {
1099     int shift = i & 0xff;
1100     if (shift >= 32) {
1101         if (shift == 32)
1102             env->CF = x & 1;
1103         else
1104             env->CF = 0;
1105         return 0;
1106     } else if (shift != 0) {
1107         env->CF = (x >> (32 - shift)) & 1;
1108         return x << shift;
1109     }
1110     return x;
1111 }
1112
1113 uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
1114 {
1115     int shift = i & 0xff;
1116     if (shift >= 32) {
1117         if (shift == 32)
1118             env->CF = (x >> 31) & 1;
1119         else
1120             env->CF = 0;
1121         return 0;
1122     } else if (shift != 0) {
1123         env->CF = (x >> (shift - 1)) & 1;
1124         return x >> shift;
1125     }
1126     return x;
1127 }
1128
1129 uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
1130 {
1131     int shift = i & 0xff;
1132     if (shift >= 32) {
1133         env->CF = (x >> 31) & 1;
1134         return (int32_t)x >> 31;
1135     } else if (shift != 0) {
1136         env->CF = (x >> (shift - 1)) & 1;
1137         return (int32_t)x >> shift;
1138     }
1139     return x;
1140 }
1141
1142 uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
1143 {
1144     int shift1, shift;
1145     shift1 = i & 0xff;
1146     shift = shift1 & 0x1f;
1147     if (shift == 0) {
1148         if (shift1 != 0)
1149             env->CF = (x >> 31) & 1;
1150         return x;
1151     } else {
1152         env->CF = (x >> (shift - 1)) & 1;
1153         return ((uint32_t)x >> shift) | (x << (32 - shift));
1154     }
1155 }