target-arm/helper.c

   1 #include "qemu/osdep.h"
   2 #include "cpu.h"
   3 #include "internals.h"
   4 #include "exec/gdbstub.h"
   5 #include "exec/helper-proto.h"
   6 #include "qemu/host-utils.h"
   7 #include "sysemu/arch_init.h"
   8 #include "sysemu/sysemu.h"
   9 #include "qemu/bitops.h"
  10 #include "qemu/crc32c.h"
  11 #include "exec/cpu_ldst.h"
  12 #include "arm_ldst.h"
  13 #include <zlib.h> /* For crc32 */
  14 #include "exec/semihost.h"
  15 #include "sysemu/kvm.h"
  16
  17 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
  18
  19 #ifndef CONFIG_USER_ONLY
  20 static bool get_phys_addr(CPUARMState *env, target_ulong address,
  21                           int access_type, ARMMMUIdx mmu_idx,
  22                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
  23                           target_ulong *page_size, uint32_t *fsr,
  24                           ARMMMUFaultInfo *fi);
  25
  26 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
  27                                int access_type, ARMMMUIdx mmu_idx,
  28                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
  29                                target_ulong *page_size_ptr, uint32_t *fsr,
  30                                ARMMMUFaultInfo *fi);
  31
  32 /* Definitions for the PMCCNTR and PMCR registers */
  33 #define PMCRD   0x8
  34 #define PMCRC   0x4
  35 #define PMCRE   0x1
  36 #endif
  37
  38 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  39 {
  40     int nregs;
  41
  42     /* VFP data registers are always little-endian.  */
  43     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  44     if (reg < nregs) {
  45         stfq_le_p(buf, env->vfp.regs[reg]);
  46         return 8;
  47     }
  48     if (arm_feature(env, ARM_FEATURE_NEON)) {
  49         /* Aliases for Q regs.  */
  50         nregs += 16;
  51         if (reg < nregs) {
  52             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  53             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  54             return 16;
  55         }
  56     }
  57     switch (reg - nregs) {
  58     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  59     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  60     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  61     }
  62     return 0;
  63 }
  64
  65 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  66 {
  67     int nregs;
  68
  69     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  70     if (reg < nregs) {
  71         env->vfp.regs[reg] = ldfq_le_p(buf);
  72         return 8;
  73     }
  74     if (arm_feature(env, ARM_FEATURE_NEON)) {
  75         nregs += 16;
  76         if (reg < nregs) {
  77             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  78             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  79             return 16;
  80         }
  81     }
  82     switch (reg - nregs) {
  83     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  84     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  85     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  86     }
  87     return 0;
  88 }
  89
  90 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  91 {
  92     switch (reg) {
  93     case 0 ... 31:
  94         /* 128 bit FP register */
  95         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  96         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  97         return 16;
  98     case 32:
  99         /* FPSR */
 100         stl_p(buf, vfp_get_fpsr(env));
 101         return 4;
 102     case 33:
 103         /* FPCR */
 104         stl_p(buf, vfp_get_fpcr(env));
 105         return 4;
 106     default:
 107         return 0;
 108     }
 109 }
 110
 111 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 112 {
 113     switch (reg) {
 114     case 0 ... 31:
 115         /* 128 bit FP register */
 116         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 117         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 118         return 16;
 119     case 32:
 120         /* FPSR */
 121         vfp_set_fpsr(env, ldl_p(buf));
 122         return 4;
 123     case 33:
 124         /* FPCR */
 125         vfp_set_fpcr(env, ldl_p(buf));
 126         return 4;
 127     default:
 128         return 0;
 129     }
 130 }
 131
 132 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 133 {
 134     assert(ri->fieldoffset);
 135     if (cpreg_field_is_64bit(ri)) {
 136         return CPREG_FIELD64(env, ri);
 137     } else {
 138         return CPREG_FIELD32(env, ri);
 139     }
 140 }
 141
 142 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 143                       uint64_t value)
 144 {
 145     assert(ri->fieldoffset);
 146     if (cpreg_field_is_64bit(ri)) {
 147         CPREG_FIELD64(env, ri) = value;
 148     } else {
 149         CPREG_FIELD32(env, ri) = value;
 150     }
 151 }
 152
 153 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
 154 {
 155     return (char *)env + ri->fieldoffset;
 156 }
 157
 158 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 159 {
 160     /* Raw read of a coprocessor register (as needed for migration, etc). */
 161     if (ri->type & ARM_CP_CONST) {
 162         return ri->resetvalue;
 163     } else if (ri->raw_readfn) {
 164         return ri->raw_readfn(env, ri);
 165     } else if (ri->readfn) {
 166         return ri->readfn(env, ri);
 167     } else {
 168         return raw_read(env, ri);
 169     }
 170 }
 171
 172 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 173                              uint64_t v)
 174 {
 175     /* Raw write of a coprocessor register (as needed for migration, etc).
 176      * Note that constant registers are treated as write-ignored; the
 177      * caller should check for success by whether a readback gives the
 178      * value written.
 179      */
 180     if (ri->type & ARM_CP_CONST) {
 181         return;
 182     } else if (ri->raw_writefn) {
 183         ri->raw_writefn(env, ri, v);
 184     } else if (ri->writefn) {
 185         ri->writefn(env, ri, v);
 186     } else {
 187         raw_write(env, ri, v);
 188     }
 189 }
 190
 191 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
 192 {
 193    /* Return true if the regdef would cause an assertion if you called
 194     * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
 195     * program bug for it not to have the NO_RAW flag).
 196     * NB that returning false here doesn't necessarily mean that calling
 197     * read/write_raw_cp_reg() is safe, because we can't distinguish "has
 198     * read/write access functions which are safe for raw use" from "has
 199     * read/write access functions which have side effects but has forgotten
 200     * to provide raw access functions".
 201     * The tests here line up with the conditions in read/write_raw_cp_reg()
 202     * and assertions in raw_read()/raw_write().
 203     */
 204     if ((ri->type & ARM_CP_CONST) ||
 205         ri->fieldoffset ||
 206         ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
 207         return false;
 208     }
 209     return true;
 210 }
 211
 212 bool write_cpustate_to_list(ARMCPU *cpu)
 213 {
 214     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 215     int i;
 216     bool ok = true;
 217
 218     for (i = 0; i < cpu->cpreg_array_len; i++) {
 219         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 220         const ARMCPRegInfo *ri;
 221
 222         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 223         if (!ri) {
 224             ok = false;
 225             continue;
 226         }
 227         if (ri->type & ARM_CP_NO_RAW) {
 228             continue;
 229         }
 230         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 231     }
 232     return ok;
 233 }
 234
 235 bool write_list_to_cpustate(ARMCPU *cpu)
 236 {
 237     int i;
 238     bool ok = true;
 239
 240     for (i = 0; i < cpu->cpreg_array_len; i++) {
 241         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 242         uint64_t v = cpu->cpreg_values[i];
 243         const ARMCPRegInfo *ri;
 244
 245         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 246         if (!ri) {
 247             ok = false;
 248             continue;
 249         }
 250         if (ri->type & ARM_CP_NO_RAW) {
 251             continue;
 252         }
 253         /* Write value and confirm it reads back as written
 254          * (to catch read-only registers and partially read-only
 255          * registers where the incoming migration value doesn't match)
 256          */
 257         write_raw_cp_reg(&cpu->env, ri, v);
 258         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 259             ok = false;
 260         }
 261     }
 262     return ok;
 263 }
 264
 265 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 266 {
 267     ARMCPU *cpu = opaque;
 268     uint64_t regidx;
 269     const ARMCPRegInfo *ri;
 270
 271     regidx = *(uint32_t *)key;
 272     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 273
 274     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 275         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 276         /* The value array need not be initialized at this point */
 277         cpu->cpreg_array_len++;
 278     }
 279 }
 280
 281 static void count_cpreg(gpointer key, gpointer opaque)
 282 {
 283     ARMCPU *cpu = opaque;
 284     uint64_t regidx;
 285     const ARMCPRegInfo *ri;
 286
 287     regidx = *(uint32_t *)key;
 288     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 289
 290     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 291         cpu->cpreg_array_len++;
 292     }
 293 }
 294
 295 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 296 {
 297     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 298     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 299
 300     if (aidx > bidx) {
 301         return 1;
 302     }
 303     if (aidx < bidx) {
 304         return -1;
 305     }
 306     return 0;
 307 }
 308
 309 void init_cpreg_list(ARMCPU *cpu)
 310 {
 311     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 312      * Note that we require cpreg_tuples[] to be sorted by key ID.
 313      */
 314     GList *keys;
 315     int arraylen;
 316
 317     keys = g_hash_table_get_keys(cpu->cp_regs);
 318     keys = g_list_sort(keys, cpreg_key_compare);
 319
 320     cpu->cpreg_array_len = 0;
 321
 322     g_list_foreach(keys, count_cpreg, cpu);
 323
 324     arraylen = cpu->cpreg_array_len;
 325     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 326     cpu->cpreg_values = g_new(uint64_t, arraylen);
 327     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 328     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 329     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 330     cpu->cpreg_array_len = 0;
 331
 332     g_list_foreach(keys, add_cpreg_to_list, cpu);
 333
 334     assert(cpu->cpreg_array_len == arraylen);
 335
 336     g_list_free(keys);
 337 }
 338
 339 /*
 340  * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
 341  * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
 342  *
 343  * access_el3_aa32ns: Used to check AArch32 register views.
 344  * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
 345  */
 346 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
 347                                         const ARMCPRegInfo *ri,
 348                                         bool isread)
 349 {
 350     bool secure = arm_is_secure_below_el3(env);
 351
 352     assert(!arm_el_is_aa64(env, 3));
 353     if (secure) {
 354         return CP_ACCESS_TRAP_UNCATEGORIZED;
 355     }
 356     return CP_ACCESS_OK;
 357 }
 358
 359 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
 360                                                 const ARMCPRegInfo *ri,
 361                                                 bool isread)
 362 {
 363     if (!arm_el_is_aa64(env, 3)) {
 364         return access_el3_aa32ns(env, ri, isread);
 365     }
 366     return CP_ACCESS_OK;
 367 }
 368
 369 /* Some secure-only AArch32 registers trap to EL3 if used from
 370  * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
 371  * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
 372  * We assume that the .access field is set to PL1_RW.
 373  */
 374 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
 375                                             const ARMCPRegInfo *ri,
 376                                             bool isread)
 377 {
 378     if (arm_current_el(env) == 3) {
 379         return CP_ACCESS_OK;
 380     }
 381     if (arm_is_secure_below_el3(env)) {
 382         return CP_ACCESS_TRAP_EL3;
 383     }
 384     /* This will be EL1 NS and EL2 NS, which just UNDEF */
 385     return CP_ACCESS_TRAP_UNCATEGORIZED;
 386 }
 387
 388 /* Check for traps to "powerdown debug" registers, which are controlled
 389  * by MDCR.TDOSA
 390  */
 391 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
 392                                    bool isread)
 393 {
 394     int el = arm_current_el(env);
 395
 396     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA)
 397         && !arm_is_secure_below_el3(env)) {
 398         return CP_ACCESS_TRAP_EL2;
 399     }
 400     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
 401         return CP_ACCESS_TRAP_EL3;
 402     }
 403     return CP_ACCESS_OK;
 404 }
 405
 406 /* Check for traps to "debug ROM" registers, which are controlled
 407  * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
 408  */
 409 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
 410                                   bool isread)
 411 {
 412     int el = arm_current_el(env);
 413
 414     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA)
 415         && !arm_is_secure_below_el3(env)) {
 416         return CP_ACCESS_TRAP_EL2;
 417     }
 418     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
 419         return CP_ACCESS_TRAP_EL3;
 420     }
 421     return CP_ACCESS_OK;
 422 }
 423
 424 /* Check for traps to general debug registers, which are controlled
 425  * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
 426  */
 427 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
 428                                   bool isread)
 429 {
 430     int el = arm_current_el(env);
 431
 432     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA)
 433         && !arm_is_secure_below_el3(env)) {
 434         return CP_ACCESS_TRAP_EL2;
 435     }
 436     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
 437         return CP_ACCESS_TRAP_EL3;
 438     }
 439     return CP_ACCESS_OK;
 440 }
 441
 442 /* Check for traps to performance monitor registers, which are controlled
 443  * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
 444  */
 445 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
 446                                  bool isread)
 447 {
 448     int el = arm_current_el(env);
 449
 450     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
 451         && !arm_is_secure_below_el3(env)) {
 452         return CP_ACCESS_TRAP_EL2;
 453     }
 454     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
 455         return CP_ACCESS_TRAP_EL3;
 456     }
 457     return CP_ACCESS_OK;
 458 }
 459
 460 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 461 {
 462     ARMCPU *cpu = arm_env_get_cpu(env);
 463
 464     raw_write(env, ri, value);
 465     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 466 }
 467
 468 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 469 {
 470     ARMCPU *cpu = arm_env_get_cpu(env);
 471
 472     if (raw_read(env, ri) != value) {
 473         /* Unlike real hardware the qemu TLB uses virtual addresses,
 474          * not modified virtual addresses, so this causes a TLB flush.
 475          */
 476         tlb_flush(CPU(cpu), 1);
 477         raw_write(env, ri, value);
 478     }
 479 }
 480
 481 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 482                              uint64_t value)
 483 {
 484     ARMCPU *cpu = arm_env_get_cpu(env);
 485
 486     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 487         && !extended_addresses_enabled(env)) {
 488         /* For VMSA (when not using the LPAE long descriptor page table
 489          * format) this register includes the ASID, so do a TLB flush.
 490          * For PMSA it is purely a process ID and no action is needed.
 491          */
 492         tlb_flush(CPU(cpu), 1);
 493     }
 494     raw_write(env, ri, value);
 495 }
 496
 497 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 498                           uint64_t value)
 499 {
 500     /* Invalidate all (TLBIALL) */
 501     ARMCPU *cpu = arm_env_get_cpu(env);
 502
 503     tlb_flush(CPU(cpu), 1);
 504 }
 505
 506 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 507                           uint64_t value)
 508 {
 509     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 510     ARMCPU *cpu = arm_env_get_cpu(env);
 511
 512     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 513 }
 514
 515 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 516                            uint64_t value)
 517 {
 518     /* Invalidate by ASID (TLBIASID) */
 519     ARMCPU *cpu = arm_env_get_cpu(env);
 520
 521     tlb_flush(CPU(cpu), value == 0);
 522 }
 523
 524 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 525                            uint64_t value)
 526 {
 527     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 528     ARMCPU *cpu = arm_env_get_cpu(env);
 529
 530     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 531 }
 532
 533 /* IS variants of TLB operations must affect all cores */
 534 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 535                              uint64_t value)
 536 {
 537     CPUState *other_cs;
 538
 539     CPU_FOREACH(other_cs) {
 540         tlb_flush(other_cs, 1);
 541     }
 542 }
 543
 544 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 545                              uint64_t value)
 546 {
 547     CPUState *other_cs;
 548
 549     CPU_FOREACH(other_cs) {
 550         tlb_flush(other_cs, value == 0);
 551     }
 552 }
 553
 554 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 555                              uint64_t value)
 556 {
 557     CPUState *other_cs;
 558
 559     CPU_FOREACH(other_cs) {
 560         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 561     }
 562 }
 563
 564 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 565                              uint64_t value)
 566 {
 567     CPUState *other_cs;
 568
 569     CPU_FOREACH(other_cs) {
 570         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 571     }
 572 }
 573
 574 static const ARMCPRegInfo cp_reginfo[] = {
 575     /* Define the secure and non-secure FCSE identifier CP registers
 576      * separately because there is no secure bank in V8 (no _EL3).  This allows
 577      * the secure register to be properly reset and migrated. There is also no
 578      * v8 EL1 version of the register so the non-secure instance stands alone.
 579      */
 580     { .name = "FCSEIDR(NS)",
 581       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 582       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 583       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
 584       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 585     { .name = "FCSEIDR(S)",
 586       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 587       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 588       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
 589       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 590     /* Define the secure and non-secure context identifier CP registers
 591      * separately because there is no secure bank in V8 (no _EL3).  This allows
 592      * the secure register to be properly reset and migrated.  In the
 593      * non-secure case, the 32-bit register will have reset and migration
 594      * disabled during registration as it is handled by the 64-bit instance.
 595      */
 596     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
 597       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 598       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 599       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
 600       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 601     { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
 602       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 603       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 604       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
 605       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 606     REGINFO_SENTINEL
 607 };
 608
 609 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 610     /* NB: Some of these registers exist in v8 but with more precise
 611      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 612      */
 613     /* MMU Domain access control / MPU write buffer control */
 614     { .name = "DACR",
 615       .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
 616       .access = PL1_RW, .resetvalue = 0,
 617       .writefn = dacr_write, .raw_writefn = raw_write,
 618       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
 619                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
 620     /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
 621      * For v6 and v5, these mappings are overly broad.
 622      */
 623     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
 624       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 625     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
 626       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 627     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
 628       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 629     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
 630       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 631     /* Cache maintenance ops; some of this space may be overridden later. */
 632     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 633       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 634       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 635     REGINFO_SENTINEL
 636 };
 637
 638 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 639     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 640      * over-broad.
 641      */
 642     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 643       .access = PL1_W, .type = ARM_CP_WFI },
 644     REGINFO_SENTINEL
 645 };
 646
 647 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 648     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 649      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 650      */
 651     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 652       .access = PL1_W, .type = ARM_CP_WFI },
 653     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 654      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 655      * OMAPCP will override this space.
 656      */
 657     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 658       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 659       .resetvalue = 0 },
 660     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 661       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 662       .resetvalue = 0 },
 663     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 664     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 665       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
 666       .resetvalue = 0 },
 667     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 668      * implementing it as RAZ means the "debug architecture version" bits
 669      * will read as a reserved value, which should cause Linux to not try
 670      * to use the debug hardware.
 671      */
 672     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 673       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 674     /* MMU TLB control. Note that the wildcarding means we cover not just
 675      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 676      */
 677     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 678       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 679       .type = ARM_CP_NO_RAW },
 680     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 681       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 682       .type = ARM_CP_NO_RAW },
 683     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 684       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 685       .type = ARM_CP_NO_RAW },
 686     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 687       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 688       .type = ARM_CP_NO_RAW },
 689     { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
 690       .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
 691     { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
 692       .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
 693     REGINFO_SENTINEL
 694 };
 695
 696 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 697                         uint64_t value)
 698 {
 699     uint32_t mask = 0;
 700
 701     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 702     if (!arm_feature(env, ARM_FEATURE_V8)) {
 703         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 704          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 705          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 706          */
 707         if (arm_feature(env, ARM_FEATURE_VFP)) {
 708             /* VFP coprocessor: cp10 & cp11 [23:20] */
 709             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 710
 711             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 712                 /* ASEDIS [31] bit is RAO/WI */
 713                 value |= (1 << 31);
 714             }
 715
 716             /* VFPv3 and upwards with NEON implement 32 double precision
 717              * registers (D0-D31).
 718              */
 719             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 720                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 721                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 722                 value |= (1 << 30);
 723             }
 724         }
 725         value &= mask;
 726     }
 727     env->cp15.cpacr_el1 = value;
 728 }
 729
 730 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
 731                                    bool isread)
 732 {
 733     if (arm_feature(env, ARM_FEATURE_V8)) {
 734         /* Check if CPACR accesses are to be trapped to EL2 */
 735         if (arm_current_el(env) == 1 &&
 736             (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
 737             return CP_ACCESS_TRAP_EL2;
 738         /* Check if CPACR accesses are to be trapped to EL3 */
 739         } else if (arm_current_el(env) < 3 &&
 740                    (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 741             return CP_ACCESS_TRAP_EL3;
 742         }
 743     }
 744
 745     return CP_ACCESS_OK;
 746 }
 747
 748 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri,
 749                                   bool isread)
 750 {
 751     /* Check if CPTR accesses are set to trap to EL3 */
 752     if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 753         return CP_ACCESS_TRAP_EL3;
 754     }
 755
 756     return CP_ACCESS_OK;
 757 }
 758
 759 static const ARMCPRegInfo v6_cp_reginfo[] = {
 760     /* prefetch by MVA in v6, NOP in v7 */
 761     { .name = "MVA_prefetch",
 762       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 763       .access = PL1_W, .type = ARM_CP_NOP },
 764     /* We need to break the TB after ISB to execute self-modifying code
 765      * correctly and also to take any pending interrupts immediately.
 766      * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
 767      */
 768     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 769       .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
 770     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 771       .access = PL0_W, .type = ARM_CP_NOP },
 772     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 773       .access = PL0_W, .type = ARM_CP_NOP },
 774     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 775       .access = PL1_RW,
 776       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
 777                              offsetof(CPUARMState, cp15.ifar_ns) },
 778       .resetvalue = 0, },
 779     /* Watchpoint Fault Address Register : should actually only be present
 780      * for 1136, 1176, 11MPCore.
 781      */
 782     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 783       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 784     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 785       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
 786       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
 787       .resetvalue = 0, .writefn = cpacr_write },
 788     REGINFO_SENTINEL
 789 };
 790
 791 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
 792                                    bool isread)
 793 {
 794     /* Performance monitor registers user accessibility is controlled
 795      * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
 796      * trapping to EL2 or EL3 for other accesses.
 797      */
 798     int el = arm_current_el(env);
 799
 800     if (el == 0 && !env->cp15.c9_pmuserenr) {
 801         return CP_ACCESS_TRAP;
 802     }
 803     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
 804         && !arm_is_secure_below_el3(env)) {
 805         return CP_ACCESS_TRAP_EL2;
 806     }
 807     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
 808         return CP_ACCESS_TRAP_EL3;
 809     }
 810
 811     return CP_ACCESS_OK;
 812 }
 813
 814 #ifndef CONFIG_USER_ONLY
 815
 816 static inline bool arm_ccnt_enabled(CPUARMState *env)
 817 {
 818     /* This does not support checking PMCCFILTR_EL0 register */
 819
 820     if (!(env->cp15.c9_pmcr & PMCRE)) {
 821         return false;
 822     }
 823
 824     return true;
 825 }
 826
 827 void pmccntr_sync(CPUARMState *env)
 828 {
 829     uint64_t temp_ticks;
 830
 831     temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 832                           ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 833
 834     if (env->cp15.c9_pmcr & PMCRD) {
 835         /* Increment once every 64 processor clock cycles */
 836         temp_ticks /= 64;
 837     }
 838
 839     if (arm_ccnt_enabled(env)) {
 840         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 841     }
 842 }
 843
 844 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 845                        uint64_t value)
 846 {
 847     pmccntr_sync(env);
 848
 849     if (value & PMCRC) {
 850         /* The counter has been reset */
 851         env->cp15.c15_ccnt = 0;
 852     }
 853
 854     /* only the DP, X, D and E bits are writable */
 855     env->cp15.c9_pmcr &= ~0x39;
 856     env->cp15.c9_pmcr |= (value & 0x39);
 857
 858     pmccntr_sync(env);
 859 }
 860
 861 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 862 {
 863     uint64_t total_ticks;
 864
 865     if (!arm_ccnt_enabled(env)) {
 866         /* Counter is disabled, do not change value */
 867         return env->cp15.c15_ccnt;
 868     }
 869
 870     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 871                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 872
 873     if (env->cp15.c9_pmcr & PMCRD) {
 874         /* Increment once every 64 processor clock cycles */
 875         total_ticks /= 64;
 876     }
 877     return total_ticks - env->cp15.c15_ccnt;
 878 }
 879
 880 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 881                         uint64_t value)
 882 {
 883     uint64_t total_ticks;
 884
 885     if (!arm_ccnt_enabled(env)) {
 886         /* Counter is disabled, set the absolute value */
 887         env->cp15.c15_ccnt = value;
 888         return;
 889     }
 890
 891     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 892                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 893
 894     if (env->cp15.c9_pmcr & PMCRD) {
 895         /* Increment once every 64 processor clock cycles */
 896         total_ticks /= 64;
 897     }
 898     env->cp15.c15_ccnt = total_ticks - value;
 899 }
 900
 901 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 902                             uint64_t value)
 903 {
 904     uint64_t cur_val = pmccntr_read(env, NULL);
 905
 906     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 907 }
 908
 909 #else /* CONFIG_USER_ONLY */
 910
 911 void pmccntr_sync(CPUARMState *env)
 912 {
 913 }
 914
 915 #endif
 916
 917 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 918                             uint64_t value)
 919 {
 920     pmccntr_sync(env);
 921     env->cp15.pmccfiltr_el0 = value & 0x7E000000;
 922     pmccntr_sync(env);
 923 }
 924
 925 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 926                             uint64_t value)
 927 {
 928     value &= (1 << 31);
 929     env->cp15.c9_pmcnten |= value;
 930 }
 931
 932 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 933                              uint64_t value)
 934 {
 935     value &= (1 << 31);
 936     env->cp15.c9_pmcnten &= ~value;
 937 }
 938
 939 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 940                          uint64_t value)
 941 {
 942     env->cp15.c9_pmovsr &= ~value;
 943 }
 944
 945 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 946                              uint64_t value)
 947 {
 948     env->cp15.c9_pmxevtyper = value & 0xff;
 949 }
 950
 951 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 952                             uint64_t value)
 953 {
 954     env->cp15.c9_pmuserenr = value & 1;
 955 }
 956
 957 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 958                              uint64_t value)
 959 {
 960     /* We have no event counters so only the C bit can be changed */
 961     value &= (1 << 31);
 962     env->cp15.c9_pminten |= value;
 963 }
 964
 965 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 966                              uint64_t value)
 967 {
 968     value &= (1 << 31);
 969     env->cp15.c9_pminten &= ~value;
 970 }
 971
 972 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 973                        uint64_t value)
 974 {
 975     /* Note that even though the AArch64 view of this register has bits
 976      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 977      * architectural requirements for bits which are RES0 only in some
 978      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 979      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 980      */
 981     raw_write(env, ri, value & ~0x1FULL);
 982 }
 983
 984 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 985 {
 986     /* We only mask off bits that are RES0 both for AArch64 and AArch32.
 987      * For bits that vary between AArch32/64, code needs to check the
 988      * current execution mode before directly using the feature bit.
 989      */
 990     uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
 991
 992     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 993         valid_mask &= ~SCR_HCE;
 994
 995         /* On ARMv7, SMD (or SCD as it is called in v7) is only
 996          * supported if EL2 exists. The bit is UNK/SBZP when
 997          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
 998          * when EL2 is unavailable.
 999          * On ARMv8, this bit is always available.
1000          */
1001         if (arm_feature(env, ARM_FEATURE_V7) &&
1002             !arm_feature(env, ARM_FEATURE_V8)) {
1003             valid_mask &= ~SCR_SMD;
1004         }
1005     }
1006
1007     /* Clear all-context RES0 bits.  */
1008     value &= valid_mask;
1009     raw_write(env, ri, value);
1010 }
1011
1012 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1013 {
1014     ARMCPU *cpu = arm_env_get_cpu(env);
1015
1016     /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1017      * bank
1018      */
1019     uint32_t index = A32_BANKED_REG_GET(env, csselr,
1020                                         ri->secure & ARM_CP_SECSTATE_S);
1021
1022     return cpu->ccsidr[index];
1023 }
1024
1025 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1026                          uint64_t value)
1027 {
1028     raw_write(env, ri, value & 0xf);
1029 }
1030
1031 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1032 {
1033     CPUState *cs = ENV_GET_CPU(env);
1034     uint64_t ret = 0;
1035
1036     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
1037         ret |= CPSR_I;
1038     }
1039     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
1040         ret |= CPSR_F;
1041     }
1042     /* External aborts are not possible in QEMU so A bit is always clear */
1043     return ret;
1044 }
1045
1046 static const ARMCPRegInfo v7_cp_reginfo[] = {
1047     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1048     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
1049       .access = PL1_W, .type = ARM_CP_NOP },
1050     /* Performance monitors are implementation defined in v7,
1051      * but with an ARM recommended set of registers, which we
1052      * follow (although we don't actually implement any counters)
1053      *
1054      * Performance registers fall into three categories:
1055      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1056      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1057      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1058      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1059      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1060      */
1061     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
1062       .access = PL0_RW, .type = ARM_CP_ALIAS,
1063       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
1064       .writefn = pmcntenset_write,
1065       .accessfn = pmreg_access,
1066       .raw_writefn = raw_write },
1067     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
1068       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
1069       .access = PL0_RW, .accessfn = pmreg_access,
1070       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
1071       .writefn = pmcntenset_write, .raw_writefn = raw_write },
1072     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
1073       .access = PL0_RW,
1074       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
1075       .accessfn = pmreg_access,
1076       .writefn = pmcntenclr_write,
1077       .type = ARM_CP_ALIAS },
1078     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
1079       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
1080       .access = PL0_RW, .accessfn = pmreg_access,
1081       .type = ARM_CP_ALIAS,
1082       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
1083       .writefn = pmcntenclr_write },
1084     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
1085       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
1086       .accessfn = pmreg_access,
1087       .writefn = pmovsr_write,
1088       .raw_writefn = raw_write },
1089     { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
1090       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
1091       .access = PL0_RW, .accessfn = pmreg_access,
1092       .type = ARM_CP_ALIAS,
1093       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
1094       .writefn = pmovsr_write,
1095       .raw_writefn = raw_write },
1096     /* Unimplemented so WI. */
1097     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
1098       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
1099     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
1100      * We choose to RAZ/WI.
1101      */
1102     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
1103       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1104       .accessfn = pmreg_access },
1105 #ifndef CONFIG_USER_ONLY
1106     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
1107       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
1108       .readfn = pmccntr_read, .writefn = pmccntr_write32,
1109       .accessfn = pmreg_access },
1110     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
1111       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
1112       .access = PL0_RW, .accessfn = pmreg_access,
1113       .type = ARM_CP_IO,
1114       .readfn = pmccntr_read, .writefn = pmccntr_write, },
1115 #endif
1116     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
1117       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
1118       .writefn = pmccfiltr_write,
1119       .access = PL0_RW, .accessfn = pmreg_access,
1120       .type = ARM_CP_IO,
1121       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
1122       .resetvalue = 0, },
1123     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
1124       .access = PL0_RW,
1125       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
1126       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
1127       .raw_writefn = raw_write },
1128     /* Unimplemented, RAZ/WI. */
1129     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
1130       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1131       .accessfn = pmreg_access },
1132     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
1133       .access = PL0_R | PL1_RW, .accessfn = access_tpm,
1134       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1135       .resetvalue = 0,
1136       .writefn = pmuserenr_write, .raw_writefn = raw_write },
1137     { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
1138       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
1139       .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1140       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1141       .resetvalue = 0,
1142       .writefn = pmuserenr_write, .raw_writefn = raw_write },
1143     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
1144       .access = PL1_RW, .accessfn = access_tpm,
1145       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1146       .resetvalue = 0,
1147       .writefn = pmintenset_write, .raw_writefn = raw_write },
1148     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
1149       .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1150       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1151       .writefn = pmintenclr_write, },
1152     { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
1153       .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
1154       .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1155       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1156       .writefn = pmintenclr_write },
1157     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
1158       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
1159       .access = PL1_RW, .writefn = vbar_write,
1160       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
1161                              offsetof(CPUARMState, cp15.vbar_ns) },
1162       .resetvalue = 0 },
1163     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
1164       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
1165       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
1166     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
1167       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
1168       .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
1169       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
1170                              offsetof(CPUARMState, cp15.csselr_ns) } },
1171     /* Auxiliary ID register: this actually has an IMPDEF value but for now
1172      * just RAZ for all cores:
1173      */
1174     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1175       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1176       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1177     /* Auxiliary fault status registers: these also are IMPDEF, and we
1178      * choose to RAZ/WI for all cores.
1179      */
1180     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1181       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1182       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1183     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1184       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1185       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1186     /* MAIR can just read-as-written because we don't implement caches
1187      * and so don't need to care about memory attributes.
1188      */
1189     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1190       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1191       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1192       .resetvalue = 0 },
1193     { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
1194       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
1195       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1196       .resetvalue = 0 },
1197     /* For non-long-descriptor page tables these are PRRR and NMRR;
1198      * regardless they still act as reads-as-written for QEMU.
1199      */
1200      /* MAIR0/1 are defined separately from their 64-bit counterpart which
1201       * allows them to assign the correct fieldoffset based on the endianness
1202       * handled in the field definitions.
1203       */
1204     { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1205       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1206       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1207                              offsetof(CPUARMState, cp15.mair0_ns) },
1208       .resetfn = arm_cp_reset_ignore },
1209     { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
1210       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1211       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1212                              offsetof(CPUARMState, cp15.mair1_ns) },
1213       .resetfn = arm_cp_reset_ignore },
1214     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1215       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1216       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1217     /* 32 bit ITLB invalidates */
1218     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1219       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1220     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1221       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1222     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1223       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1224     /* 32 bit DTLB invalidates */
1225     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1226       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1227     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1228       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1229     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1230       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1231     /* 32 bit TLB invalidates */
1232     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1233       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1234     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1235       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1236     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1237       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1238     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1239       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1240     REGINFO_SENTINEL
1241 };
1242
1243 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1244     /* 32 bit TLB invalidates, Inner Shareable */
1245     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1246       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1247     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1248       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1249     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1250       .type = ARM_CP_NO_RAW, .access = PL1_W,
1251       .writefn = tlbiasid_is_write },
1252     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1253       .type = ARM_CP_NO_RAW, .access = PL1_W,
1254       .writefn = tlbimvaa_is_write },
1255     REGINFO_SENTINEL
1256 };
1257
1258 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1259                         uint64_t value)
1260 {
1261     value &= 1;
1262     env->teecr = value;
1263 }
1264
1265 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1266                                     bool isread)
1267 {
1268     if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1269         return CP_ACCESS_TRAP;
1270     }
1271     return CP_ACCESS_OK;
1272 }
1273
1274 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1275     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1276       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1277       .resetvalue = 0,
1278       .writefn = teecr_write },
1279     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1280       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1281       .accessfn = teehbr_access, .resetvalue = 0 },
1282     REGINFO_SENTINEL
1283 };
1284
1285 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1286     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1287       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1288       .access = PL0_RW,
1289       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1290     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1291       .access = PL0_RW,
1292       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1293                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1294       .resetfn = arm_cp_reset_ignore },
1295     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1296       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1297       .access = PL0_R|PL1_W,
1298       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1299       .resetvalue = 0},
1300     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1301       .access = PL0_R|PL1_W,
1302       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1303                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1304       .resetfn = arm_cp_reset_ignore },
1305     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1306       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1307       .access = PL1_RW,
1308       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1309     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1310       .access = PL1_RW,
1311       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1312                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1313       .resetvalue = 0 },
1314     REGINFO_SENTINEL
1315 };
1316
1317 #ifndef CONFIG_USER_ONLY
1318
1319 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
1320                                        bool isread)
1321 {
1322     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
1323      * Writable only at the highest implemented exception level.
1324      */
1325     int el = arm_current_el(env);
1326
1327     switch (el) {
1328     case 0:
1329         if (!extract32(env->cp15.c14_cntkctl, 0, 2)) {
1330             return CP_ACCESS_TRAP;
1331         }
1332         break;
1333     case 1:
1334         if (!isread && ri->state == ARM_CP_STATE_AA32 &&
1335             arm_is_secure_below_el3(env)) {
1336             /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
1337             return CP_ACCESS_TRAP_UNCATEGORIZED;
1338         }
1339         break;
1340     case 2:
1341     case 3:
1342         break;
1343     }
1344
1345     if (!isread && el < arm_highest_el(env)) {
1346         return CP_ACCESS_TRAP_UNCATEGORIZED;
1347     }
1348
1349     return CP_ACCESS_OK;
1350 }
1351
1352 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
1353                                         bool isread)
1354 {
1355     unsigned int cur_el = arm_current_el(env);
1356     bool secure = arm_is_secure(env);
1357
1358     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1359     if (cur_el == 0 &&
1360         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1361         return CP_ACCESS_TRAP;
1362     }
1363
1364     if (arm_feature(env, ARM_FEATURE_EL2) &&
1365         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1366         !extract32(env->cp15.cnthctl_el2, 0, 1)) {
1367         return CP_ACCESS_TRAP_EL2;
1368     }
1369     return CP_ACCESS_OK;
1370 }
1371
1372 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
1373                                       bool isread)
1374 {
1375     unsigned int cur_el = arm_current_el(env);
1376     bool secure = arm_is_secure(env);
1377
1378     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1379      * EL0[PV]TEN is zero.
1380      */
1381     if (cur_el == 0 &&
1382         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1383         return CP_ACCESS_TRAP;
1384     }
1385
1386     if (arm_feature(env, ARM_FEATURE_EL2) &&
1387         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1388         !extract32(env->cp15.cnthctl_el2, 1, 1)) {
1389         return CP_ACCESS_TRAP_EL2;
1390     }
1391     return CP_ACCESS_OK;
1392 }
1393
1394 static CPAccessResult gt_pct_access(CPUARMState *env,
1395                                     const ARMCPRegInfo *ri,
1396                                     bool isread)
1397 {
1398     return gt_counter_access(env, GTIMER_PHYS, isread);
1399 }
1400
1401 static CPAccessResult gt_vct_access(CPUARMState *env,
1402                                     const ARMCPRegInfo *ri,
1403                                     bool isread)
1404 {
1405     return gt_counter_access(env, GTIMER_VIRT, isread);
1406 }
1407
1408 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1409                                        bool isread)
1410 {
1411     return gt_timer_access(env, GTIMER_PHYS, isread);
1412 }
1413
1414 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1415                                        bool isread)
1416 {
1417     return gt_timer_access(env, GTIMER_VIRT, isread);
1418 }
1419
1420 static CPAccessResult gt_stimer_access(CPUARMState *env,
1421                                        const ARMCPRegInfo *ri,
1422                                        bool isread)
1423 {
1424     /* The AArch64 register view of the secure physical timer is
1425      * always accessible from EL3, and configurably accessible from
1426      * Secure EL1.
1427      */
1428     switch (arm_current_el(env)) {
1429     case 1:
1430         if (!arm_is_secure(env)) {
1431             return CP_ACCESS_TRAP;
1432         }
1433         if (!(env->cp15.scr_el3 & SCR_ST)) {
1434             return CP_ACCESS_TRAP_EL3;
1435         }
1436         return CP_ACCESS_OK;
1437     case 0:
1438     case 2:
1439         return CP_ACCESS_TRAP;
1440     case 3:
1441         return CP_ACCESS_OK;
1442     default:
1443         g_assert_not_reached();
1444     }
1445 }
1446
1447 static uint64_t gt_get_countervalue(CPUARMState *env)
1448 {
1449     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1450 }
1451
1452 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1453 {
1454     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1455
1456     if (gt->ctl & 1) {
1457         /* Timer enabled: calculate and set current ISTATUS, irq, and
1458          * reset timer to when ISTATUS next has to change
1459          */
1460         uint64_t offset = timeridx == GTIMER_VIRT ?
1461                                       cpu->env.cp15.cntvoff_el2 : 0;
1462         uint64_t count = gt_get_countervalue(&cpu->env);
1463         /* Note that this must be unsigned 64 bit arithmetic: */
1464         int istatus = count - offset >= gt->cval;
1465         uint64_t nexttick;
1466
1467         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1468         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1469                      (istatus && !(gt->ctl & 2)));
1470         if (istatus) {
1471             /* Next transition is when count rolls back over to zero */
1472             nexttick = UINT64_MAX;
1473         } else {
1474             /* Next transition is when we hit cval */
1475             nexttick = gt->cval + offset;
1476         }
1477         /* Note that the desired next expiry time might be beyond the
1478          * signed-64-bit range of a QEMUTimer -- in this case we just
1479          * set the timer for as far in the future as possible. When the
1480          * timer expires we will reset the timer for any remaining period.
1481          */
1482         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1483             nexttick = INT64_MAX / GTIMER_SCALE;
1484         }
1485         timer_mod(cpu->gt_timer[timeridx], nexttick);
1486     } else {
1487         /* Timer disabled: ISTATUS and timer output always clear */
1488         gt->ctl &= ~4;
1489         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1490         timer_del(cpu->gt_timer[timeridx]);
1491     }
1492 }
1493
1494 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
1495                            int timeridx)
1496 {
1497     ARMCPU *cpu = arm_env_get_cpu(env);
1498
1499     timer_del(cpu->gt_timer[timeridx]);
1500 }
1501
1502 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1503 {
1504     return gt_get_countervalue(env);
1505 }
1506
1507 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1508 {
1509     return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
1510 }
1511
1512 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1513                           int timeridx,
1514                           uint64_t value)
1515 {
1516     env->cp15.c14_timer[timeridx].cval = value;
1517     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1518 }
1519
1520 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
1521                              int timeridx)
1522 {
1523     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1524
1525     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1526                       (gt_get_countervalue(env) - offset));
1527 }
1528
1529 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1530                           int timeridx,
1531                           uint64_t value)
1532 {
1533     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1534
1535     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
1536                                          sextract64(value, 0, 32);
1537     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1538 }
1539
1540 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1541                          int timeridx,
1542                          uint64_t value)
1543 {
1544     ARMCPU *cpu = arm_env_get_cpu(env);
1545     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1546
1547     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1548     if ((oldval ^ value) & 1) {
1549         /* Enable toggled */
1550         gt_recalc_timer(cpu, timeridx);
1551     } else if ((oldval ^ value) & 2) {
1552         /* IMASK toggled: don't need to recalculate,
1553          * just set the interrupt line based on ISTATUS
1554          */
1555         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1556                      (oldval & 4) && !(value & 2));
1557     }
1558 }
1559
1560 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1561 {
1562     gt_timer_reset(env, ri, GTIMER_PHYS);
1563 }
1564
1565 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1566                                uint64_t value)
1567 {
1568     gt_cval_write(env, ri, GTIMER_PHYS, value);
1569 }
1570
1571 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1572 {
1573     return gt_tval_read(env, ri, GTIMER_PHYS);
1574 }
1575
1576 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1577                                uint64_t value)
1578 {
1579     gt_tval_write(env, ri, GTIMER_PHYS, value);
1580 }
1581
1582 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1583                               uint64_t value)
1584 {
1585     gt_ctl_write(env, ri, GTIMER_PHYS, value);
1586 }
1587
1588 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1589 {
1590     gt_timer_reset(env, ri, GTIMER_VIRT);
1591 }
1592
1593 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1594                                uint64_t value)
1595 {
1596     gt_cval_write(env, ri, GTIMER_VIRT, value);
1597 }
1598
1599 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1600 {
1601     return gt_tval_read(env, ri, GTIMER_VIRT);
1602 }
1603
1604 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1605                                uint64_t value)
1606 {
1607     gt_tval_write(env, ri, GTIMER_VIRT, value);
1608 }
1609
1610 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1611                               uint64_t value)
1612 {
1613     gt_ctl_write(env, ri, GTIMER_VIRT, value);
1614 }
1615
1616 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
1617                               uint64_t value)
1618 {
1619     ARMCPU *cpu = arm_env_get_cpu(env);
1620
1621     raw_write(env, ri, value);
1622     gt_recalc_timer(cpu, GTIMER_VIRT);
1623 }
1624
1625 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1626 {
1627     gt_timer_reset(env, ri, GTIMER_HYP);
1628 }
1629
1630 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1631                               uint64_t value)
1632 {
1633     gt_cval_write(env, ri, GTIMER_HYP, value);
1634 }
1635
1636 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1637 {
1638     return gt_tval_read(env, ri, GTIMER_HYP);
1639 }
1640
1641 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1642                               uint64_t value)
1643 {
1644     gt_tval_write(env, ri, GTIMER_HYP, value);
1645 }
1646
1647 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1648                               uint64_t value)
1649 {
1650     gt_ctl_write(env, ri, GTIMER_HYP, value);
1651 }
1652
1653 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1654 {
1655     gt_timer_reset(env, ri, GTIMER_SEC);
1656 }
1657
1658 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1659                               uint64_t value)
1660 {
1661     gt_cval_write(env, ri, GTIMER_SEC, value);
1662 }
1663
1664 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1665 {
1666     return gt_tval_read(env, ri, GTIMER_SEC);
1667 }
1668
1669 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1670                               uint64_t value)
1671 {
1672     gt_tval_write(env, ri, GTIMER_SEC, value);
1673 }
1674
1675 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1676                               uint64_t value)
1677 {
1678     gt_ctl_write(env, ri, GTIMER_SEC, value);
1679 }
1680
1681 void arm_gt_ptimer_cb(void *opaque)
1682 {
1683     ARMCPU *cpu = opaque;
1684
1685     gt_recalc_timer(cpu, GTIMER_PHYS);
1686 }
1687
1688 void arm_gt_vtimer_cb(void *opaque)
1689 {
1690     ARMCPU *cpu = opaque;
1691
1692     gt_recalc_timer(cpu, GTIMER_VIRT);
1693 }
1694
1695 void arm_gt_htimer_cb(void *opaque)
1696 {
1697     ARMCPU *cpu = opaque;
1698
1699     gt_recalc_timer(cpu, GTIMER_HYP);
1700 }
1701
1702 void arm_gt_stimer_cb(void *opaque)
1703 {
1704     ARMCPU *cpu = opaque;
1705
1706     gt_recalc_timer(cpu, GTIMER_SEC);
1707 }
1708
1709 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1710     /* Note that CNTFRQ is purely reads-as-written for the benefit
1711      * of software; writing it doesn't actually change the timer frequency.
1712      * Our reset value matches the fixed frequency we implement the timer at.
1713      */
1714     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1715       .type = ARM_CP_ALIAS,
1716       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1717       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1718     },
1719     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1720       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1721       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1722       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1723       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1724     },
1725     /* overall control: mostly access permissions */
1726     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1727       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1728       .access = PL1_RW,
1729       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1730       .resetvalue = 0,
1731     },
1732     /* per-timer control */
1733     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1734       .secure = ARM_CP_SECSTATE_NS,
1735       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1736       .accessfn = gt_ptimer_access,
1737       .fieldoffset = offsetoflow32(CPUARMState,
1738                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1739       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1740     },
1741     { .name = "CNTP_CTL(S)",
1742       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1743       .secure = ARM_CP_SECSTATE_S,
1744       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1745       .accessfn = gt_ptimer_access,
1746       .fieldoffset = offsetoflow32(CPUARMState,
1747                                    cp15.c14_timer[GTIMER_SEC].ctl),
1748       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1749     },
1750     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1751       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1752       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1753       .accessfn = gt_ptimer_access,
1754       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1755       .resetvalue = 0,
1756       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1757     },
1758     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1759       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1760       .accessfn = gt_vtimer_access,
1761       .fieldoffset = offsetoflow32(CPUARMState,
1762                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1763       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1764     },
1765     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1766       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1767       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1768       .accessfn = gt_vtimer_access,
1769       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1770       .resetvalue = 0,
1771       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1772     },
1773     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1774     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1775       .secure = ARM_CP_SECSTATE_NS,
1776       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1777       .accessfn = gt_ptimer_access,
1778       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1779     },
1780     { .name = "CNTP_TVAL(S)",
1781       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1782       .secure = ARM_CP_SECSTATE_S,
1783       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1784       .accessfn = gt_ptimer_access,
1785       .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
1786     },
1787     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1788       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1789       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1790       .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
1791       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1792     },
1793     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1794       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1795       .accessfn = gt_vtimer_access,
1796       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1797     },
1798     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1799       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1800       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1801       .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
1802       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1803     },
1804     /* The counter itself */
1805     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1806       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1807       .accessfn = gt_pct_access,
1808       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1809     },
1810     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1811       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1812       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1813       .accessfn = gt_pct_access, .readfn = gt_cnt_read,
1814     },
1815     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1816       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1817       .accessfn = gt_vct_access,
1818       .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
1819     },
1820     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1821       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1822       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1823       .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
1824     },
1825     /* Comparison value, indicating when the timer goes off */
1826     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1827       .secure = ARM_CP_SECSTATE_NS,
1828       .access = PL1_RW | PL0_R,
1829       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1830       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1831       .accessfn = gt_ptimer_access,
1832       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1833     },
1834     { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2,
1835       .secure = ARM_CP_SECSTATE_S,
1836       .access = PL1_RW | PL0_R,
1837       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1838       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1839       .accessfn = gt_ptimer_access,
1840       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1841     },
1842     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1843       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1844       .access = PL1_RW | PL0_R,
1845       .type = ARM_CP_IO,
1846       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1847       .resetvalue = 0, .accessfn = gt_ptimer_access,
1848       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1849     },
1850     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1851       .access = PL1_RW | PL0_R,
1852       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1853       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1854       .accessfn = gt_vtimer_access,
1855       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1856     },
1857     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1858       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1859       .access = PL1_RW | PL0_R,
1860       .type = ARM_CP_IO,
1861       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1862       .resetvalue = 0, .accessfn = gt_vtimer_access,
1863       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1864     },
1865     /* Secure timer -- this is actually restricted to only EL3
1866      * and configurably Secure-EL1 via the accessfn.
1867      */
1868     { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
1869       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
1870       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
1871       .accessfn = gt_stimer_access,
1872       .readfn = gt_sec_tval_read,
1873       .writefn = gt_sec_tval_write,
1874       .resetfn = gt_sec_timer_reset,
1875     },
1876     { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
1877       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
1878       .type = ARM_CP_IO, .access = PL1_RW,
1879       .accessfn = gt_stimer_access,
1880       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
1881       .resetvalue = 0,
1882       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1883     },
1884     { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
1885       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
1886       .type = ARM_CP_IO, .access = PL1_RW,
1887       .accessfn = gt_stimer_access,
1888       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1889       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1890     },
1891     REGINFO_SENTINEL
1892 };
1893
1894 #else
1895 /* In user-mode none of the generic timer registers are accessible,
1896  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1897  * so instead just don't register any of them.
1898  */
1899 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1900     REGINFO_SENTINEL
1901 };
1902
1903 #endif
1904
1905 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1906 {
1907     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1908         raw_write(env, ri, value);
1909     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1910         raw_write(env, ri, value & 0xfffff6ff);
1911     } else {
1912         raw_write(env, ri, value & 0xfffff1ff);
1913     }
1914 }
1915
1916 #ifndef CONFIG_USER_ONLY
1917 /* get_phys_addr() isn't present for user-mode-only targets */
1918
1919 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
1920                                  bool isread)
1921 {
1922     if (ri->opc2 & 4) {
1923         /* The ATS12NSO* operations must trap to EL3 if executed in
1924          * Secure EL1 (which can only happen if EL3 is AArch64).
1925          * They are simply UNDEF if executed from NS EL1.
1926          * They function normally from EL2 or EL3.
1927          */
1928         if (arm_current_el(env) == 1) {
1929             if (arm_is_secure_below_el3(env)) {
1930                 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
1931             }
1932             return CP_ACCESS_TRAP_UNCATEGORIZED;
1933         }
1934     }
1935     return CP_ACCESS_OK;
1936 }
1937
1938 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
1939                              int access_type, ARMMMUIdx mmu_idx)
1940 {
1941     hwaddr phys_addr;
1942     target_ulong page_size;
1943     int prot;
1944     uint32_t fsr;
1945     bool ret;
1946     uint64_t par64;
1947     MemTxAttrs attrs = {};
1948     ARMMMUFaultInfo fi = {};
1949
1950     ret = get_phys_addr(env, value, access_type, mmu_idx,
1951                         &phys_addr, &attrs, &prot, &page_size, &fsr, &fi);
1952     if (extended_addresses_enabled(env)) {
1953         /* fsr is a DFSR/IFSR value for the long descriptor
1954          * translation table format, but with WnR always clear.
1955          * Convert it to a 64-bit PAR.
1956          */
1957         par64 = (1 << 11); /* LPAE bit always set */
1958         if (!ret) {
1959             par64 |= phys_addr & ~0xfffULL;
1960             if (!attrs.secure) {
1961                 par64 |= (1 << 9); /* NS */
1962             }
1963             /* We don't set the ATTR or SH fields in the PAR. */
1964         } else {
1965             par64 |= 1; /* F */
1966             par64 |= (fsr & 0x3f) << 1; /* FS */
1967             /* Note that S2WLK and FSTAGE are always zero, because we don't
1968              * implement virtualization and therefore there can't be a stage 2
1969              * fault.
1970              */
1971         }
1972     } else {
1973         /* fsr is a DFSR/IFSR value for the short descriptor
1974          * translation table format (with WnR always clear).
1975          * Convert it to a 32-bit PAR.
1976          */
1977         if (!ret) {
1978             /* We do not set any attribute bits in the PAR */
1979             if (page_size == (1 << 24)
1980                 && arm_feature(env, ARM_FEATURE_V7)) {
1981                 par64 = (phys_addr & 0xff000000) | (1 << 1);
1982             } else {
1983                 par64 = phys_addr & 0xfffff000;
1984             }
1985             if (!attrs.secure) {
1986                 par64 |= (1 << 9); /* NS */
1987             }
1988         } else {
1989             par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
1990                     ((fsr & 0xf) << 1) | 1;
1991         }
1992     }
1993     return par64;
1994 }
1995
1996 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1997 {
1998     int access_type = ri->opc2 & 1;
1999     uint64_t par64;
2000     ARMMMUIdx mmu_idx;
2001     int el = arm_current_el(env);
2002     bool secure = arm_is_secure_below_el3(env);
2003
2004     switch (ri->opc2 & 6) {
2005     case 0:
2006         /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
2007         switch (el) {
2008         case 3:
2009             mmu_idx = ARMMMUIdx_S1E3;
2010             break;
2011         case 2:
2012             mmu_idx = ARMMMUIdx_S1NSE1;
2013             break;
2014         case 1:
2015             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
2016             break;
2017         default:
2018             g_assert_not_reached();
2019         }
2020         break;
2021     case 2:
2022         /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
2023         switch (el) {
2024         case 3:
2025             mmu_idx = ARMMMUIdx_S1SE0;
2026             break;
2027         case 2:
2028             mmu_idx = ARMMMUIdx_S1NSE0;
2029             break;
2030         case 1:
2031             mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
2032             break;
2033         default:
2034             g_assert_not_reached();
2035         }
2036         break;
2037     case 4:
2038         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
2039         mmu_idx = ARMMMUIdx_S12NSE1;
2040         break;
2041     case 6:
2042         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
2043         mmu_idx = ARMMMUIdx_S12NSE0;
2044         break;
2045     default:
2046         g_assert_not_reached();
2047     }
2048
2049     par64 = do_ats_write(env, value, access_type, mmu_idx);
2050
2051     A32_BANKED_CURRENT_REG_SET(env, par, par64);
2052 }
2053
2054 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
2055                         uint64_t value)
2056 {
2057     int access_type = ri->opc2 & 1;
2058     uint64_t par64;
2059
2060     par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
2061
2062     A32_BANKED_CURRENT_REG_SET(env, par, par64);
2063 }
2064
2065 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
2066                                      bool isread)
2067 {
2068     if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
2069         return CP_ACCESS_TRAP;
2070     }
2071     return CP_ACCESS_OK;
2072 }
2073
2074 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
2075                         uint64_t value)
2076 {
2077     int access_type = ri->opc2 & 1;
2078     ARMMMUIdx mmu_idx;
2079     int secure = arm_is_secure_below_el3(env);
2080
2081     switch (ri->opc2 & 6) {
2082     case 0:
2083         switch (ri->opc1) {
2084         case 0: /* AT S1E1R, AT S1E1W */
2085             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
2086             break;
2087         case 4: /* AT S1E2R, AT S1E2W */
2088             mmu_idx = ARMMMUIdx_S1E2;
2089             break;
2090         case 6: /* AT S1E3R, AT S1E3W */
2091             mmu_idx = ARMMMUIdx_S1E3;
2092             break;
2093         default:
2094             g_assert_not_reached();
2095         }
2096         break;
2097     case 2: /* AT S1E0R, AT S1E0W */
2098         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
2099         break;
2100     case 4: /* AT S12E1R, AT S12E1W */
2101         mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
2102         break;
2103     case 6: /* AT S12E0R, AT S12E0W */
2104         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
2105         break;
2106     default:
2107         g_assert_not_reached();
2108     }
2109
2110     env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
2111 }
2112 #endif
2113
2114 static const ARMCPRegInfo vapa_cp_reginfo[] = {
2115     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
2116       .access = PL1_RW, .resetvalue = 0,
2117       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
2118                              offsetoflow32(CPUARMState, cp15.par_ns) },
2119       .writefn = par_write },
2120 #ifndef CONFIG_USER_ONLY
2121     /* This underdecoding is safe because the reginfo is NO_RAW. */
2122     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
2123       .access = PL1_W, .accessfn = ats_access,
2124       .writefn = ats_write, .type = ARM_CP_NO_RAW },
2125 #endif
2126     REGINFO_SENTINEL
2127 };
2128
2129 /* Return basic MPU access permission bits.  */
2130 static uint32_t simple_mpu_ap_bits(uint32_t val)
2131 {
2132     uint32_t ret;
2133     uint32_t mask;
2134     int i;
2135     ret = 0;
2136     mask = 3;
2137     for (i = 0; i < 16; i += 2) {
2138         ret |= (val >> i) & mask;
2139         mask <<= 2;
2140     }
2141     return ret;
2142 }
2143
2144 /* Pad basic MPU access permission bits to extended format.  */
2145 static uint32_t extended_mpu_ap_bits(uint32_t val)
2146 {
2147     uint32_t ret;
2148     uint32_t mask;
2149     int i;
2150     ret = 0;
2151     mask = 3;
2152     for (i = 0; i < 16; i += 2) {
2153         ret |= (val & mask) << i;
2154         mask <<= 2;
2155     }
2156     return ret;
2157 }
2158
2159 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2160                                  uint64_t value)
2161 {
2162     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
2163 }
2164
2165 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2166 {
2167     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
2168 }
2169
2170 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2171                                  uint64_t value)
2172 {
2173     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
2174 }
2175
2176 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2177 {
2178     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
2179 }
2180
2181 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
2182 {
2183     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2184
2185     if (!u32p) {
2186         return 0;
2187     }
2188
2189     u32p += env->cp15.c6_rgnr;
2190     return *u32p;
2191 }
2192
2193 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
2194                          uint64_t value)
2195 {
2196     ARMCPU *cpu = arm_env_get_cpu(env);
2197     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2198
2199     if (!u32p) {
2200         return;
2201     }
2202
2203     u32p += env->cp15.c6_rgnr;
2204     tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
2205     *u32p = value;
2206 }
2207
2208 static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2209 {
2210     ARMCPU *cpu = arm_env_get_cpu(env);
2211     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2212
2213     if (!u32p) {
2214         return;
2215     }
2216
2217     memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
2218 }
2219
2220 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2221                               uint64_t value)
2222 {
2223     ARMCPU *cpu = arm_env_get_cpu(env);
2224     uint32_t nrgs = cpu->pmsav7_dregion;
2225
2226     if (value >= nrgs) {
2227         qemu_log_mask(LOG_GUEST_ERROR,
2228                       "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2229                       " > %" PRIu32 "\n", (uint32_t)value, nrgs);
2230         return;
2231     }
2232
2233     raw_write(env, ri, value);
2234 }
2235
2236 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
2237     { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
2238       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2239       .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
2240       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2241     { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
2242       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2243       .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
2244       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2245     { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
2246       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2247       .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
2248       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2249     { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
2250       .access = PL1_RW,
2251       .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr),
2252       .writefn = pmsav7_rgnr_write },
2253     REGINFO_SENTINEL
2254 };
2255
2256 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
2257     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2258       .access = PL1_RW, .type = ARM_CP_ALIAS,
2259       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2260       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
2261     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2262       .access = PL1_RW, .type = ARM_CP_ALIAS,
2263       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2264       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
2265     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
2266       .access = PL1_RW,
2267       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2268       .resetvalue = 0, },
2269     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
2270       .access = PL1_RW,
2271       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2272       .resetvalue = 0, },
2273     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2274       .access = PL1_RW,
2275       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
2276     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
2277       .access = PL1_RW,
2278       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
2279     /* Protection region base and size registers */
2280     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
2281       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2282       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
2283     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
2284       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2285       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
2286     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
2287       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2288       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
2289     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
2290       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2291       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
2292     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
2293       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2294       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
2295     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
2296       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2297       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
2298     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
2299       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2300       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
2301     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
2302       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2303       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
2304     REGINFO_SENTINEL
2305 };
2306
2307 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
2308                                  uint64_t value)
2309 {
2310     TCR *tcr = raw_ptr(env, ri);
2311     int maskshift = extract32(value, 0, 3);
2312
2313     if (!arm_feature(env, ARM_FEATURE_V8)) {
2314         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
2315             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2316              * using Long-desciptor translation table format */
2317             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
2318         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
2319             /* In an implementation that includes the Security Extensions
2320              * TTBCR has additional fields PD0 [4] and PD1 [5] for
2321              * Short-descriptor translation table format.
2322              */
2323             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
2324         } else {
2325             value &= TTBCR_N;
2326         }
2327     }
2328
2329     /* Update the masks corresponding to the TCR bank being written
2330      * Note that we always calculate mask and base_mask, but
2331      * they are only used for short-descriptor tables (ie if EAE is 0);
2332      * for long-descriptor tables the TCR fields are used differently
2333      * and the mask and base_mask values are meaningless.
2334      */
2335     tcr->raw_tcr = value;
2336     tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
2337     tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
2338 }
2339
2340 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2341                              uint64_t value)
2342 {
2343     ARMCPU *cpu = arm_env_get_cpu(env);
2344
2345     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2346         /* With LPAE the TTBCR could result in a change of ASID
2347          * via the TTBCR.A1 bit, so do a TLB flush.
2348          */
2349         tlb_flush(CPU(cpu), 1);
2350     }
2351     vmsa_ttbcr_raw_write(env, ri, value);
2352 }
2353
2354 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2355 {
2356     TCR *tcr = raw_ptr(env, ri);
2357
2358     /* Reset both the TCR as well as the masks corresponding to the bank of
2359      * the TCR being reset.
2360      */
2361     tcr->raw_tcr = 0;
2362     tcr->mask = 0;
2363     tcr->base_mask = 0xffffc000u;
2364 }
2365
2366 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2367                                uint64_t value)
2368 {
2369     ARMCPU *cpu = arm_env_get_cpu(env);
2370     TCR *tcr = raw_ptr(env, ri);
2371
2372     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2373     tlb_flush(CPU(cpu), 1);
2374     tcr->raw_tcr = value;
2375 }
2376
2377 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2378                             uint64_t value)
2379 {
2380     /* 64 bit accesses to the TTBRs can change the ASID and so we
2381      * must flush the TLB.
2382      */
2383     if (cpreg_field_is_64bit(ri)) {
2384         ARMCPU *cpu = arm_env_get_cpu(env);
2385
2386         tlb_flush(CPU(cpu), 1);
2387     }
2388     raw_write(env, ri, value);
2389 }
2390
2391 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2392                         uint64_t value)
2393 {
2394     ARMCPU *cpu = arm_env_get_cpu(env);
2395     CPUState *cs = CPU(cpu);
2396
2397     /* Accesses to VTTBR may change the VMID so we must flush the TLB.  */
2398     if (raw_read(env, ri) != value) {
2399         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2400                             ARMMMUIdx_S2NS, -1);
2401         raw_write(env, ri, value);
2402     }
2403 }
2404
2405 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
2406     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2407       .access = PL1_RW, .type = ARM_CP_ALIAS,
2408       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
2409                              offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
2410     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2411       .access = PL1_RW, .resetvalue = 0,
2412       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
2413                              offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
2414     { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
2415       .access = PL1_RW, .resetvalue = 0,
2416       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
2417                              offsetof(CPUARMState, cp15.dfar_ns) } },
2418     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
2419       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
2420       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
2421       .resetvalue = 0, },
2422     REGINFO_SENTINEL
2423 };
2424
2425 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
2426     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
2427       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
2428       .access = PL1_RW,
2429       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
2430     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
2431       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
2432       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2433       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2434                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
2435     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
2436       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
2437       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2438       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2439                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
2440     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
2441       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2442       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
2443       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2444       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
2445     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2446       .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
2447       .raw_writefn = vmsa_ttbcr_raw_write,
2448       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
2449                              offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
2450     REGINFO_SENTINEL
2451 };
2452
2453 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
2454                                 uint64_t value)
2455 {
2456     env->cp15.c15_ticonfig = value & 0xe7;
2457     /* The OS_TYPE bit in this register changes the reported CPUID! */
2458     env->cp15.c0_cpuid = (value & (1 << 5)) ?
2459         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
2460 }
2461
2462 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2463                                 uint64_t value)
2464 {
2465     env->cp15.c15_threadid = value & 0xffff;
2466 }
2467
2468 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
2469                            uint64_t value)
2470 {
2471     /* Wait-for-interrupt (deprecated) */
2472     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
2473 }
2474
2475 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
2476                                   uint64_t value)
2477 {
2478     /* On OMAP there are registers indicating the max/min index of dcache lines
2479      * containing a dirty line; cache flush operations have to reset these.
2480      */
2481     env->cp15.c15_i_max = 0x000;
2482     env->cp15.c15_i_min = 0xff0;
2483 }
2484
2485 static const ARMCPRegInfo omap_cp_reginfo[] = {
2486     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
2487       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
2488       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
2489       .resetvalue = 0, },
2490     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2491       .access = PL1_RW, .type = ARM_CP_NOP },
2492     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2493       .access = PL1_RW,
2494       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
2495       .writefn = omap_ticonfig_write },
2496     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
2497       .access = PL1_RW,
2498       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
2499     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
2500       .access = PL1_RW, .resetvalue = 0xff0,
2501       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
2502     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
2503       .access = PL1_RW,
2504       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
2505       .writefn = omap_threadid_write },
2506     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
2507       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2508       .type = ARM_CP_NO_RAW,
2509       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
2510     /* TODO: Peripheral port remap register:
2511      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2512      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2513      * when MMU is off.
2514      */
2515     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
2516       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
2517       .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
2518       .writefn = omap_cachemaint_write },
2519     { .name = "C9", .cp = 15, .crn = 9,
2520       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
2521       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
2522     REGINFO_SENTINEL
2523 };
2524
2525 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2526                               uint64_t value)
2527 {
2528     env->cp15.c15_cpar = value & 0x3fff;
2529 }
2530
2531 static const ARMCPRegInfo xscale_cp_reginfo[] = {
2532     { .name = "XSCALE_CPAR",
2533       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2534       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
2535       .writefn = xscale_cpar_write, },
2536     { .name = "XSCALE_AUXCR",
2537       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
2538       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
2539       .resetvalue = 0, },
2540     /* XScale specific cache-lockdown: since we have no cache we NOP these
2541      * and hope the guest does not really rely on cache behaviour.
2542      */
2543     { .name = "XSCALE_LOCK_ICACHE_LINE",
2544       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2545       .access = PL1_W, .type = ARM_CP_NOP },
2546     { .name = "XSCALE_UNLOCK_ICACHE",
2547       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2548       .access = PL1_W, .type = ARM_CP_NOP },
2549     { .name = "XSCALE_DCACHE_LOCK",
2550       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
2551       .access = PL1_RW, .type = ARM_CP_NOP },
2552     { .name = "XSCALE_UNLOCK_DCACHE",
2553       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
2554       .access = PL1_W, .type = ARM_CP_NOP },
2555     REGINFO_SENTINEL
2556 };
2557
2558 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2559     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2560      * implementation of this implementation-defined space.
2561      * Ideally this should eventually disappear in favour of actually
2562      * implementing the correct behaviour for all cores.
2563      */
2564     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2565       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2566       .access = PL1_RW,
2567       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2568       .resetvalue = 0 },
2569     REGINFO_SENTINEL
2570 };
2571
2572 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2573     /* Cache status: RAZ because we have no cache so it's always clean */
2574     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2575       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2576       .resetvalue = 0 },
2577     REGINFO_SENTINEL
2578 };
2579
2580 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2581     /* We never have a a block transfer operation in progress */
2582     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2583       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2584       .resetvalue = 0 },
2585     /* The cache ops themselves: these all NOP for QEMU */
2586     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2587       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2588     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2589       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2590     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2591       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2592     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2593       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2594     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2595       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2596     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2597       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2598     REGINFO_SENTINEL
2599 };
2600
2601 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2602     /* The cache test-and-clean instructions always return (1 << 30)
2603      * to indicate that there are no dirty cache lines.
2604      */
2605     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2606       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2607       .resetvalue = (1 << 30) },
2608     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2609       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2610       .resetvalue = (1 << 30) },
2611     REGINFO_SENTINEL
2612 };
2613
2614 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2615     /* Ignore ReadBuffer accesses */
2616     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2617       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2618       .access = PL1_RW, .resetvalue = 0,
2619       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2620     REGINFO_SENTINEL
2621 };
2622
2623 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2624 {
2625     ARMCPU *cpu = arm_env_get_cpu(env);
2626     unsigned int cur_el = arm_current_el(env);
2627     bool secure = arm_is_secure(env);
2628
2629     if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2630         return env->cp15.vpidr_el2;
2631     }
2632     return raw_read(env, ri);
2633 }
2634
2635 static uint64_t mpidr_read_val(CPUARMState *env)
2636 {
2637     ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
2638     uint64_t mpidr = cpu->mp_affinity;
2639
2640     if (arm_feature(env, ARM_FEATURE_V7MP)) {
2641         mpidr |= (1U << 31);
2642         /* Cores which are uniprocessor (non-coherent)
2643          * but still implement the MP extensions set
2644          * bit 30. (For instance, Cortex-R5).
2645          */
2646         if (cpu->mp_is_up) {
2647             mpidr |= (1u << 30);
2648         }
2649     }
2650     return mpidr;
2651 }
2652
2653 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2654 {
2655     unsigned int cur_el = arm_current_el(env);
2656     bool secure = arm_is_secure(env);
2657
2658     if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2659         return env->cp15.vmpidr_el2;
2660     }
2661     return mpidr_read_val(env);
2662 }
2663
2664 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2665     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2666       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2667       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2668     REGINFO_SENTINEL
2669 };
2670
2671 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2672     /* NOP AMAIR0/1 */
2673     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2674       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2675       .access = PL1_RW, .type = ARM_CP_CONST,
2676       .resetvalue = 0 },
2677     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2678     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2679       .access = PL1_RW, .type = ARM_CP_CONST,
2680       .resetvalue = 0 },
2681     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2682       .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2683       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2684                              offsetof(CPUARMState, cp15.par_ns)} },
2685     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2686       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2687       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2688                              offsetof(CPUARMState, cp15.ttbr0_ns) },
2689       .writefn = vmsa_ttbr_write, },
2690     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2691       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2692       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2693                              offsetof(CPUARMState, cp15.ttbr1_ns) },
2694       .writefn = vmsa_ttbr_write, },
2695     REGINFO_SENTINEL
2696 };
2697
2698 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2699 {
2700     return vfp_get_fpcr(env);
2701 }
2702
2703 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2704                             uint64_t value)
2705 {
2706     vfp_set_fpcr(env, value);
2707 }
2708
2709 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2710 {
2711     return vfp_get_fpsr(env);
2712 }
2713
2714 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2715                             uint64_t value)
2716 {
2717     vfp_set_fpsr(env, value);
2718 }
2719
2720 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri,
2721                                        bool isread)
2722 {
2723     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2724         return CP_ACCESS_TRAP;
2725     }
2726     return CP_ACCESS_OK;
2727 }
2728
2729 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2730                             uint64_t value)
2731 {
2732     env->daif = value & PSTATE_DAIF;
2733 }
2734
2735 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2736                                           const ARMCPRegInfo *ri,
2737                                           bool isread)
2738 {
2739     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2740      * SCTLR_EL1.UCI is set.
2741      */
2742     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2743         return CP_ACCESS_TRAP;
2744     }
2745     return CP_ACCESS_OK;
2746 }
2747
2748 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2749  * Page D4-1736 (DDI0487A.b)
2750  */
2751
2752 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2753                                     uint64_t value)
2754 {
2755     ARMCPU *cpu = arm_env_get_cpu(env);
2756     CPUState *cs = CPU(cpu);
2757
2758     if (arm_is_secure_below_el3(env)) {
2759         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2760     } else {
2761         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2762     }
2763 }
2764
2765 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2766                                       uint64_t value)
2767 {
2768     bool sec = arm_is_secure_below_el3(env);
2769     CPUState *other_cs;
2770
2771     CPU_FOREACH(other_cs) {
2772         if (sec) {
2773             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2774         } else {
2775             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2776                                 ARMMMUIdx_S12NSE0, -1);
2777         }
2778     }
2779 }
2780
2781 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2782                                   uint64_t value)
2783 {
2784     /* Note that the 'ALL' scope must invalidate both stage 1 and
2785      * stage 2 translations, whereas most other scopes only invalidate
2786      * stage 1 translations.
2787      */
2788     ARMCPU *cpu = arm_env_get_cpu(env);
2789     CPUState *cs = CPU(cpu);
2790
2791     if (arm_is_secure_below_el3(env)) {
2792         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2793     } else {
2794         if (arm_feature(env, ARM_FEATURE_EL2)) {
2795             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2796                                 ARMMMUIdx_S2NS, -1);
2797         } else {
2798             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2799         }
2800     }
2801 }
2802
2803 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2804                                   uint64_t value)
2805 {
2806     ARMCPU *cpu = arm_env_get_cpu(env);
2807     CPUState *cs = CPU(cpu);
2808
2809     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1);
2810 }
2811
2812 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2813                                   uint64_t value)
2814 {
2815     ARMCPU *cpu = arm_env_get_cpu(env);
2816     CPUState *cs = CPU(cpu);
2817
2818     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1);
2819 }
2820
2821 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2822                                     uint64_t value)
2823 {
2824     /* Note that the 'ALL' scope must invalidate both stage 1 and
2825      * stage 2 translations, whereas most other scopes only invalidate
2826      * stage 1 translations.
2827      */
2828     bool sec = arm_is_secure_below_el3(env);
2829     bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
2830     CPUState *other_cs;
2831
2832     CPU_FOREACH(other_cs) {
2833         if (sec) {
2834             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2835         } else if (has_el2) {
2836             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2837                                 ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1);
2838         } else {
2839             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2840                                 ARMMMUIdx_S12NSE0, -1);
2841         }
2842     }
2843 }
2844
2845 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2846                                     uint64_t value)
2847 {
2848     CPUState *other_cs;
2849
2850     CPU_FOREACH(other_cs) {
2851         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1);
2852     }
2853 }
2854
2855 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2856                                     uint64_t value)
2857 {
2858     CPUState *other_cs;
2859
2860     CPU_FOREACH(other_cs) {
2861         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1);
2862     }
2863 }
2864
2865 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2866                                  uint64_t value)
2867 {
2868     /* Invalidate by VA, EL1&0 (AArch64 version).
2869      * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
2870      * since we don't support flush-for-specific-ASID-only or
2871      * flush-last-level-only.
2872      */
2873     ARMCPU *cpu = arm_env_get_cpu(env);
2874     CPUState *cs = CPU(cpu);
2875     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2876
2877     if (arm_is_secure_below_el3(env)) {
2878         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1,
2879                                  ARMMMUIdx_S1SE0, -1);
2880     } else {
2881         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1,
2882                                  ARMMMUIdx_S12NSE0, -1);
2883     }
2884 }
2885
2886 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2887                                  uint64_t value)
2888 {
2889     /* Invalidate by VA, EL2
2890      * Currently handles both VAE2 and VALE2, since we don't support
2891      * flush-last-level-only.
2892      */
2893     ARMCPU *cpu = arm_env_get_cpu(env);
2894     CPUState *cs = CPU(cpu);
2895     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2896
2897     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1);
2898 }
2899
2900 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2901                                  uint64_t value)
2902 {
2903     /* Invalidate by VA, EL3
2904      * Currently handles both VAE3 and VALE3, since we don't support
2905      * flush-last-level-only.
2906      */
2907     ARMCPU *cpu = arm_env_get_cpu(env);
2908     CPUState *cs = CPU(cpu);
2909     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2910
2911     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1);
2912 }
2913
2914 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2915                                    uint64_t value)
2916 {
2917     bool sec = arm_is_secure_below_el3(env);
2918     CPUState *other_cs;
2919     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2920
2921     CPU_FOREACH(other_cs) {
2922         if (sec) {
2923             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1,
2924                                      ARMMMUIdx_S1SE0, -1);
2925         } else {
2926             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1,
2927                                      ARMMMUIdx_S12NSE0, -1);
2928         }
2929     }
2930 }
2931
2932 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2933                                    uint64_t value)
2934 {
2935     CPUState *other_cs;
2936     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2937
2938     CPU_FOREACH(other_cs) {
2939         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
2940     }
2941 }
2942
2943 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2944                                    uint64_t value)
2945 {
2946     CPUState *other_cs;
2947     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2948
2949     CPU_FOREACH(other_cs) {
2950         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1);
2951     }
2952 }
2953
2954 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2955                                     uint64_t value)
2956 {
2957     /* Invalidate by IPA. This has to invalidate any structures that
2958      * contain only stage 2 translation information, but does not need
2959      * to apply to structures that contain combined stage 1 and stage 2
2960      * translation information.
2961      * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
2962      */
2963     ARMCPU *cpu = arm_env_get_cpu(env);
2964     CPUState *cs = CPU(cpu);
2965     uint64_t pageaddr;
2966
2967     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2968         return;
2969     }
2970
2971     pageaddr = sextract64(value << 12, 0, 48);
2972
2973     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);
2974 }
2975
2976 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2977                                       uint64_t value)
2978 {
2979     CPUState *other_cs;
2980     uint64_t pageaddr;
2981
2982     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2983         return;
2984     }
2985
2986     pageaddr = sextract64(value << 12, 0, 48);
2987
2988     CPU_FOREACH(other_cs) {
2989         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);
2990     }
2991 }
2992
2993 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
2994                                       bool isread)
2995 {
2996     /* We don't implement EL2, so the only control on DC ZVA is the
2997      * bit in the SCTLR which can prohibit access for EL0.
2998      */
2999     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
3000         return CP_ACCESS_TRAP;
3001     }
3002     return CP_ACCESS_OK;
3003 }
3004
3005 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
3006 {
3007     ARMCPU *cpu = arm_env_get_cpu(env);
3008     int dzp_bit = 1 << 4;
3009
3010     /* DZP indicates whether DC ZVA access is allowed */
3011     if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) {
3012         dzp_bit = 0;
3013     }
3014     return cpu->dcz_blocksize | dzp_bit;
3015 }
3016
3017 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
3018                                     bool isread)
3019 {
3020     if (!(env->pstate & PSTATE_SP)) {
3021         /* Access to SP_EL0 is undefined if it's being used as
3022          * the stack pointer.
3023          */
3024         return CP_ACCESS_TRAP_UNCATEGORIZED;
3025     }
3026     return CP_ACCESS_OK;
3027 }
3028
3029 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
3030 {
3031     return env->pstate & PSTATE_SP;
3032 }
3033
3034 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
3035 {
3036     update_spsel(env, val);
3037 }
3038
3039 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3040                         uint64_t value)
3041 {
3042     ARMCPU *cpu = arm_env_get_cpu(env);
3043
3044     if (raw_read(env, ri) == value) {
3045         /* Skip the TLB flush if nothing actually changed; Linux likes
3046          * to do a lot of pointless SCTLR writes.
3047          */
3048         return;
3049     }
3050
3051     raw_write(env, ri, value);
3052     /* ??? Lots of these bits are not implemented.  */
3053     /* This may enable/disable the MMU, so do a TLB flush.  */
3054     tlb_flush(CPU(cpu), 1);
3055 }
3056
3057 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
3058                                      bool isread)
3059 {
3060     if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
3061         return CP_ACCESS_TRAP_FP_EL2;
3062     }
3063     if (env->cp15.cptr_el[3] & CPTR_TFP) {
3064         return CP_ACCESS_TRAP_FP_EL3;
3065     }
3066     return CP_ACCESS_OK;
3067 }
3068
3069 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3070                        uint64_t value)
3071 {
3072     env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
3073 }
3074
3075 static const ARMCPRegInfo v8_cp_reginfo[] = {
3076     /* Minimal set of EL0-visible registers. This will need to be expanded
3077      * significantly for system emulation of AArch64 CPUs.
3078      */
3079     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
3080       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
3081       .access = PL0_RW, .type = ARM_CP_NZCV },
3082     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
3083       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
3084       .type = ARM_CP_NO_RAW,
3085       .access = PL0_RW, .accessfn = aa64_daif_access,
3086       .fieldoffset = offsetof(CPUARMState, daif),
3087       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
3088     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
3089       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
3090       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
3091     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
3092       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
3093       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
3094     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
3095       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
3096       .access = PL0_R, .type = ARM_CP_NO_RAW,
3097       .readfn = aa64_dczid_read },
3098     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
3099       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
3100       .access = PL0_W, .type = ARM_CP_DC_ZVA,
3101 #ifndef CONFIG_USER_ONLY
3102       /* Avoid overhead of an access check that always passes in user-mode */
3103       .accessfn = aa64_zva_access,
3104 #endif
3105     },
3106     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
3107       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
3108       .access = PL1_R, .type = ARM_CP_CURRENTEL },
3109     /* Cache ops: all NOPs since we don't emulate caches */
3110     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
3111       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3112       .access = PL1_W, .type = ARM_CP_NOP },
3113     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
3114       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3115       .access = PL1_W, .type = ARM_CP_NOP },
3116     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
3117       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
3118       .access = PL0_W, .type = ARM_CP_NOP,
3119       .accessfn = aa64_cacheop_access },
3120     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
3121       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3122       .access = PL1_W, .type = ARM_CP_NOP },
3123     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
3124       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3125       .access = PL1_W, .type = ARM_CP_NOP },
3126     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
3127       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
3128       .access = PL0_W, .type = ARM_CP_NOP,
3129       .accessfn = aa64_cacheop_access },
3130     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
3131       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3132       .access = PL1_W, .type = ARM_CP_NOP },
3133     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
3134       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
3135       .access = PL0_W, .type = ARM_CP_NOP,
3136       .accessfn = aa64_cacheop_access },
3137     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
3138       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
3139       .access = PL0_W, .type = ARM_CP_NOP,
3140       .accessfn = aa64_cacheop_access },
3141     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
3142       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3143       .access = PL1_W, .type = ARM_CP_NOP },
3144     /* TLBI operations */
3145     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
3146       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
3147       .access = PL1_W, .type = ARM_CP_NO_RAW,
3148       .writefn = tlbi_aa64_vmalle1is_write },
3149     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
3150       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
3151       .access = PL1_W, .type = ARM_CP_NO_RAW,
3152       .writefn = tlbi_aa64_vae1is_write },
3153     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
3154       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
3155       .access = PL1_W, .type = ARM_CP_NO_RAW,
3156       .writefn = tlbi_aa64_vmalle1is_write },
3157     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
3158       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
3159       .access = PL1_W, .type = ARM_CP_NO_RAW,
3160       .writefn = tlbi_aa64_vae1is_write },
3161     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
3162       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3163       .access = PL1_W, .type = ARM_CP_NO_RAW,
3164       .writefn = tlbi_aa64_vae1is_write },
3165     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
3166       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3167       .access = PL1_W, .type = ARM_CP_NO_RAW,
3168       .writefn = tlbi_aa64_vae1is_write },
3169     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
3170       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
3171       .access = PL1_W, .type = ARM_CP_NO_RAW,
3172       .writefn = tlbi_aa64_vmalle1_write },
3173     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
3174       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
3175       .access = PL1_W, .type = ARM_CP_NO_RAW,
3176       .writefn = tlbi_aa64_vae1_write },
3177     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
3178       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
3179       .access = PL1_W, .type = ARM_CP_NO_RAW,
3180       .writefn = tlbi_aa64_vmalle1_write },
3181     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
3182       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
3183       .access = PL1_W, .type = ARM_CP_NO_RAW,
3184       .writefn = tlbi_aa64_vae1_write },
3185     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
3186       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3187       .access = PL1_W, .type = ARM_CP_NO_RAW,
3188       .writefn = tlbi_aa64_vae1_write },
3189     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
3190       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3191       .access = PL1_W, .type = ARM_CP_NO_RAW,
3192       .writefn = tlbi_aa64_vae1_write },
3193     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
3194       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
3195       .access = PL2_W, .type = ARM_CP_NO_RAW,
3196       .writefn = tlbi_aa64_ipas2e1is_write },
3197     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
3198       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
3199       .access = PL2_W, .type = ARM_CP_NO_RAW,
3200       .writefn = tlbi_aa64_ipas2e1is_write },
3201     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
3202       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
3203       .access = PL2_W, .type = ARM_CP_NO_RAW,
3204       .writefn = tlbi_aa64_alle1is_write },
3205     { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
3206       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
3207       .access = PL2_W, .type = ARM_CP_NO_RAW,
3208       .writefn = tlbi_aa64_alle1is_write },
3209     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
3210       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
3211       .access = PL2_W, .type = ARM_CP_NO_RAW,
3212       .writefn = tlbi_aa64_ipas2e1_write },
3213     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
3214       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
3215       .access = PL2_W, .type = ARM_CP_NO_RAW,
3216       .writefn = tlbi_aa64_ipas2e1_write },
3217     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
3218       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
3219       .access = PL2_W, .type = ARM_CP_NO_RAW,
3220       .writefn = tlbi_aa64_alle1_write },
3221     { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
3222       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
3223       .access = PL2_W, .type = ARM_CP_NO_RAW,
3224       .writefn = tlbi_aa64_alle1is_write },
3225 #ifndef CONFIG_USER_ONLY
3226     /* 64 bit address translation operations */
3227     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
3228       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
3229       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3230     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
3231       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
3232       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3233     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
3234       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
3235       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3236     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
3237       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
3238       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3239     { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
3240       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
3241       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3242     { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
3243       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
3244       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3245     { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
3246       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
3247       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3248     { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
3249       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
3250       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3251     /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3252     { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
3253       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
3254       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3255     { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
3256       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
3257       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3258     { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
3259       .type = ARM_CP_ALIAS,
3260       .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
3261       .access = PL1_RW, .resetvalue = 0,
3262       .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
3263       .writefn = par_write },
3264 #endif
3265     /* TLB invalidate last level of translation table walk */
3266     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3267       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
3268     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3269       .type = ARM_CP_NO_RAW, .access = PL1_W,
3270       .writefn = tlbimvaa_is_write },
3271     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3272       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
3273     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3274       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
3275     /* 32 bit cache operations */
3276     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3277       .type = ARM_CP_NOP, .access = PL1_W },
3278     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
3279       .type = ARM_CP_NOP, .access = PL1_W },
3280     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3281       .type = ARM_CP_NOP, .access = PL1_W },
3282     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
3283       .type = ARM_CP_NOP, .access = PL1_W },
3284     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
3285       .type = ARM_CP_NOP, .access = PL1_W },
3286     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
3287       .type = ARM_CP_NOP, .access = PL1_W },
3288     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3289       .type = ARM_CP_NOP, .access = PL1_W },
3290     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3291       .type = ARM_CP_NOP, .access = PL1_W },
3292     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
3293       .type = ARM_CP_NOP, .access = PL1_W },
3294     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3295       .type = ARM_CP_NOP, .access = PL1_W },
3296     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
3297       .type = ARM_CP_NOP, .access = PL1_W },
3298     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
3299       .type = ARM_CP_NOP, .access = PL1_W },
3300     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3301       .type = ARM_CP_NOP, .access = PL1_W },
3302     /* MMU Domain access control / MPU write buffer control */
3303     { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
3304       .access = PL1_RW, .resetvalue = 0,
3305       .writefn = dacr_write, .raw_writefn = raw_write,
3306       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
3307                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
3308     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
3309       .type = ARM_CP_ALIAS,
3310       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
3311       .access = PL1_RW,
3312       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
3313     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
3314       .type = ARM_CP_ALIAS,
3315       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
3316       .access = PL1_RW,
3317       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
3318     /* We rely on the access checks not allowing the guest to write to the
3319      * state field when SPSel indicates that it's being used as the stack
3320      * pointer.
3321      */
3322     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
3323       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
3324       .access = PL1_RW, .accessfn = sp_el0_access,
3325       .type = ARM_CP_ALIAS,
3326       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
3327     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
3328       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
3329       .access = PL2_RW, .type = ARM_CP_ALIAS,
3330       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
3331     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
3332       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
3333       .type = ARM_CP_NO_RAW,
3334       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
3335     { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
3336       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
3337       .type = ARM_CP_ALIAS,
3338       .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
3339       .access = PL2_RW, .accessfn = fpexc32_access },
3340     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
3341       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
3342       .access = PL2_RW, .resetvalue = 0,
3343       .writefn = dacr_write, .raw_writefn = raw_write,
3344       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
3345     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
3346       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
3347       .access = PL2_RW, .resetvalue = 0,
3348       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
3349     { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
3350       .type = ARM_CP_ALIAS,
3351       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
3352       .access = PL2_RW,
3353       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
3354     { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
3355       .type = ARM_CP_ALIAS,
3356       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
3357       .access = PL2_RW,
3358       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
3359     { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
3360       .type = ARM_CP_ALIAS,
3361       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
3362       .access = PL2_RW,
3363       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
3364     { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
3365       .type = ARM_CP_ALIAS,
3366       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
3367       .access = PL2_RW,
3368       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
3369     { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
3370       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
3371       .resetvalue = 0,
3372       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
3373     { .name = "SDCR", .type = ARM_CP_ALIAS,
3374       .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
3375       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3376       .writefn = sdcr_write,
3377       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
3378     REGINFO_SENTINEL
3379 };
3380
3381 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
3382 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
3383     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3384       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3385       .access = PL2_RW,
3386       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3387     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3388       .type = ARM_CP_NO_RAW,
3389       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3390       .access = PL2_RW,
3391       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3392     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3393       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3394       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3395     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3396       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3397       .access = PL2_RW, .type = ARM_CP_CONST,
3398       .resetvalue = 0 },
3399     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3400       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3401       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3402     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3403       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3404       .access = PL2_RW, .type = ARM_CP_CONST,
3405       .resetvalue = 0 },
3406     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3407       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3408       .access = PL2_RW, .type = ARM_CP_CONST,
3409       .resetvalue = 0 },
3410     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3411       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3412       .access = PL2_RW, .type = ARM_CP_CONST,
3413       .resetvalue = 0 },
3414     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3415       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3416       .access = PL2_RW, .type = ARM_CP_CONST,
3417       .resetvalue = 0 },
3418     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3419       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3420       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3421     { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
3422       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3423       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3424       .type = ARM_CP_CONST, .resetvalue = 0 },
3425     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3426       .cp = 15, .opc1 = 6, .crm = 2,
3427       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3428       .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
3429     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3430       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3431       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3432     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3433       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3434       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3435     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3436       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3437       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3438     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3439       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3440       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3441     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3442       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3443       .resetvalue = 0 },
3444     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3445       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3446       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3447     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3448       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3449       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3450     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3451       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3452       .resetvalue = 0 },
3453     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3454       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3455       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3456     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3457       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3458       .resetvalue = 0 },
3459     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3460       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3461       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3462     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3463       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3464       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3465     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3466       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3467       .access = PL2_RW, .accessfn = access_tda,
3468       .type = ARM_CP_CONST, .resetvalue = 0 },
3469     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
3470       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3471       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3472       .type = ARM_CP_CONST, .resetvalue = 0 },
3473     REGINFO_SENTINEL
3474 };
3475
3476 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3477 {
3478     ARMCPU *cpu = arm_env_get_cpu(env);
3479     uint64_t valid_mask = HCR_MASK;
3480
3481     if (arm_feature(env, ARM_FEATURE_EL3)) {
3482         valid_mask &= ~HCR_HCD;
3483     } else {
3484         valid_mask &= ~HCR_TSC;
3485     }
3486
3487     /* Clear RES0 bits.  */
3488     value &= valid_mask;
3489
3490     /* These bits change the MMU setup:
3491      * HCR_VM enables stage 2 translation
3492      * HCR_PTW forbids certain page-table setups
3493      * HCR_DC Disables stage1 and enables stage2 translation
3494      */
3495     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
3496         tlb_flush(CPU(cpu), 1);
3497     }
3498     raw_write(env, ri, value);
3499 }
3500
3501 static const ARMCPRegInfo el2_cp_reginfo[] = {
3502     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3503       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3504       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
3505       .writefn = hcr_write },
3506     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
3507       .type = ARM_CP_ALIAS,
3508       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
3509       .access = PL2_RW,
3510       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
3511     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
3512       .type = ARM_CP_ALIAS,
3513       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
3514       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
3515     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
3516       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
3517       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
3518     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
3519       .type = ARM_CP_ALIAS,
3520       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
3521       .access = PL2_RW,
3522       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
3523     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3524       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3525       .access = PL2_RW, .writefn = vbar_write,
3526       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
3527       .resetvalue = 0 },
3528     { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
3529       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
3530       .access = PL3_RW, .type = ARM_CP_ALIAS,
3531       .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
3532     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3533       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3534       .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
3535       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
3536     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3537       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3538       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
3539       .resetvalue = 0 },
3540     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3541       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3542       .access = PL2_RW, .type = ARM_CP_ALIAS,
3543       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
3544     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3545       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3546       .access = PL2_RW, .type = ARM_CP_CONST,
3547       .resetvalue = 0 },
3548     /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3549     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3550       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3551       .access = PL2_RW, .type = ARM_CP_CONST,
3552       .resetvalue = 0 },
3553     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3554       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3555       .access = PL2_RW, .type = ARM_CP_CONST,
3556       .resetvalue = 0 },
3557     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3558       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3559       .access = PL2_RW, .type = ARM_CP_CONST,
3560       .resetvalue = 0 },
3561     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3562       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3563       .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
3564       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3565       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
3566     { .name = "VTCR", .state = ARM_CP_STATE_AA32,
3567       .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3568       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3569       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3570     { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
3571       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3572       .access = PL2_RW, .type = ARM_CP_ALIAS,
3573       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3574     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3575       .cp = 15, .opc1 = 6, .crm = 2,
3576       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3577       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3578       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
3579       .writefn = vttbr_write },
3580     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3581       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3582       .access = PL2_RW, .writefn = vttbr_write,
3583       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
3584     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3585       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3586       .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3587       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
3588     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3589       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3590       .access = PL2_RW, .resetvalue = 0,
3591       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
3592     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3593       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3594       .access = PL2_RW, .resetvalue = 0,
3595       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3596     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3597       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3598       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3599     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
3600       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
3601       .type = ARM_CP_NO_RAW, .access = PL2_W,
3602       .writefn = tlbi_aa64_alle2_write },
3603     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
3604       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
3605       .type = ARM_CP_NO_RAW, .access = PL2_W,
3606       .writefn = tlbi_aa64_vae2_write },
3607     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
3608       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
3609       .access = PL2_W, .type = ARM_CP_NO_RAW,
3610       .writefn = tlbi_aa64_vae2_write },
3611     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
3612       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
3613       .access = PL2_W, .type = ARM_CP_NO_RAW,
3614       .writefn = tlbi_aa64_alle2is_write },
3615     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
3616       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
3617       .type = ARM_CP_NO_RAW, .access = PL2_W,
3618       .writefn = tlbi_aa64_vae2is_write },
3619     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
3620       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
3621       .access = PL2_W, .type = ARM_CP_NO_RAW,
3622       .writefn = tlbi_aa64_vae2is_write },
3623 #ifndef CONFIG_USER_ONLY
3624     /* Unlike the other EL2-related AT operations, these must
3625      * UNDEF from EL3 if EL2 is not implemented, which is why we
3626      * define them here rather than with the rest of the AT ops.
3627      */
3628     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
3629       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3630       .access = PL2_W, .accessfn = at_s1e2_access,
3631       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3632     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
3633       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3634       .access = PL2_W, .accessfn = at_s1e2_access,
3635       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3636     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3637      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3638      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3639      * to behave as if SCR.NS was 1.
3640      */
3641     { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3642       .access = PL2_W,
3643       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3644     { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3645       .access = PL2_W,
3646       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3647     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3648       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3649       /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3650        * reset values as IMPDEF. We choose to reset to 3 to comply with
3651        * both ARMv7 and ARMv8.
3652        */
3653       .access = PL2_RW, .resetvalue = 3,
3654       .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
3655     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3656       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3657       .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
3658       .writefn = gt_cntvoff_write,
3659       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3660     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3661       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
3662       .writefn = gt_cntvoff_write,
3663       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3664     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3665       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3666       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3667       .type = ARM_CP_IO, .access = PL2_RW,
3668       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3669     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3670       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3671       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
3672       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3673     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3674       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3675       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
3676       .resetfn = gt_hyp_timer_reset,
3677       .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
3678     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3679       .type = ARM_CP_IO,
3680       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3681       .access = PL2_RW,
3682       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
3683       .resetvalue = 0,
3684       .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
3685 #endif
3686     /* The only field of MDCR_EL2 that has a defined architectural reset value
3687      * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
3688      * don't impelment any PMU event counters, so using zero as a reset
3689      * value for MDCR_EL2 is okay
3690      */
3691     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3692       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3693       .access = PL2_RW, .resetvalue = 0,
3694       .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
3695     { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
3696       .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3697       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3698       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3699     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
3700       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3701       .access = PL2_RW,
3702       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3703     REGINFO_SENTINEL
3704 };
3705
3706 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
3707                                    bool isread)
3708 {
3709     /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
3710      * At Secure EL1 it traps to EL3.
3711      */
3712     if (arm_current_el(env) == 3) {
3713         return CP_ACCESS_OK;
3714     }
3715     if (arm_is_secure_below_el3(env)) {
3716         return CP_ACCESS_TRAP_EL3;
3717     }
3718     /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
3719     if (isread) {
3720         return CP_ACCESS_OK;
3721     }
3722     return CP_ACCESS_TRAP_UNCATEGORIZED;
3723 }
3724
3725 static const ARMCPRegInfo el3_cp_reginfo[] = {
3726     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
3727       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
3728       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
3729       .resetvalue = 0, .writefn = scr_write },
3730     { .name = "SCR",  .type = ARM_CP_ALIAS,
3731       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
3732       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3733       .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
3734       .writefn = scr_write },
3735     { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
3736       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
3737       .access = PL3_RW, .resetvalue = 0,
3738       .fieldoffset = offsetof(CPUARMState, cp15.sder) },
3739     { .name = "SDER",
3740       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
3741       .access = PL3_RW, .resetvalue = 0,
3742       .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
3743     { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
3744       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3745       .writefn = vbar_write, .resetvalue = 0,
3746       .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
3747     { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
3748       .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */
3749       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
3750       .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3751       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },
3752     { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
3753       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
3754       .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
3755       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
3756     { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
3757       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
3758       .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
3759       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3760       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
3761     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
3762       .type = ARM_CP_ALIAS,
3763       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
3764       .access = PL3_RW,
3765       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
3766     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
3767       .type = ARM_CP_ALIAS,
3768       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
3769       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
3770     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
3771       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
3772       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
3773     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
3774       .type = ARM_CP_ALIAS,
3775       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
3776       .access = PL3_RW,
3777       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
3778     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
3779       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
3780       .access = PL3_RW, .writefn = vbar_write,
3781       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
3782       .resetvalue = 0 },
3783     { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
3784       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
3785       .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
3786       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
3787     { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
3788       .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
3789       .access = PL3_RW, .resetvalue = 0,
3790       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
3791     { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
3792       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
3793       .access = PL3_RW, .type = ARM_CP_CONST,
3794       .resetvalue = 0 },
3795     { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
3796       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
3797       .access = PL3_RW, .type = ARM_CP_CONST,
3798       .resetvalue = 0 },
3799     { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
3800       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
3801       .access = PL3_RW, .type = ARM_CP_CONST,
3802       .resetvalue = 0 },
3803     { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
3804       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
3805       .access = PL3_W, .type = ARM_CP_NO_RAW,
3806       .writefn = tlbi_aa64_alle3is_write },
3807     { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
3808       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
3809       .access = PL3_W, .type = ARM_CP_NO_RAW,
3810       .writefn = tlbi_aa64_vae3is_write },
3811     { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
3812       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
3813       .access = PL3_W, .type = ARM_CP_NO_RAW,
3814       .writefn = tlbi_aa64_vae3is_write },
3815     { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
3816       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
3817       .access = PL3_W, .type = ARM_CP_NO_RAW,
3818       .writefn = tlbi_aa64_alle3_write },
3819     { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
3820       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
3821       .access = PL3_W, .type = ARM_CP_NO_RAW,
3822       .writefn = tlbi_aa64_vae3_write },
3823     { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
3824       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
3825       .access = PL3_W, .type = ARM_CP_NO_RAW,
3826       .writefn = tlbi_aa64_vae3_write },
3827     REGINFO_SENTINEL
3828 };
3829
3830 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
3831                                      bool isread)
3832 {
3833     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
3834      * but the AArch32 CTR has its own reginfo struct)
3835      */
3836     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
3837         return CP_ACCESS_TRAP;
3838     }
3839     return CP_ACCESS_OK;
3840 }
3841
3842 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
3843                         uint64_t value)
3844 {
3845     /* Writes to OSLAR_EL1 may update the OS lock status, which can be
3846      * read via a bit in OSLSR_EL1.
3847      */
3848     int oslock;
3849
3850     if (ri->state == ARM_CP_STATE_AA32) {
3851         oslock = (value == 0xC5ACCE55);
3852     } else {
3853         oslock = value & 1;
3854     }
3855
3856     env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
3857 }
3858
3859 static const ARMCPRegInfo debug_cp_reginfo[] = {
3860     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
3861      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
3862      * unlike DBGDRAR it is never accessible from EL0.
3863      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
3864      * accessor.
3865      */
3866     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
3867       .access = PL0_R, .accessfn = access_tdra,
3868       .type = ARM_CP_CONST, .resetvalue = 0 },
3869     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
3870       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3871       .access = PL1_R, .accessfn = access_tdra,
3872       .type = ARM_CP_CONST, .resetvalue = 0 },
3873     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3874       .access = PL0_R, .accessfn = access_tdra,
3875       .type = ARM_CP_CONST, .resetvalue = 0 },
3876     /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
3877     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
3878       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3879       .access = PL1_RW, .accessfn = access_tda,
3880       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
3881       .resetvalue = 0 },
3882     /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
3883      * We don't implement the configurable EL0 access.
3884      */
3885     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
3886       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3887       .type = ARM_CP_ALIAS,
3888       .access = PL1_R, .accessfn = access_tda,
3889       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
3890     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
3891       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
3892       .access = PL1_W, .type = ARM_CP_NO_RAW,
3893       .accessfn = access_tdosa,
3894       .writefn = oslar_write },
3895     { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
3896       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
3897       .access = PL1_R, .resetvalue = 10,
3898       .accessfn = access_tdosa,
3899       .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
3900     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
3901     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
3902       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
3903       .access = PL1_RW, .accessfn = access_tdosa,
3904       .type = ARM_CP_NOP },
3905     /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
3906      * implement vector catch debug events yet.
3907      */
3908     { .name = "DBGVCR",
3909       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3910       .access = PL1_RW, .accessfn = access_tda,
3911       .type = ARM_CP_NOP },
3912     REGINFO_SENTINEL
3913 };
3914
3915 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
3916     /* 64 bit access versions of the (dummy) debug registers */
3917     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
3918       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3919     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
3920       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3921     REGINFO_SENTINEL
3922 };
3923
3924 void hw_watchpoint_update(ARMCPU *cpu, int n)
3925 {
3926     CPUARMState *env = &cpu->env;
3927     vaddr len = 0;
3928     vaddr wvr = env->cp15.dbgwvr[n];
3929     uint64_t wcr = env->cp15.dbgwcr[n];
3930     int mask;
3931     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
3932
3933     if (env->cpu_watchpoint[n]) {
3934         cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
3935         env->cpu_watchpoint[n] = NULL;
3936     }
3937
3938     if (!extract64(wcr, 0, 1)) {
3939         /* E bit clear : watchpoint disabled */
3940         return;
3941     }
3942
3943     switch (extract64(wcr, 3, 2)) {
3944     case 0:
3945         /* LSC 00 is reserved and must behave as if the wp is disabled */
3946         return;
3947     case 1:
3948         flags |= BP_MEM_READ;
3949         break;
3950     case 2:
3951         flags |= BP_MEM_WRITE;
3952         break;
3953     case 3:
3954         flags |= BP_MEM_ACCESS;
3955         break;
3956     }
3957
3958     /* Attempts to use both MASK and BAS fields simultaneously are
3959      * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
3960      * thus generating a watchpoint for every byte in the masked region.
3961      */
3962     mask = extract64(wcr, 24, 4);
3963     if (mask == 1 || mask == 2) {
3964         /* Reserved values of MASK; we must act as if the mask value was
3965          * some non-reserved value, or as if the watchpoint were disabled.
3966          * We choose the latter.
3967          */
3968         return;
3969     } else if (mask) {
3970         /* Watchpoint covers an aligned area up to 2GB in size */
3971         len = 1ULL << mask;
3972         /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
3973          * whether the watchpoint fires when the unmasked bits match; we opt
3974          * to generate the exceptions.
3975          */
3976         wvr &= ~(len - 1);
3977     } else {
3978         /* Watchpoint covers bytes defined by the byte address select bits */
3979         int bas = extract64(wcr, 5, 8);
3980         int basstart;
3981
3982         if (bas == 0) {
3983             /* This must act as if the watchpoint is disabled */
3984             return;
3985         }
3986
3987         if (extract64(wvr, 2, 1)) {
3988             /* Deprecated case of an only 4-aligned address. BAS[7:4] are
3989              * ignored, and BAS[3:0] define which bytes to watch.
3990              */
3991             bas &= 0xf;
3992         }
3993         /* The BAS bits are supposed to be programmed to indicate a contiguous
3994          * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
3995          * we fire for each byte in the word/doubleword addressed by the WVR.
3996          * We choose to ignore any non-zero bits after the first range of 1s.
3997          */
3998         basstart = ctz32(bas);
3999         len = cto32(bas >> basstart);
4000         wvr += basstart;
4001     }
4002
4003     cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
4004                           &env->cpu_watchpoint[n]);
4005 }
4006
4007 void hw_watchpoint_update_all(ARMCPU *cpu)
4008 {
4009     int i;
4010     CPUARMState *env = &cpu->env;
4011
4012     /* Completely clear out existing QEMU watchpoints and our array, to
4013      * avoid possible stale entries following migration load.
4014      */
4015     cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
4016     memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
4017
4018     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
4019         hw_watchpoint_update(cpu, i);
4020     }
4021 }
4022
4023 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4024                          uint64_t value)
4025 {
4026     ARMCPU *cpu = arm_env_get_cpu(env);
4027     int i = ri->crm;
4028
4029     /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
4030      * register reads and behaves as if values written are sign extended.
4031      * Bits [1:0] are RES0.
4032      */
4033     value = sextract64(value, 0, 49) & ~3ULL;
4034
4035     raw_write(env, ri, value);
4036     hw_watchpoint_update(cpu, i);
4037 }
4038
4039 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4040                          uint64_t value)
4041 {
4042     ARMCPU *cpu = arm_env_get_cpu(env);
4043     int i = ri->crm;
4044
4045     raw_write(env, ri, value);
4046     hw_watchpoint_update(cpu, i);
4047 }
4048
4049 void hw_breakpoint_update(ARMCPU *cpu, int n)
4050 {
4051     CPUARMState *env = &cpu->env;
4052     uint64_t bvr = env->cp15.dbgbvr[n];
4053     uint64_t bcr = env->cp15.dbgbcr[n];
4054     vaddr addr;
4055     int bt;
4056     int flags = BP_CPU;
4057
4058     if (env->cpu_breakpoint[n]) {
4059         cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
4060         env->cpu_breakpoint[n] = NULL;
4061     }
4062
4063     if (!extract64(bcr, 0, 1)) {
4064         /* E bit clear : watchpoint disabled */
4065         return;
4066     }
4067
4068     bt = extract64(bcr, 20, 4);
4069
4070     switch (bt) {
4071     case 4: /* unlinked address mismatch (reserved if AArch64) */
4072     case 5: /* linked address mismatch (reserved if AArch64) */
4073         qemu_log_mask(LOG_UNIMP,
4074                       "arm: address mismatch breakpoint types not implemented");
4075         return;
4076     case 0: /* unlinked address match */
4077     case 1: /* linked address match */
4078     {
4079         /* Bits [63:49] are hardwired to the value of bit [48]; that is,
4080          * we behave as if the register was sign extended. Bits [1:0] are
4081          * RES0. The BAS field is used to allow setting breakpoints on 16
4082          * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
4083          * a bp will fire if the addresses covered by the bp and the addresses
4084          * covered by the insn overlap but the insn doesn't start at the
4085          * start of the bp address range. We choose to require the insn and
4086          * the bp to have the same address. The constraints on writing to
4087          * BAS enforced in dbgbcr_write mean we have only four cases:
4088          *  0b0000  => no breakpoint
4089          *  0b0011  => breakpoint on addr
4090          *  0b1100  => breakpoint on addr + 2
4091          *  0b1111  => breakpoint on addr
4092          * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
4093          */
4094         int bas = extract64(bcr, 5, 4);
4095         addr = sextract64(bvr, 0, 49) & ~3ULL;
4096         if (bas == 0) {
4097             return;
4098         }
4099         if (bas == 0xc) {
4100             addr += 2;
4101         }
4102         break;
4103     }
4104     case 2: /* unlinked context ID match */
4105     case 8: /* unlinked VMID match (reserved if no EL2) */
4106     case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
4107         qemu_log_mask(LOG_UNIMP,
4108                       "arm: unlinked context breakpoint types not implemented");
4109         return;
4110     case 9: /* linked VMID match (reserved if no EL2) */
4111     case 11: /* linked context ID and VMID match (reserved if no EL2) */
4112     case 3: /* linked context ID match */
4113     default:
4114         /* We must generate no events for Linked context matches (unless
4115          * they are linked to by some other bp/wp, which is handled in
4116          * updates for the linking bp/wp). We choose to also generate no events
4117          * for reserved values.
4118          */
4119         return;
4120     }
4121
4122     cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
4123 }
4124
4125 void hw_breakpoint_update_all(ARMCPU *cpu)
4126 {
4127     int i;
4128     CPUARMState *env = &cpu->env;
4129
4130     /* Completely clear out existing QEMU breakpoints and our array, to
4131      * avoid possible stale entries following migration load.
4132      */
4133     cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
4134     memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
4135
4136     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
4137         hw_breakpoint_update(cpu, i);
4138     }
4139 }
4140
4141 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4142                          uint64_t value)
4143 {
4144     ARMCPU *cpu = arm_env_get_cpu(env);
4145     int i = ri->crm;
4146
4147     raw_write(env, ri, value);
4148     hw_breakpoint_update(cpu, i);
4149 }
4150
4151 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4152                          uint64_t value)
4153 {
4154     ARMCPU *cpu = arm_env_get_cpu(env);
4155     int i = ri->crm;
4156
4157     /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
4158      * copy of BAS[0].
4159      */
4160     value = deposit64(value, 6, 1, extract64(value, 5, 1));
4161     value = deposit64(value, 8, 1, extract64(value, 7, 1));
4162
4163     raw_write(env, ri, value);
4164     hw_breakpoint_update(cpu, i);
4165 }
4166
4167 static void define_debug_regs(ARMCPU *cpu)
4168 {
4169     /* Define v7 and v8 architectural debug registers.
4170      * These are just dummy implementations for now.
4171      */
4172     int i;
4173     int wrps, brps, ctx_cmps;
4174     ARMCPRegInfo dbgdidr = {
4175         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
4176         .access = PL0_R, .accessfn = access_tda,
4177         .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
4178     };
4179
4180     /* Note that all these register fields hold "number of Xs minus 1". */
4181     brps = extract32(cpu->dbgdidr, 24, 4);
4182     wrps = extract32(cpu->dbgdidr, 28, 4);
4183     ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
4184
4185     assert(ctx_cmps <= brps);
4186
4187     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
4188      * of the debug registers such as number of breakpoints;
4189      * check that if they both exist then they agree.
4190      */
4191     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
4192         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
4193         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
4194         assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
4195     }
4196
4197     define_one_arm_cp_reg(cpu, &dbgdidr);
4198     define_arm_cp_regs(cpu, debug_cp_reginfo);
4199
4200     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
4201         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
4202     }
4203
4204     for (i = 0; i < brps + 1; i++) {
4205         ARMCPRegInfo dbgregs[] = {
4206             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
4207               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
4208               .access = PL1_RW, .accessfn = access_tda,
4209               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
4210               .writefn = dbgbvr_write, .raw_writefn = raw_write
4211             },
4212             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
4213               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
4214               .access = PL1_RW, .accessfn = access_tda,
4215               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
4216               .writefn = dbgbcr_write, .raw_writefn = raw_write
4217             },
4218             REGINFO_SENTINEL
4219         };
4220         define_arm_cp_regs(cpu, dbgregs);
4221     }
4222
4223     for (i = 0; i < wrps + 1; i++) {
4224         ARMCPRegInfo dbgregs[] = {
4225             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
4226               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
4227               .access = PL1_RW, .accessfn = access_tda,
4228               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
4229               .writefn = dbgwvr_write, .raw_writefn = raw_write
4230             },
4231             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
4232               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
4233               .access = PL1_RW, .accessfn = access_tda,
4234               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
4235               .writefn = dbgwcr_write, .raw_writefn = raw_write
4236             },
4237             REGINFO_SENTINEL
4238         };
4239         define_arm_cp_regs(cpu, dbgregs);
4240     }
4241 }
4242
4243 void register_cp_regs_for_features(ARMCPU *cpu)
4244 {
4245     /* Register all the coprocessor registers based on feature bits */
4246     CPUARMState *env = &cpu->env;
4247     if (arm_feature(env, ARM_FEATURE_M)) {
4248         /* M profile has no coprocessor registers */
4249         return;
4250     }
4251
4252     define_arm_cp_regs(cpu, cp_reginfo);
4253     if (!arm_feature(env, ARM_FEATURE_V8)) {
4254         /* Must go early as it is full of wildcards that may be
4255          * overridden by later definitions.
4256          */
4257         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
4258     }
4259
4260     if (arm_feature(env, ARM_FEATURE_V6)) {
4261         /* The ID registers all have impdef reset values */
4262         ARMCPRegInfo v6_idregs[] = {
4263             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
4264               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
4265               .access = PL1_R, .type = ARM_CP_CONST,
4266               .resetvalue = cpu->id_pfr0 },
4267             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
4268               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
4269               .access = PL1_R, .type = ARM_CP_CONST,
4270               .resetvalue = cpu->id_pfr1 },
4271             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
4272               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
4273               .access = PL1_R, .type = ARM_CP_CONST,
4274               .resetvalue = cpu->id_dfr0 },
4275             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
4276               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
4277               .access = PL1_R, .type = ARM_CP_CONST,
4278               .resetvalue = cpu->id_afr0 },
4279             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
4280               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
4281               .access = PL1_R, .type = ARM_CP_CONST,
4282               .resetvalue = cpu->id_mmfr0 },
4283             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
4284               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
4285               .access = PL1_R, .type = ARM_CP_CONST,
4286               .resetvalue = cpu->id_mmfr1 },
4287             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
4288               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
4289               .access = PL1_R, .type = ARM_CP_CONST,
4290               .resetvalue = cpu->id_mmfr2 },
4291             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
4292               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
4293               .access = PL1_R, .type = ARM_CP_CONST,
4294               .resetvalue = cpu->id_mmfr3 },
4295             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
4296               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
4297               .access = PL1_R, .type = ARM_CP_CONST,
4298               .resetvalue = cpu->id_isar0 },
4299             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
4300               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
4301               .access = PL1_R, .type = ARM_CP_CONST,
4302               .resetvalue = cpu->id_isar1 },
4303             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
4304               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
4305               .access = PL1_R, .type = ARM_CP_CONST,
4306               .resetvalue = cpu->id_isar2 },
4307             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
4308               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
4309               .access = PL1_R, .type = ARM_CP_CONST,
4310               .resetvalue = cpu->id_isar3 },
4311             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
4312               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
4313               .access = PL1_R, .type = ARM_CP_CONST,
4314               .resetvalue = cpu->id_isar4 },
4315             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
4316               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
4317               .access = PL1_R, .type = ARM_CP_CONST,
4318               .resetvalue = cpu->id_isar5 },
4319             { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
4320               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
4321               .access = PL1_R, .type = ARM_CP_CONST,
4322               .resetvalue = cpu->id_mmfr4 },
4323             /* 7 is as yet unallocated and must RAZ */
4324             { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH,
4325               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
4326               .access = PL1_R, .type = ARM_CP_CONST,
4327               .resetvalue = 0 },
4328             REGINFO_SENTINEL
4329         };
4330         define_arm_cp_regs(cpu, v6_idregs);
4331         define_arm_cp_regs(cpu, v6_cp_reginfo);
4332     } else {
4333         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
4334     }
4335     if (arm_feature(env, ARM_FEATURE_V6K)) {
4336         define_arm_cp_regs(cpu, v6k_cp_reginfo);
4337     }
4338     if (arm_feature(env, ARM_FEATURE_V7MP) &&
4339         !arm_feature(env, ARM_FEATURE_MPU)) {
4340         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
4341     }
4342     if (arm_feature(env, ARM_FEATURE_V7)) {
4343         /* v7 performance monitor control register: same implementor
4344          * field as main ID register, and we implement only the cycle
4345          * count register.
4346          */
4347 #ifndef CONFIG_USER_ONLY
4348         ARMCPRegInfo pmcr = {
4349             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
4350             .access = PL0_RW,
4351             .type = ARM_CP_IO | ARM_CP_ALIAS,
4352             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
4353             .accessfn = pmreg_access, .writefn = pmcr_write,
4354             .raw_writefn = raw_write,
4355         };
4356         ARMCPRegInfo pmcr64 = {
4357             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
4358             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
4359             .access = PL0_RW, .accessfn = pmreg_access,
4360             .type = ARM_CP_IO,
4361             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
4362             .resetvalue = cpu->midr & 0xff000000,
4363             .writefn = pmcr_write, .raw_writefn = raw_write,
4364         };
4365         define_one_arm_cp_reg(cpu, &pmcr);
4366         define_one_arm_cp_reg(cpu, &pmcr64);
4367 #endif
4368         ARMCPRegInfo clidr = {
4369             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
4370             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
4371             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
4372         };
4373         define_one_arm_cp_reg(cpu, &clidr);
4374         define_arm_cp_regs(cpu, v7_cp_reginfo);
4375         define_debug_regs(cpu);
4376     } else {
4377         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
4378     }
4379     if (arm_feature(env, ARM_FEATURE_V8)) {
4380         /* AArch64 ID registers, which all have impdef reset values.
4381          * Note that within the ID register ranges the unused slots
4382          * must all RAZ, not UNDEF; future architecture versions may
4383          * define new registers here.
4384          */
4385         ARMCPRegInfo v8_idregs[] = {
4386             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
4387               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
4388               .access = PL1_R, .type = ARM_CP_CONST,
4389               .resetvalue = cpu->id_aa64pfr0 },
4390             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
4391               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
4392               .access = PL1_R, .type = ARM_CP_CONST,
4393               .resetvalue = cpu->id_aa64pfr1},
4394             { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4395               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
4396               .access = PL1_R, .type = ARM_CP_CONST,
4397               .resetvalue = 0 },
4398             { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4399               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
4400               .access = PL1_R, .type = ARM_CP_CONST,
4401               .resetvalue = 0 },
4402             { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4403               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
4404               .access = PL1_R, .type = ARM_CP_CONST,
4405               .resetvalue = 0 },
4406             { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4407               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
4408               .access = PL1_R, .type = ARM_CP_CONST,
4409               .resetvalue = 0 },
4410             { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4411               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
4412               .access = PL1_R, .type = ARM_CP_CONST,
4413               .resetvalue = 0 },
4414             { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4415               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
4416               .access = PL1_R, .type = ARM_CP_CONST,
4417               .resetvalue = 0 },
4418             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
4419               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
4420               .access = PL1_R, .type = ARM_CP_CONST,
4421               /* We mask out the PMUVer field, because we don't currently
4422                * implement the PMU. Not advertising it prevents the guest
4423                * from trying to use it and getting UNDEFs on registers we
4424                * don't implement.
4425                */
4426               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
4427             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
4428               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
4429               .access = PL1_R, .type = ARM_CP_CONST,
4430               .resetvalue = cpu->id_aa64dfr1 },
4431             { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4432               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
4433               .access = PL1_R, .type = ARM_CP_CONST,
4434               .resetvalue = 0 },
4435             { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4436               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
4437               .access = PL1_R, .type = ARM_CP_CONST,
4438               .resetvalue = 0 },
4439             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
4440               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
4441               .access = PL1_R, .type = ARM_CP_CONST,
4442               .resetvalue = cpu->id_aa64afr0 },
4443             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
4444               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
4445               .access = PL1_R, .type = ARM_CP_CONST,
4446               .resetvalue = cpu->id_aa64afr1 },
4447             { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4448               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
4449               .access = PL1_R, .type = ARM_CP_CONST,
4450               .resetvalue = 0 },
4451             { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4452               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
4453               .access = PL1_R, .type = ARM_CP_CONST,
4454               .resetvalue = 0 },
4455             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
4456               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
4457               .access = PL1_R, .type = ARM_CP_CONST,
4458               .resetvalue = cpu->id_aa64isar0 },
4459             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
4460               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
4461               .access = PL1_R, .type = ARM_CP_CONST,
4462               .resetvalue = cpu->id_aa64isar1 },
4463             { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4464               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
4465               .access = PL1_R, .type = ARM_CP_CONST,
4466               .resetvalue = 0 },
4467             { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4468               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
4469               .access = PL1_R, .type = ARM_CP_CONST,
4470               .resetvalue = 0 },
4471             { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4472               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
4473               .access = PL1_R, .type = ARM_CP_CONST,
4474               .resetvalue = 0 },
4475             { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4476               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
4477               .access = PL1_R, .type = ARM_CP_CONST,
4478               .resetvalue = 0 },
4479             { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4480               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
4481               .access = PL1_R, .type = ARM_CP_CONST,
4482               .resetvalue = 0 },
4483             { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4484               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
4485               .access = PL1_R, .type = ARM_CP_CONST,
4486               .resetvalue = 0 },
4487             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
4488               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
4489               .access = PL1_R, .type = ARM_CP_CONST,
4490               .resetvalue = cpu->id_aa64mmfr0 },
4491             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
4492               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
4493               .access = PL1_R, .type = ARM_CP_CONST,
4494               .resetvalue = cpu->id_aa64mmfr1 },
4495             { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4496               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
4497               .access = PL1_R, .type = ARM_CP_CONST,
4498               .resetvalue = 0 },
4499             { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4500               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
4501               .access = PL1_R, .type = ARM_CP_CONST,
4502               .resetvalue = 0 },
4503             { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4504               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
4505               .access = PL1_R, .type = ARM_CP_CONST,
4506               .resetvalue = 0 },
4507             { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4508               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
4509               .access = PL1_R, .type = ARM_CP_CONST,
4510               .resetvalue = 0 },
4511             { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4512               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
4513               .access = PL1_R, .type = ARM_CP_CONST,
4514               .resetvalue = 0 },
4515             { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4516               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
4517               .access = PL1_R, .type = ARM_CP_CONST,
4518               .resetvalue = 0 },
4519             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
4520               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
4521               .access = PL1_R, .type = ARM_CP_CONST,
4522               .resetvalue = cpu->mvfr0 },
4523             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
4524               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
4525               .access = PL1_R, .type = ARM_CP_CONST,
4526               .resetvalue = cpu->mvfr1 },
4527             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
4528               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
4529               .access = PL1_R, .type = ARM_CP_CONST,
4530               .resetvalue = cpu->mvfr2 },
4531             { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4532               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
4533               .access = PL1_R, .type = ARM_CP_CONST,
4534               .resetvalue = 0 },
4535             { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4536               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
4537               .access = PL1_R, .type = ARM_CP_CONST,
4538               .resetvalue = 0 },
4539             { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4540               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
4541               .access = PL1_R, .type = ARM_CP_CONST,
4542               .resetvalue = 0 },
4543             { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4544               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
4545               .access = PL1_R, .type = ARM_CP_CONST,
4546               .resetvalue = 0 },
4547             { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4548               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
4549               .access = PL1_R, .type = ARM_CP_CONST,
4550               .resetvalue = 0 },
4551             { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
4552               .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
4553               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4554               .resetvalue = cpu->pmceid0 },
4555             { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
4556               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
4557               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4558               .resetvalue = cpu->pmceid0 },
4559             { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
4560               .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
4561               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4562               .resetvalue = cpu->pmceid1 },
4563             { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
4564               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
4565               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4566               .resetvalue = cpu->pmceid1 },
4567             REGINFO_SENTINEL
4568         };
4569         /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4570         if (!arm_feature(env, ARM_FEATURE_EL3) &&
4571             !arm_feature(env, ARM_FEATURE_EL2)) {
4572             ARMCPRegInfo rvbar = {
4573                 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
4574                 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
4575                 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
4576             };
4577             define_one_arm_cp_reg(cpu, &rvbar);
4578         }
4579         define_arm_cp_regs(cpu, v8_idregs);
4580         define_arm_cp_regs(cpu, v8_cp_reginfo);
4581     }
4582     if (arm_feature(env, ARM_FEATURE_EL2)) {
4583         uint64_t vmpidr_def = mpidr_read_val(env);
4584         ARMCPRegInfo vpidr_regs[] = {
4585             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
4586               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4587               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4588               .resetvalue = cpu->midr,
4589               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4590             { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
4591               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4592               .access = PL2_RW, .resetvalue = cpu->midr,
4593               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4594             { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
4595               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4596               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4597               .resetvalue = vmpidr_def,
4598               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4599             { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
4600               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4601               .access = PL2_RW,
4602               .resetvalue = vmpidr_def,
4603               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4604             REGINFO_SENTINEL
4605         };
4606         define_arm_cp_regs(cpu, vpidr_regs);
4607         define_arm_cp_regs(cpu, el2_cp_reginfo);
4608         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4609         if (!arm_feature(env, ARM_FEATURE_EL3)) {
4610             ARMCPRegInfo rvbar = {
4611                 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
4612                 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
4613                 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
4614             };
4615             define_one_arm_cp_reg(cpu, &rvbar);
4616         }
4617     } else {
4618         /* If EL2 is missing but higher ELs are enabled, we need to
4619          * register the no_el2 reginfos.
4620          */
4621         if (arm_feature(env, ARM_FEATURE_EL3)) {
4622             /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4623              * of MIDR_EL1 and MPIDR_EL1.
4624              */
4625             ARMCPRegInfo vpidr_regs[] = {
4626                 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4627                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4628                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4629                   .type = ARM_CP_CONST, .resetvalue = cpu->midr,
4630                   .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4631                 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4632                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4633                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4634                   .type = ARM_CP_NO_RAW,
4635                   .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
4636                 REGINFO_SENTINEL
4637             };
4638             define_arm_cp_regs(cpu, vpidr_regs);
4639             define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
4640         }
4641     }
4642     if (arm_feature(env, ARM_FEATURE_EL3)) {
4643         define_arm_cp_regs(cpu, el3_cp_reginfo);
4644         ARMCPRegInfo rvbar = {
4645             .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
4646             .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
4647             .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar
4648         };
4649         define_one_arm_cp_reg(cpu, &rvbar);
4650     }
4651     /* The behaviour of NSACR is sufficiently various that we don't
4652      * try to describe it in a single reginfo:
4653      *  if EL3 is 64 bit, then trap to EL3 from S EL1,
4654      *     reads as constant 0xc00 from NS EL1 and NS EL2
4655      *  if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
4656      *  if v7 without EL3, register doesn't exist
4657      *  if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
4658      */
4659     if (arm_feature(env, ARM_FEATURE_EL3)) {
4660         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4661             ARMCPRegInfo nsacr = {
4662                 .name = "NSACR", .type = ARM_CP_CONST,
4663                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4664                 .access = PL1_RW, .accessfn = nsacr_access,
4665                 .resetvalue = 0xc00
4666             };
4667             define_one_arm_cp_reg(cpu, &nsacr);
4668         } else {
4669             ARMCPRegInfo nsacr = {
4670                 .name = "NSACR",
4671                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4672                 .access = PL3_RW | PL1_R,
4673                 .resetvalue = 0,
4674                 .fieldoffset = offsetof(CPUARMState, cp15.nsacr)
4675             };
4676             define_one_arm_cp_reg(cpu, &nsacr);
4677         }
4678     } else {
4679         if (arm_feature(env, ARM_FEATURE_V8)) {
4680             ARMCPRegInfo nsacr = {
4681                 .name = "NSACR", .type = ARM_CP_CONST,
4682                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4683                 .access = PL1_R,
4684                 .resetvalue = 0xc00
4685             };
4686             define_one_arm_cp_reg(cpu, &nsacr);
4687         }
4688     }
4689
4690     if (arm_feature(env, ARM_FEATURE_MPU)) {
4691         if (arm_feature(env, ARM_FEATURE_V6)) {
4692             /* PMSAv6 not implemented */
4693             assert(arm_feature(env, ARM_FEATURE_V7));
4694             define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4695             define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
4696         } else {
4697             define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
4698         }
4699     } else {
4700         define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4701         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
4702     }
4703     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
4704         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
4705     }
4706     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
4707         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
4708     }
4709     if (arm_feature(env, ARM_FEATURE_VAPA)) {
4710         define_arm_cp_regs(cpu, vapa_cp_reginfo);
4711     }
4712     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
4713         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
4714     }
4715     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
4716         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
4717     }
4718     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
4719         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
4720     }
4721     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
4722         define_arm_cp_regs(cpu, omap_cp_reginfo);
4723     }
4724     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
4725         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
4726     }
4727     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4728         define_arm_cp_regs(cpu, xscale_cp_reginfo);
4729     }
4730     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
4731         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
4732     }
4733     if (arm_feature(env, ARM_FEATURE_LPAE)) {
4734         define_arm_cp_regs(cpu, lpae_cp_reginfo);
4735     }
4736     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
4737      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
4738      * be read-only (ie write causes UNDEF exception).
4739      */
4740     {
4741         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
4742             /* Pre-v8 MIDR space.
4743              * Note that the MIDR isn't a simple constant register because
4744              * of the TI925 behaviour where writes to another register can
4745              * cause the MIDR value to change.
4746              *
4747              * Unimplemented registers in the c15 0 0 0 space default to
4748              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
4749              * and friends override accordingly.
4750              */
4751             { .name = "MIDR",
4752               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
4753               .access = PL1_R, .resetvalue = cpu->midr,
4754               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
4755               .readfn = midr_read,
4756               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4757               .type = ARM_CP_OVERRIDE },
4758             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
4759             { .name = "DUMMY",
4760               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
4761               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4762             { .name = "DUMMY",
4763               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
4764               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4765             { .name = "DUMMY",
4766               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
4767               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4768             { .name = "DUMMY",
4769               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
4770               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4771             { .name = "DUMMY",
4772               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
4773               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4774             REGINFO_SENTINEL
4775         };
4776         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
4777             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
4778               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
4779               .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
4780               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4781               .readfn = midr_read },
4782             /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
4783             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4784               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4785               .access = PL1_R, .resetvalue = cpu->midr },
4786             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4787               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
4788               .access = PL1_R, .resetvalue = cpu->midr },
4789             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
4790               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
4791               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
4792             REGINFO_SENTINEL
4793         };
4794         ARMCPRegInfo id_cp_reginfo[] = {
4795             /* These are common to v8 and pre-v8 */
4796             { .name = "CTR",
4797               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
4798               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4799             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
4800               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
4801               .access = PL0_R, .accessfn = ctr_el0_access,
4802               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4803             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
4804             { .name = "TCMTR",
4805               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
4806               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4807             REGINFO_SENTINEL
4808         };
4809         /* TLBTR is specific to VMSA */
4810         ARMCPRegInfo id_tlbtr_reginfo = {
4811               .name = "TLBTR",
4812               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
4813               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
4814         };
4815         /* MPUIR is specific to PMSA V6+ */
4816         ARMCPRegInfo id_mpuir_reginfo = {
4817               .name = "MPUIR",
4818               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4819               .access = PL1_R, .type = ARM_CP_CONST,
4820               .resetvalue = cpu->pmsav7_dregion << 8
4821         };
4822         ARMCPRegInfo crn0_wi_reginfo = {
4823             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
4824             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
4825             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
4826         };
4827         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
4828             arm_feature(env, ARM_FEATURE_STRONGARM)) {
4829             ARMCPRegInfo *r;
4830             /* Register the blanket "writes ignored" value first to cover the
4831              * whole space. Then update the specific ID registers to allow write
4832              * access, so that they ignore writes rather than causing them to
4833              * UNDEF.
4834              */
4835             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
4836             for (r = id_pre_v8_midr_cp_reginfo;
4837                  r->type != ARM_CP_SENTINEL; r++) {
4838                 r->access = PL1_RW;
4839             }
4840             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
4841                 r->access = PL1_RW;
4842             }
4843             id_tlbtr_reginfo.access = PL1_RW;
4844             id_tlbtr_reginfo.access = PL1_RW;
4845         }
4846         if (arm_feature(env, ARM_FEATURE_V8)) {
4847             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
4848         } else {
4849             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
4850         }
4851         define_arm_cp_regs(cpu, id_cp_reginfo);
4852         if (!arm_feature(env, ARM_FEATURE_MPU)) {
4853             define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
4854         } else if (arm_feature(env, ARM_FEATURE_V7)) {
4855             define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
4856         }
4857     }
4858
4859     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
4860         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
4861     }
4862
4863     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
4864         ARMCPRegInfo auxcr_reginfo[] = {
4865             { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
4866               .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
4867               .access = PL1_RW, .type = ARM_CP_CONST,
4868               .resetvalue = cpu->reset_auxcr },
4869             { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
4870               .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
4871               .access = PL2_RW, .type = ARM_CP_CONST,
4872               .resetvalue = 0 },
4873             { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
4874               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
4875               .access = PL3_RW, .type = ARM_CP_CONST,
4876               .resetvalue = 0 },
4877             REGINFO_SENTINEL
4878         };
4879         define_arm_cp_regs(cpu, auxcr_reginfo);
4880     }
4881
4882     if (arm_feature(env, ARM_FEATURE_CBAR)) {
4883         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4884             /* 32 bit view is [31:18] 0...0 [43:32]. */
4885             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
4886                 | extract64(cpu->reset_cbar, 32, 12);
4887             ARMCPRegInfo cbar_reginfo[] = {
4888                 { .name = "CBAR",
4889                   .type = ARM_CP_CONST,
4890                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4891                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
4892                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
4893                   .type = ARM_CP_CONST,
4894                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
4895                   .access = PL1_R, .resetvalue = cbar32 },
4896                 REGINFO_SENTINEL
4897             };
4898             /* We don't implement a r/w 64 bit CBAR currently */
4899             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
4900             define_arm_cp_regs(cpu, cbar_reginfo);
4901         } else {
4902             ARMCPRegInfo cbar = {
4903                 .name = "CBAR",
4904                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4905                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
4906                 .fieldoffset = offsetof(CPUARMState,
4907                                         cp15.c15_config_base_address)
4908             };
4909             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
4910                 cbar.access = PL1_R;
4911                 cbar.fieldoffset = 0;
4912                 cbar.type = ARM_CP_CONST;
4913             }
4914             define_one_arm_cp_reg(cpu, &cbar);
4915         }
4916     }
4917
4918     /* Generic registers whose values depend on the implementation */
4919     {
4920         ARMCPRegInfo sctlr = {
4921             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
4922             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
4923             .access = PL1_RW,
4924             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
4925                                    offsetof(CPUARMState, cp15.sctlr_ns) },
4926             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
4927             .raw_writefn = raw_write,
4928         };
4929         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4930             /* Normally we would always end the TB on an SCTLR write, but Linux
4931              * arch/arm/mach-pxa/sleep.S expects two instructions following
4932              * an MMU enable to execute from cache.  Imitate this behaviour.
4933              */
4934             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
4935         }
4936         define_one_arm_cp_reg(cpu, &sctlr);
4937     }
4938 }
4939
4940 ARMCPU *cpu_arm_init(const char *cpu_model)
4941 {
4942     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
4943 }
4944
4945 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
4946 {
4947     CPUState *cs = CPU(cpu);
4948     CPUARMState *env = &cpu->env;
4949
4950     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4951         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
4952                                  aarch64_fpu_gdb_set_reg,
4953                                  34, "aarch64-fpu.xml", 0);
4954     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
4955         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4956                                  51, "arm-neon.xml", 0);
4957     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
4958         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4959                                  35, "arm-vfp3.xml", 0);
4960     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
4961         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4962                                  19, "arm-vfp.xml", 0);
4963     }
4964 }
4965
4966 /* Sort alphabetically by type name, except for "any". */
4967 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
4968 {
4969     ObjectClass *class_a = (ObjectClass *)a;
4970     ObjectClass *class_b = (ObjectClass *)b;
4971     const char *name_a, *name_b;
4972
4973     name_a = object_class_get_name(class_a);
4974     name_b = object_class_get_name(class_b);
4975     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
4976         return 1;
4977     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
4978         return -1;
4979     } else {
4980         return strcmp(name_a, name_b);
4981     }
4982 }
4983
4984 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
4985 {
4986     ObjectClass *oc = data;
4987     CPUListState *s = user_data;
4988     const char *typename;
4989     char *name;
4990
4991     typename = object_class_get_name(oc);
4992     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
4993     (*s->cpu_fprintf)(s->file, "  %s\n",
4994                       name);
4995     g_free(name);
4996 }
4997
4998 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
4999 {
5000     CPUListState s = {
5001         .file = f,
5002         .cpu_fprintf = cpu_fprintf,
5003     };
5004     GSList *list;
5005
5006     list = object_class_get_list(TYPE_ARM_CPU, false);
5007     list = g_slist_sort(list, arm_cpu_list_compare);
5008     (*cpu_fprintf)(f, "Available CPUs:\n");
5009     g_slist_foreach(list, arm_cpu_list_entry, &s);
5010     g_slist_free(list);
5011 #ifdef CONFIG_KVM
5012     /* The 'host' CPU type is dynamically registered only if KVM is
5013      * enabled, so we have to special-case it here:
5014      */
5015     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
5016 #endif
5017 }
5018
5019 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
5020 {
5021     ObjectClass *oc = data;
5022     CpuDefinitionInfoList **cpu_list = user_data;
5023     CpuDefinitionInfoList *entry;
5024     CpuDefinitionInfo *info;
5025     const char *typename;
5026
5027     typename = object_class_get_name(oc);
5028     info = g_malloc0(sizeof(*info));
5029     info->name = g_strndup(typename,
5030                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
5031
5032     entry = g_malloc0(sizeof(*entry));
5033     entry->value = info;
5034     entry->next = *cpu_list;
5035     *cpu_list = entry;
5036 }
5037
5038 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
5039 {
5040     CpuDefinitionInfoList *cpu_list = NULL;
5041     GSList *list;
5042
5043     list = object_class_get_list(TYPE_ARM_CPU, false);
5044     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
5045     g_slist_free(list);
5046
5047     return cpu_list;
5048 }
5049
5050 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
5051                                    void *opaque, int state, int secstate,
5052                                    int crm, int opc1, int opc2)
5053 {
5054     /* Private utility function for define_one_arm_cp_reg_with_opaque():
5055      * add a single reginfo struct to the hash table.
5056      */
5057     uint32_t *key = g_new(uint32_t, 1);
5058     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
5059     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
5060     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
5061
5062     /* Reset the secure state to the specific incoming state.  This is
5063      * necessary as the register may have been defined with both states.
5064      */
5065     r2->secure = secstate;
5066
5067     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
5068         /* Register is banked (using both entries in array).
5069          * Overwriting fieldoffset as the array is only used to define
5070          * banked registers but later only fieldoffset is used.
5071          */
5072         r2->fieldoffset = r->bank_fieldoffsets[ns];
5073     }
5074
5075     if (state == ARM_CP_STATE_AA32) {
5076         if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
5077             /* If the register is banked then we don't need to migrate or
5078              * reset the 32-bit instance in certain cases:
5079              *
5080              * 1) If the register has both 32-bit and 64-bit instances then we
5081              *    can count on the 64-bit instance taking care of the
5082              *    non-secure bank.
5083              * 2) If ARMv8 is enabled then we can count on a 64-bit version
5084              *    taking care of the secure bank.  This requires that separate
5085              *    32 and 64-bit definitions are provided.
5086              */
5087             if ((r->state == ARM_CP_STATE_BOTH && ns) ||
5088                 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
5089                 r2->type |= ARM_CP_ALIAS;
5090             }
5091         } else if ((secstate != r->secure) && !ns) {
5092             /* The register is not banked so we only want to allow migration of
5093              * the non-secure instance.
5094              */
5095             r2->type |= ARM_CP_ALIAS;
5096         }
5097
5098         if (r->state == ARM_CP_STATE_BOTH) {
5099             /* We assume it is a cp15 register if the .cp field is left unset.
5100              */
5101             if (r2->cp == 0) {
5102                 r2->cp = 15;
5103             }
5104
5105 #ifdef HOST_WORDS_BIGENDIAN
5106             if (r2->fieldoffset) {
5107                 r2->fieldoffset += sizeof(uint32_t);
5108             }
5109 #endif
5110         }
5111     }
5112     if (state == ARM_CP_STATE_AA64) {
5113         /* To allow abbreviation of ARMCPRegInfo
5114          * definitions, we treat cp == 0 as equivalent to
5115          * the value for "standard guest-visible sysreg".
5116          * STATE_BOTH definitions are also always "standard
5117          * sysreg" in their AArch64 view (the .cp value may
5118          * be non-zero for the benefit of the AArch32 view).
5119          */
5120         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
5121             r2->cp = CP_REG_ARM64_SYSREG_CP;
5122         }
5123         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
5124                                   r2->opc0, opc1, opc2);
5125     } else {
5126         *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
5127     }
5128     if (opaque) {
5129         r2->opaque = opaque;
5130     }
5131     /* reginfo passed to helpers is correct for the actual access,
5132      * and is never ARM_CP_STATE_BOTH:
5133      */
5134     r2->state = state;
5135     /* Make sure reginfo passed to helpers for wildcarded regs
5136      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
5137      */
5138     r2->crm = crm;
5139     r2->opc1 = opc1;
5140     r2->opc2 = opc2;
5141     /* By convention, for wildcarded registers only the first
5142      * entry is used for migration; the others are marked as
5143      * ALIAS so we don't try to transfer the register
5144      * multiple times. Special registers (ie NOP/WFI) are
5145      * never migratable and not even raw-accessible.
5146      */
5147     if ((r->type & ARM_CP_SPECIAL)) {
5148         r2->type |= ARM_CP_NO_RAW;
5149     }
5150     if (((r->crm == CP_ANY) && crm != 0) ||
5151         ((r->opc1 == CP_ANY) && opc1 != 0) ||
5152         ((r->opc2 == CP_ANY) && opc2 != 0)) {
5153         r2->type |= ARM_CP_ALIAS;
5154     }
5155
5156     /* Check that raw accesses are either forbidden or handled. Note that
5157      * we can't assert this earlier because the setup of fieldoffset for
5158      * banked registers has to be done first.
5159      */
5160     if (!(r2->type & ARM_CP_NO_RAW)) {
5161         assert(!raw_accessors_invalid(r2));
5162     }
5163
5164     /* Overriding of an existing definition must be explicitly
5165      * requested.
5166      */
5167     if (!(r->type & ARM_CP_OVERRIDE)) {
5168         ARMCPRegInfo *oldreg;
5169         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
5170         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
5171             fprintf(stderr, "Register redefined: cp=%d %d bit "
5172                     "crn=%d crm=%d opc1=%d opc2=%d, "
5173                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
5174                     r2->crn, r2->crm, r2->opc1, r2->opc2,
5175                     oldreg->name, r2->name);
5176             g_assert_not_reached();
5177         }
5178     }
5179     g_hash_table_insert(cpu->cp_regs, key, r2);
5180 }
5181
5182
5183 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
5184                                        const ARMCPRegInfo *r, void *opaque)
5185 {
5186     /* Define implementations of coprocessor registers.
5187      * We store these in a hashtable because typically
5188      * there are less than 150 registers in a space which
5189      * is 16*16*16*8*8 = 262144 in size.
5190      * Wildcarding is supported for the crm, opc1 and opc2 fields.
5191      * If a register is defined twice then the second definition is
5192      * used, so this can be used to define some generic registers and
5193      * then override them with implementation specific variations.
5194      * At least one of the original and the second definition should
5195      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
5196      * against accidental use.
5197      *
5198      * The state field defines whether the register is to be
5199      * visible in the AArch32 or AArch64 execution state. If the
5200      * state is set to ARM_CP_STATE_BOTH then we synthesise a
5201      * reginfo structure for the AArch32 view, which sees the lower
5202      * 32 bits of the 64 bit register.
5203      *
5204      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
5205      * be wildcarded. AArch64 registers are always considered to be 64
5206      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
5207      * the register, if any.
5208      */
5209     int crm, opc1, opc2, state;
5210     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
5211     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
5212     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
5213     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
5214     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
5215     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
5216     /* 64 bit registers have only CRm and Opc1 fields */
5217     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
5218     /* op0 only exists in the AArch64 encodings */
5219     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
5220     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
5221     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
5222     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
5223      * encodes a minimum access level for the register. We roll this
5224      * runtime check into our general permission check code, so check
5225      * here that the reginfo's specified permissions are strict enough
5226      * to encompass the generic architectural permission check.
5227      */
5228     if (r->state != ARM_CP_STATE_AA32) {
5229         int mask = 0;
5230         switch (r->opc1) {
5231         case 0: case 1: case 2:
5232             /* min_EL EL1 */
5233             mask = PL1_RW;
5234             break;
5235         case 3:
5236             /* min_EL EL0 */
5237             mask = PL0_RW;
5238             break;
5239         case 4:
5240             /* min_EL EL2 */
5241             mask = PL2_RW;
5242             break;
5243         case 5:
5244             /* unallocated encoding, so not possible */
5245             assert(false);
5246             break;
5247         case 6:
5248             /* min_EL EL3 */
5249             mask = PL3_RW;
5250             break;
5251         case 7:
5252             /* min_EL EL1, secure mode only (we don't check the latter) */
5253             mask = PL1_RW;
5254             break;
5255         default:
5256             /* broken reginfo with out-of-range opc1 */
5257             assert(false);
5258             break;
5259         }
5260         /* assert our permissions are not too lax (stricter is fine) */
5261         assert((r->access & ~mask) == 0);
5262     }
5263
5264     /* Check that the register definition has enough info to handle
5265      * reads and writes if they are permitted.
5266      */
5267     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
5268         if (r->access & PL3_R) {
5269             assert((r->fieldoffset ||
5270                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5271                    r->readfn);
5272         }
5273         if (r->access & PL3_W) {
5274             assert((r->fieldoffset ||
5275                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5276                    r->writefn);
5277         }
5278     }
5279     /* Bad type field probably means missing sentinel at end of reg list */
5280     assert(cptype_valid(r->type));
5281     for (crm = crmmin; crm <= crmmax; crm++) {
5282         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
5283             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
5284                 for (state = ARM_CP_STATE_AA32;
5285                      state <= ARM_CP_STATE_AA64; state++) {
5286                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
5287                         continue;
5288                     }
5289                     if (state == ARM_CP_STATE_AA32) {
5290                         /* Under AArch32 CP registers can be common
5291                          * (same for secure and non-secure world) or banked.
5292                          */
5293                         switch (r->secure) {
5294                         case ARM_CP_SECSTATE_S:
5295                         case ARM_CP_SECSTATE_NS:
5296                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5297                                                    r->secure, crm, opc1, opc2);
5298                             break;
5299                         default:
5300                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5301                                                    ARM_CP_SECSTATE_S,
5302                                                    crm, opc1, opc2);
5303                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5304                                                    ARM_CP_SECSTATE_NS,
5305                                                    crm, opc1, opc2);
5306                             break;
5307                         }
5308                     } else {
5309                         /* AArch64 registers get mapped to non-secure instance
5310                          * of AArch32 */
5311                         add_cpreg_to_hashtable(cpu, r, opaque, state,
5312                                                ARM_CP_SECSTATE_NS,
5313                                                crm, opc1, opc2);
5314                     }
5315                 }
5316             }
5317         }
5318     }
5319 }
5320
5321 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
5322                                     const ARMCPRegInfo *regs, void *opaque)
5323 {
5324     /* Define a whole list of registers */
5325     const ARMCPRegInfo *r;
5326     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
5327         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
5328     }
5329 }
5330
5331 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
5332 {
5333     return g_hash_table_lookup(cpregs, &encoded_cp);
5334 }
5335
5336 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
5337                          uint64_t value)
5338 {
5339     /* Helper coprocessor write function for write-ignore registers */
5340 }
5341
5342 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
5343 {
5344     /* Helper coprocessor write function for read-as-zero registers */
5345     return 0;
5346 }
5347
5348 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
5349 {
5350     /* Helper coprocessor reset function for do-nothing-on-reset registers */
5351 }
5352
5353 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
5354 {
5355     /* Return true if it is not valid for us to switch to
5356      * this CPU mode (ie all the UNPREDICTABLE cases in
5357      * the ARM ARM CPSRWriteByInstr pseudocode).
5358      */
5359
5360     /* Changes to or from Hyp via MSR and CPS are illegal. */
5361     if (write_type == CPSRWriteByInstr &&
5362         ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||
5363          mode == ARM_CPU_MODE_HYP)) {
5364         return 1;
5365     }
5366
5367     switch (mode) {
5368     case ARM_CPU_MODE_USR:
5369         return 0;
5370     case ARM_CPU_MODE_SYS:
5371     case ARM_CPU_MODE_SVC:
5372     case ARM_CPU_MODE_ABT:
5373     case ARM_CPU_MODE_UND:
5374     case ARM_CPU_MODE_IRQ:
5375     case ARM_CPU_MODE_FIQ:
5376         /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
5377          * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
5378          */
5379         /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
5380          * and CPS are treated as illegal mode changes.
5381          */
5382         if (write_type == CPSRWriteByInstr &&
5383             (env->cp15.hcr_el2 & HCR_TGE) &&
5384             (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON &&
5385             !arm_is_secure_below_el3(env)) {
5386             return 1;
5387         }
5388         return 0;
5389     case ARM_CPU_MODE_HYP:
5390         return !arm_feature(env, ARM_FEATURE_EL2)
5391             || arm_current_el(env) < 2 || arm_is_secure(env);
5392     case ARM_CPU_MODE_MON:
5393         return arm_current_el(env) < 3;
5394     default:
5395         return 1;
5396     }
5397 }
5398
5399 uint32_t cpsr_read(CPUARMState *env)
5400 {
5401     int ZF;
5402     ZF = (env->ZF == 0);
5403     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
5404         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
5405         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
5406         | ((env->condexec_bits & 0xfc) << 8)
5407         | (env->GE << 16) | (env->daif & CPSR_AIF);
5408 }
5409
5410 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
5411                 CPSRWriteType write_type)
5412 {
5413     uint32_t changed_daif;
5414
5415     if (mask & CPSR_NZCV) {
5416         env->ZF = (~val) & CPSR_Z;
5417         env->NF = val;
5418         env->CF = (val >> 29) & 1;
5419         env->VF = (val << 3) & 0x80000000;
5420     }
5421     if (mask & CPSR_Q)
5422         env->QF = ((val & CPSR_Q) != 0);
5423     if (mask & CPSR_T)
5424         env->thumb = ((val & CPSR_T) != 0);
5425     if (mask & CPSR_IT_0_1) {
5426         env->condexec_bits &= ~3;
5427         env->condexec_bits |= (val >> 25) & 3;
5428     }
5429     if (mask & CPSR_IT_2_7) {
5430         env->condexec_bits &= 3;
5431         env->condexec_bits |= (val >> 8) & 0xfc;
5432     }
5433     if (mask & CPSR_GE) {
5434         env->GE = (val >> 16) & 0xf;
5435     }
5436
5437     /* In a V7 implementation that includes the security extensions but does
5438      * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5439      * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5440      * bits respectively.
5441      *
5442      * In a V8 implementation, it is permitted for privileged software to
5443      * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5444      */
5445     if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) &&
5446         arm_feature(env, ARM_FEATURE_EL3) &&
5447         !arm_feature(env, ARM_FEATURE_EL2) &&
5448         !arm_is_secure(env)) {
5449
5450         changed_daif = (env->daif ^ val) & mask;
5451
5452         if (changed_daif & CPSR_A) {
5453             /* Check to see if we are allowed to change the masking of async
5454              * abort exceptions from a non-secure state.
5455              */
5456             if (!(env->cp15.scr_el3 & SCR_AW)) {
5457                 qemu_log_mask(LOG_GUEST_ERROR,
5458                               "Ignoring attempt to switch CPSR_A flag from "
5459                               "non-secure world with SCR.AW bit clear\n");
5460                 mask &= ~CPSR_A;
5461             }
5462         }
5463
5464         if (changed_daif & CPSR_F) {
5465             /* Check to see if we are allowed to change the masking of FIQ
5466              * exceptions from a non-secure state.
5467              */
5468             if (!(env->cp15.scr_el3 & SCR_FW)) {
5469                 qemu_log_mask(LOG_GUEST_ERROR,
5470                               "Ignoring attempt to switch CPSR_F flag from "
5471                               "non-secure world with SCR.FW bit clear\n");
5472                 mask &= ~CPSR_F;
5473             }
5474
5475             /* Check whether non-maskable FIQ (NMFI) support is enabled.
5476              * If this bit is set software is not allowed to mask
5477              * FIQs, but is allowed to set CPSR_F to 0.
5478              */
5479             if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
5480                 (val & CPSR_F)) {
5481                 qemu_log_mask(LOG_GUEST_ERROR,
5482                               "Ignoring attempt to enable CPSR_F flag "
5483                               "(non-maskable FIQ [NMFI] support enabled)\n");
5484                 mask &= ~CPSR_F;
5485             }
5486         }
5487     }
5488
5489     env->daif &= ~(CPSR_AIF & mask);
5490     env->daif |= val & CPSR_AIF & mask;
5491
5492     if (write_type != CPSRWriteRaw &&
5493         (env->uncached_cpsr & CPSR_M) != CPSR_USER &&
5494         ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
5495         if (bad_mode_switch(env, val & CPSR_M, write_type)) {
5496             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
5497              * v7, and has defined behaviour in v8:
5498              *  + leave CPSR.M untouched
5499              *  + allow changes to the other CPSR fields
5500              *  + set PSTATE.IL
5501              * For user changes via the GDB stub, we don't set PSTATE.IL,
5502              * as this would be unnecessarily harsh for a user error.
5503              */
5504             mask &= ~CPSR_M;
5505             if (write_type != CPSRWriteByGDBStub &&
5506                 arm_feature(env, ARM_FEATURE_V8)) {
5507                 mask |= CPSR_IL;
5508                 val |= CPSR_IL;
5509             }
5510         } else {
5511             switch_mode(env, val & CPSR_M);
5512         }
5513     }
5514     mask &= ~CACHED_CPSR_BITS;
5515     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
5516 }
5517
5518 /* Sign/zero extend */
5519 uint32_t HELPER(sxtb16)(uint32_t x)
5520 {
5521     uint32_t res;
5522     res = (uint16_t)(int8_t)x;
5523     res |= (uint32_t)(int8_t)(x >> 16) << 16;
5524     return res;
5525 }
5526
5527 uint32_t HELPER(uxtb16)(uint32_t x)
5528 {
5529     uint32_t res;
5530     res = (uint16_t)(uint8_t)x;
5531     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
5532     return res;
5533 }
5534
5535 uint32_t HELPER(clz)(uint32_t x)
5536 {
5537     return clz32(x);
5538 }
5539
5540 int32_t HELPER(sdiv)(int32_t num, int32_t den)
5541 {
5542     if (den == 0)
5543       return 0;
5544     if (num == INT_MIN && den == -1)
5545       return INT_MIN;
5546     return num / den;
5547 }
5548
5549 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
5550 {
5551     if (den == 0)
5552       return 0;
5553     return num / den;
5554 }
5555
5556 uint32_t HELPER(rbit)(uint32_t x)
5557 {
5558     return revbit32(x);
5559 }
5560
5561 #if defined(CONFIG_USER_ONLY)
5562
5563 /* These should probably raise undefined insn exceptions.  */
5564 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
5565 {
5566     ARMCPU *cpu = arm_env_get_cpu(env);
5567
5568     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
5569 }
5570
5571 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
5572 {
5573     ARMCPU *cpu = arm_env_get_cpu(env);
5574
5575     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
5576     return 0;
5577 }
5578
5579 void switch_mode(CPUARMState *env, int mode)
5580 {
5581     ARMCPU *cpu = arm_env_get_cpu(env);
5582
5583     if (mode != ARM_CPU_MODE_USR) {
5584         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
5585     }
5586 }
5587
5588 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5589                                  uint32_t cur_el, bool secure)
5590 {
5591     return 1;
5592 }
5593
5594 void aarch64_sync_64_to_32(CPUARMState *env)
5595 {
5596     g_assert_not_reached();
5597 }
5598
5599 #else
5600
5601 void switch_mode(CPUARMState *env, int mode)
5602 {
5603     int old_mode;
5604     int i;
5605
5606     old_mode = env->uncached_cpsr & CPSR_M;
5607     if (mode == old_mode)
5608         return;
5609
5610     if (old_mode == ARM_CPU_MODE_FIQ) {
5611         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
5612         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
5613     } else if (mode == ARM_CPU_MODE_FIQ) {
5614         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
5615         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
5616     }
5617
5618     i = bank_number(old_mode);
5619     env->banked_r13[i] = env->regs[13];
5620     env->banked_r14[i] = env->regs[14];
5621     env->banked_spsr[i] = env->spsr;
5622
5623     i = bank_number(mode);
5624     env->regs[13] = env->banked_r13[i];
5625     env->regs[14] = env->banked_r14[i];
5626     env->spsr = env->banked_spsr[i];
5627 }
5628
5629 /* Physical Interrupt Target EL Lookup Table
5630  *
5631  * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5632  *
5633  * The below multi-dimensional table is used for looking up the target
5634  * exception level given numerous condition criteria.  Specifically, the
5635  * target EL is based on SCR and HCR routing controls as well as the
5636  * currently executing EL and secure state.
5637  *
5638  *    Dimensions:
5639  *    target_el_table[2][2][2][2][2][4]
5640  *                    |  |  |  |  |  +--- Current EL
5641  *                    |  |  |  |  +------ Non-secure(0)/Secure(1)
5642  *                    |  |  |  +--------- HCR mask override
5643  *                    |  |  +------------ SCR exec state control
5644  *                    |  +--------------- SCR mask override
5645  *                    +------------------ 32-bit(0)/64-bit(1) EL3
5646  *
5647  *    The table values are as such:
5648  *    0-3 = EL0-EL3
5649  *     -1 = Cannot occur
5650  *
5651  * The ARM ARM target EL table includes entries indicating that an "exception
5652  * is not taken".  The two cases where this is applicable are:
5653  *    1) An exception is taken from EL3 but the SCR does not have the exception
5654  *    routed to EL3.
5655  *    2) An exception is taken from EL2 but the HCR does not have the exception
5656  *    routed to EL2.
5657  * In these two cases, the below table contain a target of EL1.  This value is
5658  * returned as it is expected that the consumer of the table data will check
5659  * for "target EL >= current EL" to ensure the exception is not taken.
5660  *
5661  *            SCR     HCR
5662  *         64  EA     AMO                 From
5663  *        BIT IRQ     IMO      Non-secure         Secure
5664  *        EL3 FIQ  RW FMO   EL0 EL1 EL2 EL3   EL0 EL1 EL2 EL3
5665  */
5666 static const int8_t target_el_table[2][2][2][2][2][4] = {
5667     {{{{/* 0   0   0   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5668        {/* 0   0   0   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},
5669       {{/* 0   0   1   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5670        {/* 0   0   1   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},},
5671      {{{/* 0   1   0   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5672        {/* 0   1   0   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},
5673       {{/* 0   1   1   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5674        {/* 0   1   1   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},},},
5675     {{{{/* 1   0   0   0 */{ 1,  1,  2, -1 },{ 1,  1, -1,  1 },},
5676        {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},
5677       {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1, -1,  1 },},
5678        {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},},
5679      {{{/* 1   1   0   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5680        {/* 1   1   0   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},
5681       {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5682        {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},},},
5683 };
5684
5685 /*
5686  * Determine the target EL for physical exceptions
5687  */
5688 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5689                                  uint32_t cur_el, bool secure)
5690 {
5691     CPUARMState *env = cs->env_ptr;
5692     int rw;
5693     int scr;
5694     int hcr;
5695     int target_el;
5696     /* Is the highest EL AArch64? */
5697     int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
5698
5699     if (arm_feature(env, ARM_FEATURE_EL3)) {
5700         rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
5701     } else {
5702         /* Either EL2 is the highest EL (and so the EL2 register width
5703          * is given by is64); or there is no EL2 or EL3, in which case
5704          * the value of 'rw' does not affect the table lookup anyway.
5705          */
5706         rw = is64;
5707     }
5708
5709     switch (excp_idx) {
5710     case EXCP_IRQ:
5711         scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
5712         hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
5713         break;
5714     case EXCP_FIQ:
5715         scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
5716         hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
5717         break;
5718     default:
5719         scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
5720         hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
5721         break;
5722     };
5723
5724     /* If HCR.TGE is set then HCR is treated as being 1 */
5725     hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
5726
5727     /* Perform a table-lookup for the target EL given the current state */
5728     target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
5729
5730     assert(target_el > 0);
5731
5732     return target_el;
5733 }
5734
5735 static void v7m_push(CPUARMState *env, uint32_t val)
5736 {
5737     CPUState *cs = CPU(arm_env_get_cpu(env));
5738
5739     env->regs[13] -= 4;
5740     stl_phys(cs->as, env->regs[13], val);
5741 }
5742
5743 static uint32_t v7m_pop(CPUARMState *env)
5744 {
5745     CPUState *cs = CPU(arm_env_get_cpu(env));
5746     uint32_t val;
5747
5748     val = ldl_phys(cs->as, env->regs[13]);
5749     env->regs[13] += 4;
5750     return val;
5751 }
5752
5753 /* Switch to V7M main or process stack pointer.  */
5754 static void switch_v7m_sp(CPUARMState *env, int process)
5755 {
5756     uint32_t tmp;
5757     if (env->v7m.current_sp != process) {
5758         tmp = env->v7m.other_sp;
5759         env->v7m.other_sp = env->regs[13];
5760         env->regs[13] = tmp;
5761         env->v7m.current_sp = process;
5762     }
5763 }
5764
5765 static void do_v7m_exception_exit(CPUARMState *env)
5766 {
5767     uint32_t type;
5768     uint32_t xpsr;
5769
5770     type = env->regs[15];
5771     if (env->v7m.exception != 0)
5772         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
5773
5774     /* Switch to the target stack.  */
5775     switch_v7m_sp(env, (type & 4) != 0);
5776     /* Pop registers.  */
5777     env->regs[0] = v7m_pop(env);
5778     env->regs[1] = v7m_pop(env);
5779     env->regs[2] = v7m_pop(env);
5780     env->regs[3] = v7m_pop(env);
5781     env->regs[12] = v7m_pop(env);
5782     env->regs[14] = v7m_pop(env);
5783     env->regs[15] = v7m_pop(env);
5784     if (env->regs[15] & 1) {
5785         qemu_log_mask(LOG_GUEST_ERROR,
5786                       "M profile return from interrupt with misaligned "
5787                       "PC is UNPREDICTABLE\n");
5788         /* Actual hardware seems to ignore the lsbit, and there are several
5789          * RTOSes out there which incorrectly assume the r15 in the stack
5790          * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
5791          */
5792         env->regs[15] &= ~1U;
5793     }
5794     xpsr = v7m_pop(env);
5795     xpsr_write(env, xpsr, 0xfffffdff);
5796     /* Undo stack alignment.  */
5797     if (xpsr & 0x200)
5798         env->regs[13] |= 4;
5799     /* ??? The exception return type specifies Thread/Handler mode.  However
5800        this is also implied by the xPSR value. Not sure what to do
5801        if there is a mismatch.  */
5802     /* ??? Likewise for mismatches between the CONTROL register and the stack
5803        pointer.  */
5804 }
5805
5806 void arm_v7m_cpu_do_interrupt(CPUState *cs)
5807 {
5808     ARMCPU *cpu = ARM_CPU(cs);
5809     CPUARMState *env = &cpu->env;
5810     uint32_t xpsr = xpsr_read(env);
5811     uint32_t lr;
5812     uint32_t addr;
5813
5814     arm_log_exception(cs->exception_index);
5815
5816     lr = 0xfffffff1;
5817     if (env->v7m.current_sp)
5818         lr |= 4;
5819     if (env->v7m.exception == 0)
5820         lr |= 8;
5821
5822     /* For exceptions we just mark as pending on the NVIC, and let that
5823        handle it.  */
5824     /* TODO: Need to escalate if the current priority is higher than the
5825        one we're raising.  */
5826     switch (cs->exception_index) {
5827     case EXCP_UDEF:
5828         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
5829         return;
5830     case EXCP_SWI:
5831         /* The PC already points to the next instruction.  */
5832         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
5833         return;
5834     case EXCP_PREFETCH_ABORT:
5835     case EXCP_DATA_ABORT:
5836         /* TODO: if we implemented the MPU registers, this is where we
5837          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
5838          */
5839         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
5840         return;
5841     case EXCP_BKPT:
5842         if (semihosting_enabled()) {
5843             int nr;
5844             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
5845             if (nr == 0xab) {
5846                 env->regs[15] += 2;
5847                 qemu_log_mask(CPU_LOG_INT,
5848                               "...handling as semihosting call 0x%x\n",
5849                               env->regs[0]);
5850                 env->regs[0] = do_arm_semihosting(env);
5851                 return;
5852             }
5853         }
5854         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
5855         return;
5856     case EXCP_IRQ:
5857         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
5858         break;
5859     case EXCP_EXCEPTION_EXIT:
5860         do_v7m_exception_exit(env);
5861         return;
5862     default:
5863         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5864         return; /* Never happens.  Keep compiler happy.  */
5865     }
5866
5867     /* Align stack pointer.  */
5868     /* ??? Should only do this if Configuration Control Register
5869        STACKALIGN bit is set.  */
5870     if (env->regs[13] & 4) {
5871         env->regs[13] -= 4;
5872         xpsr |= 0x200;
5873     }
5874     /* Switch to the handler mode.  */
5875     v7m_push(env, xpsr);
5876     v7m_push(env, env->regs[15]);
5877     v7m_push(env, env->regs[14]);
5878     v7m_push(env, env->regs[12]);
5879     v7m_push(env, env->regs[3]);
5880     v7m_push(env, env->regs[2]);
5881     v7m_push(env, env->regs[1]);
5882     v7m_push(env, env->regs[0]);
5883     switch_v7m_sp(env, 0);
5884     /* Clear IT bits */
5885     env->condexec_bits = 0;
5886     env->regs[14] = lr;
5887     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
5888     env->regs[15] = addr & 0xfffffffe;
5889     env->thumb = addr & 1;
5890 }
5891
5892 /* Function used to synchronize QEMU's AArch64 register set with AArch32
5893  * register set.  This is necessary when switching between AArch32 and AArch64
5894  * execution state.
5895  */
5896 void aarch64_sync_32_to_64(CPUARMState *env)
5897 {
5898     int i;
5899     uint32_t mode = env->uncached_cpsr & CPSR_M;
5900
5901     /* We can blanket copy R[0:7] to X[0:7] */
5902     for (i = 0; i < 8; i++) {
5903         env->xregs[i] = env->regs[i];
5904     }
5905
5906     /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
5907      * Otherwise, they come from the banked user regs.
5908      */
5909     if (mode == ARM_CPU_MODE_FIQ) {
5910         for (i = 8; i < 13; i++) {
5911             env->xregs[i] = env->usr_regs[i - 8];
5912         }
5913     } else {
5914         for (i = 8; i < 13; i++) {
5915             env->xregs[i] = env->regs[i];
5916         }
5917     }
5918
5919     /* Registers x13-x23 are the various mode SP and FP registers. Registers
5920      * r13 and r14 are only copied if we are in that mode, otherwise we copy
5921      * from the mode banked register.
5922      */
5923     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5924         env->xregs[13] = env->regs[13];
5925         env->xregs[14] = env->regs[14];
5926     } else {
5927         env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
5928         /* HYP is an exception in that it is copied from r14 */
5929         if (mode == ARM_CPU_MODE_HYP) {
5930             env->xregs[14] = env->regs[14];
5931         } else {
5932             env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
5933         }
5934     }
5935
5936     if (mode == ARM_CPU_MODE_HYP) {
5937         env->xregs[15] = env->regs[13];
5938     } else {
5939         env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
5940     }
5941
5942     if (mode == ARM_CPU_MODE_IRQ) {
5943         env->xregs[16] = env->regs[14];
5944         env->xregs[17] = env->regs[13];
5945     } else {
5946         env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
5947         env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
5948     }
5949
5950     if (mode == ARM_CPU_MODE_SVC) {
5951         env->xregs[18] = env->regs[14];
5952         env->xregs[19] = env->regs[13];
5953     } else {
5954         env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
5955         env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
5956     }
5957
5958     if (mode == ARM_CPU_MODE_ABT) {
5959         env->xregs[20] = env->regs[14];
5960         env->xregs[21] = env->regs[13];
5961     } else {
5962         env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
5963         env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
5964     }
5965
5966     if (mode == ARM_CPU_MODE_UND) {
5967         env->xregs[22] = env->regs[14];
5968         env->xregs[23] = env->regs[13];
5969     } else {
5970         env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
5971         env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
5972     }
5973
5974     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5975      * mode, then we can copy from r8-r14.  Otherwise, we copy from the
5976      * FIQ bank for r8-r14.
5977      */
5978     if (mode == ARM_CPU_MODE_FIQ) {
5979         for (i = 24; i < 31; i++) {
5980             env->xregs[i] = env->regs[i - 16];   /* X[24:30] <- R[8:14] */
5981         }
5982     } else {
5983         for (i = 24; i < 29; i++) {
5984             env->xregs[i] = env->fiq_regs[i - 24];
5985         }
5986         env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
5987         env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
5988     }
5989
5990     env->pc = env->regs[15];
5991 }
5992
5993 /* Function used to synchronize QEMU's AArch32 register set with AArch64
5994  * register set.  This is necessary when switching between AArch32 and AArch64
5995  * execution state.
5996  */
5997 void aarch64_sync_64_to_32(CPUARMState *env)
5998 {
5999     int i;
6000     uint32_t mode = env->uncached_cpsr & CPSR_M;
6001
6002     /* We can blanket copy X[0:7] to R[0:7] */
6003     for (i = 0; i < 8; i++) {
6004         env->regs[i] = env->xregs[i];
6005     }
6006
6007     /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
6008      * Otherwise, we copy x8-x12 into the banked user regs.
6009      */
6010     if (mode == ARM_CPU_MODE_FIQ) {
6011         for (i = 8; i < 13; i++) {
6012             env->usr_regs[i - 8] = env->xregs[i];
6013         }
6014     } else {
6015         for (i = 8; i < 13; i++) {
6016             env->regs[i] = env->xregs[i];
6017         }
6018     }
6019
6020     /* Registers r13 & r14 depend on the current mode.
6021      * If we are in a given mode, we copy the corresponding x registers to r13
6022      * and r14.  Otherwise, we copy the x register to the banked r13 and r14
6023      * for the mode.
6024      */
6025     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
6026         env->regs[13] = env->xregs[13];
6027         env->regs[14] = env->xregs[14];
6028     } else {
6029         env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
6030
6031         /* HYP is an exception in that it does not have its own banked r14 but
6032          * shares the USR r14
6033          */
6034         if (mode == ARM_CPU_MODE_HYP) {
6035             env->regs[14] = env->xregs[14];
6036         } else {
6037             env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
6038         }
6039     }
6040
6041     if (mode == ARM_CPU_MODE_HYP) {
6042         env->regs[13] = env->xregs[15];
6043     } else {
6044         env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
6045     }
6046
6047     if (mode == ARM_CPU_MODE_IRQ) {
6048         env->regs[14] = env->xregs[16];
6049         env->regs[13] = env->xregs[17];
6050     } else {
6051         env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
6052         env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
6053     }
6054
6055     if (mode == ARM_CPU_MODE_SVC) {
6056         env->regs[14] = env->xregs[18];
6057         env->regs[13] = env->xregs[19];
6058     } else {
6059         env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
6060         env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
6061     }
6062
6063     if (mode == ARM_CPU_MODE_ABT) {
6064         env->regs[14] = env->xregs[20];
6065         env->regs[13] = env->xregs[21];
6066     } else {
6067         env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
6068         env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
6069     }
6070
6071     if (mode == ARM_CPU_MODE_UND) {
6072         env->regs[14] = env->xregs[22];
6073         env->regs[13] = env->xregs[23];
6074     } else {
6075         env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
6076         env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
6077     }
6078
6079     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
6080      * mode, then we can copy to r8-r14.  Otherwise, we copy to the
6081      * FIQ bank for r8-r14.
6082      */
6083     if (mode == ARM_CPU_MODE_FIQ) {
6084         for (i = 24; i < 31; i++) {
6085             env->regs[i - 16] = env->xregs[i];   /* X[24:30] -> R[8:14] */
6086         }
6087     } else {
6088         for (i = 24; i < 29; i++) {
6089             env->fiq_regs[i - 24] = env->xregs[i];
6090         }
6091         env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
6092         env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
6093     }
6094
6095     env->regs[15] = env->pc;
6096 }
6097
6098 static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
6099 {
6100     ARMCPU *cpu = ARM_CPU(cs);
6101     CPUARMState *env = &cpu->env;
6102     uint32_t addr;
6103     uint32_t mask;
6104     int new_mode;
6105     uint32_t offset;
6106     uint32_t moe;
6107
6108     /* If this is a debug exception we must update the DBGDSCR.MOE bits */
6109     switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
6110     case EC_BREAKPOINT:
6111     case EC_BREAKPOINT_SAME_EL:
6112         moe = 1;
6113         break;
6114     case EC_WATCHPOINT:
6115     case EC_WATCHPOINT_SAME_EL:
6116         moe = 10;
6117         break;
6118     case EC_AA32_BKPT:
6119         moe = 3;
6120         break;
6121     case EC_VECTORCATCH:
6122         moe = 5;
6123         break;
6124     default:
6125         moe = 0;
6126         break;
6127     }
6128
6129     if (moe) {
6130         env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
6131     }
6132
6133     /* TODO: Vectored interrupt controller.  */
6134     switch (cs->exception_index) {
6135     case EXCP_UDEF:
6136         new_mode = ARM_CPU_MODE_UND;
6137         addr = 0x04;
6138         mask = CPSR_I;
6139         if (env->thumb)
6140             offset = 2;
6141         else
6142             offset = 4;
6143         break;
6144     case EXCP_SWI:
6145         new_mode = ARM_CPU_MODE_SVC;
6146         addr = 0x08;
6147         mask = CPSR_I;
6148         /* The PC already points to the next instruction.  */
6149         offset = 0;
6150         break;
6151     case EXCP_BKPT:
6152         env->exception.fsr = 2;
6153         /* Fall through to prefetch abort.  */
6154     case EXCP_PREFETCH_ABORT:
6155         A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
6156         A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
6157         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
6158                       env->exception.fsr, (uint32_t)env->exception.vaddress);
6159         new_mode = ARM_CPU_MODE_ABT;
6160         addr = 0x0c;
6161         mask = CPSR_A | CPSR_I;
6162         offset = 4;
6163         break;
6164     case EXCP_DATA_ABORT:
6165         A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
6166         A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
6167         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
6168                       env->exception.fsr,
6169                       (uint32_t)env->exception.vaddress);
6170         new_mode = ARM_CPU_MODE_ABT;
6171         addr = 0x10;
6172         mask = CPSR_A | CPSR_I;
6173         offset = 8;
6174         break;
6175     case EXCP_IRQ:
6176         new_mode = ARM_CPU_MODE_IRQ;
6177         addr = 0x18;
6178         /* Disable IRQ and imprecise data aborts.  */
6179         mask = CPSR_A | CPSR_I;
6180         offset = 4;
6181         if (env->cp15.scr_el3 & SCR_IRQ) {
6182             /* IRQ routed to monitor mode */
6183             new_mode = ARM_CPU_MODE_MON;
6184             mask |= CPSR_F;
6185         }
6186         break;
6187     case EXCP_FIQ:
6188         new_mode = ARM_CPU_MODE_FIQ;
6189         addr = 0x1c;
6190         /* Disable FIQ, IRQ and imprecise data aborts.  */
6191         mask = CPSR_A | CPSR_I | CPSR_F;
6192         if (env->cp15.scr_el3 & SCR_FIQ) {
6193             /* FIQ routed to monitor mode */
6194             new_mode = ARM_CPU_MODE_MON;
6195         }
6196         offset = 4;
6197         break;
6198     case EXCP_SMC:
6199         new_mode = ARM_CPU_MODE_MON;
6200         addr = 0x08;
6201         mask = CPSR_A | CPSR_I | CPSR_F;
6202         offset = 0;
6203         break;
6204     default:
6205         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
6206         return; /* Never happens.  Keep compiler happy.  */
6207     }
6208
6209     if (new_mode == ARM_CPU_MODE_MON) {
6210         addr += env->cp15.mvbar;
6211     } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
6212         /* High vectors. When enabled, base address cannot be remapped. */
6213         addr += 0xffff0000;
6214     } else {
6215         /* ARM v7 architectures provide a vector base address register to remap
6216          * the interrupt vector table.
6217          * This register is only followed in non-monitor mode, and is banked.
6218          * Note: only bits 31:5 are valid.
6219          */
6220         addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
6221     }
6222
6223     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
6224         env->cp15.scr_el3 &= ~SCR_NS;
6225     }
6226
6227     switch_mode (env, new_mode);
6228     /* For exceptions taken to AArch32 we must clear the SS bit in both
6229      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
6230      */
6231     env->uncached_cpsr &= ~PSTATE_SS;
6232     env->spsr = cpsr_read(env);
6233     /* Clear IT bits.  */
6234     env->condexec_bits = 0;
6235     /* Switch to the new mode, and to the correct instruction set.  */
6236     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
6237     env->daif |= mask;
6238     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
6239      * and we should just guard the thumb mode on V4 */
6240     if (arm_feature(env, ARM_FEATURE_V4T)) {
6241         env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
6242     }
6243     env->regs[14] = env->regs[15] + offset;
6244     env->regs[15] = addr;
6245 }
6246
6247 /* Handle exception entry to a target EL which is using AArch64 */
6248 static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
6249 {
6250     ARMCPU *cpu = ARM_CPU(cs);
6251     CPUARMState *env = &cpu->env;
6252     unsigned int new_el = env->exception.target_el;
6253     target_ulong addr = env->cp15.vbar_el[new_el];
6254     unsigned int new_mode = aarch64_pstate_mode(new_el, true);
6255
6256     if (arm_current_el(env) < new_el) {
6257         /* Entry vector offset depends on whether the implemented EL
6258          * immediately lower than the target level is using AArch32 or AArch64
6259          */
6260         bool is_aa64;
6261
6262         switch (new_el) {
6263         case 3:
6264             is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
6265             break;
6266         case 2:
6267             is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0;
6268             break;
6269         case 1:
6270             is_aa64 = is_a64(env);
6271             break;
6272         default:
6273             g_assert_not_reached();
6274         }
6275
6276         if (is_aa64) {
6277             addr += 0x400;
6278         } else {
6279             addr += 0x600;
6280         }
6281     } else if (pstate_read(env) & PSTATE_SP) {
6282         addr += 0x200;
6283     }
6284
6285     switch (cs->exception_index) {
6286     case EXCP_PREFETCH_ABORT:
6287     case EXCP_DATA_ABORT:
6288         env->cp15.far_el[new_el] = env->exception.vaddress;
6289         qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
6290                       env->cp15.far_el[new_el]);
6291         /* fall through */
6292     case EXCP_BKPT:
6293     case EXCP_UDEF:
6294     case EXCP_SWI:
6295     case EXCP_HVC:
6296     case EXCP_HYP_TRAP:
6297     case EXCP_SMC:
6298         env->cp15.esr_el[new_el] = env->exception.syndrome;
6299         break;
6300     case EXCP_IRQ:
6301     case EXCP_VIRQ:
6302         addr += 0x80;
6303         break;
6304     case EXCP_FIQ:
6305     case EXCP_VFIQ:
6306         addr += 0x100;
6307         break;
6308     case EXCP_SEMIHOST:
6309         qemu_log_mask(CPU_LOG_INT,
6310                       "...handling as semihosting call 0x%" PRIx64 "\n",
6311                       env->xregs[0]);
6312         env->xregs[0] = do_arm_semihosting(env);
6313         return;
6314     default:
6315         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
6316     }
6317
6318     if (is_a64(env)) {
6319         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env);
6320         aarch64_save_sp(env, arm_current_el(env));
6321         env->elr_el[new_el] = env->pc;
6322     } else {
6323         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
6324         if (!env->thumb) {
6325             env->cp15.esr_el[new_el] |= 1 << 25;
6326         }
6327         env->elr_el[new_el] = env->regs[15];
6328
6329         aarch64_sync_32_to_64(env);
6330
6331         env->condexec_bits = 0;
6332     }
6333     qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
6334                   env->elr_el[new_el]);
6335
6336     pstate_write(env, PSTATE_DAIF | new_mode);
6337     env->aarch64 = 1;
6338     aarch64_restore_sp(env, new_el);
6339
6340     env->pc = addr;
6341
6342     qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
6343                   new_el, env->pc, pstate_read(env));
6344 }
6345
6346 static inline bool check_for_semihosting(CPUState *cs)
6347 {
6348     /* Check whether this exception is a semihosting call; if so
6349      * then handle it and return true; otherwise return false.
6350      */
6351     ARMCPU *cpu = ARM_CPU(cs);
6352     CPUARMState *env = &cpu->env;
6353
6354     if (is_a64(env)) {
6355         if (cs->exception_index == EXCP_SEMIHOST) {
6356             /* This is always the 64-bit semihosting exception.
6357              * The "is this usermode" and "is semihosting enabled"
6358              * checks have been done at translate time.
6359              */
6360             qemu_log_mask(CPU_LOG_INT,
6361                           "...handling as semihosting call 0x%" PRIx64 "\n",
6362                           env->xregs[0]);
6363             env->xregs[0] = do_arm_semihosting(env);
6364             return true;
6365         }
6366         return false;
6367     } else {
6368         uint32_t imm;
6369
6370         /* Only intercept calls from privileged modes, to provide some
6371          * semblance of security.
6372          */
6373         if (!semihosting_enabled() ||
6374             ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)) {
6375             return false;
6376         }
6377
6378         switch (cs->exception_index) {
6379         case EXCP_SWI:
6380             /* Check for semihosting interrupt.  */
6381             if (env->thumb) {
6382                 imm = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
6383                     & 0xff;
6384                 if (imm == 0xab) {
6385                     break;
6386                 }
6387             } else {
6388                 imm = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
6389                     & 0xffffff;
6390                 if (imm == 0x123456) {
6391                     break;
6392                 }
6393             }
6394             return false;
6395         case EXCP_BKPT:
6396             /* See if this is a semihosting syscall.  */
6397             if (env->thumb) {
6398                 imm = arm_lduw_code(env, env->regs[15], env->bswap_code)
6399                     & 0xff;
6400                 if (imm == 0xab) {
6401                     env->regs[15] += 2;
6402                     break;
6403                 }
6404             }
6405             return false;
6406         default:
6407             return false;
6408         }
6409
6410         qemu_log_mask(CPU_LOG_INT,
6411                       "...handling as semihosting call 0x%x\n",
6412                       env->regs[0]);
6413         env->regs[0] = do_arm_semihosting(env);
6414         return true;
6415     }
6416 }
6417
6418 /* Handle a CPU exception for A and R profile CPUs.
6419  * Do any appropriate logging, handle PSCI calls, and then hand off
6420  * to the AArch64-entry or AArch32-entry function depending on the
6421  * target exception level's register width.
6422  */
6423 void arm_cpu_do_interrupt(CPUState *cs)
6424 {
6425     ARMCPU *cpu = ARM_CPU(cs);
6426     CPUARMState *env = &cpu->env;
6427     unsigned int new_el = env->exception.target_el;
6428
6429     assert(!IS_M(env));
6430
6431     arm_log_exception(cs->exception_index);
6432     qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
6433                   new_el);
6434     if (qemu_loglevel_mask(CPU_LOG_INT)
6435         && !excp_is_internal(cs->exception_index)) {
6436         qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n",
6437                       env->exception.syndrome >> ARM_EL_EC_SHIFT,
6438                       env->exception.syndrome);
6439     }
6440
6441     if (arm_is_psci_call(cpu, cs->exception_index)) {
6442         arm_handle_psci_call(cpu);
6443         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
6444         return;
6445     }
6446
6447     /* Semihosting semantics depend on the register width of the
6448      * code that caused the exception, not the target exception level,
6449      * so must be handled here.
6450      */
6451     if (check_for_semihosting(cs)) {
6452         return;
6453     }
6454
6455     assert(!excp_is_internal(cs->exception_index));
6456     if (arm_el_is_aa64(env, new_el)) {
6457         arm_cpu_do_interrupt_aarch64(cs);
6458     } else {
6459         arm_cpu_do_interrupt_aarch32(cs);
6460     }
6461
6462     if (!kvm_enabled()) {
6463         cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
6464     }
6465 }
6466
6467 /* Return the exception level which controls this address translation regime */
6468 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
6469 {
6470     switch (mmu_idx) {
6471     case ARMMMUIdx_S2NS:
6472     case ARMMMUIdx_S1E2:
6473         return 2;
6474     case ARMMMUIdx_S1E3:
6475         return 3;
6476     case ARMMMUIdx_S1SE0:
6477         return arm_el_is_aa64(env, 3) ? 1 : 3;
6478     case ARMMMUIdx_S1SE1:
6479     case ARMMMUIdx_S1NSE0:
6480     case ARMMMUIdx_S1NSE1:
6481         return 1;
6482     default:
6483         g_assert_not_reached();
6484     }
6485 }
6486
6487 /* Return true if this address translation regime is secure */
6488 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
6489 {
6490     switch (mmu_idx) {
6491     case ARMMMUIdx_S12NSE0:
6492     case ARMMMUIdx_S12NSE1:
6493     case ARMMMUIdx_S1NSE0:
6494     case ARMMMUIdx_S1NSE1:
6495     case ARMMMUIdx_S1E2:
6496     case ARMMMUIdx_S2NS:
6497         return false;
6498     case ARMMMUIdx_S1E3:
6499     case ARMMMUIdx_S1SE0:
6500     case ARMMMUIdx_S1SE1:
6501         return true;
6502     default:
6503         g_assert_not_reached();
6504     }
6505 }
6506
6507 /* Return the SCTLR value which controls this address translation regime */
6508 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
6509 {
6510     return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
6511 }
6512
6513 /* Return true if the specified stage of address translation is disabled */
6514 static inline bool regime_translation_disabled(CPUARMState *env,
6515                                                ARMMMUIdx mmu_idx)
6516 {
6517     if (mmu_idx == ARMMMUIdx_S2NS) {
6518         return (env->cp15.hcr_el2 & HCR_VM) == 0;
6519     }
6520     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
6521 }
6522
6523 /* Return the TCR controlling this translation regime */
6524 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
6525 {
6526     if (mmu_idx == ARMMMUIdx_S2NS) {
6527         return &env->cp15.vtcr_el2;
6528     }
6529     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
6530 }
6531
6532 /* Return the TTBR associated with this translation regime */
6533 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
6534                                    int ttbrn)
6535 {
6536     if (mmu_idx == ARMMMUIdx_S2NS) {
6537         return env->cp15.vttbr_el2;
6538     }
6539     if (ttbrn == 0) {
6540         return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
6541     } else {
6542         return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
6543     }
6544 }
6545
6546 /* Return true if the translation regime is using LPAE format page tables */
6547 static inline bool regime_using_lpae_format(CPUARMState *env,
6548                                             ARMMMUIdx mmu_idx)
6549 {
6550     int el = regime_el(env, mmu_idx);
6551     if (el == 2 || arm_el_is_aa64(env, el)) {
6552         return true;
6553     }
6554     if (arm_feature(env, ARM_FEATURE_LPAE)
6555         && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
6556         return true;
6557     }
6558     return false;
6559 }
6560
6561 /* Returns true if the stage 1 translation regime is using LPAE format page
6562  * tables. Used when raising alignment exceptions, whose FSR changes depending
6563  * on whether the long or short descriptor format is in use. */
6564 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
6565 {
6566     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
6567         mmu_idx += ARMMMUIdx_S1NSE0;
6568     }
6569
6570     return regime_using_lpae_format(env, mmu_idx);
6571 }
6572
6573 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
6574 {
6575     switch (mmu_idx) {
6576     case ARMMMUIdx_S1SE0:
6577     case ARMMMUIdx_S1NSE0:
6578         return true;
6579     default:
6580         return false;
6581     case ARMMMUIdx_S12NSE0:
6582     case ARMMMUIdx_S12NSE1:
6583         g_assert_not_reached();
6584     }
6585 }
6586
6587 /* Translate section/page access permissions to page
6588  * R/W protection flags
6589  *
6590  * @env:         CPUARMState
6591  * @mmu_idx:     MMU index indicating required translation regime
6592  * @ap:          The 3-bit access permissions (AP[2:0])
6593  * @domain_prot: The 2-bit domain access permissions
6594  */
6595 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
6596                                 int ap, int domain_prot)
6597 {
6598     bool is_user = regime_is_user(env, mmu_idx);
6599
6600     if (domain_prot == 3) {
6601         return PAGE_READ | PAGE_WRITE;
6602     }
6603
6604     switch (ap) {
6605     case 0:
6606         if (arm_feature(env, ARM_FEATURE_V7)) {
6607             return 0;
6608         }
6609         switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
6610         case SCTLR_S:
6611             return is_user ? 0 : PAGE_READ;
6612         case SCTLR_R:
6613             return PAGE_READ;
6614         default:
6615             return 0;
6616         }
6617     case 1:
6618         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6619     case 2:
6620         if (is_user) {
6621             return PAGE_READ;
6622         } else {
6623             return PAGE_READ | PAGE_WRITE;
6624         }
6625     case 3:
6626         return PAGE_READ | PAGE_WRITE;
6627     case 4: /* Reserved.  */
6628         return 0;
6629     case 5:
6630         return is_user ? 0 : PAGE_READ;
6631     case 6:
6632         return PAGE_READ;
6633     case 7:
6634         if (!arm_feature(env, ARM_FEATURE_V6K)) {
6635             return 0;
6636         }
6637         return PAGE_READ;
6638     default:
6639         g_assert_not_reached();
6640     }
6641 }
6642
6643 /* Translate section/page access permissions to page
6644  * R/W protection flags.
6645  *
6646  * @ap:      The 2-bit simple AP (AP[2:1])
6647  * @is_user: TRUE if accessing from PL0
6648  */
6649 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
6650 {
6651     switch (ap) {
6652     case 0:
6653         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6654     case 1:
6655         return PAGE_READ | PAGE_WRITE;
6656     case 2:
6657         return is_user ? 0 : PAGE_READ;
6658     case 3:
6659         return PAGE_READ;
6660     default:
6661         g_assert_not_reached();
6662     }
6663 }
6664
6665 static inline int
6666 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
6667 {
6668     return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
6669 }
6670
6671 /* Translate S2 section/page access permissions to protection flags
6672  *
6673  * @env:     CPUARMState
6674  * @s2ap:    The 2-bit stage2 access permissions (S2AP)
6675  * @xn:      XN (execute-never) bit
6676  */
6677 static int get_S2prot(CPUARMState *env, int s2ap, int xn)
6678 {
6679     int prot = 0;
6680
6681     if (s2ap & 1) {
6682         prot |= PAGE_READ;
6683     }
6684     if (s2ap & 2) {
6685         prot |= PAGE_WRITE;
6686     }
6687     if (!xn) {
6688         prot |= PAGE_EXEC;
6689     }
6690     return prot;
6691 }
6692
6693 /* Translate section/page access permissions to protection flags
6694  *
6695  * @env:     CPUARMState
6696  * @mmu_idx: MMU index indicating required translation regime
6697  * @is_aa64: TRUE if AArch64
6698  * @ap:      The 2-bit simple AP (AP[2:1])
6699  * @ns:      NS (non-secure) bit
6700  * @xn:      XN (execute-never) bit
6701  * @pxn:     PXN (privileged execute-never) bit
6702  */
6703 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
6704                       int ap, int ns, int xn, int pxn)
6705 {
6706     bool is_user = regime_is_user(env, mmu_idx);
6707     int prot_rw, user_rw;
6708     bool have_wxn;
6709     int wxn = 0;
6710
6711     assert(mmu_idx != ARMMMUIdx_S2NS);
6712
6713     user_rw = simple_ap_to_rw_prot_is_user(ap, true);
6714     if (is_user) {
6715         prot_rw = user_rw;
6716     } else {
6717         prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
6718     }
6719
6720     if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
6721         return prot_rw;
6722     }
6723
6724     /* TODO have_wxn should be replaced with
6725      *   ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
6726      * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
6727      * compatible processors have EL2, which is required for [U]WXN.
6728      */
6729     have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
6730
6731     if (have_wxn) {
6732         wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
6733     }
6734
6735     if (is_aa64) {
6736         switch (regime_el(env, mmu_idx)) {
6737         case 1:
6738             if (!is_user) {
6739                 xn = pxn || (user_rw & PAGE_WRITE);
6740             }
6741             break;
6742         case 2:
6743         case 3:
6744             break;
6745         }
6746     } else if (arm_feature(env, ARM_FEATURE_V7)) {
6747         switch (regime_el(env, mmu_idx)) {
6748         case 1:
6749         case 3:
6750             if (is_user) {
6751                 xn = xn || !(user_rw & PAGE_READ);
6752             } else {
6753                 int uwxn = 0;
6754                 if (have_wxn) {
6755                     uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
6756                 }
6757                 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
6758                      (uwxn && (user_rw & PAGE_WRITE));
6759             }
6760             break;
6761         case 2:
6762             break;
6763         }
6764     } else {
6765         xn = wxn = 0;
6766     }
6767
6768     if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
6769         return prot_rw;
6770     }
6771     return prot_rw | PAGE_EXEC;
6772 }
6773
6774 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
6775                                      uint32_t *table, uint32_t address)
6776 {
6777     /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
6778     TCR *tcr = regime_tcr(env, mmu_idx);
6779
6780     if (address & tcr->mask) {
6781         if (tcr->raw_tcr & TTBCR_PD1) {
6782             /* Translation table walk disabled for TTBR1 */
6783             return false;
6784         }
6785         *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
6786     } else {
6787         if (tcr->raw_tcr & TTBCR_PD0) {
6788             /* Translation table walk disabled for TTBR0 */
6789             return false;
6790         }
6791         *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
6792     }
6793     *table |= (address >> 18) & 0x3ffc;
6794     return true;
6795 }
6796
6797 /* Translate a S1 pagetable walk through S2 if needed.  */
6798 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
6799                                hwaddr addr, MemTxAttrs txattrs,
6800                                uint32_t *fsr,
6801                                ARMMMUFaultInfo *fi)
6802 {
6803     if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) &&
6804         !regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
6805         target_ulong s2size;
6806         hwaddr s2pa;
6807         int s2prot;
6808         int ret;
6809
6810         ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
6811                                  &txattrs, &s2prot, &s2size, fsr, fi);
6812         if (ret) {
6813             fi->s2addr = addr;
6814             fi->stage2 = true;
6815             fi->s1ptw = true;
6816             return ~0;
6817         }
6818         addr = s2pa;
6819     }
6820     return addr;
6821 }
6822
6823 /* All loads done in the course of a page table walk go through here.
6824  * TODO: rather than ignoring errors from physical memory reads (which
6825  * are external aborts in ARM terminology) we should propagate this
6826  * error out so that we can turn it into a Data Abort if this walk
6827  * was being done for a CPU load/store or an address translation instruction
6828  * (but not if it was for a debug access).
6829  */
6830 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6831                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6832                             ARMMMUFaultInfo *fi)
6833 {
6834     ARMCPU *cpu = ARM_CPU(cs);
6835     CPUARMState *env = &cpu->env;
6836     MemTxAttrs attrs = {};
6837     AddressSpace *as;
6838
6839     attrs.secure = is_secure;
6840     as = arm_addressspace(cs, attrs);
6841     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6842     if (fi->s1ptw) {
6843         return 0;
6844     }
6845     return address_space_ldl(as, addr, attrs, NULL);
6846 }
6847
6848 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6849                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6850                             ARMMMUFaultInfo *fi)
6851 {
6852     ARMCPU *cpu = ARM_CPU(cs);
6853     CPUARMState *env = &cpu->env;
6854     MemTxAttrs attrs = {};
6855     AddressSpace *as;
6856
6857     attrs.secure = is_secure;
6858     as = arm_addressspace(cs, attrs);
6859     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6860     if (fi->s1ptw) {
6861         return 0;
6862     }
6863     return address_space_ldq(as, addr, attrs, NULL);
6864 }
6865
6866 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
6867                              int access_type, ARMMMUIdx mmu_idx,
6868                              hwaddr *phys_ptr, int *prot,
6869                              target_ulong *page_size, uint32_t *fsr,
6870                              ARMMMUFaultInfo *fi)
6871 {
6872     CPUState *cs = CPU(arm_env_get_cpu(env));
6873     int code;
6874     uint32_t table;
6875     uint32_t desc;
6876     int type;
6877     int ap;
6878     int domain = 0;
6879     int domain_prot;
6880     hwaddr phys_addr;
6881     uint32_t dacr;
6882
6883     /* Pagetable walk.  */
6884     /* Lookup l1 descriptor.  */
6885     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6886         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6887         code = 5;
6888         goto do_fault;
6889     }
6890     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6891                        mmu_idx, fsr, fi);
6892     type = (desc & 3);
6893     domain = (desc >> 5) & 0x0f;
6894     if (regime_el(env, mmu_idx) == 1) {
6895         dacr = env->cp15.dacr_ns;
6896     } else {
6897         dacr = env->cp15.dacr_s;
6898     }
6899     domain_prot = (dacr >> (domain * 2)) & 3;
6900     if (type == 0) {
6901         /* Section translation fault.  */
6902         code = 5;
6903         goto do_fault;
6904     }
6905     if (domain_prot == 0 || domain_prot == 2) {
6906         if (type == 2)
6907             code = 9; /* Section domain fault.  */
6908         else
6909             code = 11; /* Page domain fault.  */
6910         goto do_fault;
6911     }
6912     if (type == 2) {
6913         /* 1Mb section.  */
6914         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6915         ap = (desc >> 10) & 3;
6916         code = 13;
6917         *page_size = 1024 * 1024;
6918     } else {
6919         /* Lookup l2 entry.  */
6920         if (type == 1) {
6921             /* Coarse pagetable.  */
6922             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6923         } else {
6924             /* Fine pagetable.  */
6925             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
6926         }
6927         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6928                            mmu_idx, fsr, fi);
6929         switch (desc & 3) {
6930         case 0: /* Page translation fault.  */
6931             code = 7;
6932             goto do_fault;
6933         case 1: /* 64k page.  */
6934             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6935             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
6936             *page_size = 0x10000;
6937             break;
6938         case 2: /* 4k page.  */
6939             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6940             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
6941             *page_size = 0x1000;
6942             break;
6943         case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
6944             if (type == 1) {
6945                 /* ARMv6/XScale extended small page format */
6946                 if (arm_feature(env, ARM_FEATURE_XSCALE)
6947                     || arm_feature(env, ARM_FEATURE_V6)) {
6948                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6949                     *page_size = 0x1000;
6950                 } else {
6951                     /* UNPREDICTABLE in ARMv5; we choose to take a
6952                      * page translation fault.
6953                      */
6954                     code = 7;
6955                     goto do_fault;
6956                 }
6957             } else {
6958                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
6959                 *page_size = 0x400;
6960             }
6961             ap = (desc >> 4) & 3;
6962             break;
6963         default:
6964             /* Never happens, but compiler isn't smart enough to tell.  */
6965             abort();
6966         }
6967         code = 15;
6968     }
6969     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6970     *prot |= *prot ? PAGE_EXEC : 0;
6971     if (!(*prot & (1 << access_type))) {
6972         /* Access permission fault.  */
6973         goto do_fault;
6974     }
6975     *phys_ptr = phys_addr;
6976     return false;
6977 do_fault:
6978     *fsr = code | (domain << 4);
6979     return true;
6980 }
6981
6982 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
6983                              int access_type, ARMMMUIdx mmu_idx,
6984                              hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
6985                              target_ulong *page_size, uint32_t *fsr,
6986                              ARMMMUFaultInfo *fi)
6987 {
6988     CPUState *cs = CPU(arm_env_get_cpu(env));
6989     int code;
6990     uint32_t table;
6991     uint32_t desc;
6992     uint32_t xn;
6993     uint32_t pxn = 0;
6994     int type;
6995     int ap;
6996     int domain = 0;
6997     int domain_prot;
6998     hwaddr phys_addr;
6999     uint32_t dacr;
7000     bool ns;
7001
7002     /* Pagetable walk.  */
7003     /* Lookup l1 descriptor.  */
7004     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
7005         /* Section translation fault if page walk is disabled by PD0 or PD1 */
7006         code = 5;
7007         goto do_fault;
7008     }
7009     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
7010                        mmu_idx, fsr, fi);
7011     type = (desc & 3);
7012     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
7013         /* Section translation fault, or attempt to use the encoding
7014          * which is Reserved on implementations without PXN.
7015          */
7016         code = 5;
7017         goto do_fault;
7018     }
7019     if ((type == 1) || !(desc & (1 << 18))) {
7020         /* Page or Section.  */
7021         domain = (desc >> 5) & 0x0f;
7022     }
7023     if (regime_el(env, mmu_idx) == 1) {
7024         dacr = env->cp15.dacr_ns;
7025     } else {
7026         dacr = env->cp15.dacr_s;
7027     }
7028     domain_prot = (dacr >> (domain * 2)) & 3;
7029     if (domain_prot == 0 || domain_prot == 2) {
7030         if (type != 1) {
7031             code = 9; /* Section domain fault.  */
7032         } else {
7033             code = 11; /* Page domain fault.  */
7034         }
7035         goto do_fault;
7036     }
7037     if (type != 1) {
7038         if (desc & (1 << 18)) {
7039             /* Supersection.  */
7040             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
7041             phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
7042             phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
7043             *page_size = 0x1000000;
7044         } else {
7045             /* Section.  */
7046             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
7047             *page_size = 0x100000;
7048         }
7049         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
7050         xn = desc & (1 << 4);
7051         pxn = desc & 1;
7052         code = 13;
7053         ns = extract32(desc, 19, 1);
7054     } else {
7055         if (arm_feature(env, ARM_FEATURE_PXN)) {
7056             pxn = (desc >> 2) & 1;
7057         }
7058         ns = extract32(desc, 3, 1);
7059         /* Lookup l2 entry.  */
7060         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
7061         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
7062                            mmu_idx, fsr, fi);
7063         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
7064         switch (desc & 3) {
7065         case 0: /* Page translation fault.  */
7066             code = 7;
7067             goto do_fault;
7068         case 1: /* 64k page.  */
7069             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
7070             xn = desc & (1 << 15);
7071             *page_size = 0x10000;
7072             break;
7073         case 2: case 3: /* 4k page.  */
7074             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
7075             xn = desc & 1;
7076             *page_size = 0x1000;
7077             break;
7078         default:
7079             /* Never happens, but compiler isn't smart enough to tell.  */
7080             abort();
7081         }
7082         code = 15;
7083     }
7084     if (domain_prot == 3) {
7085         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7086     } else {
7087         if (pxn && !regime_is_user(env, mmu_idx)) {
7088             xn = 1;
7089         }
7090         if (xn && access_type == 2)
7091             goto do_fault;
7092
7093         if (arm_feature(env, ARM_FEATURE_V6K) &&
7094                 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
7095             /* The simplified model uses AP[0] as an access control bit.  */
7096             if ((ap & 1) == 0) {
7097                 /* Access flag fault.  */
7098                 code = (code == 15) ? 6 : 3;
7099                 goto do_fault;
7100             }
7101             *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
7102         } else {
7103             *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
7104         }
7105         if (*prot && !xn) {
7106             *prot |= PAGE_EXEC;
7107         }
7108         if (!(*prot & (1 << access_type))) {
7109             /* Access permission fault.  */
7110             goto do_fault;
7111         }
7112     }
7113     if (ns) {
7114         /* The NS bit will (as required by the architecture) have no effect if
7115          * the CPU doesn't support TZ or this is a non-secure translation
7116          * regime, because the attribute will already be non-secure.
7117          */
7118         attrs->secure = false;
7119     }
7120     *phys_ptr = phys_addr;
7121     return false;
7122 do_fault:
7123     *fsr = code | (domain << 4);
7124     return true;
7125 }
7126
7127 /* Fault type for long-descriptor MMU fault reporting; this corresponds
7128  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
7129  */
7130 typedef enum {
7131     translation_fault = 1,
7132     access_fault = 2,
7133     permission_fault = 3,
7134 } MMUFaultType;
7135
7136 /*
7137  * check_s2_mmu_setup
7138  * @cpu:        ARMCPU
7139  * @is_aa64:    True if the translation regime is in AArch64 state
7140  * @startlevel: Suggested starting level
7141  * @inputsize:  Bitsize of IPAs
7142  * @stride:     Page-table stride (See the ARM ARM)
7143  *
7144  * Returns true if the suggested S2 translation parameters are OK and
7145  * false otherwise.
7146  */
7147 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
7148                                int inputsize, int stride)
7149 {
7150     const int grainsize = stride + 3;
7151     int startsizecheck;
7152
7153     /* Negative levels are never allowed.  */
7154     if (level < 0) {
7155         return false;
7156     }
7157
7158     startsizecheck = inputsize - ((3 - level) * stride + grainsize);
7159     if (startsizecheck < 1 || startsizecheck > stride + 4) {
7160         return false;
7161     }
7162
7163     if (is_aa64) {
7164         CPUARMState *env = &cpu->env;
7165         unsigned int pamax = arm_pamax(cpu);
7166
7167         switch (stride) {
7168         case 13: /* 64KB Pages.  */
7169             if (level == 0 || (level == 1 && pamax <= 42)) {
7170                 return false;
7171             }
7172             break;
7173         case 11: /* 16KB Pages.  */
7174             if (level == 0 || (level == 1 && pamax <= 40)) {
7175                 return false;
7176             }
7177             break;
7178         case 9: /* 4KB Pages.  */
7179             if (level == 0 && pamax <= 42) {
7180                 return false;
7181             }
7182             break;
7183         default:
7184             g_assert_not_reached();
7185         }
7186
7187         /* Inputsize checks.  */
7188         if (inputsize > pamax &&
7189             (arm_el_is_aa64(env, 1) || inputsize > 40)) {
7190             /* This is CONSTRAINED UNPREDICTABLE and we choose to fault.  */
7191             return false;
7192         }
7193     } else {
7194         /* AArch32 only supports 4KB pages. Assert on that.  */
7195         assert(stride == 9);
7196
7197         if (level == 0) {
7198             return false;
7199         }
7200     }
7201     return true;
7202 }
7203
7204 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
7205                                int access_type, ARMMMUIdx mmu_idx,
7206                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
7207                                target_ulong *page_size_ptr, uint32_t *fsr,
7208                                ARMMMUFaultInfo *fi)
7209 {
7210     ARMCPU *cpu = arm_env_get_cpu(env);
7211     CPUState *cs = CPU(cpu);
7212     /* Read an LPAE long-descriptor translation table. */
7213     MMUFaultType fault_type = translation_fault;
7214     uint32_t level = 1;
7215     uint32_t epd = 0;
7216     int32_t t0sz, t1sz;
7217     uint32_t tg;
7218     uint64_t ttbr;
7219     int ttbr_select;
7220     hwaddr descaddr, descmask;
7221     uint32_t tableattrs;
7222     target_ulong page_size;
7223     uint32_t attrs;
7224     int32_t stride = 9;
7225     int32_t va_size = 32;
7226     int inputsize;
7227     int32_t tbi = 0;
7228     TCR *tcr = regime_tcr(env, mmu_idx);
7229     int ap, ns, xn, pxn;
7230     uint32_t el = regime_el(env, mmu_idx);
7231     bool ttbr1_valid = true;
7232     uint64_t descaddrmask;
7233
7234     /* TODO:
7235      * This code does not handle the different format TCR for VTCR_EL2.
7236      * This code also does not support shareability levels.
7237      * Attribute and permission bit handling should also be checked when adding
7238      * support for those page table walks.
7239      */
7240     if (arm_el_is_aa64(env, el)) {
7241         va_size = 64;
7242         if (el > 1) {
7243             if (mmu_idx != ARMMMUIdx_S2NS) {
7244                 tbi = extract64(tcr->raw_tcr, 20, 1);
7245             }
7246         } else {
7247             if (extract64(address, 55, 1)) {
7248                 tbi = extract64(tcr->raw_tcr, 38, 1);
7249             } else {
7250                 tbi = extract64(tcr->raw_tcr, 37, 1);
7251             }
7252         }
7253         tbi *= 8;
7254
7255         /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
7256          * invalid.
7257          */
7258         if (el > 1) {
7259             ttbr1_valid = false;
7260         }
7261     } else {
7262         /* There is no TTBR1 for EL2 */
7263         if (el == 2) {
7264             ttbr1_valid = false;
7265         }
7266     }
7267
7268     /* Determine whether this address is in the region controlled by
7269      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
7270      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
7271      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
7272      */
7273     if (va_size == 64) {
7274         /* AArch64 translation.  */
7275         t0sz = extract32(tcr->raw_tcr, 0, 6);
7276         t0sz = MIN(t0sz, 39);
7277         t0sz = MAX(t0sz, 16);
7278     } else if (mmu_idx != ARMMMUIdx_S2NS) {
7279         /* AArch32 stage 1 translation.  */
7280         t0sz = extract32(tcr->raw_tcr, 0, 3);
7281     } else {
7282         /* AArch32 stage 2 translation.  */
7283         bool sext = extract32(tcr->raw_tcr, 4, 1);
7284         bool sign = extract32(tcr->raw_tcr, 3, 1);
7285         t0sz = sextract32(tcr->raw_tcr, 0, 4);
7286
7287         /* If the sign-extend bit is not the same as t0sz[3], the result
7288          * is unpredictable. Flag this as a guest error.  */
7289         if (sign != sext) {
7290             qemu_log_mask(LOG_GUEST_ERROR,
7291                           "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n");
7292         }
7293     }
7294     t1sz = extract32(tcr->raw_tcr, 16, 6);
7295     if (va_size == 64) {
7296         t1sz = MIN(t1sz, 39);
7297         t1sz = MAX(t1sz, 16);
7298     }
7299     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
7300         /* there is a ttbr0 region and we are in it (high bits all zero) */
7301         ttbr_select = 0;
7302     } else if (ttbr1_valid && t1sz &&
7303                !extract64(~address, va_size - t1sz, t1sz - tbi)) {
7304         /* there is a ttbr1 region and we are in it (high bits all one) */
7305         ttbr_select = 1;
7306     } else if (!t0sz) {
7307         /* ttbr0 region is "everything not in the ttbr1 region" */
7308         ttbr_select = 0;
7309     } else if (!t1sz && ttbr1_valid) {
7310         /* ttbr1 region is "everything not in the ttbr0 region" */
7311         ttbr_select = 1;
7312     } else {
7313         /* in the gap between the two regions, this is a Translation fault */
7314         fault_type = translation_fault;
7315         goto do_fault;
7316     }
7317
7318     /* Note that QEMU ignores shareability and cacheability attributes,
7319      * so we don't need to do anything with the SH, ORGN, IRGN fields
7320      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
7321      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
7322      * implement any ASID-like capability so we can ignore it (instead
7323      * we will always flush the TLB any time the ASID is changed).
7324      */
7325     if (ttbr_select == 0) {
7326         ttbr = regime_ttbr(env, mmu_idx, 0);
7327         if (el < 2) {
7328             epd = extract32(tcr->raw_tcr, 7, 1);
7329         }
7330         inputsize = va_size - t0sz;
7331
7332         tg = extract32(tcr->raw_tcr, 14, 2);
7333         if (tg == 1) { /* 64KB pages */
7334             stride = 13;
7335         }
7336         if (tg == 2) { /* 16KB pages */
7337             stride = 11;
7338         }
7339     } else {
7340         /* We should only be here if TTBR1 is valid */
7341         assert(ttbr1_valid);
7342
7343         ttbr = regime_ttbr(env, mmu_idx, 1);
7344         epd = extract32(tcr->raw_tcr, 23, 1);
7345         inputsize = va_size - t1sz;
7346
7347         tg = extract32(tcr->raw_tcr, 30, 2);
7348         if (tg == 3)  { /* 64KB pages */
7349             stride = 13;
7350         }
7351         if (tg == 1) { /* 16KB pages */
7352             stride = 11;
7353         }
7354     }
7355
7356     /* Here we should have set up all the parameters for the translation:
7357      * va_size, inputsize, ttbr, epd, stride, tbi
7358      */
7359
7360     if (epd) {
7361         /* Translation table walk disabled => Translation fault on TLB miss
7362          * Note: This is always 0 on 64-bit EL2 and EL3.
7363          */
7364         goto do_fault;
7365     }
7366
7367     if (mmu_idx != ARMMMUIdx_S2NS) {
7368         /* The starting level depends on the virtual address size (which can
7369          * be up to 48 bits) and the translation granule size. It indicates
7370          * the number of strides (stride bits at a time) needed to
7371          * consume the bits of the input address. In the pseudocode this is:
7372          *  level = 4 - RoundUp((inputsize - grainsize) / stride)
7373          * where their 'inputsize' is our 'inputsize', 'grainsize' is
7374          * our 'stride + 3' and 'stride' is our 'stride'.
7375          * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
7376          * = 4 - (inputsize - stride - 3 + stride - 1) / stride
7377          * = 4 - (inputsize - 4) / stride;
7378          */
7379         level = 4 - (inputsize - 4) / stride;
7380     } else {
7381         /* For stage 2 translations the starting level is specified by the
7382          * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
7383          */
7384         int startlevel = extract32(tcr->raw_tcr, 6, 2);
7385         bool ok;
7386
7387         if (va_size == 32 || stride == 9) {
7388             /* AArch32 or 4KB pages */
7389             level = 2 - startlevel;
7390         } else {
7391             /* 16KB or 64KB pages */
7392             level = 3 - startlevel;
7393         }
7394
7395         /* Check that the starting level is valid. */
7396         ok = check_s2_mmu_setup(cpu, va_size == 64, level, inputsize, stride);
7397         if (!ok) {
7398             /* AArch64 reports these as level 0 faults.
7399              * AArch32 reports these as level 1 faults.
7400              */
7401             level = va_size == 64 ? 0 : 1;
7402             fault_type = translation_fault;
7403             goto do_fault;
7404         }
7405     }
7406
7407     /* Clear the vaddr bits which aren't part of the within-region address,
7408      * so that we don't have to special case things when calculating the
7409      * first descriptor address.
7410      */
7411     if (va_size != inputsize) {
7412         address &= (1ULL << inputsize) - 1;
7413     }
7414
7415     descmask = (1ULL << (stride + 3)) - 1;
7416
7417     /* Now we can extract the actual base address from the TTBR */
7418     descaddr = extract64(ttbr, 0, 48);
7419     descaddr &= ~((1ULL << (inputsize - (stride * (4 - level)))) - 1);
7420
7421     /* The address field in the descriptor goes up to bit 39 for ARMv7
7422      * but up to bit 47 for ARMv8.
7423      */
7424     if (arm_feature(env, ARM_FEATURE_V8)) {
7425         descaddrmask = 0xfffffffff000ULL;
7426     } else {
7427         descaddrmask = 0xfffffff000ULL;
7428     }
7429
7430     /* Secure accesses start with the page table in secure memory and
7431      * can be downgraded to non-secure at any step. Non-secure accesses
7432      * remain non-secure. We implement this by just ORing in the NSTable/NS
7433      * bits at each step.
7434      */
7435     tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
7436     for (;;) {
7437         uint64_t descriptor;
7438         bool nstable;
7439
7440         descaddr |= (address >> (stride * (4 - level))) & descmask;
7441         descaddr &= ~7ULL;
7442         nstable = extract32(tableattrs, 4, 1);
7443         descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi);
7444         if (fi->s1ptw) {
7445             goto do_fault;
7446         }
7447
7448         if (!(descriptor & 1) ||
7449             (!(descriptor & 2) && (level == 3))) {
7450             /* Invalid, or the Reserved level 3 encoding */
7451             goto do_fault;
7452         }
7453         descaddr = descriptor & descaddrmask;
7454
7455         if ((descriptor & 2) && (level < 3)) {
7456             /* Table entry. The top five bits are attributes which  may
7457              * propagate down through lower levels of the table (and
7458              * which are all arranged so that 0 means "no effect", so
7459              * we can gather them up by ORing in the bits at each level).
7460              */
7461             tableattrs |= extract64(descriptor, 59, 5);
7462             level++;
7463             continue;
7464         }
7465         /* Block entry at level 1 or 2, or page entry at level 3.
7466          * These are basically the same thing, although the number
7467          * of bits we pull in from the vaddr varies.
7468          */
7469         page_size = (1ULL << ((stride * (4 - level)) + 3));
7470         descaddr |= (address & (page_size - 1));
7471         /* Extract attributes from the descriptor */
7472         attrs = extract64(descriptor, 2, 10)
7473             | (extract64(descriptor, 52, 12) << 10);
7474
7475         if (mmu_idx == ARMMMUIdx_S2NS) {
7476             /* Stage 2 table descriptors do not include any attribute fields */
7477             break;
7478         }
7479         /* Merge in attributes from table descriptors */
7480         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
7481         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
7482         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
7483          * means "force PL1 access only", which means forcing AP[1] to 0.
7484          */
7485         if (extract32(tableattrs, 2, 1)) {
7486             attrs &= ~(1 << 4);
7487         }
7488         attrs |= nstable << 3; /* NS */
7489         break;
7490     }
7491     /* Here descaddr is the final physical address, and attributes
7492      * are all in attrs.
7493      */
7494     fault_type = access_fault;
7495     if ((attrs & (1 << 8)) == 0) {
7496         /* Access flag */
7497         goto do_fault;
7498     }
7499
7500     ap = extract32(attrs, 4, 2);
7501     xn = extract32(attrs, 12, 1);
7502
7503     if (mmu_idx == ARMMMUIdx_S2NS) {
7504         ns = true;
7505         *prot = get_S2prot(env, ap, xn);
7506     } else {
7507         ns = extract32(attrs, 3, 1);
7508         pxn = extract32(attrs, 11, 1);
7509         *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
7510     }
7511
7512     fault_type = permission_fault;
7513     if (!(*prot & (1 << access_type))) {
7514         goto do_fault;
7515     }
7516
7517     if (ns) {
7518         /* The NS bit will (as required by the architecture) have no effect if
7519          * the CPU doesn't support TZ or this is a non-secure translation
7520          * regime, because the attribute will already be non-secure.
7521          */
7522         txattrs->secure = false;
7523     }
7524     *phys_ptr = descaddr;
7525     *page_size_ptr = page_size;
7526     return false;
7527
7528 do_fault:
7529     /* Long-descriptor format IFSR/DFSR value */
7530     *fsr = (1 << 9) | (fault_type << 2) | level;
7531     /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2.  */
7532     fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS);
7533     return true;
7534 }
7535
7536 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
7537                                                 ARMMMUIdx mmu_idx,
7538                                                 int32_t address, int *prot)
7539 {
7540     *prot = PAGE_READ | PAGE_WRITE;
7541     switch (address) {
7542     case 0xF0000000 ... 0xFFFFFFFF:
7543         if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
7544             *prot |= PAGE_EXEC;
7545         }
7546         break;
7547     case 0x00000000 ... 0x7FFFFFFF:
7548         *prot |= PAGE_EXEC;
7549         break;
7550     }
7551
7552 }
7553
7554 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
7555                                  int access_type, ARMMMUIdx mmu_idx,
7556                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7557 {
7558     ARMCPU *cpu = arm_env_get_cpu(env);
7559     int n;
7560     bool is_user = regime_is_user(env, mmu_idx);
7561
7562     *phys_ptr = address;
7563     *prot = 0;
7564
7565     if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
7566         get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7567     } else { /* MPU enabled */
7568         for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
7569             /* region search */
7570             uint32_t base = env->pmsav7.drbar[n];
7571             uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
7572             uint32_t rmask;
7573             bool srdis = false;
7574
7575             if (!(env->pmsav7.drsr[n] & 0x1)) {
7576                 continue;
7577             }
7578
7579             if (!rsize) {
7580                 qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
7581                 continue;
7582             }
7583             rsize++;
7584             rmask = (1ull << rsize) - 1;
7585
7586             if (base & rmask) {
7587                 qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
7588                               "to DRSR region size, mask = %" PRIx32,
7589                               base, rmask);
7590                 continue;
7591             }
7592
7593             if (address < base || address > base + rmask) {
7594                 continue;
7595             }
7596
7597             /* Region matched */
7598
7599             if (rsize >= 8) { /* no subregions for regions < 256 bytes */
7600                 int i, snd;
7601                 uint32_t srdis_mask;
7602
7603                 rsize -= 3; /* sub region size (power of 2) */
7604                 snd = ((address - base) >> rsize) & 0x7;
7605                 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
7606
7607                 srdis_mask = srdis ? 0x3 : 0x0;
7608                 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
7609                     /* This will check in groups of 2, 4 and then 8, whether
7610                      * the subregion bits are consistent. rsize is incremented
7611                      * back up to give the region size, considering consistent
7612                      * adjacent subregions as one region. Stop testing if rsize
7613                      * is already big enough for an entire QEMU page.
7614                      */
7615                     int snd_rounded = snd & ~(i - 1);
7616                     uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
7617                                                      snd_rounded + 8, i);
7618                     if (srdis_mask ^ srdis_multi) {
7619                         break;
7620                     }
7621                     srdis_mask = (srdis_mask << i) | srdis_mask;
7622                     rsize++;
7623                 }
7624             }
7625             if (rsize < TARGET_PAGE_BITS) {
7626                 qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
7627                               "alignment of %" PRIu32 " bits. Minimum is %d\n",
7628                               rsize, TARGET_PAGE_BITS);
7629                 continue;
7630             }
7631             if (srdis) {
7632                 continue;
7633             }
7634             break;
7635         }
7636
7637         if (n == -1) { /* no hits */
7638             if (cpu->pmsav7_dregion &&
7639                 (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
7640                 /* background fault */
7641                 *fsr = 0;
7642                 return true;
7643             }
7644             get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7645         } else { /* a MPU hit! */
7646             uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
7647
7648             if (is_user) { /* User mode AP bit decoding */
7649                 switch (ap) {
7650                 case 0:
7651                 case 1:
7652                 case 5:
7653                     break; /* no access */
7654                 case 3:
7655                     *prot |= PAGE_WRITE;
7656                     /* fall through */
7657                 case 2:
7658                 case 6:
7659                     *prot |= PAGE_READ | PAGE_EXEC;
7660                     break;
7661                 default:
7662                     qemu_log_mask(LOG_GUEST_ERROR,
7663                                   "Bad value for AP bits in DRACR %"
7664                                   PRIx32 "\n", ap);
7665                 }
7666             } else { /* Priv. mode AP bits decoding */
7667                 switch (ap) {
7668                 case 0:
7669                     break; /* no access */
7670                 case 1:
7671                 case 2:
7672                 case 3:
7673                     *prot |= PAGE_WRITE;
7674                     /* fall through */
7675                 case 5:
7676                 case 6:
7677                     *prot |= PAGE_READ | PAGE_EXEC;
7678                     break;
7679                 default:
7680                     qemu_log_mask(LOG_GUEST_ERROR,
7681                                   "Bad value for AP bits in DRACR %"
7682                                   PRIx32 "\n", ap);
7683                 }
7684             }
7685
7686             /* execute never */
7687             if (env->pmsav7.dracr[n] & (1 << 12)) {
7688                 *prot &= ~PAGE_EXEC;
7689             }
7690         }
7691     }
7692
7693     *fsr = 0x00d; /* Permission fault */
7694     return !(*prot & (1 << access_type));
7695 }
7696
7697 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
7698                                  int access_type, ARMMMUIdx mmu_idx,
7699                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7700 {
7701     int n;
7702     uint32_t mask;
7703     uint32_t base;
7704     bool is_user = regime_is_user(env, mmu_idx);
7705
7706     *phys_ptr = address;
7707     for (n = 7; n >= 0; n--) {
7708         base = env->cp15.c6_region[n];
7709         if ((base & 1) == 0) {
7710             continue;
7711         }
7712         mask = 1 << ((base >> 1) & 0x1f);
7713         /* Keep this shift separate from the above to avoid an
7714            (undefined) << 32.  */
7715         mask = (mask << 1) - 1;
7716         if (((base ^ address) & ~mask) == 0) {
7717             break;
7718         }
7719     }
7720     if (n < 0) {
7721         *fsr = 2;
7722         return true;
7723     }
7724
7725     if (access_type == 2) {
7726         mask = env->cp15.pmsav5_insn_ap;
7727     } else {
7728         mask = env->cp15.pmsav5_data_ap;
7729     }
7730     mask = (mask >> (n * 4)) & 0xf;
7731     switch (mask) {
7732     case 0:
7733         *fsr = 1;
7734         return true;
7735     case 1:
7736         if (is_user) {
7737             *fsr = 1;
7738             return true;
7739         }
7740         *prot = PAGE_READ | PAGE_WRITE;
7741         break;
7742     case 2:
7743         *prot = PAGE_READ;
7744         if (!is_user) {
7745             *prot |= PAGE_WRITE;
7746         }
7747         break;
7748     case 3:
7749         *prot = PAGE_READ | PAGE_WRITE;
7750         break;
7751     case 5:
7752         if (is_user) {
7753             *fsr = 1;
7754             return true;
7755         }
7756         *prot = PAGE_READ;
7757         break;
7758     case 6:
7759         *prot = PAGE_READ;
7760         break;
7761     default:
7762         /* Bad permission.  */
7763         *fsr = 1;
7764         return true;
7765     }
7766     *prot |= PAGE_EXEC;
7767     return false;
7768 }
7769
7770 /* get_phys_addr - get the physical address for this virtual address
7771  *
7772  * Find the physical address corresponding to the given virtual address,
7773  * by doing a translation table walk on MMU based systems or using the
7774  * MPU state on MPU based systems.
7775  *
7776  * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
7777  * prot and page_size may not be filled in, and the populated fsr value provides
7778  * information on why the translation aborted, in the format of a
7779  * DFSR/IFSR fault register, with the following caveats:
7780  *  * we honour the short vs long DFSR format differences.
7781  *  * the WnR bit is never set (the caller must do this).
7782  *  * for PSMAv5 based systems we don't bother to return a full FSR format
7783  *    value.
7784  *
7785  * @env: CPUARMState
7786  * @address: virtual address to get physical address for
7787  * @access_type: 0 for read, 1 for write, 2 for execute
7788  * @mmu_idx: MMU index indicating required translation regime
7789  * @phys_ptr: set to the physical address corresponding to the virtual address
7790  * @attrs: set to the memory transaction attributes to use
7791  * @prot: set to the permissions for the page containing phys_ptr
7792  * @page_size: set to the size of the page containing phys_ptr
7793  * @fsr: set to the DFSR/IFSR value on failure
7794  */
7795 static bool get_phys_addr(CPUARMState *env, target_ulong address,
7796                           int access_type, ARMMMUIdx mmu_idx,
7797                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
7798                           target_ulong *page_size, uint32_t *fsr,
7799                           ARMMMUFaultInfo *fi)
7800 {
7801     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
7802         /* Call ourselves recursively to do the stage 1 and then stage 2
7803          * translations.
7804          */
7805         if (arm_feature(env, ARM_FEATURE_EL2)) {
7806             hwaddr ipa;
7807             int s2_prot;
7808             int ret;
7809
7810             ret = get_phys_addr(env, address, access_type,
7811                                 mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs,
7812                                 prot, page_size, fsr, fi);
7813
7814             /* If S1 fails or S2 is disabled, return early.  */
7815             if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
7816                 *phys_ptr = ipa;
7817                 return ret;
7818             }
7819
7820             /* S1 is done. Now do S2 translation.  */
7821             ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS,
7822                                      phys_ptr, attrs, &s2_prot,
7823                                      page_size, fsr, fi);
7824             fi->s2addr = ipa;
7825             /* Combine the S1 and S2 perms.  */
7826             *prot &= s2_prot;
7827             return ret;
7828         } else {
7829             /*
7830              * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
7831              */
7832             mmu_idx += ARMMMUIdx_S1NSE0;
7833         }
7834     }
7835
7836     /* The page table entries may downgrade secure to non-secure, but
7837      * cannot upgrade an non-secure translation regime's attributes
7838      * to secure.
7839      */
7840     attrs->secure = regime_is_secure(env, mmu_idx);
7841     attrs->user = regime_is_user(env, mmu_idx);
7842
7843     /* Fast Context Switch Extension. This doesn't exist at all in v8.
7844      * In v7 and earlier it affects all stage 1 translations.
7845      */
7846     if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
7847         && !arm_feature(env, ARM_FEATURE_V8)) {
7848         if (regime_el(env, mmu_idx) == 3) {
7849             address += env->cp15.fcseidr_s;
7850         } else {
7851             address += env->cp15.fcseidr_ns;
7852         }
7853     }
7854
7855     /* pmsav7 has special handling for when MPU is disabled so call it before
7856      * the common MMU/MPU disabled check below.
7857      */
7858     if (arm_feature(env, ARM_FEATURE_MPU) &&
7859         arm_feature(env, ARM_FEATURE_V7)) {
7860         *page_size = TARGET_PAGE_SIZE;
7861         return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
7862                                     phys_ptr, prot, fsr);
7863     }
7864
7865     if (regime_translation_disabled(env, mmu_idx)) {
7866         /* MMU/MPU disabled.  */
7867         *phys_ptr = address;
7868         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7869         *page_size = TARGET_PAGE_SIZE;
7870         return 0;
7871     }
7872
7873     if (arm_feature(env, ARM_FEATURE_MPU)) {
7874         /* Pre-v7 MPU */
7875         *page_size = TARGET_PAGE_SIZE;
7876         return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
7877                                     phys_ptr, prot, fsr);
7878     }
7879
7880     if (regime_using_lpae_format(env, mmu_idx)) {
7881         return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
7882                                   attrs, prot, page_size, fsr, fi);
7883     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
7884         return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
7885                                 attrs, prot, page_size, fsr, fi);
7886     } else {
7887         return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
7888                                 prot, page_size, fsr, fi);
7889     }
7890 }
7891
7892 /* Walk the page table and (if the mapping exists) add the page
7893  * to the TLB. Return false on success, or true on failure. Populate
7894  * fsr with ARM DFSR/IFSR fault register format value on failure.
7895  */
7896 bool arm_tlb_fill(CPUState *cs, vaddr address,
7897                   int access_type, int mmu_idx, uint32_t *fsr,
7898                   ARMMMUFaultInfo *fi)
7899 {
7900     ARMCPU *cpu = ARM_CPU(cs);
7901     CPUARMState *env = &cpu->env;
7902     hwaddr phys_addr;
7903     target_ulong page_size;
7904     int prot;
7905     int ret;
7906     MemTxAttrs attrs = {};
7907
7908     ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
7909                         &attrs, &prot, &page_size, fsr, fi);
7910     if (!ret) {
7911         /* Map a single [sub]page.  */
7912         phys_addr &= TARGET_PAGE_MASK;
7913         address &= TARGET_PAGE_MASK;
7914         tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
7915                                 prot, mmu_idx, page_size);
7916         return 0;
7917     }
7918
7919     return ret;
7920 }
7921
7922 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
7923                                          MemTxAttrs *attrs)
7924 {
7925     ARMCPU *cpu = ARM_CPU(cs);
7926     CPUARMState *env = &cpu->env;
7927     hwaddr phys_addr;
7928     target_ulong page_size;
7929     int prot;
7930     bool ret;
7931     uint32_t fsr;
7932     ARMMMUFaultInfo fi = {};
7933
7934     *attrs = (MemTxAttrs) {};
7935
7936     ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr,
7937                         attrs, &prot, &page_size, &fsr, &fi);
7938
7939     if (ret) {
7940         return -1;
7941     }
7942     return phys_addr;
7943 }
7944
7945 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
7946 {
7947     ARMCPU *cpu = arm_env_get_cpu(env);
7948
7949     switch (reg) {
7950     case 0: /* APSR */
7951         return xpsr_read(env) & 0xf8000000;
7952     case 1: /* IAPSR */
7953         return xpsr_read(env) & 0xf80001ff;
7954     case 2: /* EAPSR */
7955         return xpsr_read(env) & 0xff00fc00;
7956     case 3: /* xPSR */
7957         return xpsr_read(env) & 0xff00fdff;
7958     case 5: /* IPSR */
7959         return xpsr_read(env) & 0x000001ff;
7960     case 6: /* EPSR */
7961         return xpsr_read(env) & 0x0700fc00;
7962     case 7: /* IEPSR */
7963         return xpsr_read(env) & 0x0700edff;
7964     case 8: /* MSP */
7965         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
7966     case 9: /* PSP */
7967         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
7968     case 16: /* PRIMASK */
7969         return (env->daif & PSTATE_I) != 0;
7970     case 17: /* BASEPRI */
7971     case 18: /* BASEPRI_MAX */
7972         return env->v7m.basepri;
7973     case 19: /* FAULTMASK */
7974         return (env->daif & PSTATE_F) != 0;
7975     case 20: /* CONTROL */
7976         return env->v7m.control;
7977     default:
7978         /* ??? For debugging only.  */
7979         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
7980         return 0;
7981     }
7982 }
7983
7984 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
7985 {
7986     ARMCPU *cpu = arm_env_get_cpu(env);
7987
7988     switch (reg) {
7989     case 0: /* APSR */
7990         xpsr_write(env, val, 0xf8000000);
7991         break;
7992     case 1: /* IAPSR */
7993         xpsr_write(env, val, 0xf8000000);
7994         break;
7995     case 2: /* EAPSR */
7996         xpsr_write(env, val, 0xfe00fc00);
7997         break;
7998     case 3: /* xPSR */
7999         xpsr_write(env, val, 0xfe00fc00);
8000         break;
8001     case 5: /* IPSR */
8002         /* IPSR bits are readonly.  */
8003         break;
8004     case 6: /* EPSR */
8005         xpsr_write(env, val, 0x0600fc00);
8006         break;
8007     case 7: /* IEPSR */
8008         xpsr_write(env, val, 0x0600fc00);
8009         break;
8010     case 8: /* MSP */
8011         if (env->v7m.current_sp)
8012             env->v7m.other_sp = val;
8013         else
8014             env->regs[13] = val;
8015         break;
8016     case 9: /* PSP */
8017         if (env->v7m.current_sp)
8018             env->regs[13] = val;
8019         else
8020             env->v7m.other_sp = val;
8021         break;
8022     case 16: /* PRIMASK */
8023         if (val & 1) {
8024             env->daif |= PSTATE_I;
8025         } else {
8026             env->daif &= ~PSTATE_I;
8027         }
8028         break;
8029     case 17: /* BASEPRI */
8030         env->v7m.basepri = val & 0xff;
8031         break;
8032     case 18: /* BASEPRI_MAX */
8033         val &= 0xff;
8034         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
8035             env->v7m.basepri = val;
8036         break;
8037     case 19: /* FAULTMASK */
8038         if (val & 1) {
8039             env->daif |= PSTATE_F;
8040         } else {
8041             env->daif &= ~PSTATE_F;
8042         }
8043         break;
8044     case 20: /* CONTROL */
8045         env->v7m.control = val & 3;
8046         switch_v7m_sp(env, (val & 2) != 0);
8047         break;
8048     default:
8049         /* ??? For debugging only.  */
8050         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
8051         return;
8052     }
8053 }
8054
8055 #endif
8056
8057 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
8058 {
8059     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
8060      * Note that we do not implement the (architecturally mandated)
8061      * alignment fault for attempts to use this on Device memory
8062      * (which matches the usual QEMU behaviour of not implementing either
8063      * alignment faults or any memory attribute handling).
8064      */
8065
8066     ARMCPU *cpu = arm_env_get_cpu(env);
8067     uint64_t blocklen = 4 << cpu->dcz_blocksize;
8068     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
8069
8070 #ifndef CONFIG_USER_ONLY
8071     {
8072         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
8073          * the block size so we might have to do more than one TLB lookup.
8074          * We know that in fact for any v8 CPU the page size is at least 4K
8075          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
8076          * 1K as an artefact of legacy v5 subpage support being present in the
8077          * same QEMU executable.
8078          */
8079         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
8080         void *hostaddr[maxidx];
8081         int try, i;
8082         unsigned mmu_idx = cpu_mmu_index(env, false);
8083         TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
8084
8085         for (try = 0; try < 2; try++) {
8086
8087             for (i = 0; i < maxidx; i++) {
8088                 hostaddr[i] = tlb_vaddr_to_host(env,
8089                                                 vaddr + TARGET_PAGE_SIZE * i,
8090                                                 1, mmu_idx);
8091                 if (!hostaddr[i]) {
8092                     break;
8093                 }
8094             }
8095             if (i == maxidx) {
8096                 /* If it's all in the TLB it's fair game for just writing to;
8097                  * we know we don't need to update dirty status, etc.
8098                  */
8099                 for (i = 0; i < maxidx - 1; i++) {
8100                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
8101                 }
8102                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
8103                 return;
8104             }
8105             /* OK, try a store and see if we can populate the tlb. This
8106              * might cause an exception if the memory isn't writable,
8107              * in which case we will longjmp out of here. We must for
8108              * this purpose use the actual register value passed to us
8109              * so that we get the fault address right.
8110              */
8111             helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA());
8112             /* Now we can populate the other TLB entries, if any */
8113             for (i = 0; i < maxidx; i++) {
8114                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
8115                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
8116                     helper_ret_stb_mmu(env, va, 0, oi, GETRA());
8117                 }
8118             }
8119         }
8120
8121         /* Slow path (probably attempt to do this to an I/O device or
8122          * similar, or clearing of a block of code we have translations
8123          * cached for). Just do a series of byte writes as the architecture
8124          * demands. It's not worth trying to use a cpu_physical_memory_map(),
8125          * memset(), unmap() sequence here because:
8126          *  + we'd need to account for the blocksize being larger than a page
8127          *  + the direct-RAM access case is almost always going to be dealt
8128          *    with in the fastpath code above, so there's no speed benefit
8129          *  + we would have to deal with the map returning NULL because the
8130          *    bounce buffer was in use
8131          */
8132         for (i = 0; i < blocklen; i++) {
8133             helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA());
8134         }
8135     }
8136 #else
8137     memset(g2h(vaddr), 0, blocklen);
8138 #endif
8139 }
8140
8141 /* Note that signed overflow is undefined in C.  The following routines are
8142    careful to use unsigned types where modulo arithmetic is required.
8143    Failure to do so _will_ break on newer gcc.  */
8144
8145 /* Signed saturating arithmetic.  */
8146
8147 /* Perform 16-bit signed saturating addition.  */
8148 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
8149 {
8150     uint16_t res;
8151
8152     res = a + b;
8153     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
8154         if (a & 0x8000)
8155             res = 0x8000;
8156         else
8157             res = 0x7fff;
8158     }
8159     return res;
8160 }
8161
8162 /* Perform 8-bit signed saturating addition.  */
8163 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
8164 {
8165     uint8_t res;
8166
8167     res = a + b;
8168     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
8169         if (a & 0x80)
8170             res = 0x80;
8171         else
8172             res = 0x7f;
8173     }
8174     return res;
8175 }
8176
8177 /* Perform 16-bit signed saturating subtraction.  */
8178 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
8179 {
8180     uint16_t res;
8181
8182     res = a - b;
8183     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
8184         if (a & 0x8000)
8185             res = 0x8000;
8186         else
8187             res = 0x7fff;
8188     }
8189     return res;
8190 }
8191
8192 /* Perform 8-bit signed saturating subtraction.  */
8193 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
8194 {
8195     uint8_t res;
8196
8197     res = a - b;
8198     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
8199         if (a & 0x80)
8200             res = 0x80;
8201         else
8202             res = 0x7f;
8203     }
8204     return res;
8205 }
8206
8207 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
8208 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
8209 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
8210 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
8211 #define PFX q
8212
8213 #include "op_addsub.h"
8214
8215 /* Unsigned saturating arithmetic.  */
8216 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
8217 {
8218     uint16_t res;
8219     res = a + b;
8220     if (res < a)
8221         res = 0xffff;
8222     return res;
8223 }
8224
8225 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
8226 {
8227     if (a > b)
8228         return a - b;
8229     else
8230         return 0;
8231 }
8232
8233 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
8234 {
8235     uint8_t res;
8236     res = a + b;
8237     if (res < a)
8238         res = 0xff;
8239     return res;
8240 }
8241
8242 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
8243 {
8244     if (a > b)
8245         return a - b;
8246     else
8247         return 0;
8248 }
8249
8250 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
8251 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
8252 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
8253 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
8254 #define PFX uq
8255
8256 #include "op_addsub.h"
8257
8258 /* Signed modulo arithmetic.  */
8259 #define SARITH16(a, b, n, op) do { \
8260     int32_t sum; \
8261     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
8262     RESULT(sum, n, 16); \
8263     if (sum >= 0) \
8264         ge |= 3 << (n * 2); \
8265     } while(0)
8266
8267 #define SARITH8(a, b, n, op) do { \
8268     int32_t sum; \
8269     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
8270     RESULT(sum, n, 8); \
8271     if (sum >= 0) \
8272         ge |= 1 << n; \
8273     } while(0)
8274
8275
8276 #define ADD16(a, b, n) SARITH16(a, b, n, +)
8277 #define SUB16(a, b, n) SARITH16(a, b, n, -)
8278 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
8279 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
8280 #define PFX s
8281 #define ARITH_GE
8282
8283 #include "op_addsub.h"
8284
8285 /* Unsigned modulo arithmetic.  */
8286 #define ADD16(a, b, n) do { \
8287     uint32_t sum; \
8288     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
8289     RESULT(sum, n, 16); \
8290     if ((sum >> 16) == 1) \
8291         ge |= 3 << (n * 2); \
8292     } while(0)
8293
8294 #define ADD8(a, b, n) do { \
8295     uint32_t sum; \
8296     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
8297     RESULT(sum, n, 8); \
8298     if ((sum >> 8) == 1) \
8299         ge |= 1 << n; \
8300     } while(0)
8301
8302 #define SUB16(a, b, n) do { \
8303     uint32_t sum; \
8304     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
8305     RESULT(sum, n, 16); \
8306     if ((sum >> 16) == 0) \
8307         ge |= 3 << (n * 2); \
8308     } while(0)
8309
8310 #define SUB8(a, b, n) do { \
8311     uint32_t sum; \
8312     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
8313     RESULT(sum, n, 8); \
8314     if ((sum >> 8) == 0) \
8315         ge |= 1 << n; \
8316     } while(0)
8317
8318 #define PFX u
8319 #define ARITH_GE
8320
8321 #include "op_addsub.h"
8322
8323 /* Halved signed arithmetic.  */
8324 #define ADD16(a, b, n) \
8325   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
8326 #define SUB16(a, b, n) \
8327   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
8328 #define ADD8(a, b, n) \
8329   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
8330 #define SUB8(a, b, n) \
8331   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
8332 #define PFX sh
8333
8334 #include "op_addsub.h"
8335
8336 /* Halved unsigned arithmetic.  */
8337 #define ADD16(a, b, n) \
8338   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
8339 #define SUB16(a, b, n) \
8340   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
8341 #define ADD8(a, b, n) \
8342   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
8343 #define SUB8(a, b, n) \
8344   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
8345 #define PFX uh
8346
8347 #include "op_addsub.h"
8348
8349 static inline uint8_t do_usad(uint8_t a, uint8_t b)
8350 {
8351     if (a > b)
8352         return a - b;
8353     else
8354         return b - a;
8355 }
8356
8357 /* Unsigned sum of absolute byte differences.  */
8358 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
8359 {
8360     uint32_t sum;
8361     sum = do_usad(a, b);
8362     sum += do_usad(a >> 8, b >> 8);
8363     sum += do_usad(a >> 16, b >>16);
8364     sum += do_usad(a >> 24, b >> 24);
8365     return sum;
8366 }
8367
8368 /* For ARMv6 SEL instruction.  */
8369 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
8370 {
8371     uint32_t mask;
8372
8373     mask = 0;
8374     if (flags & 1)
8375         mask |= 0xff;
8376     if (flags & 2)
8377         mask |= 0xff00;
8378     if (flags & 4)
8379         mask |= 0xff0000;
8380     if (flags & 8)
8381         mask |= 0xff000000;
8382     return (a & mask) | (b & ~mask);
8383 }
8384
8385 /* VFP support.  We follow the convention used for VFP instructions:
8386    Single precision routines have a "s" suffix, double precision a
8387    "d" suffix.  */
8388
8389 /* Convert host exception flags to vfp form.  */
8390 static inline int vfp_exceptbits_from_host(int host_bits)
8391 {
8392     int target_bits = 0;
8393
8394     if (host_bits & float_flag_invalid)
8395         target_bits |= 1;
8396     if (host_bits & float_flag_divbyzero)
8397         target_bits |= 2;
8398     if (host_bits & float_flag_overflow)
8399         target_bits |= 4;
8400     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
8401         target_bits |= 8;
8402     if (host_bits & float_flag_inexact)
8403         target_bits |= 0x10;
8404     if (host_bits & float_flag_input_denormal)
8405         target_bits |= 0x80;
8406     return target_bits;
8407 }
8408
8409 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
8410 {
8411     int i;
8412     uint32_t fpscr;
8413
8414     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
8415             | (env->vfp.vec_len << 16)
8416             | (env->vfp.vec_stride << 20);
8417     i = get_float_exception_flags(&env->vfp.fp_status);
8418     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
8419     fpscr |= vfp_exceptbits_from_host(i);
8420     return fpscr;
8421 }
8422
8423 uint32_t vfp_get_fpscr(CPUARMState *env)
8424 {
8425     return HELPER(vfp_get_fpscr)(env);
8426 }
8427
8428 /* Convert vfp exception flags to target form.  */
8429 static inline int vfp_exceptbits_to_host(int target_bits)
8430 {
8431     int host_bits = 0;
8432
8433     if (target_bits & 1)
8434         host_bits |= float_flag_invalid;
8435     if (target_bits & 2)
8436         host_bits |= float_flag_divbyzero;
8437     if (target_bits & 4)
8438         host_bits |= float_flag_overflow;
8439     if (target_bits & 8)
8440         host_bits |= float_flag_underflow;
8441     if (target_bits & 0x10)
8442         host_bits |= float_flag_inexact;
8443     if (target_bits & 0x80)
8444         host_bits |= float_flag_input_denormal;
8445     return host_bits;
8446 }
8447
8448 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
8449 {
8450     int i;
8451     uint32_t changed;
8452
8453     changed = env->vfp.xregs[ARM_VFP_FPSCR];
8454     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
8455     env->vfp.vec_len = (val >> 16) & 7;
8456     env->vfp.vec_stride = (val >> 20) & 3;
8457
8458     changed ^= val;
8459     if (changed & (3 << 22)) {
8460         i = (val >> 22) & 3;
8461         switch (i) {
8462         case FPROUNDING_TIEEVEN:
8463             i = float_round_nearest_even;
8464             break;
8465         case FPROUNDING_POSINF:
8466             i = float_round_up;
8467             break;
8468         case FPROUNDING_NEGINF:
8469             i = float_round_down;
8470             break;
8471         case FPROUNDING_ZERO:
8472             i = float_round_to_zero;
8473             break;
8474         }
8475         set_float_rounding_mode(i, &env->vfp.fp_status);
8476     }
8477     if (changed & (1 << 24)) {
8478         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8479         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8480     }
8481     if (changed & (1 << 25))
8482         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
8483
8484     i = vfp_exceptbits_to_host(val);
8485     set_float_exception_flags(i, &env->vfp.fp_status);
8486     set_float_exception_flags(0, &env->vfp.standard_fp_status);
8487 }
8488
8489 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
8490 {
8491     HELPER(vfp_set_fpscr)(env, val);
8492 }
8493
8494 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
8495
8496 #define VFP_BINOP(name) \
8497 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
8498 { \
8499     float_status *fpst = fpstp; \
8500     return float32_ ## name(a, b, fpst); \
8501 } \
8502 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
8503 { \
8504     float_status *fpst = fpstp; \
8505     return float64_ ## name(a, b, fpst); \
8506 }
8507 VFP_BINOP(add)
8508 VFP_BINOP(sub)
8509 VFP_BINOP(mul)
8510 VFP_BINOP(div)
8511 VFP_BINOP(min)
8512 VFP_BINOP(max)
8513 VFP_BINOP(minnum)
8514 VFP_BINOP(maxnum)
8515 #undef VFP_BINOP
8516
8517 float32 VFP_HELPER(neg, s)(float32 a)
8518 {
8519     return float32_chs(a);
8520 }
8521
8522 float64 VFP_HELPER(neg, d)(float64 a)
8523 {
8524     return float64_chs(a);
8525 }
8526
8527 float32 VFP_HELPER(abs, s)(float32 a)
8528 {
8529     return float32_abs(a);
8530 }
8531
8532 float64 VFP_HELPER(abs, d)(float64 a)
8533 {
8534     return float64_abs(a);
8535 }
8536
8537 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
8538 {
8539     return float32_sqrt(a, &env->vfp.fp_status);
8540 }
8541
8542 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
8543 {
8544     return float64_sqrt(a, &env->vfp.fp_status);
8545 }
8546
8547 /* XXX: check quiet/signaling case */
8548 #define DO_VFP_cmp(p, type) \
8549 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
8550 { \
8551     uint32_t flags; \
8552     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
8553     case 0: flags = 0x6; break; \
8554     case -1: flags = 0x8; break; \
8555     case 1: flags = 0x2; break; \
8556     default: case 2: flags = 0x3; break; \
8557     } \
8558     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8559         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8560 } \
8561 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
8562 { \
8563     uint32_t flags; \
8564     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
8565     case 0: flags = 0x6; break; \
8566     case -1: flags = 0x8; break; \
8567     case 1: flags = 0x2; break; \
8568     default: case 2: flags = 0x3; break; \
8569     } \
8570     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8571         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8572 }
8573 DO_VFP_cmp(s, float32)
8574 DO_VFP_cmp(d, float64)
8575 #undef DO_VFP_cmp
8576
8577 /* Integer to float and float to integer conversions */
8578
8579 #define CONV_ITOF(name, fsz, sign) \
8580     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
8581 { \
8582     float_status *fpst = fpstp; \
8583     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
8584 }
8585
8586 #define CONV_FTOI(name, fsz, sign, round) \
8587 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
8588 { \
8589     float_status *fpst = fpstp; \
8590     if (float##fsz##_is_any_nan(x)) { \
8591         float_raise(float_flag_invalid, fpst); \
8592         return 0; \
8593     } \
8594     return float##fsz##_to_##sign##int32##round(x, fpst); \
8595 }
8596
8597 #define FLOAT_CONVS(name, p, fsz, sign) \
8598 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
8599 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
8600 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
8601
8602 FLOAT_CONVS(si, s, 32, )
8603 FLOAT_CONVS(si, d, 64, )
8604 FLOAT_CONVS(ui, s, 32, u)
8605 FLOAT_CONVS(ui, d, 64, u)
8606
8607 #undef CONV_ITOF
8608 #undef CONV_FTOI
8609 #undef FLOAT_CONVS
8610
8611 /* floating point conversion */
8612 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
8613 {
8614     float64 r = float32_to_float64(x, &env->vfp.fp_status);
8615     /* ARM requires that S<->D conversion of any kind of NaN generates
8616      * a quiet NaN by forcing the most significant frac bit to 1.
8617      */
8618     return float64_maybe_silence_nan(r);
8619 }
8620
8621 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
8622 {
8623     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
8624     /* ARM requires that S<->D conversion of any kind of NaN generates
8625      * a quiet NaN by forcing the most significant frac bit to 1.
8626      */
8627     return float32_maybe_silence_nan(r);
8628 }
8629
8630 /* VFP3 fixed point conversion.  */
8631 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8632 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
8633                                      void *fpstp) \
8634 { \
8635     float_status *fpst = fpstp; \
8636     float##fsz tmp; \
8637     tmp = itype##_to_##float##fsz(x, fpst); \
8638     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
8639 }
8640
8641 /* Notice that we want only input-denormal exception flags from the
8642  * scalbn operation: the other possible flags (overflow+inexact if
8643  * we overflow to infinity, output-denormal) aren't correct for the
8644  * complete scale-and-convert operation.
8645  */
8646 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
8647 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
8648                                              uint32_t shift, \
8649                                              void *fpstp) \
8650 { \
8651     float_status *fpst = fpstp; \
8652     int old_exc_flags = get_float_exception_flags(fpst); \
8653     float##fsz tmp; \
8654     if (float##fsz##_is_any_nan(x)) { \
8655         float_raise(float_flag_invalid, fpst); \
8656         return 0; \
8657     } \
8658     tmp = float##fsz##_scalbn(x, shift, fpst); \
8659     old_exc_flags |= get_float_exception_flags(fpst) \
8660         & float_flag_input_denormal; \
8661     set_float_exception_flags(old_exc_flags, fpst); \
8662     return float##fsz##_to_##itype##round(tmp, fpst); \
8663 }
8664
8665 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
8666 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8667 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
8668 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8669
8670 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
8671 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8672 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8673
8674 VFP_CONV_FIX(sh, d, 64, 64, int16)
8675 VFP_CONV_FIX(sl, d, 64, 64, int32)
8676 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
8677 VFP_CONV_FIX(uh, d, 64, 64, uint16)
8678 VFP_CONV_FIX(ul, d, 64, 64, uint32)
8679 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
8680 VFP_CONV_FIX(sh, s, 32, 32, int16)
8681 VFP_CONV_FIX(sl, s, 32, 32, int32)
8682 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
8683 VFP_CONV_FIX(uh, s, 32, 32, uint16)
8684 VFP_CONV_FIX(ul, s, 32, 32, uint32)
8685 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
8686 #undef VFP_CONV_FIX
8687 #undef VFP_CONV_FIX_FLOAT
8688 #undef VFP_CONV_FLOAT_FIX_ROUND
8689
8690 /* Set the current fp rounding mode and return the old one.
8691  * The argument is a softfloat float_round_ value.
8692  */
8693 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
8694 {
8695     float_status *fp_status = &env->vfp.fp_status;
8696
8697     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8698     set_float_rounding_mode(rmode, fp_status);
8699
8700     return prev_rmode;
8701 }
8702
8703 /* Set the current fp rounding mode in the standard fp status and return
8704  * the old one. This is for NEON instructions that need to change the
8705  * rounding mode but wish to use the standard FPSCR values for everything
8706  * else. Always set the rounding mode back to the correct value after
8707  * modifying it.
8708  * The argument is a softfloat float_round_ value.
8709  */
8710 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
8711 {
8712     float_status *fp_status = &env->vfp.standard_fp_status;
8713
8714     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8715     set_float_rounding_mode(rmode, fp_status);
8716
8717     return prev_rmode;
8718 }
8719
8720 /* Half precision conversions.  */
8721 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
8722 {
8723     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8724     float32 r = float16_to_float32(make_float16(a), ieee, s);
8725     if (ieee) {
8726         return float32_maybe_silence_nan(r);
8727     }
8728     return r;
8729 }
8730
8731 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
8732 {
8733     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8734     float16 r = float32_to_float16(a, ieee, s);
8735     if (ieee) {
8736         r = float16_maybe_silence_nan(r);
8737     }
8738     return float16_val(r);
8739 }
8740
8741 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8742 {
8743     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
8744 }
8745
8746 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8747 {
8748     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
8749 }
8750
8751 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8752 {
8753     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
8754 }
8755
8756 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8757 {
8758     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
8759 }
8760
8761 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
8762 {
8763     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8764     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
8765     if (ieee) {
8766         return float64_maybe_silence_nan(r);
8767     }
8768     return r;
8769 }
8770
8771 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
8772 {
8773     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8774     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
8775     if (ieee) {
8776         r = float16_maybe_silence_nan(r);
8777     }
8778     return float16_val(r);
8779 }
8780
8781 #define float32_two make_float32(0x40000000)
8782 #define float32_three make_float32(0x40400000)
8783 #define float32_one_point_five make_float32(0x3fc00000)
8784
8785 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
8786 {
8787     float_status *s = &env->vfp.standard_fp_status;
8788     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8789         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8790         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8791             float_raise(float_flag_input_denormal, s);
8792         }
8793         return float32_two;
8794     }
8795     return float32_sub(float32_two, float32_mul(a, b, s), s);
8796 }
8797
8798 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
8799 {
8800     float_status *s = &env->vfp.standard_fp_status;
8801     float32 product;
8802     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8803         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8804         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8805             float_raise(float_flag_input_denormal, s);
8806         }
8807         return float32_one_point_five;
8808     }
8809     product = float32_mul(a, b, s);
8810     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
8811 }
8812
8813 /* NEON helpers.  */
8814
8815 /* Constants 256 and 512 are used in some helpers; we avoid relying on
8816  * int->float conversions at run-time.  */
8817 #define float64_256 make_float64(0x4070000000000000LL)
8818 #define float64_512 make_float64(0x4080000000000000LL)
8819 #define float32_maxnorm make_float32(0x7f7fffff)
8820 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
8821
8822 /* Reciprocal functions
8823  *
8824  * The algorithm that must be used to calculate the estimate
8825  * is specified by the ARM ARM, see FPRecipEstimate()
8826  */
8827
8828 static float64 recip_estimate(float64 a, float_status *real_fp_status)
8829 {
8830     /* These calculations mustn't set any fp exception flags,
8831      * so we use a local copy of the fp_status.
8832      */
8833     float_status dummy_status = *real_fp_status;
8834     float_status *s = &dummy_status;
8835     /* q = (int)(a * 512.0) */
8836     float64 q = float64_mul(float64_512, a, s);
8837     int64_t q_int = float64_to_int64_round_to_zero(q, s);
8838
8839     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
8840     q = int64_to_float64(q_int, s);
8841     q = float64_add(q, float64_half, s);
8842     q = float64_div(q, float64_512, s);
8843     q = float64_div(float64_one, q, s);
8844
8845     /* s = (int)(256.0 * r + 0.5) */
8846     q = float64_mul(q, float64_256, s);
8847     q = float64_add(q, float64_half, s);
8848     q_int = float64_to_int64_round_to_zero(q, s);
8849
8850     /* return (double)s / 256.0 */
8851     return float64_div(int64_to_float64(q_int, s), float64_256, s);
8852 }
8853
8854 /* Common wrapper to call recip_estimate */
8855 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
8856 {
8857     uint64_t val64 = float64_val(num);
8858     uint64_t frac = extract64(val64, 0, 52);
8859     int64_t exp = extract64(val64, 52, 11);
8860     uint64_t sbit;
8861     float64 scaled, estimate;
8862
8863     /* Generate the scaled number for the estimate function */
8864     if (exp == 0) {
8865         if (extract64(frac, 51, 1) == 0) {
8866             exp = -1;
8867             frac = extract64(frac, 0, 50) << 2;
8868         } else {
8869             frac = extract64(frac, 0, 51) << 1;
8870         }
8871     }
8872
8873     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
8874     scaled = make_float64((0x3feULL << 52)
8875                           | extract64(frac, 44, 8) << 44);
8876
8877     estimate = recip_estimate(scaled, fpst);
8878
8879     /* Build new result */
8880     val64 = float64_val(estimate);
8881     sbit = 0x8000000000000000ULL & val64;
8882     exp = off - exp;
8883     frac = extract64(val64, 0, 52);
8884
8885     if (exp == 0) {
8886         frac = 1ULL << 51 | extract64(frac, 1, 51);
8887     } else if (exp == -1) {
8888         frac = 1ULL << 50 | extract64(frac, 2, 50);
8889         exp = 0;
8890     }
8891
8892     return make_float64(sbit | (exp << 52) | frac);
8893 }
8894
8895 static bool round_to_inf(float_status *fpst, bool sign_bit)
8896 {
8897     switch (fpst->float_rounding_mode) {
8898     case float_round_nearest_even: /* Round to Nearest */
8899         return true;
8900     case float_round_up: /* Round to +Inf */
8901         return !sign_bit;
8902     case float_round_down: /* Round to -Inf */
8903         return sign_bit;
8904     case float_round_to_zero: /* Round to Zero */
8905         return false;
8906     }
8907
8908     g_assert_not_reached();
8909 }
8910
8911 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
8912 {
8913     float_status *fpst = fpstp;
8914     float32 f32 = float32_squash_input_denormal(input, fpst);
8915     uint32_t f32_val = float32_val(f32);
8916     uint32_t f32_sbit = 0x80000000ULL & f32_val;
8917     int32_t f32_exp = extract32(f32_val, 23, 8);
8918     uint32_t f32_frac = extract32(f32_val, 0, 23);
8919     float64 f64, r64;
8920     uint64_t r64_val;
8921     int64_t r64_exp;
8922     uint64_t r64_frac;
8923
8924     if (float32_is_any_nan(f32)) {
8925         float32 nan = f32;
8926         if (float32_is_signaling_nan(f32)) {
8927             float_raise(float_flag_invalid, fpst);
8928             nan = float32_maybe_silence_nan(f32);
8929         }
8930         if (fpst->default_nan_mode) {
8931             nan =  float32_default_nan;
8932         }
8933         return nan;
8934     } else if (float32_is_infinity(f32)) {
8935         return float32_set_sign(float32_zero, float32_is_neg(f32));
8936     } else if (float32_is_zero(f32)) {
8937         float_raise(float_flag_divbyzero, fpst);
8938         return float32_set_sign(float32_infinity, float32_is_neg(f32));
8939     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
8940         /* Abs(value) < 2.0^-128 */
8941         float_raise(float_flag_overflow | float_flag_inexact, fpst);
8942         if (round_to_inf(fpst, f32_sbit)) {
8943             return float32_set_sign(float32_infinity, float32_is_neg(f32));
8944         } else {
8945             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
8946         }
8947     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
8948         float_raise(float_flag_underflow, fpst);
8949         return float32_set_sign(float32_zero, float32_is_neg(f32));
8950     }
8951
8952
8953     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
8954     r64 = call_recip_estimate(f64, 253, fpst);
8955     r64_val = float64_val(r64);
8956     r64_exp = extract64(r64_val, 52, 11);
8957     r64_frac = extract64(r64_val, 0, 52);
8958
8959     /* result = sign : result_exp<7:0> : fraction<51:29>; */
8960     return make_float32(f32_sbit |
8961                         (r64_exp & 0xff) << 23 |
8962                         extract64(r64_frac, 29, 24));
8963 }
8964
8965 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
8966 {
8967     float_status *fpst = fpstp;
8968     float64 f64 = float64_squash_input_denormal(input, fpst);
8969     uint64_t f64_val = float64_val(f64);
8970     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
8971     int64_t f64_exp = extract64(f64_val, 52, 11);
8972     float64 r64;
8973     uint64_t r64_val;
8974     int64_t r64_exp;
8975     uint64_t r64_frac;
8976
8977     /* Deal with any special cases */
8978     if (float64_is_any_nan(f64)) {
8979         float64 nan = f64;
8980         if (float64_is_signaling_nan(f64)) {
8981             float_raise(float_flag_invalid, fpst);
8982             nan = float64_maybe_silence_nan(f64);
8983         }
8984         if (fpst->default_nan_mode) {
8985             nan =  float64_default_nan;
8986         }
8987         return nan;
8988     } else if (float64_is_infinity(f64)) {
8989         return float64_set_sign(float64_zero, float64_is_neg(f64));
8990     } else if (float64_is_zero(f64)) {
8991         float_raise(float_flag_divbyzero, fpst);
8992         return float64_set_sign(float64_infinity, float64_is_neg(f64));
8993     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
8994         /* Abs(value) < 2.0^-1024 */
8995         float_raise(float_flag_overflow | float_flag_inexact, fpst);
8996         if (round_to_inf(fpst, f64_sbit)) {
8997             return float64_set_sign(float64_infinity, float64_is_neg(f64));
8998         } else {
8999             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
9000         }
9001     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
9002         float_raise(float_flag_underflow, fpst);
9003         return float64_set_sign(float64_zero, float64_is_neg(f64));
9004     }
9005
9006     r64 = call_recip_estimate(f64, 2045, fpst);
9007     r64_val = float64_val(r64);
9008     r64_exp = extract64(r64_val, 52, 11);
9009     r64_frac = extract64(r64_val, 0, 52);
9010
9011     /* result = sign : result_exp<10:0> : fraction<51:0> */
9012     return make_float64(f64_sbit |
9013                         ((r64_exp & 0x7ff) << 52) |
9014                         r64_frac);
9015 }
9016
9017 /* The algorithm that must be used to calculate the estimate
9018  * is specified by the ARM ARM.
9019  */
9020 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
9021 {
9022     /* These calculations mustn't set any fp exception flags,
9023      * so we use a local copy of the fp_status.
9024      */
9025     float_status dummy_status = *real_fp_status;
9026     float_status *s = &dummy_status;
9027     float64 q;
9028     int64_t q_int;
9029
9030     if (float64_lt(a, float64_half, s)) {
9031         /* range 0.25 <= a < 0.5 */
9032
9033         /* a in units of 1/512 rounded down */
9034         /* q0 = (int)(a * 512.0);  */
9035         q = float64_mul(float64_512, a, s);
9036         q_int = float64_to_int64_round_to_zero(q, s);
9037
9038         /* reciprocal root r */
9039         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
9040         q = int64_to_float64(q_int, s);
9041         q = float64_add(q, float64_half, s);
9042         q = float64_div(q, float64_512, s);
9043         q = float64_sqrt(q, s);
9044         q = float64_div(float64_one, q, s);
9045     } else {
9046         /* range 0.5 <= a < 1.0 */
9047
9048         /* a in units of 1/256 rounded down */
9049         /* q1 = (int)(a * 256.0); */
9050         q = float64_mul(float64_256, a, s);
9051         int64_t q_int = float64_to_int64_round_to_zero(q, s);
9052
9053         /* reciprocal root r */
9054         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
9055         q = int64_to_float64(q_int, s);
9056         q = float64_add(q, float64_half, s);
9057         q = float64_div(q, float64_256, s);
9058         q = float64_sqrt(q, s);
9059         q = float64_div(float64_one, q, s);
9060     }
9061     /* r in units of 1/256 rounded to nearest */
9062     /* s = (int)(256.0 * r + 0.5); */
9063
9064     q = float64_mul(q, float64_256,s );
9065     q = float64_add(q, float64_half, s);
9066     q_int = float64_to_int64_round_to_zero(q, s);
9067
9068     /* return (double)s / 256.0;*/
9069     return float64_div(int64_to_float64(q_int, s), float64_256, s);
9070 }
9071
9072 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
9073 {
9074     float_status *s = fpstp;
9075     float32 f32 = float32_squash_input_denormal(input, s);
9076     uint32_t val = float32_val(f32);
9077     uint32_t f32_sbit = 0x80000000 & val;
9078     int32_t f32_exp = extract32(val, 23, 8);
9079     uint32_t f32_frac = extract32(val, 0, 23);
9080     uint64_t f64_frac;
9081     uint64_t val64;
9082     int result_exp;
9083     float64 f64;
9084
9085     if (float32_is_any_nan(f32)) {
9086         float32 nan = f32;
9087         if (float32_is_signaling_nan(f32)) {
9088             float_raise(float_flag_invalid, s);
9089             nan = float32_maybe_silence_nan(f32);
9090         }
9091         if (s->default_nan_mode) {
9092             nan =  float32_default_nan;
9093         }
9094         return nan;
9095     } else if (float32_is_zero(f32)) {
9096         float_raise(float_flag_divbyzero, s);
9097         return float32_set_sign(float32_infinity, float32_is_neg(f32));
9098     } else if (float32_is_neg(f32)) {
9099         float_raise(float_flag_invalid, s);
9100         return float32_default_nan;
9101     } else if (float32_is_infinity(f32)) {
9102         return float32_zero;
9103     }
9104
9105     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
9106      * preserving the parity of the exponent.  */
9107
9108     f64_frac = ((uint64_t) f32_frac) << 29;
9109     if (f32_exp == 0) {
9110         while (extract64(f64_frac, 51, 1) == 0) {
9111             f64_frac = f64_frac << 1;
9112             f32_exp = f32_exp-1;
9113         }
9114         f64_frac = extract64(f64_frac, 0, 51) << 1;
9115     }
9116
9117     if (extract64(f32_exp, 0, 1) == 0) {
9118         f64 = make_float64(((uint64_t) f32_sbit) << 32
9119                            | (0x3feULL << 52)
9120                            | f64_frac);
9121     } else {
9122         f64 = make_float64(((uint64_t) f32_sbit) << 32
9123                            | (0x3fdULL << 52)
9124                            | f64_frac);
9125     }
9126
9127     result_exp = (380 - f32_exp) / 2;
9128
9129     f64 = recip_sqrt_estimate(f64, s);
9130
9131     val64 = float64_val(f64);
9132
9133     val = ((result_exp & 0xff) << 23)
9134         | ((val64 >> 29)  & 0x7fffff);
9135     return make_float32(val);
9136 }
9137
9138 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
9139 {
9140     float_status *s = fpstp;
9141     float64 f64 = float64_squash_input_denormal(input, s);
9142     uint64_t val = float64_val(f64);
9143     uint64_t f64_sbit = 0x8000000000000000ULL & val;
9144     int64_t f64_exp = extract64(val, 52, 11);
9145     uint64_t f64_frac = extract64(val, 0, 52);
9146     int64_t result_exp;
9147     uint64_t result_frac;
9148
9149     if (float64_is_any_nan(f64)) {
9150         float64 nan = f64;
9151         if (float64_is_signaling_nan(f64)) {
9152             float_raise(float_flag_invalid, s);
9153             nan = float64_maybe_silence_nan(f64);
9154         }
9155         if (s->default_nan_mode) {
9156             nan =  float64_default_nan;
9157         }
9158         return nan;
9159     } else if (float64_is_zero(f64)) {
9160         float_raise(float_flag_divbyzero, s);
9161         return float64_set_sign(float64_infinity, float64_is_neg(f64));
9162     } else if (float64_is_neg(f64)) {
9163         float_raise(float_flag_invalid, s);
9164         return float64_default_nan;
9165     } else if (float64_is_infinity(f64)) {
9166         return float64_zero;
9167     }
9168
9169     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
9170      * preserving the parity of the exponent.  */
9171
9172     if (f64_exp == 0) {
9173         while (extract64(f64_frac, 51, 1) == 0) {
9174             f64_frac = f64_frac << 1;
9175             f64_exp = f64_exp - 1;
9176         }
9177         f64_frac = extract64(f64_frac, 0, 51) << 1;
9178     }
9179
9180     if (extract64(f64_exp, 0, 1) == 0) {
9181         f64 = make_float64(f64_sbit
9182                            | (0x3feULL << 52)
9183                            | f64_frac);
9184     } else {
9185         f64 = make_float64(f64_sbit
9186                            | (0x3fdULL << 52)
9187                            | f64_frac);
9188     }
9189
9190     result_exp = (3068 - f64_exp) / 2;
9191
9192     f64 = recip_sqrt_estimate(f64, s);
9193
9194     result_frac = extract64(float64_val(f64), 0, 52);
9195
9196     return make_float64(f64_sbit |
9197                         ((result_exp & 0x7ff) << 52) |
9198                         result_frac);
9199 }
9200
9201 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
9202 {
9203     float_status *s = fpstp;
9204     float64 f64;
9205
9206     if ((a & 0x80000000) == 0) {
9207         return 0xffffffff;
9208     }
9209
9210     f64 = make_float64((0x3feULL << 52)
9211                        | ((int64_t)(a & 0x7fffffff) << 21));
9212
9213     f64 = recip_estimate(f64, s);
9214
9215     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
9216 }
9217
9218 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
9219 {
9220     float_status *fpst = fpstp;
9221     float64 f64;
9222
9223     if ((a & 0xc0000000) == 0) {
9224         return 0xffffffff;
9225     }
9226
9227     if (a & 0x80000000) {
9228         f64 = make_float64((0x3feULL << 52)
9229                            | ((uint64_t)(a & 0x7fffffff) << 21));
9230     } else { /* bits 31-30 == '01' */
9231         f64 = make_float64((0x3fdULL << 52)
9232                            | ((uint64_t)(a & 0x3fffffff) << 22));
9233     }
9234
9235     f64 = recip_sqrt_estimate(f64, fpst);
9236
9237     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
9238 }
9239
9240 /* VFPv4 fused multiply-accumulate */
9241 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
9242 {
9243     float_status *fpst = fpstp;
9244     return float32_muladd(a, b, c, 0, fpst);
9245 }
9246
9247 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
9248 {
9249     float_status *fpst = fpstp;
9250     return float64_muladd(a, b, c, 0, fpst);
9251 }
9252
9253 /* ARMv8 round to integral */
9254 float32 HELPER(rints_exact)(float32 x, void *fp_status)
9255 {
9256     return float32_round_to_int(x, fp_status);
9257 }
9258
9259 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
9260 {
9261     return float64_round_to_int(x, fp_status);
9262 }
9263
9264 float32 HELPER(rints)(float32 x, void *fp_status)
9265 {
9266     int old_flags = get_float_exception_flags(fp_status), new_flags;
9267     float32 ret;
9268
9269     ret = float32_round_to_int(x, fp_status);
9270
9271     /* Suppress any inexact exceptions the conversion produced */
9272     if (!(old_flags & float_flag_inexact)) {
9273         new_flags = get_float_exception_flags(fp_status);
9274         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
9275     }
9276
9277     return ret;
9278 }
9279
9280 float64 HELPER(rintd)(float64 x, void *fp_status)
9281 {
9282     int old_flags = get_float_exception_flags(fp_status), new_flags;
9283     float64 ret;
9284
9285     ret = float64_round_to_int(x, fp_status);
9286
9287     new_flags = get_float_exception_flags(fp_status);
9288
9289     /* Suppress any inexact exceptions the conversion produced */
9290     if (!(old_flags & float_flag_inexact)) {
9291         new_flags = get_float_exception_flags(fp_status);
9292         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
9293     }
9294
9295     return ret;
9296 }
9297
9298 /* Convert ARM rounding mode to softfloat */
9299 int arm_rmode_to_sf(int rmode)
9300 {
9301     switch (rmode) {
9302     case FPROUNDING_TIEAWAY:
9303         rmode = float_round_ties_away;
9304         break;
9305     case FPROUNDING_ODD:
9306         /* FIXME: add support for TIEAWAY and ODD */
9307         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
9308                       rmode);
9309     case FPROUNDING_TIEEVEN:
9310     default:
9311         rmode = float_round_nearest_even;
9312         break;
9313     case FPROUNDING_POSINF:
9314         rmode = float_round_up;
9315         break;
9316     case FPROUNDING_NEGINF:
9317         rmode = float_round_down;
9318         break;
9319     case FPROUNDING_ZERO:
9320         rmode = float_round_to_zero;
9321         break;
9322     }
9323     return rmode;
9324 }
9325
9326 /* CRC helpers.
9327  * The upper bytes of val (above the number specified by 'bytes') must have
9328  * been zeroed out by the caller.
9329  */
9330 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
9331 {
9332     uint8_t buf[4];
9333
9334     stl_le_p(buf, val);
9335
9336     /* zlib crc32 converts the accumulator and output to one's complement.  */
9337     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
9338 }
9339
9340 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
9341 {
9342     uint8_t buf[4];
9343
9344     stl_le_p(buf, val);
9345
9346     /* Linux crc32c converts the output to one's complement.  */
9347     return crc32c(acc, buf, bytes) ^ 0xffffffff;
9348 }