2 * TI OMAP interrupt controller emulation.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "hw/qdev-properties.h"
24 #include "hw/arm/omap.h"
25 #include "hw/sysbus.h"
26 #include "qemu/error-report.h"
27 #include "qemu/module.h"
28 #include "qapi/error.h"
30 /* Interrupt Handlers */
31 struct omap_intr_handler_bank_s
{
38 unsigned char priority
[32];
41 struct omap_intr_handler_s
{
42 SysBusDevice parent_obj
;
45 qemu_irq parent_intr
[2];
60 struct omap_intr_handler_bank_s bank
[3];
63 static void omap_inth_sir_update(struct omap_intr_handler_s
*s
, int is_fiq
)
65 int i
, j
, sir_intr
, p_intr
, p
;
70 /* Find the interrupt line with the highest dynamic priority.
71 * Note: 0 denotes the hightest priority.
72 * If all interrupts have the same priority, the default order is IRQ_N,
73 * IRQ_N-1,...,IRQ_0. */
74 for (j
= 0; j
< s
->nbanks
; ++j
) {
75 level
= s
->bank
[j
].irqs
& ~s
->bank
[j
].mask
&
76 (is_fiq
? s
->bank
[j
].fiq
: ~s
->bank
[j
].fiq
);
80 p
= s
->bank
[j
].priority
[i
];
83 sir_intr
= 32 * j
+ i
;
88 s
->sir_intr
[is_fiq
] = sir_intr
;
91 static inline void omap_inth_update(struct omap_intr_handler_s
*s
, int is_fiq
)
94 uint32_t has_intr
= 0;
96 for (i
= 0; i
< s
->nbanks
; ++i
)
97 has_intr
|= s
->bank
[i
].irqs
& ~s
->bank
[i
].mask
&
98 (is_fiq
? s
->bank
[i
].fiq
: ~s
->bank
[i
].fiq
);
100 if (s
->new_agr
[is_fiq
] & has_intr
& s
->mask
) {
101 s
->new_agr
[is_fiq
] = 0;
102 omap_inth_sir_update(s
, is_fiq
);
103 qemu_set_irq(s
->parent_intr
[is_fiq
], 1);
107 #define INT_FALLING_EDGE 0
108 #define INT_LOW_LEVEL 1
110 static void omap_set_intr(void *opaque
, int irq
, int req
)
112 struct omap_intr_handler_s
*ih
= (struct omap_intr_handler_s
*) opaque
;
115 struct omap_intr_handler_bank_s
*bank
= &ih
->bank
[irq
>> 5];
119 rise
= ~bank
->irqs
& (1 << n
);
120 if (~bank
->sens_edge
& (1 << n
))
121 rise
&= ~bank
->inputs
;
123 bank
->inputs
|= (1 << n
);
126 omap_inth_update(ih
, 0);
127 omap_inth_update(ih
, 1);
130 rise
= bank
->sens_edge
& bank
->irqs
& (1 << n
);
132 bank
->inputs
&= ~(1 << n
);
136 /* Simplified version with no edge detection */
137 static void omap_set_intr_noedge(void *opaque
, int irq
, int req
)
139 struct omap_intr_handler_s
*ih
= (struct omap_intr_handler_s
*) opaque
;
142 struct omap_intr_handler_bank_s
*bank
= &ih
->bank
[irq
>> 5];
146 rise
= ~bank
->inputs
& (1 << n
);
148 bank
->irqs
|= bank
->inputs
|= rise
;
149 omap_inth_update(ih
, 0);
150 omap_inth_update(ih
, 1);
153 bank
->irqs
= (bank
->inputs
&= ~(1 << n
)) | bank
->swi
;
156 static uint64_t omap_inth_read(void *opaque
, hwaddr addr
,
159 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*) opaque
;
160 int i
, offset
= addr
;
161 int bank_no
= offset
>> 8;
163 struct omap_intr_handler_bank_s
*bank
= &s
->bank
[bank_no
];
173 case 0x10: /* SIR_IRQ_CODE */
174 case 0x14: /* SIR_FIQ_CODE */
177 line_no
= s
->sir_intr
[(offset
- 0x10) >> 2];
178 bank
= &s
->bank
[line_no
>> 5];
180 if (((bank
->sens_edge
>> i
) & 1) == INT_FALLING_EDGE
)
181 bank
->irqs
&= ~(1 << i
);
184 case 0x18: /* CONTROL_REG */
189 case 0x1c: /* ILR0 */
190 case 0x20: /* ILR1 */
191 case 0x24: /* ILR2 */
192 case 0x28: /* ILR3 */
193 case 0x2c: /* ILR4 */
194 case 0x30: /* ILR5 */
195 case 0x34: /* ILR6 */
196 case 0x38: /* ILR7 */
197 case 0x3c: /* ILR8 */
198 case 0x40: /* ILR9 */
199 case 0x44: /* ILR10 */
200 case 0x48: /* ILR11 */
201 case 0x4c: /* ILR12 */
202 case 0x50: /* ILR13 */
203 case 0x54: /* ILR14 */
204 case 0x58: /* ILR15 */
205 case 0x5c: /* ILR16 */
206 case 0x60: /* ILR17 */
207 case 0x64: /* ILR18 */
208 case 0x68: /* ILR19 */
209 case 0x6c: /* ILR20 */
210 case 0x70: /* ILR21 */
211 case 0x74: /* ILR22 */
212 case 0x78: /* ILR23 */
213 case 0x7c: /* ILR24 */
214 case 0x80: /* ILR25 */
215 case 0x84: /* ILR26 */
216 case 0x88: /* ILR27 */
217 case 0x8c: /* ILR28 */
218 case 0x90: /* ILR29 */
219 case 0x94: /* ILR30 */
220 case 0x98: /* ILR31 */
221 i
= (offset
- 0x1c) >> 2;
222 return (bank
->priority
[i
] << 2) |
223 (((bank
->sens_edge
>> i
) & 1) << 1) |
224 ((bank
->fiq
>> i
) & 1);
234 static void omap_inth_write(void *opaque
, hwaddr addr
,
235 uint64_t value
, unsigned size
)
237 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*) opaque
;
238 int i
, offset
= addr
;
239 int bank_no
= offset
>> 8;
240 struct omap_intr_handler_bank_s
*bank
= &s
->bank
[bank_no
];
245 /* Important: ignore the clearing if the IRQ is level-triggered and
246 the input bit is 1 */
247 bank
->irqs
&= value
| (bank
->inputs
& bank
->sens_edge
);
252 omap_inth_update(s
, 0);
253 omap_inth_update(s
, 1);
256 case 0x10: /* SIR_IRQ_CODE */
257 case 0x14: /* SIR_FIQ_CODE */
261 case 0x18: /* CONTROL_REG */
265 qemu_set_irq(s
->parent_intr
[1], 0);
267 omap_inth_update(s
, 1);
270 qemu_set_irq(s
->parent_intr
[0], 0);
272 omap_inth_update(s
, 0);
276 case 0x1c: /* ILR0 */
277 case 0x20: /* ILR1 */
278 case 0x24: /* ILR2 */
279 case 0x28: /* ILR3 */
280 case 0x2c: /* ILR4 */
281 case 0x30: /* ILR5 */
282 case 0x34: /* ILR6 */
283 case 0x38: /* ILR7 */
284 case 0x3c: /* ILR8 */
285 case 0x40: /* ILR9 */
286 case 0x44: /* ILR10 */
287 case 0x48: /* ILR11 */
288 case 0x4c: /* ILR12 */
289 case 0x50: /* ILR13 */
290 case 0x54: /* ILR14 */
291 case 0x58: /* ILR15 */
292 case 0x5c: /* ILR16 */
293 case 0x60: /* ILR17 */
294 case 0x64: /* ILR18 */
295 case 0x68: /* ILR19 */
296 case 0x6c: /* ILR20 */
297 case 0x70: /* ILR21 */
298 case 0x74: /* ILR22 */
299 case 0x78: /* ILR23 */
300 case 0x7c: /* ILR24 */
301 case 0x80: /* ILR25 */
302 case 0x84: /* ILR26 */
303 case 0x88: /* ILR27 */
304 case 0x8c: /* ILR28 */
305 case 0x90: /* ILR29 */
306 case 0x94: /* ILR30 */
307 case 0x98: /* ILR31 */
308 i
= (offset
- 0x1c) >> 2;
309 bank
->priority
[i
] = (value
>> 2) & 0x1f;
310 bank
->sens_edge
&= ~(1 << i
);
311 bank
->sens_edge
|= ((value
>> 1) & 1) << i
;
312 bank
->fiq
&= ~(1 << i
);
313 bank
->fiq
|= (value
& 1) << i
;
317 for (i
= 0; i
< 32; i
++)
318 if (value
& (1 << i
)) {
319 omap_set_intr(s
, 32 * bank_no
+ i
, 1);
327 static const MemoryRegionOps omap_inth_mem_ops
= {
328 .read
= omap_inth_read
,
329 .write
= omap_inth_write
,
330 .endianness
= DEVICE_NATIVE_ENDIAN
,
332 .min_access_size
= 4,
333 .max_access_size
= 4,
337 static void omap_inth_reset(DeviceState
*dev
)
339 struct omap_intr_handler_s
*s
= OMAP_INTC(dev
);
342 for (i
= 0; i
< s
->nbanks
; ++i
){
343 s
->bank
[i
].irqs
= 0x00000000;
344 s
->bank
[i
].mask
= 0xffffffff;
345 s
->bank
[i
].sens_edge
= 0x00000000;
346 s
->bank
[i
].fiq
= 0x00000000;
347 s
->bank
[i
].inputs
= 0x00000000;
348 s
->bank
[i
].swi
= 0x00000000;
349 memset(s
->bank
[i
].priority
, 0, sizeof(s
->bank
[i
].priority
));
352 s
->bank
[i
].sens_edge
= 0xffffffff;
362 qemu_set_irq(s
->parent_intr
[0], 0);
363 qemu_set_irq(s
->parent_intr
[1], 0);
366 static void omap_intc_init(Object
*obj
)
368 DeviceState
*dev
= DEVICE(obj
);
369 struct omap_intr_handler_s
*s
= OMAP_INTC(obj
);
370 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
373 sysbus_init_irq(sbd
, &s
->parent_intr
[0]);
374 sysbus_init_irq(sbd
, &s
->parent_intr
[1]);
375 qdev_init_gpio_in(dev
, omap_set_intr
, s
->nbanks
* 32);
376 memory_region_init_io(&s
->mmio
, obj
, &omap_inth_mem_ops
, s
,
377 "omap-intc", s
->size
);
378 sysbus_init_mmio(sbd
, &s
->mmio
);
381 static void omap_intc_realize(DeviceState
*dev
, Error
**errp
)
383 struct omap_intr_handler_s
*s
= OMAP_INTC(dev
);
386 error_setg(errp
, "omap-intc: clk not connected");
390 void omap_intc_set_iclk(omap_intr_handler
*intc
, omap_clk clk
)
395 void omap_intc_set_fclk(omap_intr_handler
*intc
, omap_clk clk
)
400 static Property omap_intc_properties
[] = {
401 DEFINE_PROP_UINT32("size", struct omap_intr_handler_s
, size
, 0x100),
402 DEFINE_PROP_END_OF_LIST(),
405 static void omap_intc_class_init(ObjectClass
*klass
, void *data
)
407 DeviceClass
*dc
= DEVICE_CLASS(klass
);
409 dc
->reset
= omap_inth_reset
;
410 dc
->props
= omap_intc_properties
;
411 /* Reason: pointer property "clk" */
412 dc
->user_creatable
= false;
413 dc
->realize
= omap_intc_realize
;
416 static const TypeInfo omap_intc_info
= {
418 .parent
= TYPE_OMAP_INTC
,
419 .instance_init
= omap_intc_init
,
420 .class_init
= omap_intc_class_init
,
423 static uint64_t omap2_inth_read(void *opaque
, hwaddr addr
,
426 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*) opaque
;
428 int bank_no
, line_no
;
429 struct omap_intr_handler_bank_s
*bank
= NULL
;
431 if ((offset
& 0xf80) == 0x80) {
432 bank_no
= (offset
& 0x60) >> 5;
433 if (bank_no
< s
->nbanks
) {
435 bank
= &s
->bank
[bank_no
];
443 case 0x00: /* INTC_REVISION */
446 case 0x10: /* INTC_SYSCONFIG */
447 return (s
->autoidle
>> 2) & 1;
449 case 0x14: /* INTC_SYSSTATUS */
450 return 1; /* RESETDONE */
452 case 0x40: /* INTC_SIR_IRQ */
453 return s
->sir_intr
[0];
455 case 0x44: /* INTC_SIR_FIQ */
456 return s
->sir_intr
[1];
458 case 0x48: /* INTC_CONTROL */
459 return (!s
->mask
) << 2; /* GLOBALMASK */
461 case 0x4c: /* INTC_PROTECTION */
464 case 0x50: /* INTC_IDLE */
465 return s
->autoidle
& 3;
467 /* Per-bank registers */
468 case 0x80: /* INTC_ITR */
471 case 0x84: /* INTC_MIR */
474 case 0x88: /* INTC_MIR_CLEAR */
475 case 0x8c: /* INTC_MIR_SET */
478 case 0x90: /* INTC_ISR_SET */
481 case 0x94: /* INTC_ISR_CLEAR */
484 case 0x98: /* INTC_PENDING_IRQ */
485 return bank
->irqs
& ~bank
->mask
& ~bank
->fiq
;
487 case 0x9c: /* INTC_PENDING_FIQ */
488 return bank
->irqs
& ~bank
->mask
& bank
->fiq
;
490 /* Per-line registers */
491 case 0x100 ... 0x300: /* INTC_ILR */
492 bank_no
= (offset
- 0x100) >> 7;
493 if (bank_no
> s
->nbanks
)
495 bank
= &s
->bank
[bank_no
];
496 line_no
= (offset
& 0x7f) >> 2;
497 return (bank
->priority
[line_no
] << 2) |
498 ((bank
->fiq
>> line_no
) & 1);
504 static void omap2_inth_write(void *opaque
, hwaddr addr
,
505 uint64_t value
, unsigned size
)
507 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*) opaque
;
509 int bank_no
, line_no
;
510 struct omap_intr_handler_bank_s
*bank
= NULL
;
512 if ((offset
& 0xf80) == 0x80) {
513 bank_no
= (offset
& 0x60) >> 5;
514 if (bank_no
< s
->nbanks
) {
516 bank
= &s
->bank
[bank_no
];
524 case 0x10: /* INTC_SYSCONFIG */
526 s
->autoidle
|= (value
& 1) << 2;
527 if (value
& 2) { /* SOFTRESET */
528 omap_inth_reset(DEVICE(s
));
532 case 0x48: /* INTC_CONTROL */
533 s
->mask
= (value
& 4) ? 0 : ~0; /* GLOBALMASK */
534 if (value
& 2) { /* NEWFIQAGR */
535 qemu_set_irq(s
->parent_intr
[1], 0);
537 omap_inth_update(s
, 1);
539 if (value
& 1) { /* NEWIRQAGR */
540 qemu_set_irq(s
->parent_intr
[0], 0);
542 omap_inth_update(s
, 0);
546 case 0x4c: /* INTC_PROTECTION */
547 /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
548 * for every register, see Chapter 3 and 4 for privileged mode. */
550 fprintf(stderr
, "%s: protection mode enable attempt\n",
554 case 0x50: /* INTC_IDLE */
556 s
->autoidle
|= value
& 3;
559 /* Per-bank registers */
560 case 0x84: /* INTC_MIR */
562 omap_inth_update(s
, 0);
563 omap_inth_update(s
, 1);
566 case 0x88: /* INTC_MIR_CLEAR */
567 bank
->mask
&= ~value
;
568 omap_inth_update(s
, 0);
569 omap_inth_update(s
, 1);
572 case 0x8c: /* INTC_MIR_SET */
576 case 0x90: /* INTC_ISR_SET */
577 bank
->irqs
|= bank
->swi
|= value
;
578 omap_inth_update(s
, 0);
579 omap_inth_update(s
, 1);
582 case 0x94: /* INTC_ISR_CLEAR */
584 bank
->irqs
= bank
->swi
& bank
->inputs
;
587 /* Per-line registers */
588 case 0x100 ... 0x300: /* INTC_ILR */
589 bank_no
= (offset
- 0x100) >> 7;
590 if (bank_no
> s
->nbanks
)
592 bank
= &s
->bank
[bank_no
];
593 line_no
= (offset
& 0x7f) >> 2;
594 bank
->priority
[line_no
] = (value
>> 2) & 0x3f;
595 bank
->fiq
&= ~(1 << line_no
);
596 bank
->fiq
|= (value
& 1) << line_no
;
599 case 0x00: /* INTC_REVISION */
600 case 0x14: /* INTC_SYSSTATUS */
601 case 0x40: /* INTC_SIR_IRQ */
602 case 0x44: /* INTC_SIR_FIQ */
603 case 0x80: /* INTC_ITR */
604 case 0x98: /* INTC_PENDING_IRQ */
605 case 0x9c: /* INTC_PENDING_FIQ */
612 static const MemoryRegionOps omap2_inth_mem_ops
= {
613 .read
= omap2_inth_read
,
614 .write
= omap2_inth_write
,
615 .endianness
= DEVICE_NATIVE_ENDIAN
,
617 .min_access_size
= 4,
618 .max_access_size
= 4,
622 static void omap2_intc_init(Object
*obj
)
624 DeviceState
*dev
= DEVICE(obj
);
625 struct omap_intr_handler_s
*s
= OMAP_INTC(obj
);
626 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
630 sysbus_init_irq(sbd
, &s
->parent_intr
[0]);
631 sysbus_init_irq(sbd
, &s
->parent_intr
[1]);
632 qdev_init_gpio_in(dev
, omap_set_intr_noedge
, s
->nbanks
* 32);
633 memory_region_init_io(&s
->mmio
, obj
, &omap2_inth_mem_ops
, s
,
634 "omap2-intc", 0x1000);
635 sysbus_init_mmio(sbd
, &s
->mmio
);
638 static void omap2_intc_realize(DeviceState
*dev
, Error
**errp
)
640 struct omap_intr_handler_s
*s
= OMAP_INTC(dev
);
643 error_setg(errp
, "omap2-intc: iclk not connected");
647 error_setg(errp
, "omap2-intc: fclk not connected");
652 static Property omap2_intc_properties
[] = {
653 DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s
,
655 DEFINE_PROP_END_OF_LIST(),
658 static void omap2_intc_class_init(ObjectClass
*klass
, void *data
)
660 DeviceClass
*dc
= DEVICE_CLASS(klass
);
662 dc
->reset
= omap_inth_reset
;
663 dc
->props
= omap2_intc_properties
;
664 /* Reason: pointer property "iclk", "fclk" */
665 dc
->user_creatable
= false;
666 dc
->realize
= omap2_intc_realize
;
669 static const TypeInfo omap2_intc_info
= {
670 .name
= "omap2-intc",
671 .parent
= TYPE_OMAP_INTC
,
672 .instance_init
= omap2_intc_init
,
673 .class_init
= omap2_intc_class_init
,
676 static const TypeInfo omap_intc_type_info
= {
677 .name
= TYPE_OMAP_INTC
,
678 .parent
= TYPE_SYS_BUS_DEVICE
,
679 .instance_size
= sizeof(struct omap_intr_handler_s
),
683 static void omap_intc_register_types(void)
685 type_register_static(&omap_intc_type_info
);
686 type_register_static(&omap_intc_info
);
687 type_register_static(&omap2_intc_info
);
690 type_init(omap_intc_register_types
)