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qxl: require spice >= 0.8.2
[qemu/ar7.git] / hw / qxl.c
blob52df97879ea8d722073f0afab924916d7221e6e3
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu-common.h"
22 #include "qemu-timer.h"
23 #include "qemu-queue.h"
24 #include "monitor.h"
25 #include "sysemu.h"
26
27 #include "qxl.h"
28
29 #undef SPICE_RING_PROD_ITEM
30 #define SPICE_RING_PROD_ITEM(r, ret) { \
31 typeof(r) start = r; \
32 typeof(r) end = r + 1; \
33 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
34 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
35 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
36 abort(); \
37 } \
38 ret = &m_item->el; \
39 }
40
41 #undef SPICE_RING_CONS_ITEM
42 #define SPICE_RING_CONS_ITEM(r, ret) { \
43 typeof(r) start = r; \
44 typeof(r) end = r + 1; \
45 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
46 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
47 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
48 abort(); \
49 } \
50 ret = &m_item->el; \
51 }
52
53 #undef ALIGN
54 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
55
56 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
57
58 #define QXL_MODE(_x, _y, _b, _o) \
59 { .x_res = _x, \
60 .y_res = _y, \
61 .bits = _b, \
62 .stride = (_x) * (_b) / 8, \
63 .x_mili = PIXEL_SIZE * (_x), \
64 .y_mili = PIXEL_SIZE * (_y), \
65 .orientation = _o, \
66 }
67
68 #define QXL_MODE_16_32(x_res, y_res, orientation) \
69 QXL_MODE(x_res, y_res, 16, orientation), \
70 QXL_MODE(x_res, y_res, 32, orientation)
71
72 #define QXL_MODE_EX(x_res, y_res) \
73 QXL_MODE_16_32(x_res, y_res, 0), \
74 QXL_MODE_16_32(y_res, x_res, 1), \
75 QXL_MODE_16_32(x_res, y_res, 2), \
76 QXL_MODE_16_32(y_res, x_res, 3)
77
78 static QXLMode qxl_modes[] = {
79 QXL_MODE_EX(640, 480),
80 QXL_MODE_EX(800, 480),
81 QXL_MODE_EX(800, 600),
82 QXL_MODE_EX(832, 624),
83 QXL_MODE_EX(960, 640),
84 QXL_MODE_EX(1024, 600),
85 QXL_MODE_EX(1024, 768),
86 QXL_MODE_EX(1152, 864),
87 QXL_MODE_EX(1152, 870),
88 QXL_MODE_EX(1280, 720),
89 QXL_MODE_EX(1280, 760),
90 QXL_MODE_EX(1280, 768),
91 QXL_MODE_EX(1280, 800),
92 QXL_MODE_EX(1280, 960),
93 QXL_MODE_EX(1280, 1024),
94 QXL_MODE_EX(1360, 768),
95 QXL_MODE_EX(1366, 768),
96 QXL_MODE_EX(1400, 1050),
97 QXL_MODE_EX(1440, 900),
98 QXL_MODE_EX(1600, 900),
99 QXL_MODE_EX(1600, 1200),
100 QXL_MODE_EX(1680, 1050),
101 QXL_MODE_EX(1920, 1080),
102 #if VGA_RAM_SIZE >= (16 * 1024 * 1024)
103 /* these modes need more than 8 MB video memory */
104 QXL_MODE_EX(1920, 1200),
105 QXL_MODE_EX(1920, 1440),
106 QXL_MODE_EX(2048, 1536),
107 QXL_MODE_EX(2560, 1440),
108 QXL_MODE_EX(2560, 1600),
109 #endif
110 #if VGA_RAM_SIZE >= (32 * 1024 * 1024)
111 /* these modes need more than 16 MB video memory */
112 QXL_MODE_EX(2560, 2048),
113 QXL_MODE_EX(2800, 2100),
114 QXL_MODE_EX(3200, 2400),
115 #endif
116 };
117
118 static PCIQXLDevice *qxl0;
119
120 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
121 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
122 static void qxl_reset_memslots(PCIQXLDevice *d);
123 static void qxl_reset_surfaces(PCIQXLDevice *d);
124 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
125
126 void qxl_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
127 {
128 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
129 if (qxl->guestdebug) {
130 va_list ap;
131 va_start(ap, msg);
132 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
133 vfprintf(stderr, msg, ap);
134 fprintf(stderr, "\n");
135 va_end(ap);
136 }
137 }
138
139
140 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
141 struct QXLRect *area, struct QXLRect *dirty_rects,
142 uint32_t num_dirty_rects,
143 uint32_t clear_dirty_region,
144 qxl_async_io async)
145 {
146 if (async == QXL_SYNC) {
147 qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
148 dirty_rects, num_dirty_rects, clear_dirty_region);
149 } else {
150 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
151 clear_dirty_region, 0);
152 }
153 }
154
155 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
156 uint32_t id)
157 {
158 qemu_mutex_lock(&qxl->track_lock);
159 qxl->guest_surfaces.cmds[id] = 0;
160 qxl->guest_surfaces.count--;
161 qemu_mutex_unlock(&qxl->track_lock);
162 }
163
164 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
165 qxl_async_io async)
166 {
167 if (async) {
168 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id,
169 (uint64_t)id);
170 } else {
171 qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
172 qxl_spice_destroy_surface_wait_complete(qxl, id);
173 }
174 }
175
176 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
177 {
178 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 0);
179 }
180
181 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
182 uint32_t count)
183 {
184 qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count);
185 }
186
187 void qxl_spice_oom(PCIQXLDevice *qxl)
188 {
189 qxl->ssd.worker->oom(qxl->ssd.worker);
190 }
191
192 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
193 {
194 qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
195 }
196
197 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
198 {
199 qemu_mutex_lock(&qxl->track_lock);
200 memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds));
201 qxl->guest_surfaces.count = 0;
202 qemu_mutex_unlock(&qxl->track_lock);
203 }
204
205 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
206 {
207 if (async) {
208 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 0);
209 } else {
210 qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
211 qxl_spice_destroy_surfaces_complete(qxl);
212 }
213 }
214
215 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
216 {
217 qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
218 }
219
220 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
221 {
222 qxl->ssd.worker->reset_cursor(qxl->ssd.worker);
223 qemu_mutex_lock(&qxl->track_lock);
224 qxl->guest_cursor = 0;
225 qemu_mutex_unlock(&qxl->track_lock);
226 }
227
228
229 static inline uint32_t msb_mask(uint32_t val)
230 {
231 uint32_t mask;
232
233 do {
234 mask = ~(val - 1) & val;
235 val &= ~mask;
236 } while (mask < val);
237
238 return mask;
239 }
240
241 static ram_addr_t qxl_rom_size(void)
242 {
243 uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
244 rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
245 rom_size = msb_mask(rom_size * 2 - 1);
246 return rom_size;
247 }
248
249 static void init_qxl_rom(PCIQXLDevice *d)
250 {
251 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
252 QXLModes *modes = (QXLModes *)(rom + 1);
253 uint32_t ram_header_size;
254 uint32_t surface0_area_size;
255 uint32_t num_pages;
256 uint32_t fb, maxfb = 0;
257 int i;
258
259 memset(rom, 0, d->rom_size);
260
261 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
262 rom->id = cpu_to_le32(d->id);
263 rom->log_level = cpu_to_le32(d->guestdebug);
264 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
265
266 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
267 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
268 rom->slots_start = 1;
269 rom->slots_end = NUM_MEMSLOTS - 1;
270 rom->n_surfaces = cpu_to_le32(NUM_SURFACES);
271
272 modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes));
273 for (i = 0; i < modes->n_modes; i++) {
274 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
275 if (maxfb < fb) {
276 maxfb = fb;
277 }
278 modes->modes[i].id = cpu_to_le32(i);
279 modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res);
280 modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res);
281 modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits);
282 modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride);
283 modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
284 modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
285 modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation);
286 }
287 if (maxfb < VGA_RAM_SIZE && d->id == 0)
288 maxfb = VGA_RAM_SIZE;
289
290 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
291 surface0_area_size = ALIGN(maxfb, 4096);
292 num_pages = d->vga.vram_size;
293 num_pages -= ram_header_size;
294 num_pages -= surface0_area_size;
295 num_pages = num_pages / TARGET_PAGE_SIZE;
296
297 rom->draw_area_offset = cpu_to_le32(0);
298 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
299 rom->pages_offset = cpu_to_le32(surface0_area_size);
300 rom->num_pages = cpu_to_le32(num_pages);
301 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
302
303 d->shadow_rom = *rom;
304 d->rom = rom;
305 d->modes = modes;
306 }
307
308 static void init_qxl_ram(PCIQXLDevice *d)
309 {
310 uint8_t *buf;
311 uint64_t *item;
312
313 buf = d->vga.vram_ptr;
314 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
315 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
316 d->ram->int_pending = cpu_to_le32(0);
317 d->ram->int_mask = cpu_to_le32(0);
318 d->ram->update_surface = 0;
319 SPICE_RING_INIT(&d->ram->cmd_ring);
320 SPICE_RING_INIT(&d->ram->cursor_ring);
321 SPICE_RING_INIT(&d->ram->release_ring);
322 SPICE_RING_PROD_ITEM(&d->ram->release_ring, item);
323 *item = 0;
324 qxl_ring_set_dirty(d);
325 }
326
327 /* can be called from spice server thread context */
328 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
329 {
330 memory_region_set_dirty(mr, addr, end - addr);
331 }
332
333 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
334 {
335 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
336 }
337
338 /* called from spice server thread context only */
339 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
340 {
341 void *base = qxl->vga.vram_ptr;
342 intptr_t offset;
343
344 offset = ptr - base;
345 offset &= ~(TARGET_PAGE_SIZE-1);
346 assert(offset < qxl->vga.vram_size);
347 qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE);
348 }
349
350 /* can be called from spice server thread context */
351 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
352 {
353 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
354 ram_addr_t end = qxl->vga.vram_size;
355 qxl_set_dirty(&qxl->vga.vram, addr, end);
356 }
357
358 /*
359 * keep track of some command state, for savevm/loadvm.
360 * called from spice server thread context only
361 */
362 static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
363 {
364 switch (le32_to_cpu(ext->cmd.type)) {
365 case QXL_CMD_SURFACE:
366 {
367 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
368 uint32_t id = le32_to_cpu(cmd->surface_id);
369 PANIC_ON(id >= NUM_SURFACES);
370 qemu_mutex_lock(&qxl->track_lock);
371 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
372 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
373 qxl->guest_surfaces.count++;
374 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
375 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
376 }
377 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
378 qxl->guest_surfaces.cmds[id] = 0;
379 qxl->guest_surfaces.count--;
380 }
381 qemu_mutex_unlock(&qxl->track_lock);
382 break;
383 }
384 case QXL_CMD_CURSOR:
385 {
386 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
387 if (cmd->type == QXL_CURSOR_SET) {
388 qemu_mutex_lock(&qxl->track_lock);
389 qxl->guest_cursor = ext->cmd.data;
390 qemu_mutex_unlock(&qxl->track_lock);
391 }
392 break;
393 }
394 }
395 }
396
397 /* spice display interface callbacks */
398
399 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
400 {
401 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
402
403 dprint(qxl, 1, "%s:\n", __FUNCTION__);
404 qxl->ssd.worker = qxl_worker;
405 }
406
407 static void interface_set_compression_level(QXLInstance *sin, int level)
408 {
409 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
410
411 dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level);
412 qxl->shadow_rom.compression_level = cpu_to_le32(level);
413 qxl->rom->compression_level = cpu_to_le32(level);
414 qxl_rom_set_dirty(qxl);
415 }
416
417 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
418 {
419 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
420
421 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
422 qxl->rom->mm_clock = cpu_to_le32(mm_time);
423 qxl_rom_set_dirty(qxl);
424 }
425
426 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
427 {
428 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
429
430 dprint(qxl, 1, "%s:\n", __FUNCTION__);
431 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
432 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
433 info->num_memslots = NUM_MEMSLOTS;
434 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
435 info->internal_groupslot_id = 0;
436 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
437 info->n_surfaces = NUM_SURFACES;
438 }
439
440 static const char *qxl_mode_to_string(int mode)
441 {
442 switch (mode) {
443 case QXL_MODE_COMPAT:
444 return "compat";
445 case QXL_MODE_NATIVE:
446 return "native";
447 case QXL_MODE_UNDEFINED:
448 return "undefined";
449 case QXL_MODE_VGA:
450 return "vga";
451 }
452 return "INVALID";
453 }
454
455 static const char *io_port_to_string(uint32_t io_port)
456 {
457 if (io_port >= QXL_IO_RANGE_SIZE) {
458 return "out of range";
459 }
460 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
461 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
462 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
463 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
464 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
465 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
466 [QXL_IO_RESET] = "QXL_IO_RESET",
467 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
468 [QXL_IO_LOG] = "QXL_IO_LOG",
469 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
470 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
471 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
472 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
473 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
474 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
475 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
476 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
477 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
478 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
479 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
480 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
481 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
482 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
483 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
484 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
485 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
486 };
487 return io_port_to_string[io_port];
488 }
489
490 /* called from spice server thread context only */
491 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
492 {
493 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
494 SimpleSpiceUpdate *update;
495 QXLCommandRing *ring;
496 QXLCommand *cmd;
497 int notify, ret;
498
499 switch (qxl->mode) {
500 case QXL_MODE_VGA:
501 dprint(qxl, 2, "%s: vga\n", __FUNCTION__);
502 ret = false;
503 qemu_mutex_lock(&qxl->ssd.lock);
504 if (qxl->ssd.update != NULL) {
505 update = qxl->ssd.update;
506 qxl->ssd.update = NULL;
507 *ext = update->ext;
508 ret = true;
509 }
510 qemu_mutex_unlock(&qxl->ssd.lock);
511 if (ret) {
512 dprint(qxl, 2, "%s %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
513 qxl_log_command(qxl, "vga", ext);
514 }
515 return ret;
516 case QXL_MODE_COMPAT:
517 case QXL_MODE_NATIVE:
518 case QXL_MODE_UNDEFINED:
519 dprint(qxl, 4, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
520 ring = &qxl->ram->cmd_ring;
521 if (SPICE_RING_IS_EMPTY(ring)) {
522 return false;
523 }
524 dprint(qxl, 2, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
525 SPICE_RING_CONS_ITEM(ring, cmd);
526 ext->cmd = *cmd;
527 ext->group_id = MEMSLOT_GROUP_GUEST;
528 ext->flags = qxl->cmdflags;
529 SPICE_RING_POP(ring, notify);
530 qxl_ring_set_dirty(qxl);
531 if (notify) {
532 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
533 }
534 qxl->guest_primary.commands++;
535 qxl_track_command(qxl, ext);
536 qxl_log_command(qxl, "cmd", ext);
537 return true;
538 default:
539 return false;
540 }
541 }
542
543 /* called from spice server thread context only */
544 static int interface_req_cmd_notification(QXLInstance *sin)
545 {
546 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
547 int wait = 1;
548
549 switch (qxl->mode) {
550 case QXL_MODE_COMPAT:
551 case QXL_MODE_NATIVE:
552 case QXL_MODE_UNDEFINED:
553 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
554 qxl_ring_set_dirty(qxl);
555 break;
556 default:
557 /* nothing */
558 break;
559 }
560 return wait;
561 }
562
563 /* called from spice server thread context only */
564 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
565 {
566 QXLReleaseRing *ring = &d->ram->release_ring;
567 uint64_t *item;
568 int notify;
569
570 #define QXL_FREE_BUNCH_SIZE 32
571
572 if (ring->prod - ring->cons + 1 == ring->num_items) {
573 /* ring full -- can't push */
574 return;
575 }
576 if (!flush && d->oom_running) {
577 /* collect everything from oom handler before pushing */
578 return;
579 }
580 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
581 /* collect a bit more before pushing */
582 return;
583 }
584
585 SPICE_RING_PUSH(ring, notify);
586 dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
587 d->num_free_res, notify ? "yes" : "no",
588 ring->prod - ring->cons, ring->num_items,
589 ring->prod, ring->cons);
590 if (notify) {
591 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
592 }
593 SPICE_RING_PROD_ITEM(ring, item);
594 *item = 0;
595 d->num_free_res = 0;
596 d->last_release = NULL;
597 qxl_ring_set_dirty(d);
598 }
599
600 /* called from spice server thread context only */
601 static void interface_release_resource(QXLInstance *sin,
602 struct QXLReleaseInfoExt ext)
603 {
604 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
605 QXLReleaseRing *ring;
606 uint64_t *item, id;
607
608 if (ext.group_id == MEMSLOT_GROUP_HOST) {
609 /* host group -> vga mode update request */
610 qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id);
611 return;
612 }
613
614 /*
615 * ext->info points into guest-visible memory
616 * pci bar 0, $command.release_info
617 */
618 ring = &qxl->ram->release_ring;
619 SPICE_RING_PROD_ITEM(ring, item);
620 if (*item == 0) {
621 /* stick head into the ring */
622 id = ext.info->id;
623 ext.info->next = 0;
624 qxl_ram_set_dirty(qxl, &ext.info->next);
625 *item = id;
626 qxl_ring_set_dirty(qxl);
627 } else {
628 /* append item to the list */
629 qxl->last_release->next = ext.info->id;
630 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
631 ext.info->next = 0;
632 qxl_ram_set_dirty(qxl, &ext.info->next);
633 }
634 qxl->last_release = ext.info;
635 qxl->num_free_res++;
636 dprint(qxl, 3, "%4d\r", qxl->num_free_res);
637 qxl_push_free_res(qxl, 0);
638 }
639
640 /* called from spice server thread context only */
641 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
642 {
643 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
644 QXLCursorRing *ring;
645 QXLCommand *cmd;
646 int notify;
647
648 switch (qxl->mode) {
649 case QXL_MODE_COMPAT:
650 case QXL_MODE_NATIVE:
651 case QXL_MODE_UNDEFINED:
652 ring = &qxl->ram->cursor_ring;
653 if (SPICE_RING_IS_EMPTY(ring)) {
654 return false;
655 }
656 SPICE_RING_CONS_ITEM(ring, cmd);
657 ext->cmd = *cmd;
658 ext->group_id = MEMSLOT_GROUP_GUEST;
659 ext->flags = qxl->cmdflags;
660 SPICE_RING_POP(ring, notify);
661 qxl_ring_set_dirty(qxl);
662 if (notify) {
663 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
664 }
665 qxl->guest_primary.commands++;
666 qxl_track_command(qxl, ext);
667 qxl_log_command(qxl, "csr", ext);
668 if (qxl->id == 0) {
669 qxl_render_cursor(qxl, ext);
670 }
671 return true;
672 default:
673 return false;
674 }
675 }
676
677 /* called from spice server thread context only */
678 static int interface_req_cursor_notification(QXLInstance *sin)
679 {
680 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
681 int wait = 1;
682
683 switch (qxl->mode) {
684 case QXL_MODE_COMPAT:
685 case QXL_MODE_NATIVE:
686 case QXL_MODE_UNDEFINED:
687 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
688 qxl_ring_set_dirty(qxl);
689 break;
690 default:
691 /* nothing */
692 break;
693 }
694 return wait;
695 }
696
697 /* called from spice server thread context */
698 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
699 {
700 fprintf(stderr, "%s: abort()\n", __FUNCTION__);
701 abort();
702 }
703
704 /* called from spice server thread context only */
705 static int interface_flush_resources(QXLInstance *sin)
706 {
707 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
708 int ret;
709
710 dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res);
711 ret = qxl->num_free_res;
712 if (ret) {
713 qxl_push_free_res(qxl, 1);
714 }
715 return ret;
716 }
717
718 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
719
720 /* called from spice server thread context only */
721 static void interface_async_complete(QXLInstance *sin, uint64_t cookie)
722 {
723 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
724 uint32_t current_async;
725
726 qemu_mutex_lock(&qxl->async_lock);
727 current_async = qxl->current_async;
728 qxl->current_async = QXL_UNDEFINED_IO;
729 qemu_mutex_unlock(&qxl->async_lock);
730
731 dprint(qxl, 2, "async_complete: %d (%" PRId64 ") done\n",
732 current_async, cookie);
733 switch (current_async) {
734 case QXL_IO_CREATE_PRIMARY_ASYNC:
735 qxl_create_guest_primary_complete(qxl);
736 break;
737 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
738 qxl_spice_destroy_surfaces_complete(qxl);
739 break;
740 case QXL_IO_DESTROY_SURFACE_ASYNC:
741 qxl_spice_destroy_surface_wait_complete(qxl, (uint32_t)cookie);
742 break;
743 }
744 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
745 }
746
747 static const QXLInterface qxl_interface = {
748 .base.type = SPICE_INTERFACE_QXL,
749 .base.description = "qxl gpu",
750 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
751 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
752
753 .attache_worker = interface_attach_worker,
754 .set_compression_level = interface_set_compression_level,
755 .set_mm_time = interface_set_mm_time,
756 .get_init_info = interface_get_init_info,
757
758 /* the callbacks below are called from spice server thread context */
759 .get_command = interface_get_command,
760 .req_cmd_notification = interface_req_cmd_notification,
761 .release_resource = interface_release_resource,
762 .get_cursor_command = interface_get_cursor_command,
763 .req_cursor_notification = interface_req_cursor_notification,
764 .notify_update = interface_notify_update,
765 .flush_resources = interface_flush_resources,
766 .async_complete = interface_async_complete,
767 };
768
769 static void qxl_enter_vga_mode(PCIQXLDevice *d)
770 {
771 if (d->mode == QXL_MODE_VGA) {
772 return;
773 }
774 dprint(d, 1, "%s\n", __FUNCTION__);
775 qemu_spice_create_host_primary(&d->ssd);
776 d->mode = QXL_MODE_VGA;
777 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
778 }
779
780 static void qxl_exit_vga_mode(PCIQXLDevice *d)
781 {
782 if (d->mode != QXL_MODE_VGA) {
783 return;
784 }
785 dprint(d, 1, "%s\n", __FUNCTION__);
786 qxl_destroy_primary(d, QXL_SYNC);
787 }
788
789 static void qxl_update_irq(PCIQXLDevice *d)
790 {
791 uint32_t pending = le32_to_cpu(d->ram->int_pending);
792 uint32_t mask = le32_to_cpu(d->ram->int_mask);
793 int level = !!(pending & mask);
794 qemu_set_irq(d->pci.irq[0], level);
795 qxl_ring_set_dirty(d);
796 }
797
798 static void qxl_check_state(PCIQXLDevice *d)
799 {
800 QXLRam *ram = d->ram;
801
802 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
803 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
804 }
805
806 static void qxl_reset_state(PCIQXLDevice *d)
807 {
808 QXLRom *rom = d->rom;
809
810 qxl_check_state(d);
811 d->shadow_rom.update_id = cpu_to_le32(0);
812 *rom = d->shadow_rom;
813 qxl_rom_set_dirty(d);
814 init_qxl_ram(d);
815 d->num_free_res = 0;
816 d->last_release = NULL;
817 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
818 }
819
820 static void qxl_soft_reset(PCIQXLDevice *d)
821 {
822 dprint(d, 1, "%s:\n", __FUNCTION__);
823 qxl_check_state(d);
824
825 if (d->id == 0) {
826 qxl_enter_vga_mode(d);
827 } else {
828 d->mode = QXL_MODE_UNDEFINED;
829 }
830 }
831
832 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
833 {
834 dprint(d, 1, "%s: start%s\n", __FUNCTION__,
835 loadvm ? " (loadvm)" : "");
836
837 qxl_spice_reset_cursor(d);
838 qxl_spice_reset_image_cache(d);
839 qxl_reset_surfaces(d);
840 qxl_reset_memslots(d);
841
842 /* pre loadvm reset must not touch QXLRam. This lives in
843 * device memory, is migrated together with RAM and thus
844 * already loaded at this point */
845 if (!loadvm) {
846 qxl_reset_state(d);
847 }
848 qemu_spice_create_host_memslot(&d->ssd);
849 qxl_soft_reset(d);
850
851 dprint(d, 1, "%s: done\n", __FUNCTION__);
852 }
853
854 static void qxl_reset_handler(DeviceState *dev)
855 {
856 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
857 qxl_hard_reset(d, 0);
858 }
859
860 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
861 {
862 VGACommonState *vga = opaque;
863 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
864
865 if (qxl->mode != QXL_MODE_VGA) {
866 dprint(qxl, 1, "%s\n", __FUNCTION__);
867 qxl_destroy_primary(qxl, QXL_SYNC);
868 qxl_soft_reset(qxl);
869 }
870 vga_ioport_write(opaque, addr, val);
871 }
872
873 static const MemoryRegionPortio qxl_vga_portio_list[] = {
874 { 0x04, 2, 1, .read = vga_ioport_read,
875 .write = qxl_vga_ioport_write }, /* 3b4 */
876 { 0x0a, 1, 1, .read = vga_ioport_read,
877 .write = qxl_vga_ioport_write }, /* 3ba */
878 { 0x10, 16, 1, .read = vga_ioport_read,
879 .write = qxl_vga_ioport_write }, /* 3c0 */
880 { 0x24, 2, 1, .read = vga_ioport_read,
881 .write = qxl_vga_ioport_write }, /* 3d4 */
882 { 0x2a, 1, 1, .read = vga_ioport_read,
883 .write = qxl_vga_ioport_write }, /* 3da */
884 PORTIO_END_OF_LIST(),
885 };
886
887 static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
888 qxl_async_io async)
889 {
890 static const int regions[] = {
891 QXL_RAM_RANGE_INDEX,
892 QXL_VRAM_RANGE_INDEX,
893 };
894 uint64_t guest_start;
895 uint64_t guest_end;
896 int pci_region;
897 pcibus_t pci_start;
898 pcibus_t pci_end;
899 intptr_t virt_start;
900 QXLDevMemSlot memslot;
901 int i;
902
903 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
904 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
905
906 dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n",
907 __FUNCTION__, slot_id,
908 guest_start, guest_end);
909
910 PANIC_ON(slot_id >= NUM_MEMSLOTS);
911 PANIC_ON(guest_start > guest_end);
912
913 for (i = 0; i < ARRAY_SIZE(regions); i++) {
914 pci_region = regions[i];
915 pci_start = d->pci.io_regions[pci_region].addr;
916 pci_end = pci_start + d->pci.io_regions[pci_region].size;
917 /* mapped? */
918 if (pci_start == -1) {
919 continue;
920 }
921 /* start address in range ? */
922 if (guest_start < pci_start || guest_start > pci_end) {
923 continue;
924 }
925 /* end address in range ? */
926 if (guest_end > pci_end) {
927 continue;
928 }
929 /* passed */
930 break;
931 }
932 PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
933
934 switch (pci_region) {
935 case QXL_RAM_RANGE_INDEX:
936 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
937 break;
938 case QXL_VRAM_RANGE_INDEX:
939 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
940 break;
941 default:
942 /* should not happen */
943 abort();
944 }
945
946 memslot.slot_id = slot_id;
947 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
948 memslot.virt_start = virt_start + (guest_start - pci_start);
949 memslot.virt_end = virt_start + (guest_end - pci_start);
950 memslot.addr_delta = memslot.virt_start - delta;
951 memslot.generation = d->rom->slot_generation = 0;
952 qxl_rom_set_dirty(d);
953
954 dprint(d, 1, "%s: slot %d: host virt 0x%lx - 0x%lx\n",
955 __FUNCTION__, memslot.slot_id,
956 memslot.virt_start, memslot.virt_end);
957
958 qemu_spice_add_memslot(&d->ssd, &memslot, async);
959 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
960 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
961 d->guest_slots[slot_id].delta = delta;
962 d->guest_slots[slot_id].active = 1;
963 }
964
965 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
966 {
967 dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id);
968 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
969 d->guest_slots[slot_id].active = 0;
970 }
971
972 static void qxl_reset_memslots(PCIQXLDevice *d)
973 {
974 dprint(d, 1, "%s:\n", __FUNCTION__);
975 qxl_spice_reset_memslots(d);
976 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
977 }
978
979 static void qxl_reset_surfaces(PCIQXLDevice *d)
980 {
981 dprint(d, 1, "%s:\n", __FUNCTION__);
982 d->mode = QXL_MODE_UNDEFINED;
983 qxl_spice_destroy_surfaces(d, QXL_SYNC);
984 }
985
986 /* can be also called from spice server thread context */
987 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
988 {
989 uint64_t phys = le64_to_cpu(pqxl);
990 uint32_t slot = (phys >> (64 - 8)) & 0xff;
991 uint64_t offset = phys & 0xffffffffffff;
992
993 switch (group_id) {
994 case MEMSLOT_GROUP_HOST:
995 return (void *)(intptr_t)offset;
996 case MEMSLOT_GROUP_GUEST:
997 PANIC_ON(slot >= NUM_MEMSLOTS);
998 PANIC_ON(!qxl->guest_slots[slot].active);
999 PANIC_ON(offset < qxl->guest_slots[slot].delta);
1000 offset -= qxl->guest_slots[slot].delta;
1001 PANIC_ON(offset > qxl->guest_slots[slot].size)
1002 return qxl->guest_slots[slot].ptr + offset;
1003 default:
1004 PANIC_ON(1);
1005 }
1006 }
1007
1008 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1009 {
1010 /* for local rendering */
1011 qxl_render_resize(qxl);
1012 }
1013
1014 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1015 qxl_async_io async)
1016 {
1017 QXLDevSurfaceCreate surface;
1018 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1019
1020 assert(qxl->mode != QXL_MODE_NATIVE);
1021 qxl_exit_vga_mode(qxl);
1022
1023 dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__,
1024 le32_to_cpu(sc->width), le32_to_cpu(sc->height));
1025
1026 surface.format = le32_to_cpu(sc->format);
1027 surface.height = le32_to_cpu(sc->height);
1028 surface.mem = le64_to_cpu(sc->mem);
1029 surface.position = le32_to_cpu(sc->position);
1030 surface.stride = le32_to_cpu(sc->stride);
1031 surface.width = le32_to_cpu(sc->width);
1032 surface.type = le32_to_cpu(sc->type);
1033 surface.flags = le32_to_cpu(sc->flags);
1034
1035 surface.mouse_mode = true;
1036 surface.group_id = MEMSLOT_GROUP_GUEST;
1037 if (loadvm) {
1038 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1039 }
1040
1041 qxl->mode = QXL_MODE_NATIVE;
1042 qxl->cmdflags = 0;
1043 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1044
1045 if (async == QXL_SYNC) {
1046 qxl_create_guest_primary_complete(qxl);
1047 }
1048 }
1049
1050 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1051 * done (in QXL_SYNC case), 0 otherwise. */
1052 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1053 {
1054 if (d->mode == QXL_MODE_UNDEFINED) {
1055 return 0;
1056 }
1057
1058 dprint(d, 1, "%s\n", __FUNCTION__);
1059
1060 d->mode = QXL_MODE_UNDEFINED;
1061 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1062 qxl_spice_reset_cursor(d);
1063 return 1;
1064 }
1065
1066 static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1067 {
1068 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1069 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1070 QXLMode *mode = d->modes->modes + modenr;
1071 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1072 QXLMemSlot slot = {
1073 .mem_start = start,
1074 .mem_end = end
1075 };
1076 QXLSurfaceCreate surface = {
1077 .width = mode->x_res,
1078 .height = mode->y_res,
1079 .stride = -mode->x_res * 4,
1080 .format = SPICE_SURFACE_FMT_32_xRGB,
1081 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1082 .mouse_mode = true,
1083 .mem = devmem + d->shadow_rom.draw_area_offset,
1084 };
1085
1086 dprint(d, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%" PRIx64 " ]\n",
1087 __func__, modenr, mode->x_res, mode->y_res, mode->bits, devmem);
1088 if (!loadvm) {
1089 qxl_hard_reset(d, 0);
1090 }
1091
1092 d->guest_slots[0].slot = slot;
1093 qxl_add_memslot(d, 0, devmem, QXL_SYNC);
1094
1095 d->guest_primary.surface = surface;
1096 qxl_create_guest_primary(d, 0, QXL_SYNC);
1097
1098 d->mode = QXL_MODE_COMPAT;
1099 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1100 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
1101 if (mode->bits == 16) {
1102 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1103 }
1104 #endif
1105 d->shadow_rom.mode = cpu_to_le32(modenr);
1106 d->rom->mode = cpu_to_le32(modenr);
1107 qxl_rom_set_dirty(d);
1108 }
1109
1110 static void ioport_write(void *opaque, target_phys_addr_t addr,
1111 uint64_t val, unsigned size)
1112 {
1113 PCIQXLDevice *d = opaque;
1114 uint32_t io_port = addr;
1115 qxl_async_io async = QXL_SYNC;
1116 uint32_t orig_io_port = io_port;
1117
1118 switch (io_port) {
1119 case QXL_IO_RESET:
1120 case QXL_IO_SET_MODE:
1121 case QXL_IO_MEMSLOT_ADD:
1122 case QXL_IO_MEMSLOT_DEL:
1123 case QXL_IO_CREATE_PRIMARY:
1124 case QXL_IO_UPDATE_IRQ:
1125 case QXL_IO_LOG:
1126 case QXL_IO_MEMSLOT_ADD_ASYNC:
1127 case QXL_IO_CREATE_PRIMARY_ASYNC:
1128 break;
1129 default:
1130 if (d->mode != QXL_MODE_VGA) {
1131 break;
1132 }
1133 dprint(d, 1, "%s: unexpected port 0x%x (%s) in vga mode\n",
1134 __func__, io_port, io_port_to_string(io_port));
1135 /* be nice to buggy guest drivers */
1136 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1137 io_port <= QXL_IO_DESTROY_ALL_SURFACES_ASYNC) {
1138 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1139 }
1140 return;
1141 }
1142
1143 /* we change the io_port to avoid ifdeffery in the main switch */
1144 orig_io_port = io_port;
1145 switch (io_port) {
1146 case QXL_IO_UPDATE_AREA_ASYNC:
1147 io_port = QXL_IO_UPDATE_AREA;
1148 goto async_common;
1149 case QXL_IO_MEMSLOT_ADD_ASYNC:
1150 io_port = QXL_IO_MEMSLOT_ADD;
1151 goto async_common;
1152 case QXL_IO_CREATE_PRIMARY_ASYNC:
1153 io_port = QXL_IO_CREATE_PRIMARY;
1154 goto async_common;
1155 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1156 io_port = QXL_IO_DESTROY_PRIMARY;
1157 goto async_common;
1158 case QXL_IO_DESTROY_SURFACE_ASYNC:
1159 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1160 goto async_common;
1161 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1162 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1163 goto async_common;
1164 case QXL_IO_FLUSH_SURFACES_ASYNC:
1165 async_common:
1166 async = QXL_ASYNC;
1167 qemu_mutex_lock(&d->async_lock);
1168 if (d->current_async != QXL_UNDEFINED_IO) {
1169 qxl_guest_bug(d, "%d async started before last (%d) complete",
1170 io_port, d->current_async);
1171 qemu_mutex_unlock(&d->async_lock);
1172 return;
1173 }
1174 d->current_async = orig_io_port;
1175 qemu_mutex_unlock(&d->async_lock);
1176 dprint(d, 2, "start async %d (%"PRId64")\n", io_port, val);
1177 break;
1178 default:
1179 break;
1180 }
1181
1182 switch (io_port) {
1183 case QXL_IO_UPDATE_AREA:
1184 {
1185 QXLRect update = d->ram->update_area;
1186 qxl_spice_update_area(d, d->ram->update_surface,
1187 &update, NULL, 0, 0, async);
1188 break;
1189 }
1190 case QXL_IO_NOTIFY_CMD:
1191 qemu_spice_wakeup(&d->ssd);
1192 break;
1193 case QXL_IO_NOTIFY_CURSOR:
1194 qemu_spice_wakeup(&d->ssd);
1195 break;
1196 case QXL_IO_UPDATE_IRQ:
1197 qxl_update_irq(d);
1198 break;
1199 case QXL_IO_NOTIFY_OOM:
1200 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1201 break;
1202 }
1203 d->oom_running = 1;
1204 qxl_spice_oom(d);
1205 d->oom_running = 0;
1206 break;
1207 case QXL_IO_SET_MODE:
1208 dprint(d, 1, "QXL_SET_MODE %d\n", (int)val);
1209 qxl_set_mode(d, val, 0);
1210 break;
1211 case QXL_IO_LOG:
1212 if (d->guestdebug) {
1213 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1214 qemu_get_clock_ns(vm_clock), d->ram->log_buf);
1215 }
1216 break;
1217 case QXL_IO_RESET:
1218 dprint(d, 1, "QXL_IO_RESET\n");
1219 qxl_hard_reset(d, 0);
1220 break;
1221 case QXL_IO_MEMSLOT_ADD:
1222 if (val >= NUM_MEMSLOTS) {
1223 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1224 break;
1225 }
1226 if (d->guest_slots[val].active) {
1227 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: memory slot already active");
1228 break;
1229 }
1230 d->guest_slots[val].slot = d->ram->mem_slot;
1231 qxl_add_memslot(d, val, 0, async);
1232 break;
1233 case QXL_IO_MEMSLOT_DEL:
1234 if (val >= NUM_MEMSLOTS) {
1235 qxl_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1236 break;
1237 }
1238 qxl_del_memslot(d, val);
1239 break;
1240 case QXL_IO_CREATE_PRIMARY:
1241 if (val != 0) {
1242 qxl_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1243 async);
1244 goto cancel_async;
1245 }
1246 dprint(d, 1, "QXL_IO_CREATE_PRIMARY async=%d\n", async);
1247 d->guest_primary.surface = d->ram->create_surface;
1248 qxl_create_guest_primary(d, 0, async);
1249 break;
1250 case QXL_IO_DESTROY_PRIMARY:
1251 if (val != 0) {
1252 qxl_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1253 async);
1254 goto cancel_async;
1255 }
1256 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY (async=%d) (%s)\n", async,
1257 qxl_mode_to_string(d->mode));
1258 if (!qxl_destroy_primary(d, async)) {
1259 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY_ASYNC in %s, ignored\n",
1260 qxl_mode_to_string(d->mode));
1261 goto cancel_async;
1262 }
1263 break;
1264 case QXL_IO_DESTROY_SURFACE_WAIT:
1265 if (val >= NUM_SURFACES) {
1266 qxl_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1267 "%d >= NUM_SURFACES", async, val);
1268 goto cancel_async;
1269 }
1270 qxl_spice_destroy_surface_wait(d, val, async);
1271 break;
1272 case QXL_IO_FLUSH_RELEASE: {
1273 QXLReleaseRing *ring = &d->ram->release_ring;
1274 if (ring->prod - ring->cons + 1 == ring->num_items) {
1275 fprintf(stderr,
1276 "ERROR: no flush, full release ring [p%d,%dc]\n",
1277 ring->prod, ring->cons);
1278 }
1279 qxl_push_free_res(d, 1 /* flush */);
1280 dprint(d, 1, "QXL_IO_FLUSH_RELEASE exit (%s, s#=%d, res#=%d,%p)\n",
1281 qxl_mode_to_string(d->mode), d->guest_surfaces.count,
1282 d->num_free_res, d->last_release);
1283 break;
1284 }
1285 case QXL_IO_FLUSH_SURFACES_ASYNC:
1286 dprint(d, 1, "QXL_IO_FLUSH_SURFACES_ASYNC"
1287 " (%"PRId64") (%s, s#=%d, res#=%d)\n",
1288 val, qxl_mode_to_string(d->mode), d->guest_surfaces.count,
1289 d->num_free_res);
1290 qxl_spice_flush_surfaces_async(d);
1291 break;
1292 case QXL_IO_DESTROY_ALL_SURFACES:
1293 d->mode = QXL_MODE_UNDEFINED;
1294 qxl_spice_destroy_surfaces(d, async);
1295 break;
1296 default:
1297 fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
1298 abort();
1299 }
1300 return;
1301 cancel_async:
1302 if (async) {
1303 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1304 qemu_mutex_lock(&d->async_lock);
1305 d->current_async = QXL_UNDEFINED_IO;
1306 qemu_mutex_unlock(&d->async_lock);
1307 }
1308 }
1309
1310 static uint64_t ioport_read(void *opaque, target_phys_addr_t addr,
1311 unsigned size)
1312 {
1313 PCIQXLDevice *d = opaque;
1314
1315 dprint(d, 1, "%s: unexpected\n", __FUNCTION__);
1316 return 0xff;
1317 }
1318
1319 static const MemoryRegionOps qxl_io_ops = {
1320 .read = ioport_read,
1321 .write = ioport_write,
1322 .valid = {
1323 .min_access_size = 1,
1324 .max_access_size = 1,
1325 },
1326 };
1327
1328 static void pipe_read(void *opaque)
1329 {
1330 PCIQXLDevice *d = opaque;
1331 char dummy;
1332 int len;
1333
1334 do {
1335 len = read(d->pipe[0], &dummy, sizeof(dummy));
1336 } while (len == sizeof(dummy));
1337 qxl_update_irq(d);
1338 }
1339
1340 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1341 {
1342 uint32_t old_pending;
1343 uint32_t le_events = cpu_to_le32(events);
1344
1345 assert(d->ssd.running);
1346 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1347 if ((old_pending & le_events) == le_events) {
1348 return;
1349 }
1350 if (qemu_thread_is_self(&d->main)) {
1351 qxl_update_irq(d);
1352 } else {
1353 if (write(d->pipe[1], d, 1) != 1) {
1354 dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__);
1355 }
1356 }
1357 }
1358
1359 static void init_pipe_signaling(PCIQXLDevice *d)
1360 {
1361 if (pipe(d->pipe) < 0) {
1362 dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__);
1363 return;
1364 }
1365 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1366 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1367 fcntl(d->pipe[0], F_SETOWN, getpid());
1368
1369 qemu_thread_get_self(&d->main);
1370 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1371 }
1372
1373 /* graphics console */
1374
1375 static void qxl_hw_update(void *opaque)
1376 {
1377 PCIQXLDevice *qxl = opaque;
1378 VGACommonState *vga = &qxl->vga;
1379
1380 switch (qxl->mode) {
1381 case QXL_MODE_VGA:
1382 vga->update(vga);
1383 break;
1384 case QXL_MODE_COMPAT:
1385 case QXL_MODE_NATIVE:
1386 qxl_render_update(qxl);
1387 break;
1388 default:
1389 break;
1390 }
1391 }
1392
1393 static void qxl_hw_invalidate(void *opaque)
1394 {
1395 PCIQXLDevice *qxl = opaque;
1396 VGACommonState *vga = &qxl->vga;
1397
1398 vga->invalidate(vga);
1399 }
1400
1401 static void qxl_hw_screen_dump(void *opaque, const char *filename, bool cswitch)
1402 {
1403 PCIQXLDevice *qxl = opaque;
1404 VGACommonState *vga = &qxl->vga;
1405
1406 switch (qxl->mode) {
1407 case QXL_MODE_COMPAT:
1408 case QXL_MODE_NATIVE:
1409 qxl_render_update(qxl);
1410 ppm_save(filename, qxl->ssd.ds->surface);
1411 break;
1412 case QXL_MODE_VGA:
1413 vga->screen_dump(vga, filename, cswitch);
1414 break;
1415 default:
1416 break;
1417 }
1418 }
1419
1420 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1421 {
1422 PCIQXLDevice *qxl = opaque;
1423 VGACommonState *vga = &qxl->vga;
1424
1425 if (qxl->mode == QXL_MODE_VGA) {
1426 vga->text_update(vga, chardata);
1427 return;
1428 }
1429 }
1430
1431 static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1432 {
1433 intptr_t vram_start;
1434 int i;
1435
1436 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1437 return;
1438 }
1439
1440 /* dirty the primary surface */
1441 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1442 qxl->shadow_rom.surface0_area_size);
1443
1444 vram_start = (intptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
1445
1446 /* dirty the off-screen surfaces */
1447 for (i = 0; i < NUM_SURFACES; i++) {
1448 QXLSurfaceCmd *cmd;
1449 intptr_t surface_offset;
1450 int surface_size;
1451
1452 if (qxl->guest_surfaces.cmds[i] == 0) {
1453 continue;
1454 }
1455
1456 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1457 MEMSLOT_GROUP_GUEST);
1458 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1459 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1460 cmd->u.surface_create.data,
1461 MEMSLOT_GROUP_GUEST);
1462 surface_offset -= vram_start;
1463 surface_size = cmd->u.surface_create.height *
1464 abs(cmd->u.surface_create.stride);
1465 dprint(qxl, 3, "%s: dirty surface %d, offset %d, size %d\n", __func__,
1466 i, (int)surface_offset, surface_size);
1467 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1468 }
1469 }
1470
1471 static void qxl_vm_change_state_handler(void *opaque, int running,
1472 RunState state)
1473 {
1474 PCIQXLDevice *qxl = opaque;
1475 qemu_spice_vm_change_state_handler(&qxl->ssd, running, state);
1476
1477 if (running) {
1478 /*
1479 * if qxl_send_events was called from spice server context before
1480 * migration ended, qxl_update_irq for these events might not have been
1481 * called
1482 */
1483 qxl_update_irq(qxl);
1484 } else {
1485 /* make sure surfaces are saved before migration */
1486 qxl_dirty_surfaces(qxl);
1487 }
1488 }
1489
1490 /* display change listener */
1491
1492 static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1493 {
1494 if (qxl0->mode == QXL_MODE_VGA) {
1495 qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1496 }
1497 }
1498
1499 static void display_resize(struct DisplayState *ds)
1500 {
1501 if (qxl0->mode == QXL_MODE_VGA) {
1502 qemu_spice_display_resize(&qxl0->ssd);
1503 }
1504 }
1505
1506 static void display_refresh(struct DisplayState *ds)
1507 {
1508 if (qxl0->mode == QXL_MODE_VGA) {
1509 qemu_spice_display_refresh(&qxl0->ssd);
1510 } else {
1511 qemu_mutex_lock(&qxl0->ssd.lock);
1512 qemu_spice_cursor_refresh_unlocked(&qxl0->ssd);
1513 qemu_mutex_unlock(&qxl0->ssd.lock);
1514 }
1515 }
1516
1517 static DisplayChangeListener display_listener = {
1518 .dpy_update = display_update,
1519 .dpy_resize = display_resize,
1520 .dpy_refresh = display_refresh,
1521 };
1522
1523 static void qxl_init_ramsize(PCIQXLDevice *qxl, uint32_t ram_min_mb)
1524 {
1525 /* vga ram (bar 0) */
1526 if (qxl->ram_size_mb != -1) {
1527 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1528 }
1529 if (qxl->vga.vram_size < ram_min_mb * 1024 * 1024) {
1530 qxl->vga.vram_size = ram_min_mb * 1024 * 1024;
1531 }
1532
1533 /* vram (surfaces, bar 1) */
1534 if (qxl->vram_size_mb != -1) {
1535 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1536 }
1537 if (qxl->vram_size < 4096) {
1538 qxl->vram_size = 4096;
1539 }
1540 if (qxl->revision == 1) {
1541 qxl->vram_size = 4096;
1542 }
1543
1544 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1545 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1546 }
1547
1548 static int qxl_init_common(PCIQXLDevice *qxl)
1549 {
1550 uint8_t* config = qxl->pci.config;
1551 uint32_t pci_device_rev;
1552 uint32_t io_size;
1553
1554 qxl->mode = QXL_MODE_UNDEFINED;
1555 qxl->generation = 1;
1556 qxl->num_memslots = NUM_MEMSLOTS;
1557 qxl->num_surfaces = NUM_SURFACES;
1558 qemu_mutex_init(&qxl->track_lock);
1559 qemu_mutex_init(&qxl->async_lock);
1560 qxl->current_async = QXL_UNDEFINED_IO;
1561
1562 switch (qxl->revision) {
1563 case 1: /* spice 0.4 -- qxl-1 */
1564 pci_device_rev = QXL_REVISION_STABLE_V04;
1565 break;
1566 case 2: /* spice 0.6 -- qxl-2 */
1567 pci_device_rev = QXL_REVISION_STABLE_V06;
1568 break;
1569 case 3: /* qxl-3 */
1570 default:
1571 pci_device_rev = QXL_DEFAULT_REVISION;
1572 break;
1573 }
1574
1575 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1576 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1577
1578 qxl->rom_size = qxl_rom_size();
1579 memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size);
1580 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
1581 init_qxl_rom(qxl);
1582 init_qxl_ram(qxl);
1583
1584 memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size);
1585 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
1586
1587 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1588 if (qxl->revision == 1) {
1589 io_size = 8;
1590 }
1591
1592 memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
1593 "qxl-ioports", io_size);
1594 if (qxl->id == 0) {
1595 vga_dirty_log_start(&qxl->vga);
1596 }
1597
1598
1599 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1600 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
1601
1602 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1603 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
1604
1605 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1606 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
1607
1608 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
1609 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram_bar);
1610
1611 qxl->ssd.qxl.base.sif = &qxl_interface.base;
1612 qxl->ssd.qxl.id = qxl->id;
1613 qemu_spice_add_interface(&qxl->ssd.qxl.base);
1614 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
1615
1616 init_pipe_signaling(qxl);
1617 qxl_reset_state(qxl);
1618
1619 return 0;
1620 }
1621
1622 static int qxl_init_primary(PCIDevice *dev)
1623 {
1624 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1625 VGACommonState *vga = &qxl->vga;
1626 PortioList *qxl_vga_port_list = g_new(PortioList, 1);
1627
1628 qxl->id = 0;
1629 qxl_init_ramsize(qxl, 32);
1630 vga_common_init(vga, qxl->vga.vram_size);
1631 vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false);
1632 portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
1633 portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
1634
1635 vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
1636 qxl_hw_screen_dump, qxl_hw_text_update, qxl);
1637 qemu_spice_display_init_common(&qxl->ssd, vga->ds);
1638
1639 qxl0 = qxl;
1640 register_displaychangelistener(vga->ds, &display_listener);
1641
1642 return qxl_init_common(qxl);
1643 }
1644
1645 static int qxl_init_secondary(PCIDevice *dev)
1646 {
1647 static int device_id = 1;
1648 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1649
1650 qxl->id = device_id++;
1651 qxl_init_ramsize(qxl, 16);
1652 memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size);
1653 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
1654 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
1655
1656 return qxl_init_common(qxl);
1657 }
1658
1659 static void qxl_pre_save(void *opaque)
1660 {
1661 PCIQXLDevice* d = opaque;
1662 uint8_t *ram_start = d->vga.vram_ptr;
1663
1664 dprint(d, 1, "%s:\n", __FUNCTION__);
1665 if (d->last_release == NULL) {
1666 d->last_release_offset = 0;
1667 } else {
1668 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
1669 }
1670 assert(d->last_release_offset < d->vga.vram_size);
1671 }
1672
1673 static int qxl_pre_load(void *opaque)
1674 {
1675 PCIQXLDevice* d = opaque;
1676
1677 dprint(d, 1, "%s: start\n", __FUNCTION__);
1678 qxl_hard_reset(d, 1);
1679 qxl_exit_vga_mode(d);
1680 dprint(d, 1, "%s: done\n", __FUNCTION__);
1681 return 0;
1682 }
1683
1684 static void qxl_create_memslots(PCIQXLDevice *d)
1685 {
1686 int i;
1687
1688 for (i = 0; i < NUM_MEMSLOTS; i++) {
1689 if (!d->guest_slots[i].active) {
1690 continue;
1691 }
1692 dprint(d, 1, "%s: restoring guest slot %d\n", __func__, i);
1693 qxl_add_memslot(d, i, 0, QXL_SYNC);
1694 }
1695 }
1696
1697 static int qxl_post_load(void *opaque, int version)
1698 {
1699 PCIQXLDevice* d = opaque;
1700 uint8_t *ram_start = d->vga.vram_ptr;
1701 QXLCommandExt *cmds;
1702 int in, out, newmode;
1703
1704 dprint(d, 1, "%s: start\n", __FUNCTION__);
1705
1706 assert(d->last_release_offset < d->vga.vram_size);
1707 if (d->last_release_offset == 0) {
1708 d->last_release = NULL;
1709 } else {
1710 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
1711 }
1712
1713 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
1714
1715 dprint(d, 1, "%s: restore mode (%s)\n", __FUNCTION__,
1716 qxl_mode_to_string(d->mode));
1717 newmode = d->mode;
1718 d->mode = QXL_MODE_UNDEFINED;
1719
1720 switch (newmode) {
1721 case QXL_MODE_UNDEFINED:
1722 break;
1723 case QXL_MODE_VGA:
1724 qxl_create_memslots(d);
1725 qxl_enter_vga_mode(d);
1726 break;
1727 case QXL_MODE_NATIVE:
1728 qxl_create_memslots(d);
1729 qxl_create_guest_primary(d, 1, QXL_SYNC);
1730
1731 /* replay surface-create and cursor-set commands */
1732 cmds = g_malloc0(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
1733 for (in = 0, out = 0; in < NUM_SURFACES; in++) {
1734 if (d->guest_surfaces.cmds[in] == 0) {
1735 continue;
1736 }
1737 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
1738 cmds[out].cmd.type = QXL_CMD_SURFACE;
1739 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1740 out++;
1741 }
1742 if (d->guest_cursor) {
1743 cmds[out].cmd.data = d->guest_cursor;
1744 cmds[out].cmd.type = QXL_CMD_CURSOR;
1745 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1746 out++;
1747 }
1748 qxl_spice_loadvm_commands(d, cmds, out);
1749 g_free(cmds);
1750
1751 break;
1752 case QXL_MODE_COMPAT:
1753 /* note: no need to call qxl_create_memslots, qxl_set_mode
1754 * creates the mem slot. */
1755 qxl_set_mode(d, d->shadow_rom.mode, 1);
1756 break;
1757 }
1758 dprint(d, 1, "%s: done\n", __FUNCTION__);
1759
1760 return 0;
1761 }
1762
1763 #define QXL_SAVE_VERSION 21
1764
1765 static VMStateDescription qxl_memslot = {
1766 .name = "qxl-memslot",
1767 .version_id = QXL_SAVE_VERSION,
1768 .minimum_version_id = QXL_SAVE_VERSION,
1769 .fields = (VMStateField[]) {
1770 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
1771 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
1772 VMSTATE_UINT32(active, struct guest_slots),
1773 VMSTATE_END_OF_LIST()
1774 }
1775 };
1776
1777 static VMStateDescription qxl_surface = {
1778 .name = "qxl-surface",
1779 .version_id = QXL_SAVE_VERSION,
1780 .minimum_version_id = QXL_SAVE_VERSION,
1781 .fields = (VMStateField[]) {
1782 VMSTATE_UINT32(width, QXLSurfaceCreate),
1783 VMSTATE_UINT32(height, QXLSurfaceCreate),
1784 VMSTATE_INT32(stride, QXLSurfaceCreate),
1785 VMSTATE_UINT32(format, QXLSurfaceCreate),
1786 VMSTATE_UINT32(position, QXLSurfaceCreate),
1787 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
1788 VMSTATE_UINT32(flags, QXLSurfaceCreate),
1789 VMSTATE_UINT32(type, QXLSurfaceCreate),
1790 VMSTATE_UINT64(mem, QXLSurfaceCreate),
1791 VMSTATE_END_OF_LIST()
1792 }
1793 };
1794
1795 static VMStateDescription qxl_vmstate = {
1796 .name = "qxl",
1797 .version_id = QXL_SAVE_VERSION,
1798 .minimum_version_id = QXL_SAVE_VERSION,
1799 .pre_save = qxl_pre_save,
1800 .pre_load = qxl_pre_load,
1801 .post_load = qxl_post_load,
1802 .fields = (VMStateField []) {
1803 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
1804 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
1805 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
1806 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
1807 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
1808 VMSTATE_UINT32(mode, PCIQXLDevice),
1809 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
1810 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
1811 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
1812 qxl_memslot, struct guest_slots),
1813 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
1814 qxl_surface, QXLSurfaceCreate),
1815 VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice),
1816 VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
1817 vmstate_info_uint64, uint64_t),
1818 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
1819 VMSTATE_END_OF_LIST()
1820 },
1821 };
1822
1823 static Property qxl_properties[] = {
1824 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
1825 64 * 1024 * 1024),
1826 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size,
1827 64 * 1024 * 1024),
1828 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
1829 QXL_DEFAULT_REVISION),
1830 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1831 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1832 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1833 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
1834 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram_size_mb, -1),
1835 DEFINE_PROP_END_OF_LIST(),
1836 };
1837
1838 static void qxl_primary_class_init(ObjectClass *klass, void *data)
1839 {
1840 DeviceClass *dc = DEVICE_CLASS(klass);
1841 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1842
1843 k->no_hotplug = 1;
1844 k->init = qxl_init_primary;
1845 k->romfile = "vgabios-qxl.bin";
1846 k->vendor_id = REDHAT_PCI_VENDOR_ID;
1847 k->device_id = QXL_DEVICE_ID_STABLE;
1848 k->class_id = PCI_CLASS_DISPLAY_VGA;
1849 dc->desc = "Spice QXL GPU (primary, vga compatible)";
1850 dc->reset = qxl_reset_handler;
1851 dc->vmsd = &qxl_vmstate;
1852 dc->props = qxl_properties;
1853 }
1854
1855 static TypeInfo qxl_primary_info = {
1856 .name = "qxl-vga",
1857 .parent = TYPE_PCI_DEVICE,
1858 .instance_size = sizeof(PCIQXLDevice),
1859 .class_init = qxl_primary_class_init,
1860 };
1861
1862 static void qxl_secondary_class_init(ObjectClass *klass, void *data)
1863 {
1864 DeviceClass *dc = DEVICE_CLASS(klass);
1865 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1866
1867 k->init = qxl_init_secondary;
1868 k->vendor_id = REDHAT_PCI_VENDOR_ID;
1869 k->device_id = QXL_DEVICE_ID_STABLE;
1870 k->class_id = PCI_CLASS_DISPLAY_OTHER;
1871 dc->desc = "Spice QXL GPU (secondary)";
1872 dc->reset = qxl_reset_handler;
1873 dc->vmsd = &qxl_vmstate;
1874 dc->props = qxl_properties;
1875 }
1876
1877 static TypeInfo qxl_secondary_info = {
1878 .name = "qxl",
1879 .parent = TYPE_PCI_DEVICE,
1880 .instance_size = sizeof(PCIQXLDevice),
1881 .class_init = qxl_secondary_class_init,
1882 };
1883
1884 static void qxl_register_types(void)
1885 {
1886 type_register_static(&qxl_primary_info);
1887 type_register_static(&qxl_secondary_info);
1888 }
1889
1890 type_init(qxl_register_types)
AR7 emulation for QEMU