4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
26 #include "translate.h"
27 #include "internals.h"
28 #include "qemu/host-utils.h"
30 #include "exec/semihost.h"
31 #include "exec/gen-icount.h"
33 #include "exec/helper-proto.h"
34 #include "exec/helper-gen.h"
37 #include "trace-tcg.h"
39 static TCGv_i64 cpu_X
[32];
40 static TCGv_i64 cpu_pc
;
42 /* Load/store exclusive handling */
43 static TCGv_i64 cpu_exclusive_high
;
44 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
);
46 static const char *regnames
[] = {
47 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
48 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
49 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
50 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
54 A64_SHIFT_TYPE_LSL
= 0,
55 A64_SHIFT_TYPE_LSR
= 1,
56 A64_SHIFT_TYPE_ASR
= 2,
57 A64_SHIFT_TYPE_ROR
= 3
60 /* Table based decoder typedefs - used when the relevant bits for decode
61 * are too awkwardly scattered across the instruction (eg SIMD).
63 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
65 typedef struct AArch64DecodeTable
{
68 AArch64DecodeFn
*disas_fn
;
71 /* Function prototype for gen_ functions for calling Neon helpers */
72 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
73 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
74 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
75 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
76 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
77 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
78 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
79 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
80 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
81 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
82 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
83 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
84 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
86 /* initialize TCG globals. */
87 void a64_translate_init(void)
91 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
92 offsetof(CPUARMState
, pc
),
94 for (i
= 0; i
< 32; i
++) {
95 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, xregs
[i
]),
100 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
101 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
104 static inline ARMMMUIdx
get_a64_user_mem_index(DisasContext
*s
)
106 /* Return the mmu_idx to use for A64 "unprivileged load/store" insns:
107 * if EL1, access as if EL0; otherwise access at current EL
109 switch (s
->mmu_idx
) {
110 case ARMMMUIdx_S12NSE1
:
111 return ARMMMUIdx_S12NSE0
;
112 case ARMMMUIdx_S1SE1
:
113 return ARMMMUIdx_S1SE0
;
115 g_assert_not_reached();
121 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
122 fprintf_function cpu_fprintf
, int flags
)
124 ARMCPU
*cpu
= ARM_CPU(cs
);
125 CPUARMState
*env
= &cpu
->env
;
126 uint32_t psr
= pstate_read(env
);
128 int el
= arm_current_el(env
);
129 const char *ns_status
;
131 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
132 env
->pc
, env
->xregs
[31]);
133 for (i
= 0; i
< 31; i
++) {
134 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
136 cpu_fprintf(f
, "\n");
142 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
143 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
148 cpu_fprintf(f
, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
150 psr
& PSTATE_N
? 'N' : '-',
151 psr
& PSTATE_Z
? 'Z' : '-',
152 psr
& PSTATE_C
? 'C' : '-',
153 psr
& PSTATE_V
? 'V' : '-',
156 psr
& PSTATE_SP
? 'h' : 't');
158 if (flags
& CPU_DUMP_FPU
) {
160 for (i
= 0; i
< numvfpregs
; i
+= 2) {
161 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
162 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
163 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
165 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
166 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
167 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
170 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
171 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
175 void gen_a64_set_pc_im(uint64_t val
)
177 tcg_gen_movi_i64(cpu_pc
, val
);
180 /* Load the PC from a generic TCG variable.
182 * If address tagging is enabled via the TCR TBI bits, then loading
183 * an address into the PC will clear out any tag in the it:
184 * + for EL2 and EL3 there is only one TBI bit, and if it is set
185 * then the address is zero-extended, clearing bits [63:56]
186 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
187 * and TBI1 controls addressses with bit 55 == 1.
188 * If the appropriate TBI bit is set for the address then
189 * the address is sign-extended from bit 55 into bits [63:56]
191 * We can avoid doing this for relative-branches, because the
192 * PC + offset can never overflow into the tag bits (assuming
193 * that virtual addresses are less than 56 bits wide, as they
194 * are currently), but we must handle it for branch-to-register.
196 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
199 if (s
->current_el
<= 1) {
200 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
201 * examine bit 55 of address, can just generate code.
202 * If mixed, then test via generated code
204 if (s
->tbi0
&& s
->tbi1
) {
205 TCGv_i64 tmp_reg
= tcg_temp_new_i64();
206 /* Both bits set, sign extension from bit 55 into [63:56] will
209 tcg_gen_shli_i64(tmp_reg
, src
, 8);
210 tcg_gen_sari_i64(cpu_pc
, tmp_reg
, 8);
211 tcg_temp_free_i64(tmp_reg
);
212 } else if (!s
->tbi0
&& !s
->tbi1
) {
213 /* Neither bit set, just load it as-is */
214 tcg_gen_mov_i64(cpu_pc
, src
);
216 TCGv_i64 tcg_tmpval
= tcg_temp_new_i64();
217 TCGv_i64 tcg_bit55
= tcg_temp_new_i64();
218 TCGv_i64 tcg_zero
= tcg_const_i64(0);
220 tcg_gen_andi_i64(tcg_bit55
, src
, (1ull << 55));
223 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
224 tcg_gen_andi_i64(tcg_tmpval
, src
,
225 0x00FFFFFFFFFFFFFFull
);
226 tcg_gen_movcond_i64(TCG_COND_EQ
, cpu_pc
, tcg_bit55
, tcg_zero
,
229 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
230 tcg_gen_ori_i64(tcg_tmpval
, src
,
231 0xFF00000000000000ull
);
232 tcg_gen_movcond_i64(TCG_COND_NE
, cpu_pc
, tcg_bit55
, tcg_zero
,
235 tcg_temp_free_i64(tcg_zero
);
236 tcg_temp_free_i64(tcg_bit55
);
237 tcg_temp_free_i64(tcg_tmpval
);
239 } else { /* EL > 1 */
241 /* Force tag byte to all zero */
242 tcg_gen_andi_i64(cpu_pc
, src
, 0x00FFFFFFFFFFFFFFull
);
244 /* Load unmodified address */
245 tcg_gen_mov_i64(cpu_pc
, src
);
250 typedef struct DisasCompare64
{
255 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
259 arm_test_cc(&c32
, cc
);
261 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
262 * properly. The NE/EQ comparisons are also fine with this choice. */
263 c64
->cond
= c32
.cond
;
264 c64
->value
= tcg_temp_new_i64();
265 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
270 static void a64_free_cc(DisasCompare64
*c64
)
272 tcg_temp_free_i64(c64
->value
);
275 static void gen_exception_internal(int excp
)
277 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
279 assert(excp_is_internal(excp
));
280 gen_helper_exception_internal(cpu_env
, tcg_excp
);
281 tcg_temp_free_i32(tcg_excp
);
284 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
286 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
287 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
288 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
290 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
292 tcg_temp_free_i32(tcg_el
);
293 tcg_temp_free_i32(tcg_syn
);
294 tcg_temp_free_i32(tcg_excp
);
297 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
299 gen_a64_set_pc_im(s
->pc
- offset
);
300 gen_exception_internal(excp
);
301 s
->is_jmp
= DISAS_EXC
;
304 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
305 uint32_t syndrome
, uint32_t target_el
)
307 gen_a64_set_pc_im(s
->pc
- offset
);
308 gen_exception(excp
, syndrome
, target_el
);
309 s
->is_jmp
= DISAS_EXC
;
312 static void gen_ss_advance(DisasContext
*s
)
314 /* If the singlestep state is Active-not-pending, advance to
319 gen_helper_clear_pstate_ss(cpu_env
);
323 static void gen_step_complete_exception(DisasContext
*s
)
325 /* We just completed step of an insn. Move from Active-not-pending
326 * to Active-pending, and then also take the swstep exception.
327 * This corresponds to making the (IMPDEF) choice to prioritize
328 * swstep exceptions over asynchronous exceptions taken to an exception
329 * level where debug is disabled. This choice has the advantage that
330 * we do not need to maintain internal state corresponding to the
331 * ISV/EX syndrome bits between completion of the step and generation
332 * of the exception, and our syndrome information is always correct.
335 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
336 default_exception_el(s
));
337 s
->is_jmp
= DISAS_EXC
;
340 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
342 /* No direct tb linking with singlestep (either QEMU's or the ARM
343 * debug architecture kind) or deterministic io
345 if (s
->singlestep_enabled
|| s
->ss_active
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
349 #ifndef CONFIG_USER_ONLY
350 /* Only link tbs from inside the same guest page */
351 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
359 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
361 TranslationBlock
*tb
;
364 if (use_goto_tb(s
, n
, dest
)) {
366 gen_a64_set_pc_im(dest
);
367 tcg_gen_exit_tb((intptr_t)tb
+ n
);
368 s
->is_jmp
= DISAS_TB_JUMP
;
370 gen_a64_set_pc_im(dest
);
372 gen_step_complete_exception(s
);
373 } else if (s
->singlestep_enabled
) {
374 gen_exception_internal(EXCP_DEBUG
);
377 s
->is_jmp
= DISAS_TB_JUMP
;
382 static void disas_set_insn_syndrome(DisasContext
*s
, uint32_t syn
)
384 /* We don't need to save all of the syndrome so we mask and shift
385 * out uneeded bits to help the sleb128 encoder do a better job.
387 syn
&= ARM_INSN_START_WORD2_MASK
;
388 syn
>>= ARM_INSN_START_WORD2_SHIFT
;
390 /* We check and clear insn_start_idx to catch multiple updates. */
391 assert(s
->insn_start_idx
!= 0);
392 tcg_set_insn_param(s
->insn_start_idx
, 2, syn
);
393 s
->insn_start_idx
= 0;
396 static void unallocated_encoding(DisasContext
*s
)
398 /* Unallocated and reserved encodings are uncategorized */
399 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
400 default_exception_el(s
));
403 #define unsupported_encoding(s, insn) \
405 qemu_log_mask(LOG_UNIMP, \
406 "%s:%d: unsupported instruction encoding 0x%08x " \
407 "at pc=%016" PRIx64 "\n", \
408 __FILE__, __LINE__, insn, s->pc - 4); \
409 unallocated_encoding(s); \
412 static void init_tmp_a64_array(DisasContext
*s
)
414 #ifdef CONFIG_DEBUG_TCG
416 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
417 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
420 s
->tmp_a64_count
= 0;
423 static void free_tmp_a64(DisasContext
*s
)
426 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
427 tcg_temp_free_i64(s
->tmp_a64
[i
]);
429 init_tmp_a64_array(s
);
432 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
434 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
435 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
438 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
440 TCGv_i64 t
= new_tmp_a64(s
);
441 tcg_gen_movi_i64(t
, 0);
446 * Register access functions
448 * These functions are used for directly accessing a register in where
449 * changes to the final register value are likely to be made. If you
450 * need to use a register for temporary calculation (e.g. index type
451 * operations) use the read_* form.
453 * B1.2.1 Register mappings
455 * In instruction register encoding 31 can refer to ZR (zero register) or
456 * the SP (stack pointer) depending on context. In QEMU's case we map SP
457 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
458 * This is the point of the _sp forms.
460 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
463 return new_tmp_a64_zero(s
);
469 /* register access for when 31 == SP */
470 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
475 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
476 * representing the register contents. This TCGv is an auto-freed
477 * temporary so it need not be explicitly freed, and may be modified.
479 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
481 TCGv_i64 v
= new_tmp_a64(s
);
484 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
486 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
489 tcg_gen_movi_i64(v
, 0);
494 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
496 TCGv_i64 v
= new_tmp_a64(s
);
498 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
500 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
505 /* We should have at some point before trying to access an FP register
506 * done the necessary access check, so assert that
507 * (a) we did the check and
508 * (b) we didn't then just plough ahead anyway if it failed.
509 * Print the instruction pattern in the abort message so we can figure
510 * out what we need to fix if a user encounters this problem in the wild.
512 static inline void assert_fp_access_checked(DisasContext
*s
)
514 #ifdef CONFIG_DEBUG_TCG
515 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
516 fprintf(stderr
, "target-arm: FP access check missing for "
517 "instruction 0x%08x\n", s
->insn
);
523 /* Return the offset into CPUARMState of an element of specified
524 * size, 'element' places in from the least significant end of
525 * the FP/vector register Qn.
527 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
528 int element
, TCGMemOp size
)
531 #ifdef HOST_WORDS_BIGENDIAN
532 /* This is complicated slightly because vfp.regs[2n] is
533 * still the low half and vfp.regs[2n+1] the high half
534 * of the 128 bit vector, even on big endian systems.
535 * Calculate the offset assuming a fully bigendian 128 bits,
536 * then XOR to account for the order of the two 64 bit halves.
538 offs
+= (16 - ((element
+ 1) * (1 << size
)));
541 offs
+= element
* (1 << size
);
543 offs
+= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
544 assert_fp_access_checked(s
);
548 /* Return the offset into CPUARMState of a slice (from
549 * the least significant end) of FP register Qn (ie
551 * (Note that this is not the same mapping as for A32; see cpu.h)
553 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
555 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
556 #ifdef HOST_WORDS_BIGENDIAN
557 offs
+= (8 - (1 << size
));
559 assert_fp_access_checked(s
);
563 /* Offset of the high half of the 128 bit vector Qn */
564 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
566 assert_fp_access_checked(s
);
567 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
570 /* Convenience accessors for reading and writing single and double
571 * FP registers. Writing clears the upper parts of the associated
572 * 128 bit vector register, as required by the architecture.
573 * Note that unlike the GP register accessors, the values returned
574 * by the read functions must be manually freed.
576 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
578 TCGv_i64 v
= tcg_temp_new_i64();
580 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
584 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
586 TCGv_i32 v
= tcg_temp_new_i32();
588 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
592 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
594 TCGv_i64 tcg_zero
= tcg_const_i64(0);
596 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
597 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
598 tcg_temp_free_i64(tcg_zero
);
601 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
603 TCGv_i64 tmp
= tcg_temp_new_i64();
605 tcg_gen_extu_i32_i64(tmp
, v
);
606 write_fp_dreg(s
, reg
, tmp
);
607 tcg_temp_free_i64(tmp
);
610 static TCGv_ptr
get_fpstatus_ptr(void)
612 TCGv_ptr statusptr
= tcg_temp_new_ptr();
615 /* In A64 all instructions (both FP and Neon) use the FPCR;
616 * there is no equivalent of the A32 Neon "standard FPSCR value"
617 * and all operations use vfp.fp_status.
619 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
620 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
624 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
625 * than the 32 bit equivalent.
627 static inline void gen_set_NZ64(TCGv_i64 result
)
629 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
630 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
633 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
634 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
637 gen_set_NZ64(result
);
639 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
640 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
642 tcg_gen_movi_i32(cpu_CF
, 0);
643 tcg_gen_movi_i32(cpu_VF
, 0);
646 /* dest = T0 + T1; compute C, N, V and Z flags */
647 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
650 TCGv_i64 result
, flag
, tmp
;
651 result
= tcg_temp_new_i64();
652 flag
= tcg_temp_new_i64();
653 tmp
= tcg_temp_new_i64();
655 tcg_gen_movi_i64(tmp
, 0);
656 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
658 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
660 gen_set_NZ64(result
);
662 tcg_gen_xor_i64(flag
, result
, t0
);
663 tcg_gen_xor_i64(tmp
, t0
, t1
);
664 tcg_gen_andc_i64(flag
, flag
, tmp
);
665 tcg_temp_free_i64(tmp
);
666 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
668 tcg_gen_mov_i64(dest
, result
);
669 tcg_temp_free_i64(result
);
670 tcg_temp_free_i64(flag
);
672 /* 32 bit arithmetic */
673 TCGv_i32 t0_32
= tcg_temp_new_i32();
674 TCGv_i32 t1_32
= tcg_temp_new_i32();
675 TCGv_i32 tmp
= tcg_temp_new_i32();
677 tcg_gen_movi_i32(tmp
, 0);
678 tcg_gen_extrl_i64_i32(t0_32
, t0
);
679 tcg_gen_extrl_i64_i32(t1_32
, t1
);
680 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
681 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
682 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
683 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
684 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
685 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
687 tcg_temp_free_i32(tmp
);
688 tcg_temp_free_i32(t0_32
);
689 tcg_temp_free_i32(t1_32
);
693 /* dest = T0 - T1; compute C, N, V and Z flags */
694 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
697 /* 64 bit arithmetic */
698 TCGv_i64 result
, flag
, tmp
;
700 result
= tcg_temp_new_i64();
701 flag
= tcg_temp_new_i64();
702 tcg_gen_sub_i64(result
, t0
, t1
);
704 gen_set_NZ64(result
);
706 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
707 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
709 tcg_gen_xor_i64(flag
, result
, t0
);
710 tmp
= tcg_temp_new_i64();
711 tcg_gen_xor_i64(tmp
, t0
, t1
);
712 tcg_gen_and_i64(flag
, flag
, tmp
);
713 tcg_temp_free_i64(tmp
);
714 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
715 tcg_gen_mov_i64(dest
, result
);
716 tcg_temp_free_i64(flag
);
717 tcg_temp_free_i64(result
);
719 /* 32 bit arithmetic */
720 TCGv_i32 t0_32
= tcg_temp_new_i32();
721 TCGv_i32 t1_32
= tcg_temp_new_i32();
724 tcg_gen_extrl_i64_i32(t0_32
, t0
);
725 tcg_gen_extrl_i64_i32(t1_32
, t1
);
726 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
727 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
728 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
729 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
730 tmp
= tcg_temp_new_i32();
731 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
732 tcg_temp_free_i32(t0_32
);
733 tcg_temp_free_i32(t1_32
);
734 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
735 tcg_temp_free_i32(tmp
);
736 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
740 /* dest = T0 + T1 + CF; do not compute flags. */
741 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
743 TCGv_i64 flag
= tcg_temp_new_i64();
744 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
745 tcg_gen_add_i64(dest
, t0
, t1
);
746 tcg_gen_add_i64(dest
, dest
, flag
);
747 tcg_temp_free_i64(flag
);
750 tcg_gen_ext32u_i64(dest
, dest
);
754 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
755 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
758 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
759 result
= tcg_temp_new_i64();
760 cf_64
= tcg_temp_new_i64();
761 vf_64
= tcg_temp_new_i64();
762 tmp
= tcg_const_i64(0);
764 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
765 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
766 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
767 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
768 gen_set_NZ64(result
);
770 tcg_gen_xor_i64(vf_64
, result
, t0
);
771 tcg_gen_xor_i64(tmp
, t0
, t1
);
772 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
773 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
775 tcg_gen_mov_i64(dest
, result
);
777 tcg_temp_free_i64(tmp
);
778 tcg_temp_free_i64(vf_64
);
779 tcg_temp_free_i64(cf_64
);
780 tcg_temp_free_i64(result
);
782 TCGv_i32 t0_32
, t1_32
, tmp
;
783 t0_32
= tcg_temp_new_i32();
784 t1_32
= tcg_temp_new_i32();
785 tmp
= tcg_const_i32(0);
787 tcg_gen_extrl_i64_i32(t0_32
, t0
);
788 tcg_gen_extrl_i64_i32(t1_32
, t1
);
789 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
790 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
792 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
793 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
794 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
795 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
796 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
798 tcg_temp_free_i32(tmp
);
799 tcg_temp_free_i32(t1_32
);
800 tcg_temp_free_i32(t0_32
);
805 * Load/Store generators
809 * Store from GPR register to memory.
811 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
812 TCGv_i64 tcg_addr
, int size
, int memidx
,
814 unsigned int iss_srt
,
815 bool iss_sf
, bool iss_ar
)
818 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
823 syn
= syn_data_abort_with_iss(0,
829 0, 0, 0, 0, 0, false);
830 disas_set_insn_syndrome(s
, syn
);
834 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
835 TCGv_i64 tcg_addr
, int size
,
837 unsigned int iss_srt
,
838 bool iss_sf
, bool iss_ar
)
840 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
841 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
845 * Load from memory to GPR register
847 static void do_gpr_ld_memidx(DisasContext
*s
,
848 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
849 int size
, bool is_signed
,
850 bool extend
, int memidx
,
851 bool iss_valid
, unsigned int iss_srt
,
852 bool iss_sf
, bool iss_ar
)
854 TCGMemOp memop
= s
->be_data
+ size
;
862 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
864 if (extend
&& is_signed
) {
866 tcg_gen_ext32u_i64(dest
, dest
);
872 syn
= syn_data_abort_with_iss(0,
878 0, 0, 0, 0, 0, false);
879 disas_set_insn_syndrome(s
, syn
);
883 static void do_gpr_ld(DisasContext
*s
,
884 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
885 int size
, bool is_signed
, bool extend
,
886 bool iss_valid
, unsigned int iss_srt
,
887 bool iss_sf
, bool iss_ar
)
889 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
891 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
895 * Store from FP register to memory
897 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
899 /* This writes the bottom N bits of a 128 bit wide vector to memory */
900 TCGv_i64 tmp
= tcg_temp_new_i64();
901 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
903 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
906 bool be
= s
->be_data
== MO_BE
;
907 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
909 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
910 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
912 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
913 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
915 tcg_temp_free_i64(tcg_hiaddr
);
918 tcg_temp_free_i64(tmp
);
922 * Load from memory to FP register
924 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
926 /* This always zero-extends and writes to a full 128 bit wide vector */
927 TCGv_i64 tmplo
= tcg_temp_new_i64();
931 TCGMemOp memop
= s
->be_data
+ size
;
932 tmphi
= tcg_const_i64(0);
933 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
935 bool be
= s
->be_data
== MO_BE
;
938 tmphi
= tcg_temp_new_i64();
939 tcg_hiaddr
= tcg_temp_new_i64();
941 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
942 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
944 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
946 tcg_temp_free_i64(tcg_hiaddr
);
949 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
950 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
952 tcg_temp_free_i64(tmplo
);
953 tcg_temp_free_i64(tmphi
);
957 * Vector load/store helpers.
959 * The principal difference between this and a FP load is that we don't
960 * zero extend as we are filling a partial chunk of the vector register.
961 * These functions don't support 128 bit loads/stores, which would be
962 * normal load/store operations.
964 * The _i32 versions are useful when operating on 32 bit quantities
965 * (eg for floating point single or using Neon helper functions).
968 /* Get value of an element within a vector register */
969 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
970 int element
, TCGMemOp memop
)
972 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
975 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
978 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
981 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
984 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
987 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
990 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
994 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
997 g_assert_not_reached();
1001 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1002 int element
, TCGMemOp memop
)
1004 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1007 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1010 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1013 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1016 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1020 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1023 g_assert_not_reached();
1027 /* Set value of an element within a vector register */
1028 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1029 int element
, TCGMemOp memop
)
1031 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1034 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1037 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1040 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1043 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1046 g_assert_not_reached();
1050 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1051 int destidx
, int element
, TCGMemOp memop
)
1053 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1056 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1059 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1062 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1065 g_assert_not_reached();
1069 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
1070 * vector ops all need to do this).
1072 static void clear_vec_high(DisasContext
*s
, int rd
)
1074 TCGv_i64 tcg_zero
= tcg_const_i64(0);
1076 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
1077 tcg_temp_free_i64(tcg_zero
);
1080 /* Store from vector register to memory */
1081 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1082 TCGv_i64 tcg_addr
, int size
)
1084 TCGMemOp memop
= s
->be_data
+ size
;
1085 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1087 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1088 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1090 tcg_temp_free_i64(tcg_tmp
);
1093 /* Load from memory to vector register */
1094 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1095 TCGv_i64 tcg_addr
, int size
)
1097 TCGMemOp memop
= s
->be_data
+ size
;
1098 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1100 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1101 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1103 tcg_temp_free_i64(tcg_tmp
);
1106 /* Check that FP/Neon access is enabled. If it is, return
1107 * true. If not, emit code to generate an appropriate exception,
1108 * and return false; the caller should not emit any code for
1109 * the instruction. Note that this check must happen after all
1110 * unallocated-encoding checks (otherwise the syndrome information
1111 * for the resulting exception will be incorrect).
1113 static inline bool fp_access_check(DisasContext
*s
)
1115 assert(!s
->fp_access_checked
);
1116 s
->fp_access_checked
= true;
1118 if (!s
->fp_excp_el
) {
1122 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1128 * This utility function is for doing register extension with an
1129 * optional shift. You will likely want to pass a temporary for the
1130 * destination register. See DecodeRegExtend() in the ARM ARM.
1132 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1133 int option
, unsigned int shift
)
1135 int extsize
= extract32(option
, 0, 2);
1136 bool is_signed
= extract32(option
, 2, 1);
1141 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1144 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1147 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1150 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1156 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1159 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1162 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1165 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1171 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1175 static inline void gen_check_sp_alignment(DisasContext
*s
)
1177 /* The AArch64 architecture mandates that (if enabled via PSTATE
1178 * or SCTLR bits) there is a check that SP is 16-aligned on every
1179 * SP-relative load or store (with an exception generated if it is not).
1180 * In line with general QEMU practice regarding misaligned accesses,
1181 * we omit these checks for the sake of guest program performance.
1182 * This function is provided as a hook so we can more easily add these
1183 * checks in future (possibly as a "favour catching guest program bugs
1184 * over speed" user selectable option).
1189 * This provides a simple table based table lookup decoder. It is
1190 * intended to be used when the relevant bits for decode are too
1191 * awkwardly placed and switch/if based logic would be confusing and
1192 * deeply nested. Since it's a linear search through the table, tables
1193 * should be kept small.
1195 * It returns the first handler where insn & mask == pattern, or
1196 * NULL if there is no match.
1197 * The table is terminated by an empty mask (i.e. 0)
1199 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1202 const AArch64DecodeTable
*tptr
= table
;
1204 while (tptr
->mask
) {
1205 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1206 return tptr
->disas_fn
;
1214 * the instruction disassembly implemented here matches
1215 * the instruction encoding classifications in chapter 3 (C3)
1216 * of the ARM Architecture Reference Manual (DDI0487A_a)
1219 /* C3.2.7 Unconditional branch (immediate)
1221 * +----+-----------+-------------------------------------+
1222 * | op | 0 0 1 0 1 | imm26 |
1223 * +----+-----------+-------------------------------------+
1225 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1227 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1229 if (insn
& (1U << 31)) {
1230 /* C5.6.26 BL Branch with link */
1231 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1234 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1235 gen_goto_tb(s
, 0, addr
);
1238 /* C3.2.1 Compare & branch (immediate)
1239 * 31 30 25 24 23 5 4 0
1240 * +----+-------------+----+---------------------+--------+
1241 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1242 * +----+-------------+----+---------------------+--------+
1244 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1246 unsigned int sf
, op
, rt
;
1248 TCGLabel
*label_match
;
1251 sf
= extract32(insn
, 31, 1);
1252 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1253 rt
= extract32(insn
, 0, 5);
1254 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1256 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1257 label_match
= gen_new_label();
1259 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1260 tcg_cmp
, 0, label_match
);
1262 gen_goto_tb(s
, 0, s
->pc
);
1263 gen_set_label(label_match
);
1264 gen_goto_tb(s
, 1, addr
);
1267 /* C3.2.5 Test & branch (immediate)
1268 * 31 30 25 24 23 19 18 5 4 0
1269 * +----+-------------+----+-------+-------------+------+
1270 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1271 * +----+-------------+----+-------+-------------+------+
1273 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1275 unsigned int bit_pos
, op
, rt
;
1277 TCGLabel
*label_match
;
1280 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1281 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1282 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1283 rt
= extract32(insn
, 0, 5);
1285 tcg_cmp
= tcg_temp_new_i64();
1286 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1287 label_match
= gen_new_label();
1288 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1289 tcg_cmp
, 0, label_match
);
1290 tcg_temp_free_i64(tcg_cmp
);
1291 gen_goto_tb(s
, 0, s
->pc
);
1292 gen_set_label(label_match
);
1293 gen_goto_tb(s
, 1, addr
);
1296 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1297 * 31 25 24 23 5 4 3 0
1298 * +---------------+----+---------------------+----+------+
1299 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1300 * +---------------+----+---------------------+----+------+
1302 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1307 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1308 unallocated_encoding(s
);
1311 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1312 cond
= extract32(insn
, 0, 4);
1315 /* genuinely conditional branches */
1316 TCGLabel
*label_match
= gen_new_label();
1317 arm_gen_test_cc(cond
, label_match
);
1318 gen_goto_tb(s
, 0, s
->pc
);
1319 gen_set_label(label_match
);
1320 gen_goto_tb(s
, 1, addr
);
1322 /* 0xe and 0xf are both "always" conditions */
1323 gen_goto_tb(s
, 0, addr
);
1328 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1329 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1331 unsigned int selector
= crm
<< 3 | op2
;
1334 unallocated_encoding(s
);
1342 s
->is_jmp
= DISAS_WFI
;
1345 s
->is_jmp
= DISAS_YIELD
;
1348 s
->is_jmp
= DISAS_WFE
;
1352 /* we treat all as NOP at least for now */
1355 /* default specified as NOP equivalent */
1360 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1362 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1365 /* CLREX, DSB, DMB, ISB */
1366 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1367 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1372 unallocated_encoding(s
);
1383 case 1: /* MBReqTypes_Reads */
1384 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1386 case 2: /* MBReqTypes_Writes */
1387 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1389 default: /* MBReqTypes_All */
1390 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1396 /* We need to break the TB after this insn to execute
1397 * a self-modified code correctly and also to take
1398 * any pending interrupts immediately.
1400 s
->is_jmp
= DISAS_UPDATE
;
1403 unallocated_encoding(s
);
1408 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1409 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1410 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1412 int op
= op1
<< 3 | op2
;
1414 case 0x05: /* SPSel */
1415 if (s
->current_el
== 0) {
1416 unallocated_encoding(s
);
1420 case 0x1e: /* DAIFSet */
1421 case 0x1f: /* DAIFClear */
1423 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1424 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1425 gen_a64_set_pc_im(s
->pc
- 4);
1426 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1427 tcg_temp_free_i32(tcg_imm
);
1428 tcg_temp_free_i32(tcg_op
);
1429 s
->is_jmp
= DISAS_UPDATE
;
1433 unallocated_encoding(s
);
1438 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1440 TCGv_i32 tmp
= tcg_temp_new_i32();
1441 TCGv_i32 nzcv
= tcg_temp_new_i32();
1443 /* build bit 31, N */
1444 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1445 /* build bit 30, Z */
1446 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1447 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1448 /* build bit 29, C */
1449 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1450 /* build bit 28, V */
1451 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1452 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1453 /* generate result */
1454 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1456 tcg_temp_free_i32(nzcv
);
1457 tcg_temp_free_i32(tmp
);
1460 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1463 TCGv_i32 nzcv
= tcg_temp_new_i32();
1465 /* take NZCV from R[t] */
1466 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1469 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1471 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1472 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1474 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1475 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1477 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1478 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1479 tcg_temp_free_i32(nzcv
);
1482 /* C5.6.129 MRS - move from system register
1483 * C5.6.131 MSR (register) - move to system register
1486 * These are all essentially the same insn in 'read' and 'write'
1487 * versions, with varying op0 fields.
1489 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1490 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1491 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1493 const ARMCPRegInfo
*ri
;
1496 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1497 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1498 crn
, crm
, op0
, op1
, op2
));
1501 /* Unknown register; this might be a guest error or a QEMU
1502 * unimplemented feature.
1504 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1505 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1506 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1507 unallocated_encoding(s
);
1511 /* Check access permissions */
1512 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1513 unallocated_encoding(s
);
1518 /* Emit code to perform further access permissions checks at
1519 * runtime; this may result in an exception.
1522 TCGv_i32 tcg_syn
, tcg_isread
;
1525 gen_a64_set_pc_im(s
->pc
- 4);
1526 tmpptr
= tcg_const_ptr(ri
);
1527 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1528 tcg_syn
= tcg_const_i32(syndrome
);
1529 tcg_isread
= tcg_const_i32(isread
);
1530 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1531 tcg_temp_free_ptr(tmpptr
);
1532 tcg_temp_free_i32(tcg_syn
);
1533 tcg_temp_free_i32(tcg_isread
);
1536 /* Handle special cases first */
1537 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1541 tcg_rt
= cpu_reg(s
, rt
);
1543 gen_get_nzcv(tcg_rt
);
1545 gen_set_nzcv(tcg_rt
);
1548 case ARM_CP_CURRENTEL
:
1549 /* Reads as current EL value from pstate, which is
1550 * guaranteed to be constant by the tb flags.
1552 tcg_rt
= cpu_reg(s
, rt
);
1553 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1556 /* Writes clear the aligned block of memory which rt points into. */
1557 tcg_rt
= cpu_reg(s
, rt
);
1558 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1564 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1568 tcg_rt
= cpu_reg(s
, rt
);
1571 if (ri
->type
& ARM_CP_CONST
) {
1572 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1573 } else if (ri
->readfn
) {
1575 tmpptr
= tcg_const_ptr(ri
);
1576 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1577 tcg_temp_free_ptr(tmpptr
);
1579 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1582 if (ri
->type
& ARM_CP_CONST
) {
1583 /* If not forbidden by access permissions, treat as WI */
1585 } else if (ri
->writefn
) {
1587 tmpptr
= tcg_const_ptr(ri
);
1588 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1589 tcg_temp_free_ptr(tmpptr
);
1591 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1595 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1596 /* I/O operations must end the TB here (whether read or write) */
1598 s
->is_jmp
= DISAS_UPDATE
;
1599 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1600 /* We default to ending the TB on a coprocessor register write,
1601 * but allow this to be suppressed by the register definition
1602 * (usually only necessary to work around guest bugs).
1604 s
->is_jmp
= DISAS_UPDATE
;
1609 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1610 * +---------------------+---+-----+-----+-------+-------+-----+------+
1611 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1612 * +---------------------+---+-----+-----+-------+-------+-----+------+
1614 static void disas_system(DisasContext
*s
, uint32_t insn
)
1616 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1617 l
= extract32(insn
, 21, 1);
1618 op0
= extract32(insn
, 19, 2);
1619 op1
= extract32(insn
, 16, 3);
1620 crn
= extract32(insn
, 12, 4);
1621 crm
= extract32(insn
, 8, 4);
1622 op2
= extract32(insn
, 5, 3);
1623 rt
= extract32(insn
, 0, 5);
1626 if (l
|| rt
!= 31) {
1627 unallocated_encoding(s
);
1631 case 2: /* C5.6.68 HINT */
1632 handle_hint(s
, insn
, op1
, op2
, crm
);
1634 case 3: /* CLREX, DSB, DMB, ISB */
1635 handle_sync(s
, insn
, op1
, op2
, crm
);
1637 case 4: /* C5.6.130 MSR (immediate) */
1638 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1641 unallocated_encoding(s
);
1646 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1649 /* C3.2.3 Exception generation
1651 * 31 24 23 21 20 5 4 2 1 0
1652 * +-----------------+-----+------------------------+-----+----+
1653 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1654 * +-----------------------+------------------------+----------+
1656 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1658 int opc
= extract32(insn
, 21, 3);
1659 int op2_ll
= extract32(insn
, 0, 5);
1660 int imm16
= extract32(insn
, 5, 16);
1665 /* For SVC, HVC and SMC we advance the single-step state
1666 * machine before taking the exception. This is architecturally
1667 * mandated, to ensure that single-stepping a system call
1668 * instruction works properly.
1673 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1674 default_exception_el(s
));
1677 if (s
->current_el
== 0) {
1678 unallocated_encoding(s
);
1681 /* The pre HVC helper handles cases when HVC gets trapped
1682 * as an undefined insn by runtime configuration.
1684 gen_a64_set_pc_im(s
->pc
- 4);
1685 gen_helper_pre_hvc(cpu_env
);
1687 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1690 if (s
->current_el
== 0) {
1691 unallocated_encoding(s
);
1694 gen_a64_set_pc_im(s
->pc
- 4);
1695 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1696 gen_helper_pre_smc(cpu_env
, tmp
);
1697 tcg_temp_free_i32(tmp
);
1699 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1702 unallocated_encoding(s
);
1708 unallocated_encoding(s
);
1712 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
),
1713 default_exception_el(s
));
1717 unallocated_encoding(s
);
1720 /* HLT. This has two purposes.
1721 * Architecturally, it is an external halting debug instruction.
1722 * Since QEMU doesn't implement external debug, we treat this as
1723 * it is required for halting debug disabled: it will UNDEF.
1724 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1726 if (semihosting_enabled() && imm16
== 0xf000) {
1727 #ifndef CONFIG_USER_ONLY
1728 /* In system mode, don't allow userspace access to semihosting,
1729 * to provide some semblance of security (and for consistency
1730 * with our 32-bit semihosting).
1732 if (s
->current_el
== 0) {
1733 unsupported_encoding(s
, insn
);
1737 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1739 unsupported_encoding(s
, insn
);
1743 if (op2_ll
< 1 || op2_ll
> 3) {
1744 unallocated_encoding(s
);
1747 /* DCPS1, DCPS2, DCPS3 */
1748 unsupported_encoding(s
, insn
);
1751 unallocated_encoding(s
);
1756 /* C3.2.7 Unconditional branch (register)
1757 * 31 25 24 21 20 16 15 10 9 5 4 0
1758 * +---------------+-------+-------+-------+------+-------+
1759 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1760 * +---------------+-------+-------+-------+------+-------+
1762 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1764 unsigned int opc
, op2
, op3
, rn
, op4
;
1766 opc
= extract32(insn
, 21, 4);
1767 op2
= extract32(insn
, 16, 5);
1768 op3
= extract32(insn
, 10, 6);
1769 rn
= extract32(insn
, 5, 5);
1770 op4
= extract32(insn
, 0, 5);
1772 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1773 unallocated_encoding(s
);
1781 gen_a64_set_pc(s
, cpu_reg(s
, rn
));
1782 /* BLR also needs to load return address */
1784 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1788 if (s
->current_el
== 0) {
1789 unallocated_encoding(s
);
1792 gen_helper_exception_return(cpu_env
);
1793 s
->is_jmp
= DISAS_JUMP
;
1797 unallocated_encoding(s
);
1799 unsupported_encoding(s
, insn
);
1803 unallocated_encoding(s
);
1807 s
->is_jmp
= DISAS_JUMP
;
1810 /* C3.2 Branches, exception generating and system instructions */
1811 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1813 switch (extract32(insn
, 25, 7)) {
1814 case 0x0a: case 0x0b:
1815 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1816 disas_uncond_b_imm(s
, insn
);
1818 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1819 disas_comp_b_imm(s
, insn
);
1821 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1822 disas_test_b_imm(s
, insn
);
1824 case 0x2a: /* Conditional branch (immediate) */
1825 disas_cond_b_imm(s
, insn
);
1827 case 0x6a: /* Exception generation / System */
1828 if (insn
& (1 << 24)) {
1829 disas_system(s
, insn
);
1834 case 0x6b: /* Unconditional branch (register) */
1835 disas_uncond_b_reg(s
, insn
);
1838 unallocated_encoding(s
);
1844 * Load/Store exclusive instructions are implemented by remembering
1845 * the value/address loaded, and seeing if these are the same
1846 * when the store is performed. This is not actually the architecturally
1847 * mandated semantics, but it works for typical guest code sequences
1848 * and avoids having to monitor regular stores.
1850 * The store exclusive uses the atomic cmpxchg primitives to avoid
1851 * races in multi-threaded linux-user and when MTTCG softmmu is
1854 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1855 TCGv_i64 addr
, int size
, bool is_pair
)
1857 TCGv_i64 tmp
= tcg_temp_new_i64();
1858 TCGMemOp memop
= s
->be_data
+ size
;
1860 g_assert(size
<= 3);
1861 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1864 TCGv_i64 addr2
= tcg_temp_new_i64();
1865 TCGv_i64 hitmp
= tcg_temp_new_i64();
1867 g_assert(size
>= 2);
1868 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1869 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1870 tcg_temp_free_i64(addr2
);
1871 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1872 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1873 tcg_temp_free_i64(hitmp
);
1876 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1877 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1879 tcg_temp_free_i64(tmp
);
1880 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1883 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1884 TCGv_i64 inaddr
, int size
, int is_pair
)
1886 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1887 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1890 * [addr + datasize] = {Rt2};
1896 * env->exclusive_addr = -1;
1898 TCGLabel
*fail_label
= gen_new_label();
1899 TCGLabel
*done_label
= gen_new_label();
1900 TCGv_i64 addr
= tcg_temp_local_new_i64();
1903 /* Copy input into a local temp so it is not trashed when the
1904 * basic block ends at the branch insn.
1906 tcg_gen_mov_i64(addr
, inaddr
);
1907 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1909 tmp
= tcg_temp_new_i64();
1912 TCGv_i64 val
= tcg_temp_new_i64();
1913 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1914 tcg_gen_concat32_i64(val
, cpu_exclusive_val
, cpu_exclusive_high
);
1915 tcg_gen_atomic_cmpxchg_i64(tmp
, addr
, val
, tmp
,
1917 size
| MO_ALIGN
| s
->be_data
);
1918 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, val
);
1919 tcg_temp_free_i64(val
);
1920 } else if (s
->be_data
== MO_LE
) {
1921 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, addr
, cpu_reg(s
, rt
),
1924 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, addr
, cpu_reg(s
, rt
),
1928 TCGv_i64 val
= cpu_reg(s
, rt
);
1929 tcg_gen_atomic_cmpxchg_i64(tmp
, addr
, cpu_exclusive_val
, val
,
1931 size
| MO_ALIGN
| s
->be_data
);
1932 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
1935 tcg_temp_free_i64(addr
);
1937 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
1938 tcg_temp_free_i64(tmp
);
1939 tcg_gen_br(done_label
);
1941 gen_set_label(fail_label
);
1942 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1943 gen_set_label(done_label
);
1944 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1947 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
1948 * from the ARMv8 specs for LDR (Shared decode for all encodings).
1950 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
1952 int opc0
= extract32(opc
, 0, 1);
1956 regsize
= opc0
? 32 : 64;
1958 regsize
= size
== 3 ? 64 : 32;
1960 return regsize
== 64;
1963 /* C3.3.6 Load/store exclusive
1965 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1966 * +-----+-------------+----+---+----+------+----+-------+------+------+
1967 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1968 * +-----+-------------+----+---+----+------+----+-------+------+------+
1970 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1971 * L: 0 -> store, 1 -> load
1972 * o2: 0 -> exclusive, 1 -> not
1973 * o1: 0 -> single register, 1 -> register pair
1974 * o0: 1 -> load-acquire/store-release, 0 -> not
1976 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1978 int rt
= extract32(insn
, 0, 5);
1979 int rn
= extract32(insn
, 5, 5);
1980 int rt2
= extract32(insn
, 10, 5);
1981 int is_lasr
= extract32(insn
, 15, 1);
1982 int rs
= extract32(insn
, 16, 5);
1983 int is_pair
= extract32(insn
, 21, 1);
1984 int is_store
= !extract32(insn
, 22, 1);
1985 int is_excl
= !extract32(insn
, 23, 1);
1986 int size
= extract32(insn
, 30, 2);
1989 if ((!is_excl
&& !is_pair
&& !is_lasr
) ||
1990 (!is_excl
&& is_pair
) ||
1991 (is_pair
&& size
< 2)) {
1992 unallocated_encoding(s
);
1997 gen_check_sp_alignment(s
);
1999 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2001 /* Note that since TCG is single threaded load-acquire/store-release
2002 * semantics require no extra if (is_lasr) { ... } handling.
2008 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2010 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2014 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2016 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2019 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2020 bool iss_sf
= disas_ldst_compute_iss_sf(size
, false, 0);
2022 /* Generate ISS for non-exclusive accesses including LASR. */
2025 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2027 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2028 true, rt
, iss_sf
, is_lasr
);
2030 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false,
2031 true, rt
, iss_sf
, is_lasr
);
2033 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2040 * C3.3.5 Load register (literal)
2042 * 31 30 29 27 26 25 24 23 5 4 0
2043 * +-----+-------+---+-----+-------------------+-------+
2044 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2045 * +-----+-------+---+-----+-------------------+-------+
2047 * V: 1 -> vector (simd/fp)
2048 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2049 * 10-> 32 bit signed, 11 -> prefetch
2050 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2052 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2054 int rt
= extract32(insn
, 0, 5);
2055 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2056 bool is_vector
= extract32(insn
, 26, 1);
2057 int opc
= extract32(insn
, 30, 2);
2058 bool is_signed
= false;
2060 TCGv_i64 tcg_rt
, tcg_addr
;
2064 unallocated_encoding(s
);
2068 if (!fp_access_check(s
)) {
2073 /* PRFM (literal) : prefetch */
2076 size
= 2 + extract32(opc
, 0, 1);
2077 is_signed
= extract32(opc
, 1, 1);
2080 tcg_rt
= cpu_reg(s
, rt
);
2082 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2084 do_fp_ld(s
, rt
, tcg_addr
, size
);
2086 /* Only unsigned 32bit loads target 32bit registers. */
2087 bool iss_sf
= opc
!= 0;
2089 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2090 true, rt
, iss_sf
, false);
2092 tcg_temp_free_i64(tcg_addr
);
2096 * C5.6.80 LDNP (Load Pair - non-temporal hint)
2097 * C5.6.81 LDP (Load Pair - non vector)
2098 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
2099 * C5.6.176 STNP (Store Pair - non-temporal hint)
2100 * C5.6.177 STP (Store Pair - non vector)
2101 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
2102 * C6.3.165 LDP (Load Pair of SIMD&FP)
2103 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
2104 * C6.3.284 STP (Store Pair of SIMD&FP)
2106 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2107 * +-----+-------+---+---+-------+---+-----------------------------+
2108 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2109 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2111 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2113 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2114 * V: 0 -> GPR, 1 -> Vector
2115 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2116 * 10 -> signed offset, 11 -> pre-index
2117 * L: 0 -> Store 1 -> Load
2119 * Rt, Rt2 = GPR or SIMD registers to be stored
2120 * Rn = general purpose register containing address
2121 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2123 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2125 int rt
= extract32(insn
, 0, 5);
2126 int rn
= extract32(insn
, 5, 5);
2127 int rt2
= extract32(insn
, 10, 5);
2128 uint64_t offset
= sextract64(insn
, 15, 7);
2129 int index
= extract32(insn
, 23, 2);
2130 bool is_vector
= extract32(insn
, 26, 1);
2131 bool is_load
= extract32(insn
, 22, 1);
2132 int opc
= extract32(insn
, 30, 2);
2134 bool is_signed
= false;
2135 bool postindex
= false;
2138 TCGv_i64 tcg_addr
; /* calculated address */
2142 unallocated_encoding(s
);
2149 size
= 2 + extract32(opc
, 1, 1);
2150 is_signed
= extract32(opc
, 0, 1);
2151 if (!is_load
&& is_signed
) {
2152 unallocated_encoding(s
);
2158 case 1: /* post-index */
2163 /* signed offset with "non-temporal" hint. Since we don't emulate
2164 * caches we don't care about hints to the cache system about
2165 * data access patterns, and handle this identically to plain
2169 /* There is no non-temporal-hint version of LDPSW */
2170 unallocated_encoding(s
);
2175 case 2: /* signed offset, rn not updated */
2178 case 3: /* pre-index */
2184 if (is_vector
&& !fp_access_check(s
)) {
2191 gen_check_sp_alignment(s
);
2194 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2197 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2202 do_fp_ld(s
, rt
, tcg_addr
, size
);
2204 do_fp_st(s
, rt
, tcg_addr
, size
);
2207 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2209 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2210 false, 0, false, false);
2212 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2213 false, 0, false, false);
2216 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2219 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2221 do_fp_st(s
, rt2
, tcg_addr
, size
);
2224 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2226 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2227 false, 0, false, false);
2229 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2230 false, 0, false, false);
2236 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2238 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2240 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2245 * C3.3.8 Load/store (immediate post-indexed)
2246 * C3.3.9 Load/store (immediate pre-indexed)
2247 * C3.3.12 Load/store (unscaled immediate)
2249 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2250 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2251 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2252 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2254 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2256 * V = 0 -> non-vector
2257 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2258 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2260 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2266 int rn
= extract32(insn
, 5, 5);
2267 int imm9
= sextract32(insn
, 12, 9);
2268 int idx
= extract32(insn
, 10, 2);
2269 bool is_signed
= false;
2270 bool is_store
= false;
2271 bool is_extended
= false;
2272 bool is_unpriv
= (idx
== 2);
2273 bool iss_valid
= !is_vector
;
2280 size
|= (opc
& 2) << 1;
2281 if (size
> 4 || is_unpriv
) {
2282 unallocated_encoding(s
);
2285 is_store
= ((opc
& 1) == 0);
2286 if (!fp_access_check(s
)) {
2290 if (size
== 3 && opc
== 2) {
2291 /* PRFM - prefetch */
2293 unallocated_encoding(s
);
2298 if (opc
== 3 && size
> 1) {
2299 unallocated_encoding(s
);
2302 is_store
= (opc
== 0);
2303 is_signed
= extract32(opc
, 1, 1);
2304 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2324 gen_check_sp_alignment(s
);
2326 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2329 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2334 do_fp_st(s
, rt
, tcg_addr
, size
);
2336 do_fp_ld(s
, rt
, tcg_addr
, size
);
2339 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2340 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2341 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2344 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2345 iss_valid
, rt
, iss_sf
, false);
2347 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2348 is_signed
, is_extended
, memidx
,
2349 iss_valid
, rt
, iss_sf
, false);
2354 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2356 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2358 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2363 * C3.3.10 Load/store (register offset)
2365 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2366 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2367 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2368 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2371 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2372 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2374 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2375 * opc<0>: 0 -> store, 1 -> load
2376 * V: 1 -> vector/simd
2377 * opt: extend encoding (see DecodeRegExtend)
2378 * S: if S=1 then scale (essentially index by sizeof(size))
2379 * Rt: register to transfer into/out of
2380 * Rn: address register or SP for base
2381 * Rm: offset register or ZR for offset
2383 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2389 int rn
= extract32(insn
, 5, 5);
2390 int shift
= extract32(insn
, 12, 1);
2391 int rm
= extract32(insn
, 16, 5);
2392 int opt
= extract32(insn
, 13, 3);
2393 bool is_signed
= false;
2394 bool is_store
= false;
2395 bool is_extended
= false;
2400 if (extract32(opt
, 1, 1) == 0) {
2401 unallocated_encoding(s
);
2406 size
|= (opc
& 2) << 1;
2408 unallocated_encoding(s
);
2411 is_store
= !extract32(opc
, 0, 1);
2412 if (!fp_access_check(s
)) {
2416 if (size
== 3 && opc
== 2) {
2417 /* PRFM - prefetch */
2420 if (opc
== 3 && size
> 1) {
2421 unallocated_encoding(s
);
2424 is_store
= (opc
== 0);
2425 is_signed
= extract32(opc
, 1, 1);
2426 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2430 gen_check_sp_alignment(s
);
2432 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2434 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2435 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2437 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2441 do_fp_st(s
, rt
, tcg_addr
, size
);
2443 do_fp_ld(s
, rt
, tcg_addr
, size
);
2446 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2447 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2449 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2450 true, rt
, iss_sf
, false);
2452 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2453 is_signed
, is_extended
,
2454 true, rt
, iss_sf
, false);
2460 * C3.3.13 Load/store (unsigned immediate)
2462 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2463 * +----+-------+---+-----+-----+------------+-------+------+
2464 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2465 * +----+-------+---+-----+-----+------------+-------+------+
2468 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2469 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2471 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2472 * opc<0>: 0 -> store, 1 -> load
2473 * Rn: base address register (inc SP)
2474 * Rt: target register
2476 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2482 int rn
= extract32(insn
, 5, 5);
2483 unsigned int imm12
= extract32(insn
, 10, 12);
2484 unsigned int offset
;
2489 bool is_signed
= false;
2490 bool is_extended
= false;
2493 size
|= (opc
& 2) << 1;
2495 unallocated_encoding(s
);
2498 is_store
= !extract32(opc
, 0, 1);
2499 if (!fp_access_check(s
)) {
2503 if (size
== 3 && opc
== 2) {
2504 /* PRFM - prefetch */
2507 if (opc
== 3 && size
> 1) {
2508 unallocated_encoding(s
);
2511 is_store
= (opc
== 0);
2512 is_signed
= extract32(opc
, 1, 1);
2513 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2517 gen_check_sp_alignment(s
);
2519 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2520 offset
= imm12
<< size
;
2521 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2525 do_fp_st(s
, rt
, tcg_addr
, size
);
2527 do_fp_ld(s
, rt
, tcg_addr
, size
);
2530 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2531 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2533 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2534 true, rt
, iss_sf
, false);
2536 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
2537 true, rt
, iss_sf
, false);
2542 /* Load/store register (all forms) */
2543 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2545 int rt
= extract32(insn
, 0, 5);
2546 int opc
= extract32(insn
, 22, 2);
2547 bool is_vector
= extract32(insn
, 26, 1);
2548 int size
= extract32(insn
, 30, 2);
2550 switch (extract32(insn
, 24, 2)) {
2552 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2553 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2555 /* Load/store register (unscaled immediate)
2556 * Load/store immediate pre/post-indexed
2557 * Load/store register unprivileged
2559 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2563 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
2566 unallocated_encoding(s
);
2571 /* C3.3.1 AdvSIMD load/store multiple structures
2573 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2574 * +---+---+---------------+---+-------------+--------+------+------+------+
2575 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2576 * +---+---+---------------+---+-------------+--------+------+------+------+
2578 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2580 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2581 * +---+---+---------------+---+---+---------+--------+------+------+------+
2582 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2583 * +---+---+---------------+---+---+---------+--------+------+------+------+
2585 * Rt: first (or only) SIMD&FP register to be transferred
2586 * Rn: base address or SP
2587 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2589 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2591 int rt
= extract32(insn
, 0, 5);
2592 int rn
= extract32(insn
, 5, 5);
2593 int size
= extract32(insn
, 10, 2);
2594 int opcode
= extract32(insn
, 12, 4);
2595 bool is_store
= !extract32(insn
, 22, 1);
2596 bool is_postidx
= extract32(insn
, 23, 1);
2597 bool is_q
= extract32(insn
, 30, 1);
2598 TCGv_i64 tcg_addr
, tcg_rn
;
2600 int ebytes
= 1 << size
;
2601 int elements
= (is_q
? 128 : 64) / (8 << size
);
2602 int rpt
; /* num iterations */
2603 int selem
; /* structure elements */
2606 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2607 unallocated_encoding(s
);
2611 /* From the shared decode logic */
2642 unallocated_encoding(s
);
2646 if (size
== 3 && !is_q
&& selem
!= 1) {
2648 unallocated_encoding(s
);
2652 if (!fp_access_check(s
)) {
2657 gen_check_sp_alignment(s
);
2660 tcg_rn
= cpu_reg_sp(s
, rn
);
2661 tcg_addr
= tcg_temp_new_i64();
2662 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2664 for (r
= 0; r
< rpt
; r
++) {
2666 for (e
= 0; e
< elements
; e
++) {
2667 int tt
= (rt
+ r
) % 32;
2669 for (xs
= 0; xs
< selem
; xs
++) {
2671 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2673 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2675 /* For non-quad operations, setting a slice of the low
2676 * 64 bits of the register clears the high 64 bits (in
2677 * the ARM ARM pseudocode this is implicit in the fact
2678 * that 'rval' is a 64 bit wide variable). We optimize
2679 * by noticing that we only need to do this the first
2680 * time we touch a register.
2682 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2683 clear_vec_high(s
, tt
);
2686 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2693 int rm
= extract32(insn
, 16, 5);
2695 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2697 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2700 tcg_temp_free_i64(tcg_addr
);
2703 /* C3.3.3 AdvSIMD load/store single structure
2705 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2706 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2707 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2708 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2710 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2712 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2713 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2714 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2715 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2717 * Rt: first (or only) SIMD&FP register to be transferred
2718 * Rn: base address or SP
2719 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2720 * index = encoded in Q:S:size dependent on size
2722 * lane_size = encoded in R, opc
2723 * transfer width = encoded in opc, S, size
2725 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2727 int rt
= extract32(insn
, 0, 5);
2728 int rn
= extract32(insn
, 5, 5);
2729 int size
= extract32(insn
, 10, 2);
2730 int S
= extract32(insn
, 12, 1);
2731 int opc
= extract32(insn
, 13, 3);
2732 int R
= extract32(insn
, 21, 1);
2733 int is_load
= extract32(insn
, 22, 1);
2734 int is_postidx
= extract32(insn
, 23, 1);
2735 int is_q
= extract32(insn
, 30, 1);
2737 int scale
= extract32(opc
, 1, 2);
2738 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2739 bool replicate
= false;
2740 int index
= is_q
<< 3 | S
<< 2 | size
;
2742 TCGv_i64 tcg_addr
, tcg_rn
;
2746 if (!is_load
|| S
) {
2747 unallocated_encoding(s
);
2756 if (extract32(size
, 0, 1)) {
2757 unallocated_encoding(s
);
2763 if (extract32(size
, 1, 1)) {
2764 unallocated_encoding(s
);
2767 if (!extract32(size
, 0, 1)) {
2771 unallocated_encoding(s
);
2779 g_assert_not_reached();
2782 if (!fp_access_check(s
)) {
2786 ebytes
= 1 << scale
;
2789 gen_check_sp_alignment(s
);
2792 tcg_rn
= cpu_reg_sp(s
, rn
);
2793 tcg_addr
= tcg_temp_new_i64();
2794 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2796 for (xs
= 0; xs
< selem
; xs
++) {
2798 /* Load and replicate to all elements */
2800 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2802 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2803 get_mem_index(s
), s
->be_data
+ scale
);
2806 mulconst
= 0x0101010101010101ULL
;
2809 mulconst
= 0x0001000100010001ULL
;
2812 mulconst
= 0x0000000100000001ULL
;
2818 g_assert_not_reached();
2821 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2823 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2825 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2827 clear_vec_high(s
, rt
);
2829 tcg_temp_free_i64(tcg_tmp
);
2831 /* Load/store one element per register */
2833 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
);
2835 do_vec_st(s
, rt
, index
, tcg_addr
, scale
);
2838 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2843 int rm
= extract32(insn
, 16, 5);
2845 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2847 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2850 tcg_temp_free_i64(tcg_addr
);
2853 /* C3.3 Loads and stores */
2854 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2856 switch (extract32(insn
, 24, 6)) {
2857 case 0x08: /* Load/store exclusive */
2858 disas_ldst_excl(s
, insn
);
2860 case 0x18: case 0x1c: /* Load register (literal) */
2861 disas_ld_lit(s
, insn
);
2863 case 0x28: case 0x29:
2864 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2865 disas_ldst_pair(s
, insn
);
2867 case 0x38: case 0x39:
2868 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2869 disas_ldst_reg(s
, insn
);
2871 case 0x0c: /* AdvSIMD load/store multiple structures */
2872 disas_ldst_multiple_struct(s
, insn
);
2874 case 0x0d: /* AdvSIMD load/store single structure */
2875 disas_ldst_single_struct(s
, insn
);
2878 unallocated_encoding(s
);
2883 /* C3.4.6 PC-rel. addressing
2884 * 31 30 29 28 24 23 5 4 0
2885 * +----+-------+-----------+-------------------+------+
2886 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2887 * +----+-------+-----------+-------------------+------+
2889 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2891 unsigned int page
, rd
;
2895 page
= extract32(insn
, 31, 1);
2896 /* SignExtend(immhi:immlo) -> offset */
2897 offset
= sextract64(insn
, 5, 19);
2898 offset
= offset
<< 2 | extract32(insn
, 29, 2);
2899 rd
= extract32(insn
, 0, 5);
2903 /* ADRP (page based) */
2908 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2912 * C3.4.1 Add/subtract (immediate)
2914 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2915 * +--+--+--+-----------+-----+-------------+-----+-----+
2916 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2917 * +--+--+--+-----------+-----+-------------+-----+-----+
2919 * sf: 0 -> 32bit, 1 -> 64bit
2920 * op: 0 -> add , 1 -> sub
2922 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2924 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2926 int rd
= extract32(insn
, 0, 5);
2927 int rn
= extract32(insn
, 5, 5);
2928 uint64_t imm
= extract32(insn
, 10, 12);
2929 int shift
= extract32(insn
, 22, 2);
2930 bool setflags
= extract32(insn
, 29, 1);
2931 bool sub_op
= extract32(insn
, 30, 1);
2932 bool is_64bit
= extract32(insn
, 31, 1);
2934 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2935 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2936 TCGv_i64 tcg_result
;
2945 unallocated_encoding(s
);
2949 tcg_result
= tcg_temp_new_i64();
2952 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2954 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2957 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2959 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2961 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2963 tcg_temp_free_i64(tcg_imm
);
2967 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2969 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2972 tcg_temp_free_i64(tcg_result
);
2975 /* The input should be a value in the bottom e bits (with higher
2976 * bits zero); returns that value replicated into every element
2977 * of size e in a 64 bit integer.
2979 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2989 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2990 static inline uint64_t bitmask64(unsigned int length
)
2992 assert(length
> 0 && length
<= 64);
2993 return ~0ULL >> (64 - length
);
2996 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2997 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2998 * value (ie should cause a guest UNDEF exception), and true if they are
2999 * valid, in which case the decoded bit pattern is written to result.
3001 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3002 unsigned int imms
, unsigned int immr
)
3005 unsigned e
, levels
, s
, r
;
3008 assert(immn
< 2 && imms
< 64 && immr
< 64);
3010 /* The bit patterns we create here are 64 bit patterns which
3011 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3012 * 64 bits each. Each element contains the same value: a run
3013 * of between 1 and e-1 non-zero bits, rotated within the
3014 * element by between 0 and e-1 bits.
3016 * The element size and run length are encoded into immn (1 bit)
3017 * and imms (6 bits) as follows:
3018 * 64 bit elements: immn = 1, imms = <length of run - 1>
3019 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3020 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3021 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3022 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3023 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3024 * Notice that immn = 0, imms = 11111x is the only combination
3025 * not covered by one of the above options; this is reserved.
3026 * Further, <length of run - 1> all-ones is a reserved pattern.
3028 * In all cases the rotation is by immr % e (and immr is 6 bits).
3031 /* First determine the element size */
3032 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3034 /* This is the immn == 0, imms == 0x11111x case */
3044 /* <length of run - 1> mustn't be all-ones. */
3048 /* Create the value of one element: s+1 set bits rotated
3049 * by r within the element (which is e bits wide)...
3051 mask
= bitmask64(s
+ 1);
3053 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3054 mask
&= bitmask64(e
);
3056 /* ...then replicate the element over the whole 64 bit value */
3057 mask
= bitfield_replicate(mask
, e
);
3062 /* C3.4.4 Logical (immediate)
3063 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3064 * +----+-----+-------------+---+------+------+------+------+
3065 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3066 * +----+-----+-------------+---+------+------+------+------+
3068 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3070 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3071 TCGv_i64 tcg_rd
, tcg_rn
;
3073 bool is_and
= false;
3075 sf
= extract32(insn
, 31, 1);
3076 opc
= extract32(insn
, 29, 2);
3077 is_n
= extract32(insn
, 22, 1);
3078 immr
= extract32(insn
, 16, 6);
3079 imms
= extract32(insn
, 10, 6);
3080 rn
= extract32(insn
, 5, 5);
3081 rd
= extract32(insn
, 0, 5);
3084 unallocated_encoding(s
);
3088 if (opc
== 0x3) { /* ANDS */
3089 tcg_rd
= cpu_reg(s
, rd
);
3091 tcg_rd
= cpu_reg_sp(s
, rd
);
3093 tcg_rn
= cpu_reg(s
, rn
);
3095 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3096 /* some immediate field values are reserved */
3097 unallocated_encoding(s
);
3102 wmask
&= 0xffffffff;
3106 case 0x3: /* ANDS */
3108 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3112 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3115 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3118 assert(FALSE
); /* must handle all above */
3122 if (!sf
&& !is_and
) {
3123 /* zero extend final result; we know we can skip this for AND
3124 * since the immediate had the high 32 bits clear.
3126 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3129 if (opc
== 3) { /* ANDS */
3130 gen_logic_CC(sf
, tcg_rd
);
3135 * C3.4.5 Move wide (immediate)
3137 * 31 30 29 28 23 22 21 20 5 4 0
3138 * +--+-----+-------------+-----+----------------+------+
3139 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3140 * +--+-----+-------------+-----+----------------+------+
3142 * sf: 0 -> 32 bit, 1 -> 64 bit
3143 * opc: 00 -> N, 10 -> Z, 11 -> K
3144 * hw: shift/16 (0,16, and sf only 32, 48)
3146 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3148 int rd
= extract32(insn
, 0, 5);
3149 uint64_t imm
= extract32(insn
, 5, 16);
3150 int sf
= extract32(insn
, 31, 1);
3151 int opc
= extract32(insn
, 29, 2);
3152 int pos
= extract32(insn
, 21, 2) << 4;
3153 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3156 if (!sf
&& (pos
>= 32)) {
3157 unallocated_encoding(s
);
3171 tcg_gen_movi_i64(tcg_rd
, imm
);
3174 tcg_imm
= tcg_const_i64(imm
);
3175 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3176 tcg_temp_free_i64(tcg_imm
);
3178 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3182 unallocated_encoding(s
);
3188 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3189 * +----+-----+-------------+---+------+------+------+------+
3190 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3191 * +----+-----+-------------+---+------+------+------+------+
3193 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3195 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3196 TCGv_i64 tcg_rd
, tcg_tmp
;
3198 sf
= extract32(insn
, 31, 1);
3199 opc
= extract32(insn
, 29, 2);
3200 n
= extract32(insn
, 22, 1);
3201 ri
= extract32(insn
, 16, 6);
3202 si
= extract32(insn
, 10, 6);
3203 rn
= extract32(insn
, 5, 5);
3204 rd
= extract32(insn
, 0, 5);
3205 bitsize
= sf
? 64 : 32;
3207 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3208 unallocated_encoding(s
);
3212 tcg_rd
= cpu_reg(s
, rd
);
3214 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3215 to be smaller than bitsize, we'll never reference data outside the
3216 low 32-bits anyway. */
3217 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3219 /* Recognize simple(r) extractions. */
3221 /* Wd<s-r:0> = Wn<s:r> */
3222 len
= (si
- ri
) + 1;
3223 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3224 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3226 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3227 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3230 /* opc == 1, BXFIL fall through to deposit */
3231 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3234 /* Handle the ri > si case with a deposit
3235 * Wd<32+s-r,32-r> = Wn<s:0>
3238 pos
= (bitsize
- ri
) & (bitsize
- 1);
3241 if (opc
== 0 && len
< ri
) {
3242 /* SBFM: sign extend the destination field from len to fill
3243 the balance of the word. Let the deposit below insert all
3244 of those sign bits. */
3245 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3249 if (opc
== 1) { /* BFM, BXFIL */
3250 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3252 /* SBFM or UBFM: We start with zero, and we haven't modified
3253 any bits outside bitsize, therefore the zero-extension
3254 below is unneeded. */
3255 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3260 if (!sf
) { /* zero extend final result */
3261 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3266 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3267 * +----+------+-------------+---+----+------+--------+------+------+
3268 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3269 * +----+------+-------------+---+----+------+--------+------+------+
3271 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3273 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3275 sf
= extract32(insn
, 31, 1);
3276 n
= extract32(insn
, 22, 1);
3277 rm
= extract32(insn
, 16, 5);
3278 imm
= extract32(insn
, 10, 6);
3279 rn
= extract32(insn
, 5, 5);
3280 rd
= extract32(insn
, 0, 5);
3281 op21
= extract32(insn
, 29, 2);
3282 op0
= extract32(insn
, 21, 1);
3283 bitsize
= sf
? 64 : 32;
3285 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3286 unallocated_encoding(s
);
3288 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3290 tcg_rd
= cpu_reg(s
, rd
);
3292 if (unlikely(imm
== 0)) {
3293 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3294 * so an extract from bit 0 is a special case.
3297 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3299 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3301 } else if (rm
== rn
) { /* ROR */
3302 tcg_rm
= cpu_reg(s
, rm
);
3304 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3306 TCGv_i32 tmp
= tcg_temp_new_i32();
3307 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3308 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3309 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3310 tcg_temp_free_i32(tmp
);
3313 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3314 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3315 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3316 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3317 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3319 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3325 /* C3.4 Data processing - immediate */
3326 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3328 switch (extract32(insn
, 23, 6)) {
3329 case 0x20: case 0x21: /* PC-rel. addressing */
3330 disas_pc_rel_adr(s
, insn
);
3332 case 0x22: case 0x23: /* Add/subtract (immediate) */
3333 disas_add_sub_imm(s
, insn
);
3335 case 0x24: /* Logical (immediate) */
3336 disas_logic_imm(s
, insn
);
3338 case 0x25: /* Move wide (immediate) */
3339 disas_movw_imm(s
, insn
);
3341 case 0x26: /* Bitfield */
3342 disas_bitfield(s
, insn
);
3344 case 0x27: /* Extract */
3345 disas_extract(s
, insn
);
3348 unallocated_encoding(s
);
3353 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3354 * Note that it is the caller's responsibility to ensure that the
3355 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3356 * mandated semantics for out of range shifts.
3358 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3359 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3361 switch (shift_type
) {
3362 case A64_SHIFT_TYPE_LSL
:
3363 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3365 case A64_SHIFT_TYPE_LSR
:
3366 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3368 case A64_SHIFT_TYPE_ASR
:
3370 tcg_gen_ext32s_i64(dst
, src
);
3372 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3374 case A64_SHIFT_TYPE_ROR
:
3376 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3379 t0
= tcg_temp_new_i32();
3380 t1
= tcg_temp_new_i32();
3381 tcg_gen_extrl_i64_i32(t0
, src
);
3382 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3383 tcg_gen_rotr_i32(t0
, t0
, t1
);
3384 tcg_gen_extu_i32_i64(dst
, t0
);
3385 tcg_temp_free_i32(t0
);
3386 tcg_temp_free_i32(t1
);
3390 assert(FALSE
); /* all shift types should be handled */
3394 if (!sf
) { /* zero extend final result */
3395 tcg_gen_ext32u_i64(dst
, dst
);
3399 /* Shift a TCGv src by immediate, put result in dst.
3400 * The shift amount must be in range (this should always be true as the
3401 * relevant instructions will UNDEF on bad shift immediates).
3403 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3404 enum a64_shift_type shift_type
, unsigned int shift_i
)
3406 assert(shift_i
< (sf
? 64 : 32));
3409 tcg_gen_mov_i64(dst
, src
);
3411 TCGv_i64 shift_const
;
3413 shift_const
= tcg_const_i64(shift_i
);
3414 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3415 tcg_temp_free_i64(shift_const
);
3419 /* C3.5.10 Logical (shifted register)
3420 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3421 * +----+-----+-----------+-------+---+------+--------+------+------+
3422 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3423 * +----+-----+-----------+-------+---+------+--------+------+------+
3425 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3427 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3428 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3430 sf
= extract32(insn
, 31, 1);
3431 opc
= extract32(insn
, 29, 2);
3432 shift_type
= extract32(insn
, 22, 2);
3433 invert
= extract32(insn
, 21, 1);
3434 rm
= extract32(insn
, 16, 5);
3435 shift_amount
= extract32(insn
, 10, 6);
3436 rn
= extract32(insn
, 5, 5);
3437 rd
= extract32(insn
, 0, 5);
3439 if (!sf
&& (shift_amount
& (1 << 5))) {
3440 unallocated_encoding(s
);
3444 tcg_rd
= cpu_reg(s
, rd
);
3446 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3447 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3448 * register-register MOV and MVN, so it is worth special casing.
3450 tcg_rm
= cpu_reg(s
, rm
);
3452 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3454 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3458 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3460 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3466 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3469 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3472 tcg_rn
= cpu_reg(s
, rn
);
3474 switch (opc
| (invert
<< 2)) {
3477 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3480 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3483 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3487 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3490 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3493 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3501 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3505 gen_logic_CC(sf
, tcg_rd
);
3510 * C3.5.1 Add/subtract (extended register)
3512 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3513 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3514 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3515 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3517 * sf: 0 -> 32bit, 1 -> 64bit
3518 * op: 0 -> add , 1 -> sub
3521 * option: extension type (see DecodeRegExtend)
3522 * imm3: optional shift to Rm
3524 * Rd = Rn + LSL(extend(Rm), amount)
3526 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3528 int rd
= extract32(insn
, 0, 5);
3529 int rn
= extract32(insn
, 5, 5);
3530 int imm3
= extract32(insn
, 10, 3);
3531 int option
= extract32(insn
, 13, 3);
3532 int rm
= extract32(insn
, 16, 5);
3533 bool setflags
= extract32(insn
, 29, 1);
3534 bool sub_op
= extract32(insn
, 30, 1);
3535 bool sf
= extract32(insn
, 31, 1);
3537 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3539 TCGv_i64 tcg_result
;
3542 unallocated_encoding(s
);
3546 /* non-flag setting ops may use SP */
3548 tcg_rd
= cpu_reg_sp(s
, rd
);
3550 tcg_rd
= cpu_reg(s
, rd
);
3552 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3554 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3555 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3557 tcg_result
= tcg_temp_new_i64();
3561 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3563 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3567 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3569 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3574 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3576 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3579 tcg_temp_free_i64(tcg_result
);
3583 * C3.5.2 Add/subtract (shifted register)
3585 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3586 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3587 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3588 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3590 * sf: 0 -> 32bit, 1 -> 64bit
3591 * op: 0 -> add , 1 -> sub
3593 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3594 * imm6: Shift amount to apply to Rm before the add/sub
3596 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3598 int rd
= extract32(insn
, 0, 5);
3599 int rn
= extract32(insn
, 5, 5);
3600 int imm6
= extract32(insn
, 10, 6);
3601 int rm
= extract32(insn
, 16, 5);
3602 int shift_type
= extract32(insn
, 22, 2);
3603 bool setflags
= extract32(insn
, 29, 1);
3604 bool sub_op
= extract32(insn
, 30, 1);
3605 bool sf
= extract32(insn
, 31, 1);
3607 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3608 TCGv_i64 tcg_rn
, tcg_rm
;
3609 TCGv_i64 tcg_result
;
3611 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3612 unallocated_encoding(s
);
3616 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3617 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3619 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3621 tcg_result
= tcg_temp_new_i64();
3625 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3627 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3631 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3633 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3638 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3640 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3643 tcg_temp_free_i64(tcg_result
);
3646 /* C3.5.9 Data-processing (3 source)
3648 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3649 +--+------+-----------+------+------+----+------+------+------+
3650 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3651 +--+------+-----------+------+------+----+------+------+------+
3654 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3656 int rd
= extract32(insn
, 0, 5);
3657 int rn
= extract32(insn
, 5, 5);
3658 int ra
= extract32(insn
, 10, 5);
3659 int rm
= extract32(insn
, 16, 5);
3660 int op_id
= (extract32(insn
, 29, 3) << 4) |
3661 (extract32(insn
, 21, 3) << 1) |
3662 extract32(insn
, 15, 1);
3663 bool sf
= extract32(insn
, 31, 1);
3664 bool is_sub
= extract32(op_id
, 0, 1);
3665 bool is_high
= extract32(op_id
, 2, 1);
3666 bool is_signed
= false;
3671 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3673 case 0x42: /* SMADDL */
3674 case 0x43: /* SMSUBL */
3675 case 0x44: /* SMULH */
3678 case 0x0: /* MADD (32bit) */
3679 case 0x1: /* MSUB (32bit) */
3680 case 0x40: /* MADD (64bit) */
3681 case 0x41: /* MSUB (64bit) */
3682 case 0x4a: /* UMADDL */
3683 case 0x4b: /* UMSUBL */
3684 case 0x4c: /* UMULH */
3687 unallocated_encoding(s
);
3692 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3693 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3694 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3695 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3698 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3700 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3703 tcg_temp_free_i64(low_bits
);
3707 tcg_op1
= tcg_temp_new_i64();
3708 tcg_op2
= tcg_temp_new_i64();
3709 tcg_tmp
= tcg_temp_new_i64();
3712 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3713 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3716 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3717 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3719 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3720 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3724 if (ra
== 31 && !is_sub
) {
3725 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3726 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3728 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3730 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3732 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3737 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3740 tcg_temp_free_i64(tcg_op1
);
3741 tcg_temp_free_i64(tcg_op2
);
3742 tcg_temp_free_i64(tcg_tmp
);
3745 /* C3.5.3 - Add/subtract (with carry)
3746 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3747 * +--+--+--+------------------------+------+---------+------+-----+
3748 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3749 * +--+--+--+------------------------+------+---------+------+-----+
3753 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3755 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3756 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3758 if (extract32(insn
, 10, 6) != 0) {
3759 unallocated_encoding(s
);
3763 sf
= extract32(insn
, 31, 1);
3764 op
= extract32(insn
, 30, 1);
3765 setflags
= extract32(insn
, 29, 1);
3766 rm
= extract32(insn
, 16, 5);
3767 rn
= extract32(insn
, 5, 5);
3768 rd
= extract32(insn
, 0, 5);
3770 tcg_rd
= cpu_reg(s
, rd
);
3771 tcg_rn
= cpu_reg(s
, rn
);
3774 tcg_y
= new_tmp_a64(s
);
3775 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3777 tcg_y
= cpu_reg(s
, rm
);
3781 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3783 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3787 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3788 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3789 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3790 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3791 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3794 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3796 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3797 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
3798 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3801 if (!extract32(insn
, 29, 1)) {
3802 unallocated_encoding(s
);
3805 if (insn
& (1 << 10 | 1 << 4)) {
3806 unallocated_encoding(s
);
3809 sf
= extract32(insn
, 31, 1);
3810 op
= extract32(insn
, 30, 1);
3811 is_imm
= extract32(insn
, 11, 1);
3812 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3813 cond
= extract32(insn
, 12, 4);
3814 rn
= extract32(insn
, 5, 5);
3815 nzcv
= extract32(insn
, 0, 4);
3817 /* Set T0 = !COND. */
3818 tcg_t0
= tcg_temp_new_i32();
3819 arm_test_cc(&c
, cond
);
3820 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
3823 /* Load the arguments for the new comparison. */
3825 tcg_y
= new_tmp_a64(s
);
3826 tcg_gen_movi_i64(tcg_y
, y
);
3828 tcg_y
= cpu_reg(s
, y
);
3830 tcg_rn
= cpu_reg(s
, rn
);
3832 /* Set the flags for the new comparison. */
3833 tcg_tmp
= tcg_temp_new_i64();
3835 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3837 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3839 tcg_temp_free_i64(tcg_tmp
);
3841 /* If COND was false, force the flags to #nzcv. Compute two masks
3842 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
3843 * For tcg hosts that support ANDC, we can make do with just T1.
3844 * In either case, allow the tcg optimizer to delete any unused mask.
3846 tcg_t1
= tcg_temp_new_i32();
3847 tcg_t2
= tcg_temp_new_i32();
3848 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
3849 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
3851 if (nzcv
& 8) { /* N */
3852 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3854 if (TCG_TARGET_HAS_andc_i32
) {
3855 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3857 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
3860 if (nzcv
& 4) { /* Z */
3861 if (TCG_TARGET_HAS_andc_i32
) {
3862 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
3864 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
3867 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
3869 if (nzcv
& 2) { /* C */
3870 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
3872 if (TCG_TARGET_HAS_andc_i32
) {
3873 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
3875 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
3878 if (nzcv
& 1) { /* V */
3879 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3881 if (TCG_TARGET_HAS_andc_i32
) {
3882 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3884 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
3887 tcg_temp_free_i32(tcg_t0
);
3888 tcg_temp_free_i32(tcg_t1
);
3889 tcg_temp_free_i32(tcg_t2
);
3892 /* C3.5.6 Conditional select
3893 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3894 * +----+----+---+-----------------+------+------+-----+------+------+
3895 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3896 * +----+----+---+-----------------+------+------+-----+------+------+
3898 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3900 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3901 TCGv_i64 tcg_rd
, zero
;
3904 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3905 /* S == 1 or op2<1> == 1 */
3906 unallocated_encoding(s
);
3909 sf
= extract32(insn
, 31, 1);
3910 else_inv
= extract32(insn
, 30, 1);
3911 rm
= extract32(insn
, 16, 5);
3912 cond
= extract32(insn
, 12, 4);
3913 else_inc
= extract32(insn
, 10, 1);
3914 rn
= extract32(insn
, 5, 5);
3915 rd
= extract32(insn
, 0, 5);
3917 tcg_rd
= cpu_reg(s
, rd
);
3919 a64_test_cc(&c
, cond
);
3920 zero
= tcg_const_i64(0);
3922 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
3924 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
3926 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
3929 TCGv_i64 t_true
= cpu_reg(s
, rn
);
3930 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
3931 if (else_inv
&& else_inc
) {
3932 tcg_gen_neg_i64(t_false
, t_false
);
3933 } else if (else_inv
) {
3934 tcg_gen_not_i64(t_false
, t_false
);
3935 } else if (else_inc
) {
3936 tcg_gen_addi_i64(t_false
, t_false
, 1);
3938 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
3941 tcg_temp_free_i64(zero
);
3945 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3949 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3950 unsigned int rn
, unsigned int rd
)
3952 TCGv_i64 tcg_rd
, tcg_rn
;
3953 tcg_rd
= cpu_reg(s
, rd
);
3954 tcg_rn
= cpu_reg(s
, rn
);
3957 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
3959 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3960 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3961 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
3962 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3963 tcg_temp_free_i32(tcg_tmp32
);
3967 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3968 unsigned int rn
, unsigned int rd
)
3970 TCGv_i64 tcg_rd
, tcg_rn
;
3971 tcg_rd
= cpu_reg(s
, rd
);
3972 tcg_rn
= cpu_reg(s
, rn
);
3975 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
3977 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3978 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3979 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
3980 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3981 tcg_temp_free_i32(tcg_tmp32
);
3985 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3986 unsigned int rn
, unsigned int rd
)
3988 TCGv_i64 tcg_rd
, tcg_rn
;
3989 tcg_rd
= cpu_reg(s
, rd
);
3990 tcg_rn
= cpu_reg(s
, rn
);
3993 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3995 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3996 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3997 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3998 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3999 tcg_temp_free_i32(tcg_tmp32
);
4003 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
4004 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4005 unsigned int rn
, unsigned int rd
)
4008 unallocated_encoding(s
);
4011 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4014 /* C5.6.149 REV with sf==0, opcode==2
4015 * C5.6.151 REV32 (sf==1, opcode==2)
4017 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4018 unsigned int rn
, unsigned int rd
)
4020 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4023 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4024 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4026 /* bswap32_i64 requires zero high word */
4027 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4028 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4029 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4030 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4031 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4033 tcg_temp_free_i64(tcg_tmp
);
4035 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4036 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4040 /* C5.6.150 REV16 (opcode==1) */
4041 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4042 unsigned int rn
, unsigned int rd
)
4044 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4045 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4046 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4048 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
4049 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
4051 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
4052 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
4053 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
4054 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
4057 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4058 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
4059 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
4060 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
4062 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
4063 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
4064 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
4067 tcg_temp_free_i64(tcg_tmp
);
4070 /* C3.5.7 Data-processing (1 source)
4071 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4072 * +----+---+---+-----------------+---------+--------+------+------+
4073 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4074 * +----+---+---+-----------------+---------+--------+------+------+
4076 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4078 unsigned int sf
, opcode
, rn
, rd
;
4080 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
4081 unallocated_encoding(s
);
4085 sf
= extract32(insn
, 31, 1);
4086 opcode
= extract32(insn
, 10, 6);
4087 rn
= extract32(insn
, 5, 5);
4088 rd
= extract32(insn
, 0, 5);
4092 handle_rbit(s
, sf
, rn
, rd
);
4095 handle_rev16(s
, sf
, rn
, rd
);
4098 handle_rev32(s
, sf
, rn
, rd
);
4101 handle_rev64(s
, sf
, rn
, rd
);
4104 handle_clz(s
, sf
, rn
, rd
);
4107 handle_cls(s
, sf
, rn
, rd
);
4112 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4113 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4115 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4116 tcg_rd
= cpu_reg(s
, rd
);
4118 if (!sf
&& is_signed
) {
4119 tcg_n
= new_tmp_a64(s
);
4120 tcg_m
= new_tmp_a64(s
);
4121 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4122 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4124 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4125 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4129 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4131 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4134 if (!sf
) { /* zero extend final result */
4135 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4139 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
4140 static void handle_shift_reg(DisasContext
*s
,
4141 enum a64_shift_type shift_type
, unsigned int sf
,
4142 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4144 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4145 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4146 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4148 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4149 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4150 tcg_temp_free_i64(tcg_shift
);
4153 /* CRC32[BHWX], CRC32C[BHWX] */
4154 static void handle_crc32(DisasContext
*s
,
4155 unsigned int sf
, unsigned int sz
, bool crc32c
,
4156 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4158 TCGv_i64 tcg_acc
, tcg_val
;
4161 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
4162 || (sf
== 1 && sz
!= 3)
4163 || (sf
== 0 && sz
== 3)) {
4164 unallocated_encoding(s
);
4169 tcg_val
= cpu_reg(s
, rm
);
4183 g_assert_not_reached();
4185 tcg_val
= new_tmp_a64(s
);
4186 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4189 tcg_acc
= cpu_reg(s
, rn
);
4190 tcg_bytes
= tcg_const_i32(1 << sz
);
4193 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4195 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4198 tcg_temp_free_i32(tcg_bytes
);
4201 /* C3.5.8 Data-processing (2 source)
4202 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4203 * +----+---+---+-----------------+------+--------+------+------+
4204 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4205 * +----+---+---+-----------------+------+--------+------+------+
4207 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4209 unsigned int sf
, rm
, opcode
, rn
, rd
;
4210 sf
= extract32(insn
, 31, 1);
4211 rm
= extract32(insn
, 16, 5);
4212 opcode
= extract32(insn
, 10, 6);
4213 rn
= extract32(insn
, 5, 5);
4214 rd
= extract32(insn
, 0, 5);
4216 if (extract32(insn
, 29, 1)) {
4217 unallocated_encoding(s
);
4223 handle_div(s
, false, sf
, rm
, rn
, rd
);
4226 handle_div(s
, true, sf
, rm
, rn
, rd
);
4229 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4232 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4235 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4238 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4247 case 23: /* CRC32 */
4249 int sz
= extract32(opcode
, 0, 2);
4250 bool crc32c
= extract32(opcode
, 2, 1);
4251 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4255 unallocated_encoding(s
);
4260 /* C3.5 Data processing - register */
4261 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4263 switch (extract32(insn
, 24, 5)) {
4264 case 0x0a: /* Logical (shifted register) */
4265 disas_logic_reg(s
, insn
);
4267 case 0x0b: /* Add/subtract */
4268 if (insn
& (1 << 21)) { /* (extended register) */
4269 disas_add_sub_ext_reg(s
, insn
);
4271 disas_add_sub_reg(s
, insn
);
4274 case 0x1b: /* Data-processing (3 source) */
4275 disas_data_proc_3src(s
, insn
);
4278 switch (extract32(insn
, 21, 3)) {
4279 case 0x0: /* Add/subtract (with carry) */
4280 disas_adc_sbc(s
, insn
);
4282 case 0x2: /* Conditional compare */
4283 disas_cc(s
, insn
); /* both imm and reg forms */
4285 case 0x4: /* Conditional select */
4286 disas_cond_select(s
, insn
);
4288 case 0x6: /* Data-processing */
4289 if (insn
& (1 << 30)) { /* (1 source) */
4290 disas_data_proc_1src(s
, insn
);
4291 } else { /* (2 source) */
4292 disas_data_proc_2src(s
, insn
);
4296 unallocated_encoding(s
);
4301 unallocated_encoding(s
);
4306 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
4307 unsigned int rn
, unsigned int rm
,
4308 bool cmp_with_zero
, bool signal_all_nans
)
4310 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4311 TCGv_ptr fpst
= get_fpstatus_ptr();
4314 TCGv_i64 tcg_vn
, tcg_vm
;
4316 tcg_vn
= read_fp_dreg(s
, rn
);
4317 if (cmp_with_zero
) {
4318 tcg_vm
= tcg_const_i64(0);
4320 tcg_vm
= read_fp_dreg(s
, rm
);
4322 if (signal_all_nans
) {
4323 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4325 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4327 tcg_temp_free_i64(tcg_vn
);
4328 tcg_temp_free_i64(tcg_vm
);
4330 TCGv_i32 tcg_vn
, tcg_vm
;
4332 tcg_vn
= read_fp_sreg(s
, rn
);
4333 if (cmp_with_zero
) {
4334 tcg_vm
= tcg_const_i32(0);
4336 tcg_vm
= read_fp_sreg(s
, rm
);
4338 if (signal_all_nans
) {
4339 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4341 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4343 tcg_temp_free_i32(tcg_vn
);
4344 tcg_temp_free_i32(tcg_vm
);
4347 tcg_temp_free_ptr(fpst
);
4349 gen_set_nzcv(tcg_flags
);
4351 tcg_temp_free_i64(tcg_flags
);
4354 /* C3.6.22 Floating point compare
4355 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4356 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4357 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4358 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4360 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4362 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4364 mos
= extract32(insn
, 29, 3);
4365 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4366 rm
= extract32(insn
, 16, 5);
4367 op
= extract32(insn
, 14, 2);
4368 rn
= extract32(insn
, 5, 5);
4369 opc
= extract32(insn
, 3, 2);
4370 op2r
= extract32(insn
, 0, 3);
4372 if (mos
|| op
|| op2r
|| type
> 1) {
4373 unallocated_encoding(s
);
4377 if (!fp_access_check(s
)) {
4381 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4384 /* C3.6.23 Floating point conditional compare
4385 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4386 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4387 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4388 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4390 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4392 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4394 TCGLabel
*label_continue
= NULL
;
4396 mos
= extract32(insn
, 29, 3);
4397 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4398 rm
= extract32(insn
, 16, 5);
4399 cond
= extract32(insn
, 12, 4);
4400 rn
= extract32(insn
, 5, 5);
4401 op
= extract32(insn
, 4, 1);
4402 nzcv
= extract32(insn
, 0, 4);
4404 if (mos
|| type
> 1) {
4405 unallocated_encoding(s
);
4409 if (!fp_access_check(s
)) {
4413 if (cond
< 0x0e) { /* not always */
4414 TCGLabel
*label_match
= gen_new_label();
4415 label_continue
= gen_new_label();
4416 arm_gen_test_cc(cond
, label_match
);
4418 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4419 gen_set_nzcv(tcg_flags
);
4420 tcg_temp_free_i64(tcg_flags
);
4421 tcg_gen_br(label_continue
);
4422 gen_set_label(label_match
);
4425 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4428 gen_set_label(label_continue
);
4432 /* C3.6.24 Floating point conditional select
4433 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4434 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4435 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4436 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4438 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4440 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4441 TCGv_i64 t_true
, t_false
, t_zero
;
4444 mos
= extract32(insn
, 29, 3);
4445 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4446 rm
= extract32(insn
, 16, 5);
4447 cond
= extract32(insn
, 12, 4);
4448 rn
= extract32(insn
, 5, 5);
4449 rd
= extract32(insn
, 0, 5);
4451 if (mos
|| type
> 1) {
4452 unallocated_encoding(s
);
4456 if (!fp_access_check(s
)) {
4460 /* Zero extend sreg inputs to 64 bits now. */
4461 t_true
= tcg_temp_new_i64();
4462 t_false
= tcg_temp_new_i64();
4463 read_vec_element(s
, t_true
, rn
, 0, type
? MO_64
: MO_32
);
4464 read_vec_element(s
, t_false
, rm
, 0, type
? MO_64
: MO_32
);
4466 a64_test_cc(&c
, cond
);
4467 t_zero
= tcg_const_i64(0);
4468 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4469 tcg_temp_free_i64(t_zero
);
4470 tcg_temp_free_i64(t_false
);
4473 /* Note that sregs write back zeros to the high bits,
4474 and we've already done the zero-extension. */
4475 write_fp_dreg(s
, rd
, t_true
);
4476 tcg_temp_free_i64(t_true
);
4479 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4480 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4486 fpst
= get_fpstatus_ptr();
4487 tcg_op
= read_fp_sreg(s
, rn
);
4488 tcg_res
= tcg_temp_new_i32();
4491 case 0x0: /* FMOV */
4492 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4494 case 0x1: /* FABS */
4495 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4497 case 0x2: /* FNEG */
4498 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4500 case 0x3: /* FSQRT */
4501 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4503 case 0x8: /* FRINTN */
4504 case 0x9: /* FRINTP */
4505 case 0xa: /* FRINTM */
4506 case 0xb: /* FRINTZ */
4507 case 0xc: /* FRINTA */
4509 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4511 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4512 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4514 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4515 tcg_temp_free_i32(tcg_rmode
);
4518 case 0xe: /* FRINTX */
4519 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4521 case 0xf: /* FRINTI */
4522 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4528 write_fp_sreg(s
, rd
, tcg_res
);
4530 tcg_temp_free_ptr(fpst
);
4531 tcg_temp_free_i32(tcg_op
);
4532 tcg_temp_free_i32(tcg_res
);
4535 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4536 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4542 fpst
= get_fpstatus_ptr();
4543 tcg_op
= read_fp_dreg(s
, rn
);
4544 tcg_res
= tcg_temp_new_i64();
4547 case 0x0: /* FMOV */
4548 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4550 case 0x1: /* FABS */
4551 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4553 case 0x2: /* FNEG */
4554 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4556 case 0x3: /* FSQRT */
4557 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4559 case 0x8: /* FRINTN */
4560 case 0x9: /* FRINTP */
4561 case 0xa: /* FRINTM */
4562 case 0xb: /* FRINTZ */
4563 case 0xc: /* FRINTA */
4565 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4567 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4568 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4570 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4571 tcg_temp_free_i32(tcg_rmode
);
4574 case 0xe: /* FRINTX */
4575 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4577 case 0xf: /* FRINTI */
4578 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4584 write_fp_dreg(s
, rd
, tcg_res
);
4586 tcg_temp_free_ptr(fpst
);
4587 tcg_temp_free_i64(tcg_op
);
4588 tcg_temp_free_i64(tcg_res
);
4591 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4592 int rd
, int rn
, int dtype
, int ntype
)
4597 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4599 /* Single to double */
4600 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4601 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4602 write_fp_dreg(s
, rd
, tcg_rd
);
4603 tcg_temp_free_i64(tcg_rd
);
4605 /* Single to half */
4606 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4607 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4608 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4609 write_fp_sreg(s
, rd
, tcg_rd
);
4610 tcg_temp_free_i32(tcg_rd
);
4612 tcg_temp_free_i32(tcg_rn
);
4617 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4618 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4620 /* Double to single */
4621 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4623 /* Double to half */
4624 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4625 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4627 write_fp_sreg(s
, rd
, tcg_rd
);
4628 tcg_temp_free_i32(tcg_rd
);
4629 tcg_temp_free_i64(tcg_rn
);
4634 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4635 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4637 /* Half to single */
4638 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4639 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4640 write_fp_sreg(s
, rd
, tcg_rd
);
4641 tcg_temp_free_i32(tcg_rd
);
4643 /* Half to double */
4644 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4645 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4646 write_fp_dreg(s
, rd
, tcg_rd
);
4647 tcg_temp_free_i64(tcg_rd
);
4649 tcg_temp_free_i32(tcg_rn
);
4657 /* C3.6.25 Floating point data-processing (1 source)
4658 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4659 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4660 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4661 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4663 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4665 int type
= extract32(insn
, 22, 2);
4666 int opcode
= extract32(insn
, 15, 6);
4667 int rn
= extract32(insn
, 5, 5);
4668 int rd
= extract32(insn
, 0, 5);
4671 case 0x4: case 0x5: case 0x7:
4673 /* FCVT between half, single and double precision */
4674 int dtype
= extract32(opcode
, 0, 2);
4675 if (type
== 2 || dtype
== type
) {
4676 unallocated_encoding(s
);
4679 if (!fp_access_check(s
)) {
4683 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4689 /* 32-to-32 and 64-to-64 ops */
4692 if (!fp_access_check(s
)) {
4696 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4699 if (!fp_access_check(s
)) {
4703 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4706 unallocated_encoding(s
);
4710 unallocated_encoding(s
);
4715 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4716 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4717 int rd
, int rn
, int rm
)
4724 tcg_res
= tcg_temp_new_i32();
4725 fpst
= get_fpstatus_ptr();
4726 tcg_op1
= read_fp_sreg(s
, rn
);
4727 tcg_op2
= read_fp_sreg(s
, rm
);
4730 case 0x0: /* FMUL */
4731 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4733 case 0x1: /* FDIV */
4734 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4736 case 0x2: /* FADD */
4737 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4739 case 0x3: /* FSUB */
4740 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4742 case 0x4: /* FMAX */
4743 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4745 case 0x5: /* FMIN */
4746 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4748 case 0x6: /* FMAXNM */
4749 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4751 case 0x7: /* FMINNM */
4752 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4754 case 0x8: /* FNMUL */
4755 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4756 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4760 write_fp_sreg(s
, rd
, tcg_res
);
4762 tcg_temp_free_ptr(fpst
);
4763 tcg_temp_free_i32(tcg_op1
);
4764 tcg_temp_free_i32(tcg_op2
);
4765 tcg_temp_free_i32(tcg_res
);
4768 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4769 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4770 int rd
, int rn
, int rm
)
4777 tcg_res
= tcg_temp_new_i64();
4778 fpst
= get_fpstatus_ptr();
4779 tcg_op1
= read_fp_dreg(s
, rn
);
4780 tcg_op2
= read_fp_dreg(s
, rm
);
4783 case 0x0: /* FMUL */
4784 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4786 case 0x1: /* FDIV */
4787 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4789 case 0x2: /* FADD */
4790 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4792 case 0x3: /* FSUB */
4793 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4795 case 0x4: /* FMAX */
4796 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4798 case 0x5: /* FMIN */
4799 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4801 case 0x6: /* FMAXNM */
4802 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4804 case 0x7: /* FMINNM */
4805 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4807 case 0x8: /* FNMUL */
4808 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4809 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4813 write_fp_dreg(s
, rd
, tcg_res
);
4815 tcg_temp_free_ptr(fpst
);
4816 tcg_temp_free_i64(tcg_op1
);
4817 tcg_temp_free_i64(tcg_op2
);
4818 tcg_temp_free_i64(tcg_res
);
4821 /* C3.6.26 Floating point data-processing (2 source)
4822 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4823 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4824 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4825 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4827 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4829 int type
= extract32(insn
, 22, 2);
4830 int rd
= extract32(insn
, 0, 5);
4831 int rn
= extract32(insn
, 5, 5);
4832 int rm
= extract32(insn
, 16, 5);
4833 int opcode
= extract32(insn
, 12, 4);
4836 unallocated_encoding(s
);
4842 if (!fp_access_check(s
)) {
4845 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4848 if (!fp_access_check(s
)) {
4851 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4854 unallocated_encoding(s
);
4858 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4859 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4860 int rd
, int rn
, int rm
, int ra
)
4862 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4863 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4864 TCGv_ptr fpst
= get_fpstatus_ptr();
4866 tcg_op1
= read_fp_sreg(s
, rn
);
4867 tcg_op2
= read_fp_sreg(s
, rm
);
4868 tcg_op3
= read_fp_sreg(s
, ra
);
4870 /* These are fused multiply-add, and must be done as one
4871 * floating point operation with no rounding between the
4872 * multiplication and addition steps.
4873 * NB that doing the negations here as separate steps is
4874 * correct : an input NaN should come out with its sign bit
4875 * flipped if it is a negated-input.
4878 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4882 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4885 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4887 write_fp_sreg(s
, rd
, tcg_res
);
4889 tcg_temp_free_ptr(fpst
);
4890 tcg_temp_free_i32(tcg_op1
);
4891 tcg_temp_free_i32(tcg_op2
);
4892 tcg_temp_free_i32(tcg_op3
);
4893 tcg_temp_free_i32(tcg_res
);
4896 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4897 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4898 int rd
, int rn
, int rm
, int ra
)
4900 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4901 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4902 TCGv_ptr fpst
= get_fpstatus_ptr();
4904 tcg_op1
= read_fp_dreg(s
, rn
);
4905 tcg_op2
= read_fp_dreg(s
, rm
);
4906 tcg_op3
= read_fp_dreg(s
, ra
);
4908 /* These are fused multiply-add, and must be done as one
4909 * floating point operation with no rounding between the
4910 * multiplication and addition steps.
4911 * NB that doing the negations here as separate steps is
4912 * correct : an input NaN should come out with its sign bit
4913 * flipped if it is a negated-input.
4916 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4920 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4923 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4925 write_fp_dreg(s
, rd
, tcg_res
);
4927 tcg_temp_free_ptr(fpst
);
4928 tcg_temp_free_i64(tcg_op1
);
4929 tcg_temp_free_i64(tcg_op2
);
4930 tcg_temp_free_i64(tcg_op3
);
4931 tcg_temp_free_i64(tcg_res
);
4934 /* C3.6.27 Floating point data-processing (3 source)
4935 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4936 * +---+---+---+-----------+------+----+------+----+------+------+------+
4937 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4938 * +---+---+---+-----------+------+----+------+----+------+------+------+
4940 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4942 int type
= extract32(insn
, 22, 2);
4943 int rd
= extract32(insn
, 0, 5);
4944 int rn
= extract32(insn
, 5, 5);
4945 int ra
= extract32(insn
, 10, 5);
4946 int rm
= extract32(insn
, 16, 5);
4947 bool o0
= extract32(insn
, 15, 1);
4948 bool o1
= extract32(insn
, 21, 1);
4952 if (!fp_access_check(s
)) {
4955 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4958 if (!fp_access_check(s
)) {
4961 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4964 unallocated_encoding(s
);
4968 /* C3.6.28 Floating point immediate
4969 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4970 * +---+---+---+-----------+------+---+------------+-------+------+------+
4971 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4972 * +---+---+---+-----------+------+---+------------+-------+------+------+
4974 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4976 int rd
= extract32(insn
, 0, 5);
4977 int imm8
= extract32(insn
, 13, 8);
4978 int is_double
= extract32(insn
, 22, 2);
4982 if (is_double
> 1) {
4983 unallocated_encoding(s
);
4987 if (!fp_access_check(s
)) {
4991 /* The imm8 encodes the sign bit, enough bits to represent
4992 * an exponent in the range 01....1xx to 10....0xx,
4993 * and the most significant 4 bits of the mantissa; see
4994 * VFPExpandImm() in the v8 ARM ARM.
4997 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4998 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4999 extract32(imm8
, 0, 6);
5002 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5003 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
5004 (extract32(imm8
, 0, 6) << 3);
5008 tcg_res
= tcg_const_i64(imm
);
5009 write_fp_dreg(s
, rd
, tcg_res
);
5010 tcg_temp_free_i64(tcg_res
);
5013 /* Handle floating point <=> fixed point conversions. Note that we can
5014 * also deal with fp <=> integer conversions as a special case (scale == 64)
5015 * OPTME: consider handling that special case specially or at least skipping
5016 * the call to scalbn in the helpers for zero shifts.
5018 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
5019 bool itof
, int rmode
, int scale
, int sf
, int type
)
5021 bool is_signed
= !(opcode
& 1);
5022 bool is_double
= type
;
5023 TCGv_ptr tcg_fpstatus
;
5026 tcg_fpstatus
= get_fpstatus_ptr();
5028 tcg_shift
= tcg_const_i32(64 - scale
);
5031 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
5033 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
5036 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
5038 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
5041 tcg_int
= tcg_extend
;
5045 TCGv_i64 tcg_double
= tcg_temp_new_i64();
5047 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
5048 tcg_shift
, tcg_fpstatus
);
5050 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
5051 tcg_shift
, tcg_fpstatus
);
5053 write_fp_dreg(s
, rd
, tcg_double
);
5054 tcg_temp_free_i64(tcg_double
);
5056 TCGv_i32 tcg_single
= tcg_temp_new_i32();
5058 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
5059 tcg_shift
, tcg_fpstatus
);
5061 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
5062 tcg_shift
, tcg_fpstatus
);
5064 write_fp_sreg(s
, rd
, tcg_single
);
5065 tcg_temp_free_i32(tcg_single
);
5068 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
5071 if (extract32(opcode
, 2, 1)) {
5072 /* There are too many rounding modes to all fit into rmode,
5073 * so FCVTA[US] is a special case.
5075 rmode
= FPROUNDING_TIEAWAY
;
5078 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5080 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5083 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
5086 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
5087 tcg_shift
, tcg_fpstatus
);
5089 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
5090 tcg_shift
, tcg_fpstatus
);
5094 gen_helper_vfp_tould(tcg_int
, tcg_double
,
5095 tcg_shift
, tcg_fpstatus
);
5097 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
5098 tcg_shift
, tcg_fpstatus
);
5101 tcg_temp_free_i64(tcg_double
);
5103 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
5106 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
5107 tcg_shift
, tcg_fpstatus
);
5109 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
5110 tcg_shift
, tcg_fpstatus
);
5113 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5115 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
5116 tcg_shift
, tcg_fpstatus
);
5118 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
5119 tcg_shift
, tcg_fpstatus
);
5121 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5122 tcg_temp_free_i32(tcg_dest
);
5124 tcg_temp_free_i32(tcg_single
);
5127 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5128 tcg_temp_free_i32(tcg_rmode
);
5131 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
5135 tcg_temp_free_ptr(tcg_fpstatus
);
5136 tcg_temp_free_i32(tcg_shift
);
5139 /* C3.6.29 Floating point <-> fixed point conversions
5140 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5141 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5142 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5143 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5145 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
5147 int rd
= extract32(insn
, 0, 5);
5148 int rn
= extract32(insn
, 5, 5);
5149 int scale
= extract32(insn
, 10, 6);
5150 int opcode
= extract32(insn
, 16, 3);
5151 int rmode
= extract32(insn
, 19, 2);
5152 int type
= extract32(insn
, 22, 2);
5153 bool sbit
= extract32(insn
, 29, 1);
5154 bool sf
= extract32(insn
, 31, 1);
5157 if (sbit
|| (type
> 1)
5158 || (!sf
&& scale
< 32)) {
5159 unallocated_encoding(s
);
5163 switch ((rmode
<< 3) | opcode
) {
5164 case 0x2: /* SCVTF */
5165 case 0x3: /* UCVTF */
5168 case 0x18: /* FCVTZS */
5169 case 0x19: /* FCVTZU */
5173 unallocated_encoding(s
);
5177 if (!fp_access_check(s
)) {
5181 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5184 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5186 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5187 * without conversion.
5191 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5197 TCGv_i64 tmp
= tcg_temp_new_i64();
5198 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5199 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5200 tcg_gen_movi_i64(tmp
, 0);
5201 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5202 tcg_temp_free_i64(tmp
);
5208 TCGv_i64 tmp
= tcg_const_i64(0);
5209 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5210 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5211 tcg_temp_free_i64(tmp
);
5215 /* 64 bit to top half. */
5216 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5220 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5225 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5229 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5232 /* 64 bits from top half */
5233 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
5239 /* C3.6.30 Floating point <-> integer conversions
5240 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5241 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5242 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5243 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5245 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
5247 int rd
= extract32(insn
, 0, 5);
5248 int rn
= extract32(insn
, 5, 5);
5249 int opcode
= extract32(insn
, 16, 3);
5250 int rmode
= extract32(insn
, 19, 2);
5251 int type
= extract32(insn
, 22, 2);
5252 bool sbit
= extract32(insn
, 29, 1);
5253 bool sf
= extract32(insn
, 31, 1);
5256 unallocated_encoding(s
);
5262 bool itof
= opcode
& 1;
5265 unallocated_encoding(s
);
5269 switch (sf
<< 3 | type
<< 1 | rmode
) {
5270 case 0x0: /* 32 bit */
5271 case 0xa: /* 64 bit */
5272 case 0xd: /* 64 bit to top half of quad */
5275 /* all other sf/type/rmode combinations are invalid */
5276 unallocated_encoding(s
);
5280 if (!fp_access_check(s
)) {
5283 handle_fmov(s
, rd
, rn
, type
, itof
);
5285 /* actual FP conversions */
5286 bool itof
= extract32(opcode
, 1, 1);
5288 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
5289 unallocated_encoding(s
);
5293 if (!fp_access_check(s
)) {
5296 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
5300 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5301 * 31 30 29 28 25 24 0
5302 * +---+---+---+---------+-----------------------------+
5303 * | | 0 | | 1 1 1 1 | |
5304 * +---+---+---+---------+-----------------------------+
5306 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
5308 if (extract32(insn
, 24, 1)) {
5309 /* Floating point data-processing (3 source) */
5310 disas_fp_3src(s
, insn
);
5311 } else if (extract32(insn
, 21, 1) == 0) {
5312 /* Floating point to fixed point conversions */
5313 disas_fp_fixed_conv(s
, insn
);
5315 switch (extract32(insn
, 10, 2)) {
5317 /* Floating point conditional compare */
5318 disas_fp_ccomp(s
, insn
);
5321 /* Floating point data-processing (2 source) */
5322 disas_fp_2src(s
, insn
);
5325 /* Floating point conditional select */
5326 disas_fp_csel(s
, insn
);
5329 switch (ctz32(extract32(insn
, 12, 4))) {
5330 case 0: /* [15:12] == xxx1 */
5331 /* Floating point immediate */
5332 disas_fp_imm(s
, insn
);
5334 case 1: /* [15:12] == xx10 */
5335 /* Floating point compare */
5336 disas_fp_compare(s
, insn
);
5338 case 2: /* [15:12] == x100 */
5339 /* Floating point data-processing (1 source) */
5340 disas_fp_1src(s
, insn
);
5342 case 3: /* [15:12] == 1000 */
5343 unallocated_encoding(s
);
5345 default: /* [15:12] == 0000 */
5346 /* Floating point <-> integer conversions */
5347 disas_fp_int_conv(s
, insn
);
5355 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5358 /* Extract 64 bits from the middle of two concatenated 64 bit
5359 * vector register slices left:right. The extracted bits start
5360 * at 'pos' bits into the right (least significant) side.
5361 * We return the result in tcg_right, and guarantee not to
5364 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5365 assert(pos
> 0 && pos
< 64);
5367 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5368 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5369 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5371 tcg_temp_free_i64(tcg_tmp
);
5375 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5376 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5377 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5378 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5380 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5382 int is_q
= extract32(insn
, 30, 1);
5383 int op2
= extract32(insn
, 22, 2);
5384 int imm4
= extract32(insn
, 11, 4);
5385 int rm
= extract32(insn
, 16, 5);
5386 int rn
= extract32(insn
, 5, 5);
5387 int rd
= extract32(insn
, 0, 5);
5388 int pos
= imm4
<< 3;
5389 TCGv_i64 tcg_resl
, tcg_resh
;
5391 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5392 unallocated_encoding(s
);
5396 if (!fp_access_check(s
)) {
5400 tcg_resh
= tcg_temp_new_i64();
5401 tcg_resl
= tcg_temp_new_i64();
5403 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5404 * either extracting 128 bits from a 128:128 concatenation, or
5405 * extracting 64 bits from a 64:64 concatenation.
5408 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5410 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5411 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5413 tcg_gen_movi_i64(tcg_resh
, 0);
5420 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5421 EltPosns
*elt
= eltposns
;
5428 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5430 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5433 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5434 tcg_hh
= tcg_temp_new_i64();
5435 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5436 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5437 tcg_temp_free_i64(tcg_hh
);
5441 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5442 tcg_temp_free_i64(tcg_resl
);
5443 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5444 tcg_temp_free_i64(tcg_resh
);
5448 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5449 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5450 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5451 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5453 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5455 int op2
= extract32(insn
, 22, 2);
5456 int is_q
= extract32(insn
, 30, 1);
5457 int rm
= extract32(insn
, 16, 5);
5458 int rn
= extract32(insn
, 5, 5);
5459 int rd
= extract32(insn
, 0, 5);
5460 int is_tblx
= extract32(insn
, 12, 1);
5461 int len
= extract32(insn
, 13, 2);
5462 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5463 TCGv_i32 tcg_regno
, tcg_numregs
;
5466 unallocated_encoding(s
);
5470 if (!fp_access_check(s
)) {
5474 /* This does a table lookup: for every byte element in the input
5475 * we index into a table formed from up to four vector registers,
5476 * and then the output is the result of the lookups. Our helper
5477 * function does the lookup operation for a single 64 bit part of
5480 tcg_resl
= tcg_temp_new_i64();
5481 tcg_resh
= tcg_temp_new_i64();
5484 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5486 tcg_gen_movi_i64(tcg_resl
, 0);
5488 if (is_tblx
&& is_q
) {
5489 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5491 tcg_gen_movi_i64(tcg_resh
, 0);
5494 tcg_idx
= tcg_temp_new_i64();
5495 tcg_regno
= tcg_const_i32(rn
);
5496 tcg_numregs
= tcg_const_i32(len
+ 1);
5497 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5498 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5499 tcg_regno
, tcg_numregs
);
5501 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5502 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5503 tcg_regno
, tcg_numregs
);
5505 tcg_temp_free_i64(tcg_idx
);
5506 tcg_temp_free_i32(tcg_regno
);
5507 tcg_temp_free_i32(tcg_numregs
);
5509 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5510 tcg_temp_free_i64(tcg_resl
);
5511 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5512 tcg_temp_free_i64(tcg_resh
);
5515 /* C3.6.3 ZIP/UZP/TRN
5516 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5517 * +---+---+-------------+------+---+------+---+------------------+------+
5518 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5519 * +---+---+-------------+------+---+------+---+------------------+------+
5521 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5523 int rd
= extract32(insn
, 0, 5);
5524 int rn
= extract32(insn
, 5, 5);
5525 int rm
= extract32(insn
, 16, 5);
5526 int size
= extract32(insn
, 22, 2);
5527 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5528 * bit 2 indicates 1 vs 2 variant of the insn.
5530 int opcode
= extract32(insn
, 12, 2);
5531 bool part
= extract32(insn
, 14, 1);
5532 bool is_q
= extract32(insn
, 30, 1);
5533 int esize
= 8 << size
;
5535 int datasize
= is_q
? 128 : 64;
5536 int elements
= datasize
/ esize
;
5537 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5539 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5540 unallocated_encoding(s
);
5544 if (!fp_access_check(s
)) {
5548 tcg_resl
= tcg_const_i64(0);
5549 tcg_resh
= tcg_const_i64(0);
5550 tcg_res
= tcg_temp_new_i64();
5552 for (i
= 0; i
< elements
; i
++) {
5554 case 1: /* UZP1/2 */
5556 int midpoint
= elements
/ 2;
5558 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5560 read_vec_element(s
, tcg_res
, rm
,
5561 2 * (i
- midpoint
) + part
, size
);
5565 case 2: /* TRN1/2 */
5567 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5569 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5572 case 3: /* ZIP1/2 */
5574 int base
= part
* elements
/ 2;
5576 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5578 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5583 g_assert_not_reached();
5588 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5589 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5591 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5592 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5596 tcg_temp_free_i64(tcg_res
);
5598 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5599 tcg_temp_free_i64(tcg_resl
);
5600 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5601 tcg_temp_free_i64(tcg_resh
);
5604 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5605 int opc
, bool is_min
, TCGv_ptr fpst
)
5607 /* Helper function for disas_simd_across_lanes: do a single precision
5608 * min/max operation on the specified two inputs,
5609 * and return the result in tcg_elt1.
5613 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5615 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5620 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5622 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5627 /* C3.6.4 AdvSIMD across lanes
5628 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5629 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5630 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5631 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5633 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5635 int rd
= extract32(insn
, 0, 5);
5636 int rn
= extract32(insn
, 5, 5);
5637 int size
= extract32(insn
, 22, 2);
5638 int opcode
= extract32(insn
, 12, 5);
5639 bool is_q
= extract32(insn
, 30, 1);
5640 bool is_u
= extract32(insn
, 29, 1);
5642 bool is_min
= false;
5646 TCGv_i64 tcg_res
, tcg_elt
;
5649 case 0x1b: /* ADDV */
5651 unallocated_encoding(s
);
5655 case 0x3: /* SADDLV, UADDLV */
5656 case 0xa: /* SMAXV, UMAXV */
5657 case 0x1a: /* SMINV, UMINV */
5658 if (size
== 3 || (size
== 2 && !is_q
)) {
5659 unallocated_encoding(s
);
5663 case 0xc: /* FMAXNMV, FMINNMV */
5664 case 0xf: /* FMAXV, FMINV */
5665 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5666 unallocated_encoding(s
);
5669 /* Bit 1 of size field encodes min vs max, and actual size is always
5670 * 32 bits: adjust the size variable so following code can rely on it
5672 is_min
= extract32(size
, 1, 1);
5677 unallocated_encoding(s
);
5681 if (!fp_access_check(s
)) {
5686 elements
= (is_q
? 128 : 64) / esize
;
5688 tcg_res
= tcg_temp_new_i64();
5689 tcg_elt
= tcg_temp_new_i64();
5691 /* These instructions operate across all lanes of a vector
5692 * to produce a single result. We can guarantee that a 64
5693 * bit intermediate is sufficient:
5694 * + for [US]ADDLV the maximum element size is 32 bits, and
5695 * the result type is 64 bits
5696 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5697 * same as the element size, which is 32 bits at most
5698 * For the integer operations we can choose to work at 64
5699 * or 32 bits and truncate at the end; for simplicity
5700 * we use 64 bits always. The floating point
5701 * ops do require 32 bit intermediates, though.
5704 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5706 for (i
= 1; i
< elements
; i
++) {
5707 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5710 case 0x03: /* SADDLV / UADDLV */
5711 case 0x1b: /* ADDV */
5712 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5714 case 0x0a: /* SMAXV / UMAXV */
5715 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5717 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5719 case 0x1a: /* SMINV / UMINV */
5720 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5722 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5726 g_assert_not_reached();
5731 /* Floating point ops which work on 32 bit (single) intermediates.
5732 * Note that correct NaN propagation requires that we do these
5733 * operations in exactly the order specified by the pseudocode.
5735 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5736 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5737 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5738 TCGv_ptr fpst
= get_fpstatus_ptr();
5740 assert(esize
== 32);
5741 assert(elements
== 4);
5743 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5744 tcg_gen_extrl_i64_i32(tcg_elt1
, tcg_elt
);
5745 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5746 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5748 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5750 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5751 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5752 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5753 tcg_gen_extrl_i64_i32(tcg_elt3
, tcg_elt
);
5755 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5757 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5759 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5760 tcg_temp_free_i32(tcg_elt1
);
5761 tcg_temp_free_i32(tcg_elt2
);
5762 tcg_temp_free_i32(tcg_elt3
);
5763 tcg_temp_free_ptr(fpst
);
5766 tcg_temp_free_i64(tcg_elt
);
5768 /* Now truncate the result to the width required for the final output */
5769 if (opcode
== 0x03) {
5770 /* SADDLV, UADDLV: result is 2*esize */
5776 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5779 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5782 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5787 g_assert_not_reached();
5790 write_fp_dreg(s
, rd
, tcg_res
);
5791 tcg_temp_free_i64(tcg_res
);
5794 /* C6.3.31 DUP (Element, Vector)
5796 * 31 30 29 21 20 16 15 10 9 5 4 0
5797 * +---+---+-------------------+--------+-------------+------+------+
5798 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5799 * +---+---+-------------------+--------+-------------+------+------+
5801 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5803 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5806 int size
= ctz32(imm5
);
5807 int esize
= 8 << size
;
5808 int elements
= (is_q
? 128 : 64) / esize
;
5812 if (size
> 3 || (size
== 3 && !is_q
)) {
5813 unallocated_encoding(s
);
5817 if (!fp_access_check(s
)) {
5821 index
= imm5
>> (size
+ 1);
5823 tmp
= tcg_temp_new_i64();
5824 read_vec_element(s
, tmp
, rn
, index
, size
);
5826 for (i
= 0; i
< elements
; i
++) {
5827 write_vec_element(s
, tmp
, rd
, i
, size
);
5831 clear_vec_high(s
, rd
);
5834 tcg_temp_free_i64(tmp
);
5837 /* C6.3.31 DUP (element, scalar)
5838 * 31 21 20 16 15 10 9 5 4 0
5839 * +-----------------------+--------+-------------+------+------+
5840 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5841 * +-----------------------+--------+-------------+------+------+
5843 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5846 int size
= ctz32(imm5
);
5851 unallocated_encoding(s
);
5855 if (!fp_access_check(s
)) {
5859 index
= imm5
>> (size
+ 1);
5861 /* This instruction just extracts the specified element and
5862 * zero-extends it into the bottom of the destination register.
5864 tmp
= tcg_temp_new_i64();
5865 read_vec_element(s
, tmp
, rn
, index
, size
);
5866 write_fp_dreg(s
, rd
, tmp
);
5867 tcg_temp_free_i64(tmp
);
5870 /* C6.3.32 DUP (General)
5872 * 31 30 29 21 20 16 15 10 9 5 4 0
5873 * +---+---+-------------------+--------+-------------+------+------+
5874 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5875 * +---+---+-------------------+--------+-------------+------+------+
5877 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5879 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5882 int size
= ctz32(imm5
);
5883 int esize
= 8 << size
;
5884 int elements
= (is_q
? 128 : 64)/esize
;
5887 if (size
> 3 || ((size
== 3) && !is_q
)) {
5888 unallocated_encoding(s
);
5892 if (!fp_access_check(s
)) {
5896 for (i
= 0; i
< elements
; i
++) {
5897 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5900 clear_vec_high(s
, rd
);
5904 /* C6.3.150 INS (Element)
5906 * 31 21 20 16 15 14 11 10 9 5 4 0
5907 * +-----------------------+--------+------------+---+------+------+
5908 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5909 * +-----------------------+--------+------------+---+------+------+
5911 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5912 * index: encoded in imm5<4:size+1>
5914 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5917 int size
= ctz32(imm5
);
5918 int src_index
, dst_index
;
5922 unallocated_encoding(s
);
5926 if (!fp_access_check(s
)) {
5930 dst_index
= extract32(imm5
, 1+size
, 5);
5931 src_index
= extract32(imm4
, size
, 4);
5933 tmp
= tcg_temp_new_i64();
5935 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5936 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5938 tcg_temp_free_i64(tmp
);
5942 /* C6.3.151 INS (General)
5944 * 31 21 20 16 15 10 9 5 4 0
5945 * +-----------------------+--------+-------------+------+------+
5946 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5947 * +-----------------------+--------+-------------+------+------+
5949 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5950 * index: encoded in imm5<4:size+1>
5952 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5954 int size
= ctz32(imm5
);
5958 unallocated_encoding(s
);
5962 if (!fp_access_check(s
)) {
5966 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5967 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5971 * C6.3.321 UMOV (General)
5972 * C6.3.237 SMOV (General)
5974 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5975 * +---+---+-------------------+--------+-------------+------+------+
5976 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5977 * +---+---+-------------------+--------+-------------+------+------+
5979 * U: unsigned when set
5980 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5982 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5983 int rn
, int rd
, int imm5
)
5985 int size
= ctz32(imm5
);
5989 /* Check for UnallocatedEncodings */
5991 if (size
> 2 || (size
== 2 && !is_q
)) {
5992 unallocated_encoding(s
);
5997 || (size
< 3 && is_q
)
5998 || (size
== 3 && !is_q
)) {
5999 unallocated_encoding(s
);
6004 if (!fp_access_check(s
)) {
6008 element
= extract32(imm5
, 1+size
, 4);
6010 tcg_rd
= cpu_reg(s
, rd
);
6011 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
6012 if (is_signed
&& !is_q
) {
6013 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
6017 /* C3.6.5 AdvSIMD copy
6018 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6019 * +---+---+----+-----------------+------+---+------+---+------+------+
6020 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6021 * +---+---+----+-----------------+------+---+------+---+------+------+
6023 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
6025 int rd
= extract32(insn
, 0, 5);
6026 int rn
= extract32(insn
, 5, 5);
6027 int imm4
= extract32(insn
, 11, 4);
6028 int op
= extract32(insn
, 29, 1);
6029 int is_q
= extract32(insn
, 30, 1);
6030 int imm5
= extract32(insn
, 16, 5);
6035 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
6037 unallocated_encoding(s
);
6042 /* DUP (element - vector) */
6043 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
6047 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
6052 handle_simd_insg(s
, rd
, rn
, imm5
);
6054 unallocated_encoding(s
);
6059 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6060 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
6063 unallocated_encoding(s
);
6069 /* C3.6.6 AdvSIMD modified immediate
6070 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6071 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6072 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6073 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6075 * There are a number of operations that can be carried out here:
6076 * MOVI - move (shifted) imm into register
6077 * MVNI - move inverted (shifted) imm into register
6078 * ORR - bitwise OR of (shifted) imm with register
6079 * BIC - bitwise clear of (shifted) imm with register
6081 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
6083 int rd
= extract32(insn
, 0, 5);
6084 int cmode
= extract32(insn
, 12, 4);
6085 int cmode_3_1
= extract32(cmode
, 1, 3);
6086 int cmode_0
= extract32(cmode
, 0, 1);
6087 int o2
= extract32(insn
, 11, 1);
6088 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
6089 bool is_neg
= extract32(insn
, 29, 1);
6090 bool is_q
= extract32(insn
, 30, 1);
6092 TCGv_i64 tcg_rd
, tcg_imm
;
6095 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
6096 unallocated_encoding(s
);
6100 if (!fp_access_check(s
)) {
6104 /* See AdvSIMDExpandImm() in ARM ARM */
6105 switch (cmode_3_1
) {
6106 case 0: /* Replicate(Zeros(24):imm8, 2) */
6107 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6108 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6109 case 3: /* Replicate(imm8:Zeros(24), 2) */
6111 int shift
= cmode_3_1
* 8;
6112 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
6115 case 4: /* Replicate(Zeros(8):imm8, 4) */
6116 case 5: /* Replicate(imm8:Zeros(8), 4) */
6118 int shift
= (cmode_3_1
& 0x1) * 8;
6119 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
6124 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6125 imm
= (abcdefgh
<< 16) | 0xffff;
6127 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6128 imm
= (abcdefgh
<< 8) | 0xff;
6130 imm
= bitfield_replicate(imm
, 32);
6133 if (!cmode_0
&& !is_neg
) {
6134 imm
= bitfield_replicate(abcdefgh
, 8);
6135 } else if (!cmode_0
&& is_neg
) {
6138 for (i
= 0; i
< 8; i
++) {
6139 if ((abcdefgh
) & (1 << i
)) {
6140 imm
|= 0xffULL
<< (i
* 8);
6143 } else if (cmode_0
) {
6145 imm
= (abcdefgh
& 0x3f) << 48;
6146 if (abcdefgh
& 0x80) {
6147 imm
|= 0x8000000000000000ULL
;
6149 if (abcdefgh
& 0x40) {
6150 imm
|= 0x3fc0000000000000ULL
;
6152 imm
|= 0x4000000000000000ULL
;
6155 imm
= (abcdefgh
& 0x3f) << 19;
6156 if (abcdefgh
& 0x80) {
6159 if (abcdefgh
& 0x40) {
6170 if (cmode_3_1
!= 7 && is_neg
) {
6174 tcg_imm
= tcg_const_i64(imm
);
6175 tcg_rd
= new_tmp_a64(s
);
6177 for (i
= 0; i
< 2; i
++) {
6178 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
6180 if (i
== 1 && !is_q
) {
6181 /* non-quad ops clear high half of vector */
6182 tcg_gen_movi_i64(tcg_rd
, 0);
6183 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
6184 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
6187 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6190 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6194 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
6196 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
6199 tcg_temp_free_i64(tcg_imm
);
6202 /* C3.6.7 AdvSIMD scalar copy
6203 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6204 * +-----+----+-----------------+------+---+------+---+------+------+
6205 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6206 * +-----+----+-----------------+------+---+------+---+------+------+
6208 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
6210 int rd
= extract32(insn
, 0, 5);
6211 int rn
= extract32(insn
, 5, 5);
6212 int imm4
= extract32(insn
, 11, 4);
6213 int imm5
= extract32(insn
, 16, 5);
6214 int op
= extract32(insn
, 29, 1);
6216 if (op
!= 0 || imm4
!= 0) {
6217 unallocated_encoding(s
);
6221 /* DUP (element, scalar) */
6222 handle_simd_dupes(s
, rd
, rn
, imm5
);
6225 /* C3.6.8 AdvSIMD scalar pairwise
6226 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6227 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6228 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6229 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6231 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
6233 int u
= extract32(insn
, 29, 1);
6234 int size
= extract32(insn
, 22, 2);
6235 int opcode
= extract32(insn
, 12, 5);
6236 int rn
= extract32(insn
, 5, 5);
6237 int rd
= extract32(insn
, 0, 5);
6240 /* For some ops (the FP ones), size[1] is part of the encoding.
6241 * For ADDP strictly it is not but size[1] is always 1 for valid
6244 opcode
|= (extract32(size
, 1, 1) << 5);
6247 case 0x3b: /* ADDP */
6248 if (u
|| size
!= 3) {
6249 unallocated_encoding(s
);
6252 if (!fp_access_check(s
)) {
6256 TCGV_UNUSED_PTR(fpst
);
6258 case 0xc: /* FMAXNMP */
6259 case 0xd: /* FADDP */
6260 case 0xf: /* FMAXP */
6261 case 0x2c: /* FMINNMP */
6262 case 0x2f: /* FMINP */
6263 /* FP op, size[0] is 32 or 64 bit */
6265 unallocated_encoding(s
);
6268 if (!fp_access_check(s
)) {
6272 size
= extract32(size
, 0, 1) ? 3 : 2;
6273 fpst
= get_fpstatus_ptr();
6276 unallocated_encoding(s
);
6281 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6282 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6283 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6285 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
6286 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
6289 case 0x3b: /* ADDP */
6290 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
6292 case 0xc: /* FMAXNMP */
6293 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6295 case 0xd: /* FADDP */
6296 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6298 case 0xf: /* FMAXP */
6299 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6301 case 0x2c: /* FMINNMP */
6302 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6304 case 0x2f: /* FMINP */
6305 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6308 g_assert_not_reached();
6311 write_fp_dreg(s
, rd
, tcg_res
);
6313 tcg_temp_free_i64(tcg_op1
);
6314 tcg_temp_free_i64(tcg_op2
);
6315 tcg_temp_free_i64(tcg_res
);
6317 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6318 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6319 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6321 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6322 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6325 case 0xc: /* FMAXNMP */
6326 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6328 case 0xd: /* FADDP */
6329 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6331 case 0xf: /* FMAXP */
6332 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6334 case 0x2c: /* FMINNMP */
6335 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6337 case 0x2f: /* FMINP */
6338 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6341 g_assert_not_reached();
6344 write_fp_sreg(s
, rd
, tcg_res
);
6346 tcg_temp_free_i32(tcg_op1
);
6347 tcg_temp_free_i32(tcg_op2
);
6348 tcg_temp_free_i32(tcg_res
);
6351 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
6352 tcg_temp_free_ptr(fpst
);
6357 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6359 * This code is handles the common shifting code and is used by both
6360 * the vector and scalar code.
6362 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6363 TCGv_i64 tcg_rnd
, bool accumulate
,
6364 bool is_u
, int size
, int shift
)
6366 bool extended_result
= false;
6367 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
6369 TCGv_i64 tcg_src_hi
;
6371 if (round
&& size
== 3) {
6372 extended_result
= true;
6373 ext_lshift
= 64 - shift
;
6374 tcg_src_hi
= tcg_temp_new_i64();
6375 } else if (shift
== 64) {
6376 if (!accumulate
&& is_u
) {
6377 /* result is zero */
6378 tcg_gen_movi_i64(tcg_res
, 0);
6383 /* Deal with the rounding step */
6385 if (extended_result
) {
6386 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6388 /* take care of sign extending tcg_res */
6389 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6390 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6391 tcg_src
, tcg_src_hi
,
6394 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6398 tcg_temp_free_i64(tcg_zero
);
6400 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6404 /* Now do the shift right */
6405 if (round
&& extended_result
) {
6406 /* extended case, >64 bit precision required */
6407 if (ext_lshift
== 0) {
6408 /* special case, only high bits matter */
6409 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6411 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6412 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6413 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6418 /* essentially shifting in 64 zeros */
6419 tcg_gen_movi_i64(tcg_src
, 0);
6421 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6425 /* effectively extending the sign-bit */
6426 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6428 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6434 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6436 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6439 if (extended_result
) {
6440 tcg_temp_free_i64(tcg_src_hi
);
6444 /* Common SHL/SLI - Shift left with an optional insert */
6445 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6446 bool insert
, int shift
)
6448 if (insert
) { /* SLI */
6449 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6451 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6455 /* SRI: shift right with insert */
6456 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6457 int size
, int shift
)
6459 int esize
= 8 << size
;
6461 /* shift count same as element size is valid but does nothing;
6462 * special case to avoid potential shift by 64.
6464 if (shift
!= esize
) {
6465 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6466 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6470 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6471 static void handle_scalar_simd_shri(DisasContext
*s
,
6472 bool is_u
, int immh
, int immb
,
6473 int opcode
, int rn
, int rd
)
6476 int immhb
= immh
<< 3 | immb
;
6477 int shift
= 2 * (8 << size
) - immhb
;
6478 bool accumulate
= false;
6480 bool insert
= false;
6485 if (!extract32(immh
, 3, 1)) {
6486 unallocated_encoding(s
);
6490 if (!fp_access_check(s
)) {
6495 case 0x02: /* SSRA / USRA (accumulate) */
6498 case 0x04: /* SRSHR / URSHR (rounding) */
6501 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6502 accumulate
= round
= true;
6504 case 0x08: /* SRI */
6510 uint64_t round_const
= 1ULL << (shift
- 1);
6511 tcg_round
= tcg_const_i64(round_const
);
6513 TCGV_UNUSED_I64(tcg_round
);
6516 tcg_rn
= read_fp_dreg(s
, rn
);
6517 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6520 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6522 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6523 accumulate
, is_u
, size
, shift
);
6526 write_fp_dreg(s
, rd
, tcg_rd
);
6528 tcg_temp_free_i64(tcg_rn
);
6529 tcg_temp_free_i64(tcg_rd
);
6531 tcg_temp_free_i64(tcg_round
);
6535 /* SHL/SLI - Scalar shift left */
6536 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6537 int immh
, int immb
, int opcode
,
6540 int size
= 32 - clz32(immh
) - 1;
6541 int immhb
= immh
<< 3 | immb
;
6542 int shift
= immhb
- (8 << size
);
6543 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6544 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6546 if (!extract32(immh
, 3, 1)) {
6547 unallocated_encoding(s
);
6551 if (!fp_access_check(s
)) {
6555 tcg_rn
= read_fp_dreg(s
, rn
);
6556 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6558 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6560 write_fp_dreg(s
, rd
, tcg_rd
);
6562 tcg_temp_free_i64(tcg_rn
);
6563 tcg_temp_free_i64(tcg_rd
);
6566 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6567 * (signed/unsigned) narrowing */
6568 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6569 bool is_u_shift
, bool is_u_narrow
,
6570 int immh
, int immb
, int opcode
,
6573 int immhb
= immh
<< 3 | immb
;
6574 int size
= 32 - clz32(immh
) - 1;
6575 int esize
= 8 << size
;
6576 int shift
= (2 * esize
) - immhb
;
6577 int elements
= is_scalar
? 1 : (64 / esize
);
6578 bool round
= extract32(opcode
, 0, 1);
6579 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6580 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6581 TCGv_i32 tcg_rd_narrowed
;
6584 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6585 { gen_helper_neon_narrow_sat_s8
,
6586 gen_helper_neon_unarrow_sat8
},
6587 { gen_helper_neon_narrow_sat_s16
,
6588 gen_helper_neon_unarrow_sat16
},
6589 { gen_helper_neon_narrow_sat_s32
,
6590 gen_helper_neon_unarrow_sat32
},
6593 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6594 gen_helper_neon_narrow_sat_u8
,
6595 gen_helper_neon_narrow_sat_u16
,
6596 gen_helper_neon_narrow_sat_u32
,
6599 NeonGenNarrowEnvFn
*narrowfn
;
6605 if (extract32(immh
, 3, 1)) {
6606 unallocated_encoding(s
);
6610 if (!fp_access_check(s
)) {
6615 narrowfn
= unsigned_narrow_fns
[size
];
6617 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6620 tcg_rn
= tcg_temp_new_i64();
6621 tcg_rd
= tcg_temp_new_i64();
6622 tcg_rd_narrowed
= tcg_temp_new_i32();
6623 tcg_final
= tcg_const_i64(0);
6626 uint64_t round_const
= 1ULL << (shift
- 1);
6627 tcg_round
= tcg_const_i64(round_const
);
6629 TCGV_UNUSED_I64(tcg_round
);
6632 for (i
= 0; i
< elements
; i
++) {
6633 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6634 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6635 false, is_u_shift
, size
+1, shift
);
6636 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6637 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6638 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6642 clear_vec_high(s
, rd
);
6643 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6645 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6649 tcg_temp_free_i64(tcg_round
);
6651 tcg_temp_free_i64(tcg_rn
);
6652 tcg_temp_free_i64(tcg_rd
);
6653 tcg_temp_free_i32(tcg_rd_narrowed
);
6654 tcg_temp_free_i64(tcg_final
);
6658 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6659 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6660 bool src_unsigned
, bool dst_unsigned
,
6661 int immh
, int immb
, int rn
, int rd
)
6663 int immhb
= immh
<< 3 | immb
;
6664 int size
= 32 - clz32(immh
) - 1;
6665 int shift
= immhb
- (8 << size
);
6669 assert(!(scalar
&& is_q
));
6672 if (!is_q
&& extract32(immh
, 3, 1)) {
6673 unallocated_encoding(s
);
6677 /* Since we use the variable-shift helpers we must
6678 * replicate the shift count into each element of
6679 * the tcg_shift value.
6683 shift
|= shift
<< 8;
6686 shift
|= shift
<< 16;
6692 g_assert_not_reached();
6696 if (!fp_access_check(s
)) {
6701 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6702 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6703 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6704 { NULL
, gen_helper_neon_qshl_u64
},
6706 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6707 int maxpass
= is_q
? 2 : 1;
6709 for (pass
= 0; pass
< maxpass
; pass
++) {
6710 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6712 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6713 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6714 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6716 tcg_temp_free_i64(tcg_op
);
6718 tcg_temp_free_i64(tcg_shift
);
6721 clear_vec_high(s
, rd
);
6724 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6725 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6727 { gen_helper_neon_qshl_s8
,
6728 gen_helper_neon_qshl_s16
,
6729 gen_helper_neon_qshl_s32
},
6730 { gen_helper_neon_qshlu_s8
,
6731 gen_helper_neon_qshlu_s16
,
6732 gen_helper_neon_qshlu_s32
}
6734 { NULL
, NULL
, NULL
},
6735 { gen_helper_neon_qshl_u8
,
6736 gen_helper_neon_qshl_u16
,
6737 gen_helper_neon_qshl_u32
}
6740 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6741 TCGMemOp memop
= scalar
? size
: MO_32
;
6742 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6744 for (pass
= 0; pass
< maxpass
; pass
++) {
6745 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6747 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6748 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6752 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6755 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6760 g_assert_not_reached();
6762 write_fp_sreg(s
, rd
, tcg_op
);
6764 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6767 tcg_temp_free_i32(tcg_op
);
6769 tcg_temp_free_i32(tcg_shift
);
6771 if (!is_q
&& !scalar
) {
6772 clear_vec_high(s
, rd
);
6777 /* Common vector code for handling integer to FP conversion */
6778 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6779 int elements
, int is_signed
,
6780 int fracbits
, int size
)
6782 bool is_double
= size
== 3 ? true : false;
6783 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6784 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6785 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6786 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6789 for (pass
= 0; pass
< elements
; pass
++) {
6790 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6793 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6795 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6796 tcg_shift
, tcg_fpst
);
6798 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6799 tcg_shift
, tcg_fpst
);
6801 if (elements
== 1) {
6802 write_fp_dreg(s
, rd
, tcg_double
);
6804 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6806 tcg_temp_free_i64(tcg_double
);
6808 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6810 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6811 tcg_shift
, tcg_fpst
);
6813 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6814 tcg_shift
, tcg_fpst
);
6816 if (elements
== 1) {
6817 write_fp_sreg(s
, rd
, tcg_single
);
6819 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6821 tcg_temp_free_i32(tcg_single
);
6825 if (!is_double
&& elements
== 2) {
6826 clear_vec_high(s
, rd
);
6829 tcg_temp_free_i64(tcg_int
);
6830 tcg_temp_free_ptr(tcg_fpst
);
6831 tcg_temp_free_i32(tcg_shift
);
6834 /* UCVTF/SCVTF - Integer to FP conversion */
6835 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6836 bool is_q
, bool is_u
,
6837 int immh
, int immb
, int opcode
,
6840 bool is_double
= extract32(immh
, 3, 1);
6841 int size
= is_double
? MO_64
: MO_32
;
6843 int immhb
= immh
<< 3 | immb
;
6844 int fracbits
= (is_double
? 128 : 64) - immhb
;
6846 if (!extract32(immh
, 2, 2)) {
6847 unallocated_encoding(s
);
6854 elements
= is_double
? 2 : is_q
? 4 : 2;
6855 if (is_double
&& !is_q
) {
6856 unallocated_encoding(s
);
6861 if (!fp_access_check(s
)) {
6865 /* immh == 0 would be a failure of the decode logic */
6868 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6871 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6872 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6873 bool is_q
, bool is_u
,
6874 int immh
, int immb
, int rn
, int rd
)
6876 bool is_double
= extract32(immh
, 3, 1);
6877 int immhb
= immh
<< 3 | immb
;
6878 int fracbits
= (is_double
? 128 : 64) - immhb
;
6880 TCGv_ptr tcg_fpstatus
;
6881 TCGv_i32 tcg_rmode
, tcg_shift
;
6883 if (!extract32(immh
, 2, 2)) {
6884 unallocated_encoding(s
);
6888 if (!is_scalar
&& !is_q
&& is_double
) {
6889 unallocated_encoding(s
);
6893 if (!fp_access_check(s
)) {
6897 assert(!(is_scalar
&& is_q
));
6899 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6900 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6901 tcg_fpstatus
= get_fpstatus_ptr();
6902 tcg_shift
= tcg_const_i32(fracbits
);
6905 int maxpass
= is_scalar
? 1 : 2;
6907 for (pass
= 0; pass
< maxpass
; pass
++) {
6908 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6910 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6912 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6914 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6916 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6917 tcg_temp_free_i64(tcg_op
);
6920 clear_vec_high(s
, rd
);
6923 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6924 for (pass
= 0; pass
< maxpass
; pass
++) {
6925 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6927 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6929 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6931 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6934 write_fp_sreg(s
, rd
, tcg_op
);
6936 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6938 tcg_temp_free_i32(tcg_op
);
6940 if (!is_q
&& !is_scalar
) {
6941 clear_vec_high(s
, rd
);
6945 tcg_temp_free_ptr(tcg_fpstatus
);
6946 tcg_temp_free_i32(tcg_shift
);
6947 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6948 tcg_temp_free_i32(tcg_rmode
);
6951 /* C3.6.9 AdvSIMD scalar shift by immediate
6952 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6953 * +-----+---+-------------+------+------+--------+---+------+------+
6954 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6955 * +-----+---+-------------+------+------+--------+---+------+------+
6957 * This is the scalar version so it works on a fixed sized registers
6959 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6961 int rd
= extract32(insn
, 0, 5);
6962 int rn
= extract32(insn
, 5, 5);
6963 int opcode
= extract32(insn
, 11, 5);
6964 int immb
= extract32(insn
, 16, 3);
6965 int immh
= extract32(insn
, 19, 4);
6966 bool is_u
= extract32(insn
, 29, 1);
6969 unallocated_encoding(s
);
6974 case 0x08: /* SRI */
6976 unallocated_encoding(s
);
6980 case 0x00: /* SSHR / USHR */
6981 case 0x02: /* SSRA / USRA */
6982 case 0x04: /* SRSHR / URSHR */
6983 case 0x06: /* SRSRA / URSRA */
6984 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6986 case 0x0a: /* SHL / SLI */
6987 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6989 case 0x1c: /* SCVTF, UCVTF */
6990 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6993 case 0x10: /* SQSHRUN, SQSHRUN2 */
6994 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6996 unallocated_encoding(s
);
6999 handle_vec_simd_sqshrn(s
, true, false, false, true,
7000 immh
, immb
, opcode
, rn
, rd
);
7002 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
7003 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
7004 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
7005 immh
, immb
, opcode
, rn
, rd
);
7007 case 0xc: /* SQSHLU */
7009 unallocated_encoding(s
);
7012 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
7014 case 0xe: /* SQSHL, UQSHL */
7015 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
7017 case 0x1f: /* FCVTZS, FCVTZU */
7018 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
7021 unallocated_encoding(s
);
7026 /* C3.6.10 AdvSIMD scalar three different
7027 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7028 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7029 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7030 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7032 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7034 bool is_u
= extract32(insn
, 29, 1);
7035 int size
= extract32(insn
, 22, 2);
7036 int opcode
= extract32(insn
, 12, 4);
7037 int rm
= extract32(insn
, 16, 5);
7038 int rn
= extract32(insn
, 5, 5);
7039 int rd
= extract32(insn
, 0, 5);
7042 unallocated_encoding(s
);
7047 case 0x9: /* SQDMLAL, SQDMLAL2 */
7048 case 0xb: /* SQDMLSL, SQDMLSL2 */
7049 case 0xd: /* SQDMULL, SQDMULL2 */
7050 if (size
== 0 || size
== 3) {
7051 unallocated_encoding(s
);
7056 unallocated_encoding(s
);
7060 if (!fp_access_check(s
)) {
7065 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7066 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7067 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7069 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
7070 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
7072 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
7073 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7076 case 0xd: /* SQDMULL, SQDMULL2 */
7078 case 0xb: /* SQDMLSL, SQDMLSL2 */
7079 tcg_gen_neg_i64(tcg_res
, tcg_res
);
7081 case 0x9: /* SQDMLAL, SQDMLAL2 */
7082 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
7083 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
7087 g_assert_not_reached();
7090 write_fp_dreg(s
, rd
, tcg_res
);
7092 tcg_temp_free_i64(tcg_op1
);
7093 tcg_temp_free_i64(tcg_op2
);
7094 tcg_temp_free_i64(tcg_res
);
7096 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7097 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7098 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7100 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
7101 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
7103 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
7104 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7107 case 0xd: /* SQDMULL, SQDMULL2 */
7109 case 0xb: /* SQDMLSL, SQDMLSL2 */
7110 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
7112 case 0x9: /* SQDMLAL, SQDMLAL2 */
7114 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
7115 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
7116 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
7118 tcg_temp_free_i64(tcg_op3
);
7122 g_assert_not_reached();
7125 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7126 write_fp_dreg(s
, rd
, tcg_res
);
7128 tcg_temp_free_i32(tcg_op1
);
7129 tcg_temp_free_i32(tcg_op2
);
7130 tcg_temp_free_i64(tcg_res
);
7134 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
7135 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
7137 /* Handle 64x64->64 opcodes which are shared between the scalar
7138 * and vector 3-same groups. We cover every opcode where size == 3
7139 * is valid in either the three-reg-same (integer, not pairwise)
7140 * or scalar-three-reg-same groups. (Some opcodes are not yet
7146 case 0x1: /* SQADD */
7148 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7150 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7153 case 0x5: /* SQSUB */
7155 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7157 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7160 case 0x6: /* CMGT, CMHI */
7161 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
7162 * We implement this using setcond (test) and then negating.
7164 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
7166 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
7167 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7169 case 0x7: /* CMGE, CMHS */
7170 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
7172 case 0x11: /* CMTST, CMEQ */
7177 /* CMTST : test is "if (X & Y != 0)". */
7178 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7179 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
7180 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7182 case 0x8: /* SSHL, USHL */
7184 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7186 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7189 case 0x9: /* SQSHL, UQSHL */
7191 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7193 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7196 case 0xa: /* SRSHL, URSHL */
7198 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7200 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7203 case 0xb: /* SQRSHL, UQRSHL */
7205 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7207 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7210 case 0x10: /* ADD, SUB */
7212 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7214 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7218 g_assert_not_reached();
7222 /* Handle the 3-same-operands float operations; shared by the scalar
7223 * and vector encodings. The caller must filter out any encodings
7224 * not allocated for the encoding it is dealing with.
7226 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
7227 int fpopcode
, int rd
, int rn
, int rm
)
7230 TCGv_ptr fpst
= get_fpstatus_ptr();
7232 for (pass
= 0; pass
< elements
; pass
++) {
7235 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7236 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7237 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7239 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7240 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7243 case 0x39: /* FMLS */
7244 /* As usual for ARM, separate negation for fused multiply-add */
7245 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
7247 case 0x19: /* FMLA */
7248 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7249 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
7252 case 0x18: /* FMAXNM */
7253 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7255 case 0x1a: /* FADD */
7256 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7258 case 0x1b: /* FMULX */
7259 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7261 case 0x1c: /* FCMEQ */
7262 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7264 case 0x1e: /* FMAX */
7265 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7267 case 0x1f: /* FRECPS */
7268 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7270 case 0x38: /* FMINNM */
7271 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7273 case 0x3a: /* FSUB */
7274 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7276 case 0x3e: /* FMIN */
7277 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7279 case 0x3f: /* FRSQRTS */
7280 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7282 case 0x5b: /* FMUL */
7283 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7285 case 0x5c: /* FCMGE */
7286 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7288 case 0x5d: /* FACGE */
7289 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7291 case 0x5f: /* FDIV */
7292 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7294 case 0x7a: /* FABD */
7295 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7296 gen_helper_vfp_absd(tcg_res
, tcg_res
);
7298 case 0x7c: /* FCMGT */
7299 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7301 case 0x7d: /* FACGT */
7302 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7305 g_assert_not_reached();
7308 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7310 tcg_temp_free_i64(tcg_res
);
7311 tcg_temp_free_i64(tcg_op1
);
7312 tcg_temp_free_i64(tcg_op2
);
7315 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7316 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7317 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7319 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7320 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7323 case 0x39: /* FMLS */
7324 /* As usual for ARM, separate negation for fused multiply-add */
7325 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7327 case 0x19: /* FMLA */
7328 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7329 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7332 case 0x1a: /* FADD */
7333 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7335 case 0x1b: /* FMULX */
7336 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7338 case 0x1c: /* FCMEQ */
7339 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7341 case 0x1e: /* FMAX */
7342 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7344 case 0x1f: /* FRECPS */
7345 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7347 case 0x18: /* FMAXNM */
7348 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7350 case 0x38: /* FMINNM */
7351 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7353 case 0x3a: /* FSUB */
7354 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7356 case 0x3e: /* FMIN */
7357 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7359 case 0x3f: /* FRSQRTS */
7360 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7362 case 0x5b: /* FMUL */
7363 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7365 case 0x5c: /* FCMGE */
7366 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7368 case 0x5d: /* FACGE */
7369 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7371 case 0x5f: /* FDIV */
7372 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7374 case 0x7a: /* FABD */
7375 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7376 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7378 case 0x7c: /* FCMGT */
7379 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7381 case 0x7d: /* FACGT */
7382 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7385 g_assert_not_reached();
7388 if (elements
== 1) {
7389 /* scalar single so clear high part */
7390 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7392 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7393 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7394 tcg_temp_free_i64(tcg_tmp
);
7396 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7399 tcg_temp_free_i32(tcg_res
);
7400 tcg_temp_free_i32(tcg_op1
);
7401 tcg_temp_free_i32(tcg_op2
);
7405 tcg_temp_free_ptr(fpst
);
7407 if ((elements
<< size
) < 4) {
7408 /* scalar, or non-quad vector op */
7409 clear_vec_high(s
, rd
);
7413 /* C3.6.11 AdvSIMD scalar three same
7414 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7415 * +-----+---+-----------+------+---+------+--------+---+------+------+
7416 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7417 * +-----+---+-----------+------+---+------+--------+---+------+------+
7419 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7421 int rd
= extract32(insn
, 0, 5);
7422 int rn
= extract32(insn
, 5, 5);
7423 int opcode
= extract32(insn
, 11, 5);
7424 int rm
= extract32(insn
, 16, 5);
7425 int size
= extract32(insn
, 22, 2);
7426 bool u
= extract32(insn
, 29, 1);
7429 if (opcode
>= 0x18) {
7430 /* Floating point: U, size[1] and opcode indicate operation */
7431 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7433 case 0x1b: /* FMULX */
7434 case 0x1f: /* FRECPS */
7435 case 0x3f: /* FRSQRTS */
7436 case 0x5d: /* FACGE */
7437 case 0x7d: /* FACGT */
7438 case 0x1c: /* FCMEQ */
7439 case 0x5c: /* FCMGE */
7440 case 0x7c: /* FCMGT */
7441 case 0x7a: /* FABD */
7444 unallocated_encoding(s
);
7448 if (!fp_access_check(s
)) {
7452 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7457 case 0x1: /* SQADD, UQADD */
7458 case 0x5: /* SQSUB, UQSUB */
7459 case 0x9: /* SQSHL, UQSHL */
7460 case 0xb: /* SQRSHL, UQRSHL */
7462 case 0x8: /* SSHL, USHL */
7463 case 0xa: /* SRSHL, URSHL */
7464 case 0x6: /* CMGT, CMHI */
7465 case 0x7: /* CMGE, CMHS */
7466 case 0x11: /* CMTST, CMEQ */
7467 case 0x10: /* ADD, SUB (vector) */
7469 unallocated_encoding(s
);
7473 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7474 if (size
!= 1 && size
!= 2) {
7475 unallocated_encoding(s
);
7480 unallocated_encoding(s
);
7484 if (!fp_access_check(s
)) {
7488 tcg_rd
= tcg_temp_new_i64();
7491 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7492 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7494 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7495 tcg_temp_free_i64(tcg_rn
);
7496 tcg_temp_free_i64(tcg_rm
);
7498 /* Do a single operation on the lowest element in the vector.
7499 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7500 * no side effects for all these operations.
7501 * OPTME: special-purpose helpers would avoid doing some
7502 * unnecessary work in the helper for the 8 and 16 bit cases.
7504 NeonGenTwoOpEnvFn
*genenvfn
;
7505 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7506 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7507 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7509 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7510 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7513 case 0x1: /* SQADD, UQADD */
7515 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7516 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7517 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7518 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7520 genenvfn
= fns
[size
][u
];
7523 case 0x5: /* SQSUB, UQSUB */
7525 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7526 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7527 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7528 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7530 genenvfn
= fns
[size
][u
];
7533 case 0x9: /* SQSHL, UQSHL */
7535 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7536 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7537 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7538 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7540 genenvfn
= fns
[size
][u
];
7543 case 0xb: /* SQRSHL, UQRSHL */
7545 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7546 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7547 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7548 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7550 genenvfn
= fns
[size
][u
];
7553 case 0x16: /* SQDMULH, SQRDMULH */
7555 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7556 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7557 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7559 assert(size
== 1 || size
== 2);
7560 genenvfn
= fns
[size
- 1][u
];
7564 g_assert_not_reached();
7567 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7568 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7569 tcg_temp_free_i32(tcg_rd32
);
7570 tcg_temp_free_i32(tcg_rn
);
7571 tcg_temp_free_i32(tcg_rm
);
7574 write_fp_dreg(s
, rd
, tcg_rd
);
7576 tcg_temp_free_i64(tcg_rd
);
7579 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7580 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7581 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7583 /* Handle 64->64 opcodes which are shared between the scalar and
7584 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7585 * is valid in either group and also the double-precision fp ops.
7586 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7592 case 0x4: /* CLS, CLZ */
7594 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
7596 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
7600 /* This opcode is shared with CNT and RBIT but we have earlier
7601 * enforced that size == 3 if and only if this is the NOT insn.
7603 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7605 case 0x7: /* SQABS, SQNEG */
7607 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7609 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7612 case 0xa: /* CMLT */
7613 /* 64 bit integer comparison against zero, result is
7614 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7619 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7620 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7622 case 0x8: /* CMGT, CMGE */
7623 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7625 case 0x9: /* CMEQ, CMLE */
7626 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7628 case 0xb: /* ABS, NEG */
7630 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7632 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7633 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7634 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7636 tcg_temp_free_i64(tcg_zero
);
7639 case 0x2f: /* FABS */
7640 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7642 case 0x6f: /* FNEG */
7643 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7645 case 0x7f: /* FSQRT */
7646 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7648 case 0x1a: /* FCVTNS */
7649 case 0x1b: /* FCVTMS */
7650 case 0x1c: /* FCVTAS */
7651 case 0x3a: /* FCVTPS */
7652 case 0x3b: /* FCVTZS */
7654 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7655 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7656 tcg_temp_free_i32(tcg_shift
);
7659 case 0x5a: /* FCVTNU */
7660 case 0x5b: /* FCVTMU */
7661 case 0x5c: /* FCVTAU */
7662 case 0x7a: /* FCVTPU */
7663 case 0x7b: /* FCVTZU */
7665 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7666 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7667 tcg_temp_free_i32(tcg_shift
);
7670 case 0x18: /* FRINTN */
7671 case 0x19: /* FRINTM */
7672 case 0x38: /* FRINTP */
7673 case 0x39: /* FRINTZ */
7674 case 0x58: /* FRINTA */
7675 case 0x79: /* FRINTI */
7676 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7678 case 0x59: /* FRINTX */
7679 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7682 g_assert_not_reached();
7686 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7687 bool is_scalar
, bool is_u
, bool is_q
,
7688 int size
, int rn
, int rd
)
7690 bool is_double
= (size
== 3);
7693 if (!fp_access_check(s
)) {
7697 fpst
= get_fpstatus_ptr();
7700 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7701 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7702 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7703 NeonGenTwoDoubleOPFn
*genfn
;
7708 case 0x2e: /* FCMLT (zero) */
7711 case 0x2c: /* FCMGT (zero) */
7712 genfn
= gen_helper_neon_cgt_f64
;
7714 case 0x2d: /* FCMEQ (zero) */
7715 genfn
= gen_helper_neon_ceq_f64
;
7717 case 0x6d: /* FCMLE (zero) */
7720 case 0x6c: /* FCMGE (zero) */
7721 genfn
= gen_helper_neon_cge_f64
;
7724 g_assert_not_reached();
7727 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7728 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7730 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7732 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7734 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7737 clear_vec_high(s
, rd
);
7740 tcg_temp_free_i64(tcg_res
);
7741 tcg_temp_free_i64(tcg_zero
);
7742 tcg_temp_free_i64(tcg_op
);
7744 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7745 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7746 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7747 NeonGenTwoSingleOPFn
*genfn
;
7749 int pass
, maxpasses
;
7752 case 0x2e: /* FCMLT (zero) */
7755 case 0x2c: /* FCMGT (zero) */
7756 genfn
= gen_helper_neon_cgt_f32
;
7758 case 0x2d: /* FCMEQ (zero) */
7759 genfn
= gen_helper_neon_ceq_f32
;
7761 case 0x6d: /* FCMLE (zero) */
7764 case 0x6c: /* FCMGE (zero) */
7765 genfn
= gen_helper_neon_cge_f32
;
7768 g_assert_not_reached();
7774 maxpasses
= is_q
? 4 : 2;
7777 for (pass
= 0; pass
< maxpasses
; pass
++) {
7778 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7780 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7782 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7785 write_fp_sreg(s
, rd
, tcg_res
);
7787 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7790 tcg_temp_free_i32(tcg_res
);
7791 tcg_temp_free_i32(tcg_zero
);
7792 tcg_temp_free_i32(tcg_op
);
7793 if (!is_q
&& !is_scalar
) {
7794 clear_vec_high(s
, rd
);
7798 tcg_temp_free_ptr(fpst
);
7801 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7802 bool is_scalar
, bool is_u
, bool is_q
,
7803 int size
, int rn
, int rd
)
7805 bool is_double
= (size
== 3);
7806 TCGv_ptr fpst
= get_fpstatus_ptr();
7809 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7810 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7813 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7814 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7816 case 0x3d: /* FRECPE */
7817 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7819 case 0x3f: /* FRECPX */
7820 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7822 case 0x7d: /* FRSQRTE */
7823 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7826 g_assert_not_reached();
7828 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7831 clear_vec_high(s
, rd
);
7834 tcg_temp_free_i64(tcg_res
);
7835 tcg_temp_free_i64(tcg_op
);
7837 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7838 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7839 int pass
, maxpasses
;
7844 maxpasses
= is_q
? 4 : 2;
7847 for (pass
= 0; pass
< maxpasses
; pass
++) {
7848 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7851 case 0x3c: /* URECPE */
7852 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7854 case 0x3d: /* FRECPE */
7855 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7857 case 0x3f: /* FRECPX */
7858 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7860 case 0x7d: /* FRSQRTE */
7861 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7864 g_assert_not_reached();
7868 write_fp_sreg(s
, rd
, tcg_res
);
7870 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7873 tcg_temp_free_i32(tcg_res
);
7874 tcg_temp_free_i32(tcg_op
);
7875 if (!is_q
&& !is_scalar
) {
7876 clear_vec_high(s
, rd
);
7879 tcg_temp_free_ptr(fpst
);
7882 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7883 int opcode
, bool u
, bool is_q
,
7884 int size
, int rn
, int rd
)
7886 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7887 * in the source becomes a size element in the destination).
7890 TCGv_i32 tcg_res
[2];
7891 int destelt
= is_q
? 2 : 0;
7892 int passes
= scalar
? 1 : 2;
7895 tcg_res
[1] = tcg_const_i32(0);
7898 for (pass
= 0; pass
< passes
; pass
++) {
7899 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7900 NeonGenNarrowFn
*genfn
= NULL
;
7901 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7904 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7906 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7908 tcg_res
[pass
] = tcg_temp_new_i32();
7911 case 0x12: /* XTN, SQXTUN */
7913 static NeonGenNarrowFn
* const xtnfns
[3] = {
7914 gen_helper_neon_narrow_u8
,
7915 gen_helper_neon_narrow_u16
,
7916 tcg_gen_extrl_i64_i32
,
7918 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7919 gen_helper_neon_unarrow_sat8
,
7920 gen_helper_neon_unarrow_sat16
,
7921 gen_helper_neon_unarrow_sat32
,
7924 genenvfn
= sqxtunfns
[size
];
7926 genfn
= xtnfns
[size
];
7930 case 0x14: /* SQXTN, UQXTN */
7932 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7933 { gen_helper_neon_narrow_sat_s8
,
7934 gen_helper_neon_narrow_sat_u8
},
7935 { gen_helper_neon_narrow_sat_s16
,
7936 gen_helper_neon_narrow_sat_u16
},
7937 { gen_helper_neon_narrow_sat_s32
,
7938 gen_helper_neon_narrow_sat_u32
},
7940 genenvfn
= fns
[size
][u
];
7943 case 0x16: /* FCVTN, FCVTN2 */
7944 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7946 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7948 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7949 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7950 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
7951 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7952 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7953 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7954 tcg_temp_free_i32(tcg_lo
);
7955 tcg_temp_free_i32(tcg_hi
);
7958 case 0x56: /* FCVTXN, FCVTXN2 */
7959 /* 64 bit to 32 bit float conversion
7960 * with von Neumann rounding (round to odd)
7963 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7966 g_assert_not_reached();
7970 genfn(tcg_res
[pass
], tcg_op
);
7971 } else if (genenvfn
) {
7972 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7975 tcg_temp_free_i64(tcg_op
);
7978 for (pass
= 0; pass
< 2; pass
++) {
7979 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7980 tcg_temp_free_i32(tcg_res
[pass
]);
7983 clear_vec_high(s
, rd
);
7987 /* Remaining saturating accumulating ops */
7988 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
7989 bool is_q
, int size
, int rn
, int rd
)
7991 bool is_double
= (size
== 3);
7994 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
7995 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7998 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7999 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
8000 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
8002 if (is_u
) { /* USQADD */
8003 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8004 } else { /* SUQADD */
8005 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8007 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
8010 clear_vec_high(s
, rd
);
8013 tcg_temp_free_i64(tcg_rd
);
8014 tcg_temp_free_i64(tcg_rn
);
8016 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8017 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8018 int pass
, maxpasses
;
8023 maxpasses
= is_q
? 4 : 2;
8026 for (pass
= 0; pass
< maxpasses
; pass
++) {
8028 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
8029 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
8031 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
8032 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8035 if (is_u
) { /* USQADD */
8038 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8041 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8044 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8047 g_assert_not_reached();
8049 } else { /* SUQADD */
8052 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8055 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8058 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8061 g_assert_not_reached();
8066 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8067 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
8068 tcg_temp_free_i64(tcg_zero
);
8070 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8074 clear_vec_high(s
, rd
);
8077 tcg_temp_free_i32(tcg_rd
);
8078 tcg_temp_free_i32(tcg_rn
);
8082 /* C3.6.12 AdvSIMD scalar two reg misc
8083 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8084 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8085 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
8086 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8088 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
8090 int rd
= extract32(insn
, 0, 5);
8091 int rn
= extract32(insn
, 5, 5);
8092 int opcode
= extract32(insn
, 12, 5);
8093 int size
= extract32(insn
, 22, 2);
8094 bool u
= extract32(insn
, 29, 1);
8095 bool is_fcvt
= false;
8098 TCGv_ptr tcg_fpstatus
;
8101 case 0x3: /* USQADD / SUQADD*/
8102 if (!fp_access_check(s
)) {
8105 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
8107 case 0x7: /* SQABS / SQNEG */
8109 case 0xa: /* CMLT */
8111 unallocated_encoding(s
);
8115 case 0x8: /* CMGT, CMGE */
8116 case 0x9: /* CMEQ, CMLE */
8117 case 0xb: /* ABS, NEG */
8119 unallocated_encoding(s
);
8123 case 0x12: /* SQXTUN */
8125 unallocated_encoding(s
);
8129 case 0x14: /* SQXTN, UQXTN */
8131 unallocated_encoding(s
);
8134 if (!fp_access_check(s
)) {
8137 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
8142 /* Floating point: U, size[1] and opcode indicate operation;
8143 * size[0] indicates single or double precision.
8145 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
8146 size
= extract32(size
, 0, 1) ? 3 : 2;
8148 case 0x2c: /* FCMGT (zero) */
8149 case 0x2d: /* FCMEQ (zero) */
8150 case 0x2e: /* FCMLT (zero) */
8151 case 0x6c: /* FCMGE (zero) */
8152 case 0x6d: /* FCMLE (zero) */
8153 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
8155 case 0x1d: /* SCVTF */
8156 case 0x5d: /* UCVTF */
8158 bool is_signed
= (opcode
== 0x1d);
8159 if (!fp_access_check(s
)) {
8162 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
8165 case 0x3d: /* FRECPE */
8166 case 0x3f: /* FRECPX */
8167 case 0x7d: /* FRSQRTE */
8168 if (!fp_access_check(s
)) {
8171 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
8173 case 0x1a: /* FCVTNS */
8174 case 0x1b: /* FCVTMS */
8175 case 0x3a: /* FCVTPS */
8176 case 0x3b: /* FCVTZS */
8177 case 0x5a: /* FCVTNU */
8178 case 0x5b: /* FCVTMU */
8179 case 0x7a: /* FCVTPU */
8180 case 0x7b: /* FCVTZU */
8182 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
8184 case 0x1c: /* FCVTAS */
8185 case 0x5c: /* FCVTAU */
8186 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
8188 rmode
= FPROUNDING_TIEAWAY
;
8190 case 0x56: /* FCVTXN, FCVTXN2 */
8192 unallocated_encoding(s
);
8195 if (!fp_access_check(s
)) {
8198 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
8201 unallocated_encoding(s
);
8206 unallocated_encoding(s
);
8210 if (!fp_access_check(s
)) {
8215 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
8216 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8217 tcg_fpstatus
= get_fpstatus_ptr();
8219 TCGV_UNUSED_I32(tcg_rmode
);
8220 TCGV_UNUSED_PTR(tcg_fpstatus
);
8224 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8225 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8227 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
8228 write_fp_dreg(s
, rd
, tcg_rd
);
8229 tcg_temp_free_i64(tcg_rd
);
8230 tcg_temp_free_i64(tcg_rn
);
8232 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8233 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8235 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8238 case 0x7: /* SQABS, SQNEG */
8240 NeonGenOneOpEnvFn
*genfn
;
8241 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
8242 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
8243 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
8244 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
8246 genfn
= fns
[size
][u
];
8247 genfn(tcg_rd
, cpu_env
, tcg_rn
);
8250 case 0x1a: /* FCVTNS */
8251 case 0x1b: /* FCVTMS */
8252 case 0x1c: /* FCVTAS */
8253 case 0x3a: /* FCVTPS */
8254 case 0x3b: /* FCVTZS */
8256 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8257 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8258 tcg_temp_free_i32(tcg_shift
);
8261 case 0x5a: /* FCVTNU */
8262 case 0x5b: /* FCVTMU */
8263 case 0x5c: /* FCVTAU */
8264 case 0x7a: /* FCVTPU */
8265 case 0x7b: /* FCVTZU */
8267 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8268 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8269 tcg_temp_free_i32(tcg_shift
);
8273 g_assert_not_reached();
8276 write_fp_sreg(s
, rd
, tcg_rd
);
8277 tcg_temp_free_i32(tcg_rd
);
8278 tcg_temp_free_i32(tcg_rn
);
8282 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8283 tcg_temp_free_i32(tcg_rmode
);
8284 tcg_temp_free_ptr(tcg_fpstatus
);
8288 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8289 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
8290 int immh
, int immb
, int opcode
, int rn
, int rd
)
8292 int size
= 32 - clz32(immh
) - 1;
8293 int immhb
= immh
<< 3 | immb
;
8294 int shift
= 2 * (8 << size
) - immhb
;
8295 bool accumulate
= false;
8297 bool insert
= false;
8298 int dsize
= is_q
? 128 : 64;
8299 int esize
= 8 << size
;
8300 int elements
= dsize
/esize
;
8301 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
8302 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8303 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8307 if (extract32(immh
, 3, 1) && !is_q
) {
8308 unallocated_encoding(s
);
8312 if (size
> 3 && !is_q
) {
8313 unallocated_encoding(s
);
8317 if (!fp_access_check(s
)) {
8322 case 0x02: /* SSRA / USRA (accumulate) */
8325 case 0x04: /* SRSHR / URSHR (rounding) */
8328 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8329 accumulate
= round
= true;
8331 case 0x08: /* SRI */
8337 uint64_t round_const
= 1ULL << (shift
- 1);
8338 tcg_round
= tcg_const_i64(round_const
);
8340 TCGV_UNUSED_I64(tcg_round
);
8343 for (i
= 0; i
< elements
; i
++) {
8344 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8345 if (accumulate
|| insert
) {
8346 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8350 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8352 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8353 accumulate
, is_u
, size
, shift
);
8356 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8360 clear_vec_high(s
, rd
);
8364 tcg_temp_free_i64(tcg_round
);
8368 /* SHL/SLI - Vector shift left */
8369 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8370 int immh
, int immb
, int opcode
, int rn
, int rd
)
8372 int size
= 32 - clz32(immh
) - 1;
8373 int immhb
= immh
<< 3 | immb
;
8374 int shift
= immhb
- (8 << size
);
8375 int dsize
= is_q
? 128 : 64;
8376 int esize
= 8 << size
;
8377 int elements
= dsize
/esize
;
8378 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8379 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8382 if (extract32(immh
, 3, 1) && !is_q
) {
8383 unallocated_encoding(s
);
8387 if (size
> 3 && !is_q
) {
8388 unallocated_encoding(s
);
8392 if (!fp_access_check(s
)) {
8396 for (i
= 0; i
< elements
; i
++) {
8397 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8399 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8402 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8404 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8408 clear_vec_high(s
, rd
);
8412 /* USHLL/SHLL - Vector shift left with widening */
8413 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8414 int immh
, int immb
, int opcode
, int rn
, int rd
)
8416 int size
= 32 - clz32(immh
) - 1;
8417 int immhb
= immh
<< 3 | immb
;
8418 int shift
= immhb
- (8 << size
);
8420 int esize
= 8 << size
;
8421 int elements
= dsize
/esize
;
8422 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8423 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8427 unallocated_encoding(s
);
8431 if (!fp_access_check(s
)) {
8435 /* For the LL variants the store is larger than the load,
8436 * so if rd == rn we would overwrite parts of our input.
8437 * So load everything right now and use shifts in the main loop.
8439 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8441 for (i
= 0; i
< elements
; i
++) {
8442 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8443 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8444 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8445 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8449 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8450 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8451 int immh
, int immb
, int opcode
, int rn
, int rd
)
8453 int immhb
= immh
<< 3 | immb
;
8454 int size
= 32 - clz32(immh
) - 1;
8456 int esize
= 8 << size
;
8457 int elements
= dsize
/esize
;
8458 int shift
= (2 * esize
) - immhb
;
8459 bool round
= extract32(opcode
, 0, 1);
8460 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8464 if (extract32(immh
, 3, 1)) {
8465 unallocated_encoding(s
);
8469 if (!fp_access_check(s
)) {
8473 tcg_rn
= tcg_temp_new_i64();
8474 tcg_rd
= tcg_temp_new_i64();
8475 tcg_final
= tcg_temp_new_i64();
8476 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8479 uint64_t round_const
= 1ULL << (shift
- 1);
8480 tcg_round
= tcg_const_i64(round_const
);
8482 TCGV_UNUSED_I64(tcg_round
);
8485 for (i
= 0; i
< elements
; i
++) {
8486 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8487 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8488 false, true, size
+1, shift
);
8490 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8494 clear_vec_high(s
, rd
);
8495 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8497 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8501 tcg_temp_free_i64(tcg_round
);
8503 tcg_temp_free_i64(tcg_rn
);
8504 tcg_temp_free_i64(tcg_rd
);
8505 tcg_temp_free_i64(tcg_final
);
8510 /* C3.6.14 AdvSIMD shift by immediate
8511 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8512 * +---+---+---+-------------+------+------+--------+---+------+------+
8513 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8514 * +---+---+---+-------------+------+------+--------+---+------+------+
8516 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8518 int rd
= extract32(insn
, 0, 5);
8519 int rn
= extract32(insn
, 5, 5);
8520 int opcode
= extract32(insn
, 11, 5);
8521 int immb
= extract32(insn
, 16, 3);
8522 int immh
= extract32(insn
, 19, 4);
8523 bool is_u
= extract32(insn
, 29, 1);
8524 bool is_q
= extract32(insn
, 30, 1);
8527 case 0x08: /* SRI */
8529 unallocated_encoding(s
);
8533 case 0x00: /* SSHR / USHR */
8534 case 0x02: /* SSRA / USRA (accumulate) */
8535 case 0x04: /* SRSHR / URSHR (rounding) */
8536 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8537 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8539 case 0x0a: /* SHL / SLI */
8540 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8542 case 0x10: /* SHRN */
8543 case 0x11: /* RSHRN / SQRSHRUN */
8545 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8548 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8551 case 0x12: /* SQSHRN / UQSHRN */
8552 case 0x13: /* SQRSHRN / UQRSHRN */
8553 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8556 case 0x14: /* SSHLL / USHLL */
8557 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8559 case 0x1c: /* SCVTF / UCVTF */
8560 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8563 case 0xc: /* SQSHLU */
8565 unallocated_encoding(s
);
8568 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8570 case 0xe: /* SQSHL, UQSHL */
8571 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8573 case 0x1f: /* FCVTZS/ FCVTZU */
8574 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8577 unallocated_encoding(s
);
8582 /* Generate code to do a "long" addition or subtraction, ie one done in
8583 * TCGv_i64 on vector lanes twice the width specified by size.
8585 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8586 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8588 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8589 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8590 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8591 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8593 NeonGenTwo64OpFn
*genfn
;
8596 genfn
= fns
[size
][is_sub
];
8597 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8600 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8601 int opcode
, int rd
, int rn
, int rm
)
8603 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8604 TCGv_i64 tcg_res
[2];
8607 tcg_res
[0] = tcg_temp_new_i64();
8608 tcg_res
[1] = tcg_temp_new_i64();
8610 /* Does this op do an adding accumulate, a subtracting accumulate,
8611 * or no accumulate at all?
8629 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8630 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8633 /* size == 2 means two 32x32->64 operations; this is worth special
8634 * casing because we can generally handle it inline.
8637 for (pass
= 0; pass
< 2; pass
++) {
8638 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8639 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8640 TCGv_i64 tcg_passres
;
8641 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8643 int elt
= pass
+ is_q
* 2;
8645 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8646 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8649 tcg_passres
= tcg_res
[pass
];
8651 tcg_passres
= tcg_temp_new_i64();
8655 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8656 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8658 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8659 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8661 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8662 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8664 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8665 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8667 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8668 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8669 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8671 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8672 tcg_temp_free_i64(tcg_tmp1
);
8673 tcg_temp_free_i64(tcg_tmp2
);
8676 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8677 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8678 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8679 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8681 case 9: /* SQDMLAL, SQDMLAL2 */
8682 case 11: /* SQDMLSL, SQDMLSL2 */
8683 case 13: /* SQDMULL, SQDMULL2 */
8684 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8685 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8686 tcg_passres
, tcg_passres
);
8689 g_assert_not_reached();
8692 if (opcode
== 9 || opcode
== 11) {
8693 /* saturating accumulate ops */
8695 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8697 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8698 tcg_res
[pass
], tcg_passres
);
8699 } else if (accop
> 0) {
8700 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8701 } else if (accop
< 0) {
8702 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8706 tcg_temp_free_i64(tcg_passres
);
8709 tcg_temp_free_i64(tcg_op1
);
8710 tcg_temp_free_i64(tcg_op2
);
8713 /* size 0 or 1, generally helper functions */
8714 for (pass
= 0; pass
< 2; pass
++) {
8715 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8716 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8717 TCGv_i64 tcg_passres
;
8718 int elt
= pass
+ is_q
* 2;
8720 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8721 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8724 tcg_passres
= tcg_res
[pass
];
8726 tcg_passres
= tcg_temp_new_i64();
8730 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8731 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8733 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8734 static NeonGenWidenFn
* const widenfns
[2][2] = {
8735 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8736 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8738 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8740 widenfn(tcg_op2_64
, tcg_op2
);
8741 widenfn(tcg_passres
, tcg_op1
);
8742 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8743 tcg_passres
, tcg_op2_64
);
8744 tcg_temp_free_i64(tcg_op2_64
);
8747 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8748 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8751 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8753 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8757 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8759 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8763 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8764 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8765 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8768 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8770 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8774 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8776 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8780 case 9: /* SQDMLAL, SQDMLAL2 */
8781 case 11: /* SQDMLSL, SQDMLSL2 */
8782 case 13: /* SQDMULL, SQDMULL2 */
8784 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8785 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8786 tcg_passres
, tcg_passres
);
8788 case 14: /* PMULL */
8790 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8793 g_assert_not_reached();
8795 tcg_temp_free_i32(tcg_op1
);
8796 tcg_temp_free_i32(tcg_op2
);
8799 if (opcode
== 9 || opcode
== 11) {
8800 /* saturating accumulate ops */
8802 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8804 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8808 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8809 tcg_res
[pass
], tcg_passres
);
8811 tcg_temp_free_i64(tcg_passres
);
8816 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8817 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8818 tcg_temp_free_i64(tcg_res
[0]);
8819 tcg_temp_free_i64(tcg_res
[1]);
8822 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8823 int opcode
, int rd
, int rn
, int rm
)
8825 TCGv_i64 tcg_res
[2];
8826 int part
= is_q
? 2 : 0;
8829 for (pass
= 0; pass
< 2; pass
++) {
8830 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8831 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8832 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8833 static NeonGenWidenFn
* const widenfns
[3][2] = {
8834 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8835 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8836 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8838 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8840 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8841 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8842 widenfn(tcg_op2_wide
, tcg_op2
);
8843 tcg_temp_free_i32(tcg_op2
);
8844 tcg_res
[pass
] = tcg_temp_new_i64();
8845 gen_neon_addl(size
, (opcode
== 3),
8846 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8847 tcg_temp_free_i64(tcg_op1
);
8848 tcg_temp_free_i64(tcg_op2_wide
);
8851 for (pass
= 0; pass
< 2; pass
++) {
8852 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8853 tcg_temp_free_i64(tcg_res
[pass
]);
8857 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8859 tcg_gen_addi_i64(in
, in
, 1U << 31);
8860 tcg_gen_extrh_i64_i32(res
, in
);
8863 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8864 int opcode
, int rd
, int rn
, int rm
)
8866 TCGv_i32 tcg_res
[2];
8867 int part
= is_q
? 2 : 0;
8870 for (pass
= 0; pass
< 2; pass
++) {
8871 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8872 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8873 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8874 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8875 { gen_helper_neon_narrow_high_u8
,
8876 gen_helper_neon_narrow_round_high_u8
},
8877 { gen_helper_neon_narrow_high_u16
,
8878 gen_helper_neon_narrow_round_high_u16
},
8879 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
8881 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8883 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8884 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8886 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8888 tcg_temp_free_i64(tcg_op1
);
8889 tcg_temp_free_i64(tcg_op2
);
8891 tcg_res
[pass
] = tcg_temp_new_i32();
8892 gennarrow(tcg_res
[pass
], tcg_wideres
);
8893 tcg_temp_free_i64(tcg_wideres
);
8896 for (pass
= 0; pass
< 2; pass
++) {
8897 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8898 tcg_temp_free_i32(tcg_res
[pass
]);
8901 clear_vec_high(s
, rd
);
8905 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8907 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8908 * is the only three-reg-diff instruction which produces a
8909 * 128-bit wide result from a single operation. However since
8910 * it's possible to calculate the two halves more or less
8911 * separately we just use two helper calls.
8913 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8914 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8915 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8917 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8918 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8919 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8920 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8921 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8922 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8924 tcg_temp_free_i64(tcg_op1
);
8925 tcg_temp_free_i64(tcg_op2
);
8926 tcg_temp_free_i64(tcg_res
);
8929 /* C3.6.15 AdvSIMD three different
8930 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8931 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8932 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8933 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8935 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8937 /* Instructions in this group fall into three basic classes
8938 * (in each case with the operation working on each element in
8939 * the input vectors):
8940 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8942 * (2) wide 64 x 128 -> 128
8943 * (3) narrowing 128 x 128 -> 64
8944 * Here we do initial decode, catch unallocated cases and
8945 * dispatch to separate functions for each class.
8947 int is_q
= extract32(insn
, 30, 1);
8948 int is_u
= extract32(insn
, 29, 1);
8949 int size
= extract32(insn
, 22, 2);
8950 int opcode
= extract32(insn
, 12, 4);
8951 int rm
= extract32(insn
, 16, 5);
8952 int rn
= extract32(insn
, 5, 5);
8953 int rd
= extract32(insn
, 0, 5);
8956 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8957 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8958 /* 64 x 128 -> 128 */
8960 unallocated_encoding(s
);
8963 if (!fp_access_check(s
)) {
8966 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8968 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8969 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8970 /* 128 x 128 -> 64 */
8972 unallocated_encoding(s
);
8975 if (!fp_access_check(s
)) {
8978 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8980 case 14: /* PMULL, PMULL2 */
8981 if (is_u
|| size
== 1 || size
== 2) {
8982 unallocated_encoding(s
);
8986 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
8987 unallocated_encoding(s
);
8990 if (!fp_access_check(s
)) {
8993 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8997 case 9: /* SQDMLAL, SQDMLAL2 */
8998 case 11: /* SQDMLSL, SQDMLSL2 */
8999 case 13: /* SQDMULL, SQDMULL2 */
9000 if (is_u
|| size
== 0) {
9001 unallocated_encoding(s
);
9005 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
9006 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
9007 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
9008 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
9009 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9010 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9011 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
9012 /* 64 x 64 -> 128 */
9014 unallocated_encoding(s
);
9018 if (!fp_access_check(s
)) {
9022 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9025 /* opcode 15 not allocated */
9026 unallocated_encoding(s
);
9031 /* Logic op (opcode == 3) subgroup of C3.6.16. */
9032 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
9034 int rd
= extract32(insn
, 0, 5);
9035 int rn
= extract32(insn
, 5, 5);
9036 int rm
= extract32(insn
, 16, 5);
9037 int size
= extract32(insn
, 22, 2);
9038 bool is_u
= extract32(insn
, 29, 1);
9039 bool is_q
= extract32(insn
, 30, 1);
9040 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
9043 if (!fp_access_check(s
)) {
9047 tcg_op1
= tcg_temp_new_i64();
9048 tcg_op2
= tcg_temp_new_i64();
9049 tcg_res
[0] = tcg_temp_new_i64();
9050 tcg_res
[1] = tcg_temp_new_i64();
9052 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9053 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9054 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9059 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9062 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9065 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9068 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9073 /* B* ops need res loaded to operate on */
9074 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9079 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9081 case 1: /* BSL bitwise select */
9082 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9083 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9084 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
9086 case 2: /* BIT, bitwise insert if true */
9087 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9088 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9089 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9091 case 3: /* BIF, bitwise insert if false */
9092 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9093 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9094 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9100 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9102 tcg_gen_movi_i64(tcg_res
[1], 0);
9104 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9106 tcg_temp_free_i64(tcg_op1
);
9107 tcg_temp_free_i64(tcg_op2
);
9108 tcg_temp_free_i64(tcg_res
[0]);
9109 tcg_temp_free_i64(tcg_res
[1]);
9112 /* Helper functions for 32 bit comparisons */
9113 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9115 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
9118 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9120 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
9123 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9125 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
9128 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9130 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
9133 /* Pairwise op subgroup of C3.6.16.
9135 * This is called directly or via the handle_3same_float for float pairwise
9136 * operations where the opcode and size are calculated differently.
9138 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
9139 int size
, int rn
, int rm
, int rd
)
9144 /* Floating point operations need fpst */
9145 if (opcode
>= 0x58) {
9146 fpst
= get_fpstatus_ptr();
9148 TCGV_UNUSED_PTR(fpst
);
9151 if (!fp_access_check(s
)) {
9155 /* These operations work on the concatenated rm:rn, with each pair of
9156 * adjacent elements being operated on to produce an element in the result.
9159 TCGv_i64 tcg_res
[2];
9161 for (pass
= 0; pass
< 2; pass
++) {
9162 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9163 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9164 int passreg
= (pass
== 0) ? rn
: rm
;
9166 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
9167 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
9168 tcg_res
[pass
] = tcg_temp_new_i64();
9171 case 0x17: /* ADDP */
9172 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9174 case 0x58: /* FMAXNMP */
9175 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9177 case 0x5a: /* FADDP */
9178 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9180 case 0x5e: /* FMAXP */
9181 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9183 case 0x78: /* FMINNMP */
9184 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9186 case 0x7e: /* FMINP */
9187 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9190 g_assert_not_reached();
9193 tcg_temp_free_i64(tcg_op1
);
9194 tcg_temp_free_i64(tcg_op2
);
9197 for (pass
= 0; pass
< 2; pass
++) {
9198 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9199 tcg_temp_free_i64(tcg_res
[pass
]);
9202 int maxpass
= is_q
? 4 : 2;
9203 TCGv_i32 tcg_res
[4];
9205 for (pass
= 0; pass
< maxpass
; pass
++) {
9206 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9207 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9208 NeonGenTwoOpFn
*genfn
= NULL
;
9209 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
9210 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
9212 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
9213 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
9214 tcg_res
[pass
] = tcg_temp_new_i32();
9217 case 0x17: /* ADDP */
9219 static NeonGenTwoOpFn
* const fns
[3] = {
9220 gen_helper_neon_padd_u8
,
9221 gen_helper_neon_padd_u16
,
9227 case 0x14: /* SMAXP, UMAXP */
9229 static NeonGenTwoOpFn
* const fns
[3][2] = {
9230 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
9231 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
9232 { gen_max_s32
, gen_max_u32
},
9234 genfn
= fns
[size
][u
];
9237 case 0x15: /* SMINP, UMINP */
9239 static NeonGenTwoOpFn
* const fns
[3][2] = {
9240 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
9241 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
9242 { gen_min_s32
, gen_min_u32
},
9244 genfn
= fns
[size
][u
];
9247 /* The FP operations are all on single floats (32 bit) */
9248 case 0x58: /* FMAXNMP */
9249 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9251 case 0x5a: /* FADDP */
9252 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9254 case 0x5e: /* FMAXP */
9255 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9257 case 0x78: /* FMINNMP */
9258 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9260 case 0x7e: /* FMINP */
9261 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9264 g_assert_not_reached();
9267 /* FP ops called directly, otherwise call now */
9269 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9272 tcg_temp_free_i32(tcg_op1
);
9273 tcg_temp_free_i32(tcg_op2
);
9276 for (pass
= 0; pass
< maxpass
; pass
++) {
9277 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9278 tcg_temp_free_i32(tcg_res
[pass
]);
9281 clear_vec_high(s
, rd
);
9285 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
9286 tcg_temp_free_ptr(fpst
);
9290 /* Floating point op subgroup of C3.6.16. */
9291 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
9293 /* For floating point ops, the U, size[1] and opcode bits
9294 * together indicate the operation. size[0] indicates single
9297 int fpopcode
= extract32(insn
, 11, 5)
9298 | (extract32(insn
, 23, 1) << 5)
9299 | (extract32(insn
, 29, 1) << 6);
9300 int is_q
= extract32(insn
, 30, 1);
9301 int size
= extract32(insn
, 22, 1);
9302 int rm
= extract32(insn
, 16, 5);
9303 int rn
= extract32(insn
, 5, 5);
9304 int rd
= extract32(insn
, 0, 5);
9306 int datasize
= is_q
? 128 : 64;
9307 int esize
= 32 << size
;
9308 int elements
= datasize
/ esize
;
9310 if (size
== 1 && !is_q
) {
9311 unallocated_encoding(s
);
9316 case 0x58: /* FMAXNMP */
9317 case 0x5a: /* FADDP */
9318 case 0x5e: /* FMAXP */
9319 case 0x78: /* FMINNMP */
9320 case 0x7e: /* FMINP */
9321 if (size
&& !is_q
) {
9322 unallocated_encoding(s
);
9325 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9328 case 0x1b: /* FMULX */
9329 case 0x1f: /* FRECPS */
9330 case 0x3f: /* FRSQRTS */
9331 case 0x5d: /* FACGE */
9332 case 0x7d: /* FACGT */
9333 case 0x19: /* FMLA */
9334 case 0x39: /* FMLS */
9335 case 0x18: /* FMAXNM */
9336 case 0x1a: /* FADD */
9337 case 0x1c: /* FCMEQ */
9338 case 0x1e: /* FMAX */
9339 case 0x38: /* FMINNM */
9340 case 0x3a: /* FSUB */
9341 case 0x3e: /* FMIN */
9342 case 0x5b: /* FMUL */
9343 case 0x5c: /* FCMGE */
9344 case 0x5f: /* FDIV */
9345 case 0x7a: /* FABD */
9346 case 0x7c: /* FCMGT */
9347 if (!fp_access_check(s
)) {
9351 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9354 unallocated_encoding(s
);
9359 /* Integer op subgroup of C3.6.16. */
9360 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9362 int is_q
= extract32(insn
, 30, 1);
9363 int u
= extract32(insn
, 29, 1);
9364 int size
= extract32(insn
, 22, 2);
9365 int opcode
= extract32(insn
, 11, 5);
9366 int rm
= extract32(insn
, 16, 5);
9367 int rn
= extract32(insn
, 5, 5);
9368 int rd
= extract32(insn
, 0, 5);
9372 case 0x13: /* MUL, PMUL */
9373 if (u
&& size
!= 0) {
9374 unallocated_encoding(s
);
9378 case 0x0: /* SHADD, UHADD */
9379 case 0x2: /* SRHADD, URHADD */
9380 case 0x4: /* SHSUB, UHSUB */
9381 case 0xc: /* SMAX, UMAX */
9382 case 0xd: /* SMIN, UMIN */
9383 case 0xe: /* SABD, UABD */
9384 case 0xf: /* SABA, UABA */
9385 case 0x12: /* MLA, MLS */
9387 unallocated_encoding(s
);
9391 case 0x16: /* SQDMULH, SQRDMULH */
9392 if (size
== 0 || size
== 3) {
9393 unallocated_encoding(s
);
9398 if (size
== 3 && !is_q
) {
9399 unallocated_encoding(s
);
9405 if (!fp_access_check(s
)) {
9411 for (pass
= 0; pass
< 2; pass
++) {
9412 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9413 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9414 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9416 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9417 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9419 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9421 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9423 tcg_temp_free_i64(tcg_res
);
9424 tcg_temp_free_i64(tcg_op1
);
9425 tcg_temp_free_i64(tcg_op2
);
9428 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9429 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9430 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9431 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9432 NeonGenTwoOpFn
*genfn
= NULL
;
9433 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9435 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9436 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9439 case 0x0: /* SHADD, UHADD */
9441 static NeonGenTwoOpFn
* const fns
[3][2] = {
9442 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9443 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9444 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9446 genfn
= fns
[size
][u
];
9449 case 0x1: /* SQADD, UQADD */
9451 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9452 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9453 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9454 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9456 genenvfn
= fns
[size
][u
];
9459 case 0x2: /* SRHADD, URHADD */
9461 static NeonGenTwoOpFn
* const fns
[3][2] = {
9462 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9463 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9464 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9466 genfn
= fns
[size
][u
];
9469 case 0x4: /* SHSUB, UHSUB */
9471 static NeonGenTwoOpFn
* const fns
[3][2] = {
9472 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9473 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9474 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9476 genfn
= fns
[size
][u
];
9479 case 0x5: /* SQSUB, UQSUB */
9481 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9482 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9483 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9484 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9486 genenvfn
= fns
[size
][u
];
9489 case 0x6: /* CMGT, CMHI */
9491 static NeonGenTwoOpFn
* const fns
[3][2] = {
9492 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9493 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9494 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9496 genfn
= fns
[size
][u
];
9499 case 0x7: /* CMGE, CMHS */
9501 static NeonGenTwoOpFn
* const fns
[3][2] = {
9502 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9503 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9504 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9506 genfn
= fns
[size
][u
];
9509 case 0x8: /* SSHL, USHL */
9511 static NeonGenTwoOpFn
* const fns
[3][2] = {
9512 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9513 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9514 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9516 genfn
= fns
[size
][u
];
9519 case 0x9: /* SQSHL, UQSHL */
9521 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9522 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9523 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9524 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9526 genenvfn
= fns
[size
][u
];
9529 case 0xa: /* SRSHL, URSHL */
9531 static NeonGenTwoOpFn
* const fns
[3][2] = {
9532 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9533 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9534 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9536 genfn
= fns
[size
][u
];
9539 case 0xb: /* SQRSHL, UQRSHL */
9541 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9542 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9543 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9544 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9546 genenvfn
= fns
[size
][u
];
9549 case 0xc: /* SMAX, UMAX */
9551 static NeonGenTwoOpFn
* const fns
[3][2] = {
9552 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9553 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9554 { gen_max_s32
, gen_max_u32
},
9556 genfn
= fns
[size
][u
];
9560 case 0xd: /* SMIN, UMIN */
9562 static NeonGenTwoOpFn
* const fns
[3][2] = {
9563 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9564 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9565 { gen_min_s32
, gen_min_u32
},
9567 genfn
= fns
[size
][u
];
9570 case 0xe: /* SABD, UABD */
9571 case 0xf: /* SABA, UABA */
9573 static NeonGenTwoOpFn
* const fns
[3][2] = {
9574 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9575 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9576 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9578 genfn
= fns
[size
][u
];
9581 case 0x10: /* ADD, SUB */
9583 static NeonGenTwoOpFn
* const fns
[3][2] = {
9584 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9585 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9586 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9588 genfn
= fns
[size
][u
];
9591 case 0x11: /* CMTST, CMEQ */
9593 static NeonGenTwoOpFn
* const fns
[3][2] = {
9594 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9595 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9596 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9598 genfn
= fns
[size
][u
];
9601 case 0x13: /* MUL, PMUL */
9605 genfn
= gen_helper_neon_mul_p8
;
9608 /* fall through : MUL */
9609 case 0x12: /* MLA, MLS */
9611 static NeonGenTwoOpFn
* const fns
[3] = {
9612 gen_helper_neon_mul_u8
,
9613 gen_helper_neon_mul_u16
,
9619 case 0x16: /* SQDMULH, SQRDMULH */
9621 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9622 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9623 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9625 assert(size
== 1 || size
== 2);
9626 genenvfn
= fns
[size
- 1][u
];
9630 g_assert_not_reached();
9634 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9636 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9639 if (opcode
== 0xf || opcode
== 0x12) {
9640 /* SABA, UABA, MLA, MLS: accumulating ops */
9641 static NeonGenTwoOpFn
* const fns
[3][2] = {
9642 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9643 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9644 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9646 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9648 genfn
= fns
[size
][is_sub
];
9649 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9650 genfn(tcg_res
, tcg_op1
, tcg_res
);
9653 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9655 tcg_temp_free_i32(tcg_res
);
9656 tcg_temp_free_i32(tcg_op1
);
9657 tcg_temp_free_i32(tcg_op2
);
9662 clear_vec_high(s
, rd
);
9666 /* C3.6.16 AdvSIMD three same
9667 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9668 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9669 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9670 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9672 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9674 int opcode
= extract32(insn
, 11, 5);
9677 case 0x3: /* logic ops */
9678 disas_simd_3same_logic(s
, insn
);
9680 case 0x17: /* ADDP */
9681 case 0x14: /* SMAXP, UMAXP */
9682 case 0x15: /* SMINP, UMINP */
9684 /* Pairwise operations */
9685 int is_q
= extract32(insn
, 30, 1);
9686 int u
= extract32(insn
, 29, 1);
9687 int size
= extract32(insn
, 22, 2);
9688 int rm
= extract32(insn
, 16, 5);
9689 int rn
= extract32(insn
, 5, 5);
9690 int rd
= extract32(insn
, 0, 5);
9691 if (opcode
== 0x17) {
9692 if (u
|| (size
== 3 && !is_q
)) {
9693 unallocated_encoding(s
);
9698 unallocated_encoding(s
);
9702 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9706 /* floating point ops, sz[1] and U are part of opcode */
9707 disas_simd_3same_float(s
, insn
);
9710 disas_simd_3same_int(s
, insn
);
9715 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9716 int size
, int rn
, int rd
)
9718 /* Handle 2-reg-misc ops which are widening (so each size element
9719 * in the source becomes a 2*size element in the destination.
9720 * The only instruction like this is FCVTL.
9725 /* 32 -> 64 bit fp conversion */
9726 TCGv_i64 tcg_res
[2];
9727 int srcelt
= is_q
? 2 : 0;
9729 for (pass
= 0; pass
< 2; pass
++) {
9730 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9731 tcg_res
[pass
] = tcg_temp_new_i64();
9733 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9734 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9735 tcg_temp_free_i32(tcg_op
);
9737 for (pass
= 0; pass
< 2; pass
++) {
9738 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9739 tcg_temp_free_i64(tcg_res
[pass
]);
9742 /* 16 -> 32 bit fp conversion */
9743 int srcelt
= is_q
? 4 : 0;
9744 TCGv_i32 tcg_res
[4];
9746 for (pass
= 0; pass
< 4; pass
++) {
9747 tcg_res
[pass
] = tcg_temp_new_i32();
9749 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9750 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9753 for (pass
= 0; pass
< 4; pass
++) {
9754 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9755 tcg_temp_free_i32(tcg_res
[pass
]);
9760 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9761 bool is_q
, int size
, int rn
, int rd
)
9763 int op
= (opcode
<< 1) | u
;
9764 int opsz
= op
+ size
;
9765 int grp_size
= 3 - opsz
;
9766 int dsize
= is_q
? 128 : 64;
9770 unallocated_encoding(s
);
9774 if (!fp_access_check(s
)) {
9779 /* Special case bytes, use bswap op on each group of elements */
9780 int groups
= dsize
/ (8 << grp_size
);
9782 for (i
= 0; i
< groups
; i
++) {
9783 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9785 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9788 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9791 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9794 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9797 g_assert_not_reached();
9799 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9800 tcg_temp_free_i64(tcg_tmp
);
9803 clear_vec_high(s
, rd
);
9806 int revmask
= (1 << grp_size
) - 1;
9807 int esize
= 8 << size
;
9808 int elements
= dsize
/ esize
;
9809 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9810 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9811 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9813 for (i
= 0; i
< elements
; i
++) {
9814 int e_rev
= (i
& 0xf) ^ revmask
;
9815 int off
= e_rev
* esize
;
9816 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9818 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9819 tcg_rn
, off
- 64, esize
);
9821 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9824 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9825 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9827 tcg_temp_free_i64(tcg_rd_hi
);
9828 tcg_temp_free_i64(tcg_rd
);
9829 tcg_temp_free_i64(tcg_rn
);
9833 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9834 bool is_q
, int size
, int rn
, int rd
)
9836 /* Implement the pairwise operations from 2-misc:
9837 * SADDLP, UADDLP, SADALP, UADALP.
9838 * These all add pairs of elements in the input to produce a
9839 * double-width result element in the output (possibly accumulating).
9841 bool accum
= (opcode
== 0x6);
9842 int maxpass
= is_q
? 2 : 1;
9844 TCGv_i64 tcg_res
[2];
9847 /* 32 + 32 -> 64 op */
9848 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9850 for (pass
= 0; pass
< maxpass
; pass
++) {
9851 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9852 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9854 tcg_res
[pass
] = tcg_temp_new_i64();
9856 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9857 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9858 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9860 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9861 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9864 tcg_temp_free_i64(tcg_op1
);
9865 tcg_temp_free_i64(tcg_op2
);
9868 for (pass
= 0; pass
< maxpass
; pass
++) {
9869 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9870 NeonGenOneOpFn
*genfn
;
9871 static NeonGenOneOpFn
* const fns
[2][2] = {
9872 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9873 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9876 genfn
= fns
[size
][u
];
9878 tcg_res
[pass
] = tcg_temp_new_i64();
9880 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9881 genfn(tcg_res
[pass
], tcg_op
);
9884 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9886 gen_helper_neon_addl_u16(tcg_res
[pass
],
9887 tcg_res
[pass
], tcg_op
);
9889 gen_helper_neon_addl_u32(tcg_res
[pass
],
9890 tcg_res
[pass
], tcg_op
);
9893 tcg_temp_free_i64(tcg_op
);
9897 tcg_res
[1] = tcg_const_i64(0);
9899 for (pass
= 0; pass
< 2; pass
++) {
9900 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9901 tcg_temp_free_i64(tcg_res
[pass
]);
9905 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9907 /* Implement SHLL and SHLL2 */
9909 int part
= is_q
? 2 : 0;
9910 TCGv_i64 tcg_res
[2];
9912 for (pass
= 0; pass
< 2; pass
++) {
9913 static NeonGenWidenFn
* const widenfns
[3] = {
9914 gen_helper_neon_widen_u8
,
9915 gen_helper_neon_widen_u16
,
9916 tcg_gen_extu_i32_i64
,
9918 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9919 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9921 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9922 tcg_res
[pass
] = tcg_temp_new_i64();
9923 widenfn(tcg_res
[pass
], tcg_op
);
9924 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9926 tcg_temp_free_i32(tcg_op
);
9929 for (pass
= 0; pass
< 2; pass
++) {
9930 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9931 tcg_temp_free_i64(tcg_res
[pass
]);
9935 /* C3.6.17 AdvSIMD two reg misc
9936 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9937 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9938 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9939 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9941 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9943 int size
= extract32(insn
, 22, 2);
9944 int opcode
= extract32(insn
, 12, 5);
9945 bool u
= extract32(insn
, 29, 1);
9946 bool is_q
= extract32(insn
, 30, 1);
9947 int rn
= extract32(insn
, 5, 5);
9948 int rd
= extract32(insn
, 0, 5);
9949 bool need_fpstatus
= false;
9950 bool need_rmode
= false;
9953 TCGv_ptr tcg_fpstatus
;
9956 case 0x0: /* REV64, REV32 */
9957 case 0x1: /* REV16 */
9958 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9960 case 0x5: /* CNT, NOT, RBIT */
9961 if (u
&& size
== 0) {
9962 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9965 } else if (u
&& size
== 1) {
9968 } else if (!u
&& size
== 0) {
9972 unallocated_encoding(s
);
9974 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9975 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9977 unallocated_encoding(s
);
9980 if (!fp_access_check(s
)) {
9984 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9986 case 0x4: /* CLS, CLZ */
9988 unallocated_encoding(s
);
9992 case 0x2: /* SADDLP, UADDLP */
9993 case 0x6: /* SADALP, UADALP */
9995 unallocated_encoding(s
);
9998 if (!fp_access_check(s
)) {
10001 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
10003 case 0x13: /* SHLL, SHLL2 */
10004 if (u
== 0 || size
== 3) {
10005 unallocated_encoding(s
);
10008 if (!fp_access_check(s
)) {
10011 handle_shll(s
, is_q
, size
, rn
, rd
);
10013 case 0xa: /* CMLT */
10015 unallocated_encoding(s
);
10019 case 0x8: /* CMGT, CMGE */
10020 case 0x9: /* CMEQ, CMLE */
10021 case 0xb: /* ABS, NEG */
10022 if (size
== 3 && !is_q
) {
10023 unallocated_encoding(s
);
10027 case 0x3: /* SUQADD, USQADD */
10028 if (size
== 3 && !is_q
) {
10029 unallocated_encoding(s
);
10032 if (!fp_access_check(s
)) {
10035 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
10037 case 0x7: /* SQABS, SQNEG */
10038 if (size
== 3 && !is_q
) {
10039 unallocated_encoding(s
);
10044 case 0x16 ... 0x1d:
10047 /* Floating point: U, size[1] and opcode indicate operation;
10048 * size[0] indicates single or double precision.
10050 int is_double
= extract32(size
, 0, 1);
10051 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10052 size
= is_double
? 3 : 2;
10054 case 0x2f: /* FABS */
10055 case 0x6f: /* FNEG */
10056 if (size
== 3 && !is_q
) {
10057 unallocated_encoding(s
);
10061 case 0x1d: /* SCVTF */
10062 case 0x5d: /* UCVTF */
10064 bool is_signed
= (opcode
== 0x1d) ? true : false;
10065 int elements
= is_double
? 2 : is_q
? 4 : 2;
10066 if (is_double
&& !is_q
) {
10067 unallocated_encoding(s
);
10070 if (!fp_access_check(s
)) {
10073 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
10076 case 0x2c: /* FCMGT (zero) */
10077 case 0x2d: /* FCMEQ (zero) */
10078 case 0x2e: /* FCMLT (zero) */
10079 case 0x6c: /* FCMGE (zero) */
10080 case 0x6d: /* FCMLE (zero) */
10081 if (size
== 3 && !is_q
) {
10082 unallocated_encoding(s
);
10085 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10087 case 0x7f: /* FSQRT */
10088 if (size
== 3 && !is_q
) {
10089 unallocated_encoding(s
);
10093 case 0x1a: /* FCVTNS */
10094 case 0x1b: /* FCVTMS */
10095 case 0x3a: /* FCVTPS */
10096 case 0x3b: /* FCVTZS */
10097 case 0x5a: /* FCVTNU */
10098 case 0x5b: /* FCVTMU */
10099 case 0x7a: /* FCVTPU */
10100 case 0x7b: /* FCVTZU */
10101 need_fpstatus
= true;
10103 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10104 if (size
== 3 && !is_q
) {
10105 unallocated_encoding(s
);
10109 case 0x5c: /* FCVTAU */
10110 case 0x1c: /* FCVTAS */
10111 need_fpstatus
= true;
10113 rmode
= FPROUNDING_TIEAWAY
;
10114 if (size
== 3 && !is_q
) {
10115 unallocated_encoding(s
);
10119 case 0x3c: /* URECPE */
10121 unallocated_encoding(s
);
10125 case 0x3d: /* FRECPE */
10126 case 0x7d: /* FRSQRTE */
10127 if (size
== 3 && !is_q
) {
10128 unallocated_encoding(s
);
10131 if (!fp_access_check(s
)) {
10134 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10136 case 0x56: /* FCVTXN, FCVTXN2 */
10138 unallocated_encoding(s
);
10142 case 0x16: /* FCVTN, FCVTN2 */
10143 /* handle_2misc_narrow does a 2*size -> size operation, but these
10144 * instructions encode the source size rather than dest size.
10146 if (!fp_access_check(s
)) {
10149 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
10151 case 0x17: /* FCVTL, FCVTL2 */
10152 if (!fp_access_check(s
)) {
10155 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
10157 case 0x18: /* FRINTN */
10158 case 0x19: /* FRINTM */
10159 case 0x38: /* FRINTP */
10160 case 0x39: /* FRINTZ */
10162 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10164 case 0x59: /* FRINTX */
10165 case 0x79: /* FRINTI */
10166 need_fpstatus
= true;
10167 if (size
== 3 && !is_q
) {
10168 unallocated_encoding(s
);
10172 case 0x58: /* FRINTA */
10174 rmode
= FPROUNDING_TIEAWAY
;
10175 need_fpstatus
= true;
10176 if (size
== 3 && !is_q
) {
10177 unallocated_encoding(s
);
10181 case 0x7c: /* URSQRTE */
10183 unallocated_encoding(s
);
10186 need_fpstatus
= true;
10189 unallocated_encoding(s
);
10195 unallocated_encoding(s
);
10199 if (!fp_access_check(s
)) {
10203 if (need_fpstatus
) {
10204 tcg_fpstatus
= get_fpstatus_ptr();
10206 TCGV_UNUSED_PTR(tcg_fpstatus
);
10209 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10210 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10212 TCGV_UNUSED_I32(tcg_rmode
);
10216 /* All 64-bit element operations can be shared with scalar 2misc */
10219 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
10220 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10221 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10223 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10225 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
10226 tcg_rmode
, tcg_fpstatus
);
10228 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10230 tcg_temp_free_i64(tcg_res
);
10231 tcg_temp_free_i64(tcg_op
);
10236 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10237 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10238 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10241 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10244 /* Special cases for 32 bit elements */
10246 case 0xa: /* CMLT */
10247 /* 32 bit integer comparison against zero, result is
10248 * test ? (2^32 - 1) : 0. We implement via setcond(test)
10251 cond
= TCG_COND_LT
;
10253 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
10254 tcg_gen_neg_i32(tcg_res
, tcg_res
);
10256 case 0x8: /* CMGT, CMGE */
10257 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
10259 case 0x9: /* CMEQ, CMLE */
10260 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
10262 case 0x4: /* CLS */
10264 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
10266 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
10269 case 0x7: /* SQABS, SQNEG */
10271 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
10273 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
10276 case 0xb: /* ABS, NEG */
10278 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10280 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10281 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10282 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
10283 tcg_zero
, tcg_op
, tcg_res
);
10284 tcg_temp_free_i32(tcg_zero
);
10287 case 0x2f: /* FABS */
10288 gen_helper_vfp_abss(tcg_res
, tcg_op
);
10290 case 0x6f: /* FNEG */
10291 gen_helper_vfp_negs(tcg_res
, tcg_op
);
10293 case 0x7f: /* FSQRT */
10294 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
10296 case 0x1a: /* FCVTNS */
10297 case 0x1b: /* FCVTMS */
10298 case 0x1c: /* FCVTAS */
10299 case 0x3a: /* FCVTPS */
10300 case 0x3b: /* FCVTZS */
10302 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10303 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
10304 tcg_shift
, tcg_fpstatus
);
10305 tcg_temp_free_i32(tcg_shift
);
10308 case 0x5a: /* FCVTNU */
10309 case 0x5b: /* FCVTMU */
10310 case 0x5c: /* FCVTAU */
10311 case 0x7a: /* FCVTPU */
10312 case 0x7b: /* FCVTZU */
10314 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10315 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10316 tcg_shift
, tcg_fpstatus
);
10317 tcg_temp_free_i32(tcg_shift
);
10320 case 0x18: /* FRINTN */
10321 case 0x19: /* FRINTM */
10322 case 0x38: /* FRINTP */
10323 case 0x39: /* FRINTZ */
10324 case 0x58: /* FRINTA */
10325 case 0x79: /* FRINTI */
10326 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10328 case 0x59: /* FRINTX */
10329 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10331 case 0x7c: /* URSQRTE */
10332 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10335 g_assert_not_reached();
10338 /* Use helpers for 8 and 16 bit elements */
10340 case 0x5: /* CNT, RBIT */
10341 /* For these two insns size is part of the opcode specifier
10342 * (handled earlier); they always operate on byte elements.
10345 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10347 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10350 case 0x7: /* SQABS, SQNEG */
10352 NeonGenOneOpEnvFn
*genfn
;
10353 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10354 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10355 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10357 genfn
= fns
[size
][u
];
10358 genfn(tcg_res
, cpu_env
, tcg_op
);
10361 case 0x8: /* CMGT, CMGE */
10362 case 0x9: /* CMEQ, CMLE */
10363 case 0xa: /* CMLT */
10365 static NeonGenTwoOpFn
* const fns
[3][2] = {
10366 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10367 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10368 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10370 NeonGenTwoOpFn
*genfn
;
10373 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10375 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10376 comp
= (opcode
- 0x8) * 2 + u
;
10377 /* ...but LE, LT are implemented as reverse GE, GT */
10378 reverse
= (comp
> 2);
10382 genfn
= fns
[comp
][size
];
10384 genfn(tcg_res
, tcg_zero
, tcg_op
);
10386 genfn(tcg_res
, tcg_op
, tcg_zero
);
10388 tcg_temp_free_i32(tcg_zero
);
10391 case 0xb: /* ABS, NEG */
10393 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10395 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10397 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10399 tcg_temp_free_i32(tcg_zero
);
10402 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10404 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10408 case 0x4: /* CLS, CLZ */
10411 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10413 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10417 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10419 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10424 g_assert_not_reached();
10428 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10430 tcg_temp_free_i32(tcg_res
);
10431 tcg_temp_free_i32(tcg_op
);
10435 clear_vec_high(s
, rd
);
10439 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10440 tcg_temp_free_i32(tcg_rmode
);
10442 if (need_fpstatus
) {
10443 tcg_temp_free_ptr(tcg_fpstatus
);
10447 /* C3.6.13 AdvSIMD scalar x indexed element
10448 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10449 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10450 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10451 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10452 * C3.6.18 AdvSIMD vector x indexed element
10453 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10454 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10455 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10456 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10458 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10460 /* This encoding has two kinds of instruction:
10461 * normal, where we perform elt x idxelt => elt for each
10462 * element in the vector
10463 * long, where we perform elt x idxelt and generate a result of
10464 * double the width of the input element
10465 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10467 bool is_scalar
= extract32(insn
, 28, 1);
10468 bool is_q
= extract32(insn
, 30, 1);
10469 bool u
= extract32(insn
, 29, 1);
10470 int size
= extract32(insn
, 22, 2);
10471 int l
= extract32(insn
, 21, 1);
10472 int m
= extract32(insn
, 20, 1);
10473 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10474 int rm
= extract32(insn
, 16, 4);
10475 int opcode
= extract32(insn
, 12, 4);
10476 int h
= extract32(insn
, 11, 1);
10477 int rn
= extract32(insn
, 5, 5);
10478 int rd
= extract32(insn
, 0, 5);
10479 bool is_long
= false;
10480 bool is_fp
= false;
10485 case 0x0: /* MLA */
10486 case 0x4: /* MLS */
10487 if (!u
|| is_scalar
) {
10488 unallocated_encoding(s
);
10492 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10493 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10494 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10496 unallocated_encoding(s
);
10501 case 0x3: /* SQDMLAL, SQDMLAL2 */
10502 case 0x7: /* SQDMLSL, SQDMLSL2 */
10503 case 0xb: /* SQDMULL, SQDMULL2 */
10506 case 0xc: /* SQDMULH */
10507 case 0xd: /* SQRDMULH */
10509 unallocated_encoding(s
);
10513 case 0x8: /* MUL */
10514 if (u
|| is_scalar
) {
10515 unallocated_encoding(s
);
10519 case 0x1: /* FMLA */
10520 case 0x5: /* FMLS */
10522 unallocated_encoding(s
);
10526 case 0x9: /* FMUL, FMULX */
10527 if (!extract32(size
, 1, 1)) {
10528 unallocated_encoding(s
);
10534 unallocated_encoding(s
);
10539 /* low bit of size indicates single/double */
10540 size
= extract32(size
, 0, 1) ? 3 : 2;
10542 index
= h
<< 1 | l
;
10545 unallocated_encoding(s
);
10554 index
= h
<< 2 | l
<< 1 | m
;
10557 index
= h
<< 1 | l
;
10561 unallocated_encoding(s
);
10566 if (!fp_access_check(s
)) {
10571 fpst
= get_fpstatus_ptr();
10573 TCGV_UNUSED_PTR(fpst
);
10577 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10580 assert(is_fp
&& is_q
&& !is_long
);
10582 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10584 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10585 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10586 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10588 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10591 case 0x5: /* FMLS */
10592 /* As usual for ARM, separate negation for fused multiply-add */
10593 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10595 case 0x1: /* FMLA */
10596 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10597 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10599 case 0x9: /* FMUL, FMULX */
10601 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10603 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10607 g_assert_not_reached();
10610 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10611 tcg_temp_free_i64(tcg_op
);
10612 tcg_temp_free_i64(tcg_res
);
10616 clear_vec_high(s
, rd
);
10619 tcg_temp_free_i64(tcg_idx
);
10620 } else if (!is_long
) {
10621 /* 32 bit floating point, or 16 or 32 bit integer.
10622 * For the 16 bit scalar case we use the usual Neon helpers and
10623 * rely on the fact that 0 op 0 == 0 with no side effects.
10625 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10626 int pass
, maxpasses
;
10631 maxpasses
= is_q
? 4 : 2;
10634 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10636 if (size
== 1 && !is_scalar
) {
10637 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10638 * the index into both halves of the 32 bit tcg_idx and then use
10639 * the usual Neon helpers.
10641 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10644 for (pass
= 0; pass
< maxpasses
; pass
++) {
10645 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10646 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10648 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10651 case 0x0: /* MLA */
10652 case 0x4: /* MLS */
10653 case 0x8: /* MUL */
10655 static NeonGenTwoOpFn
* const fns
[2][2] = {
10656 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10657 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10659 NeonGenTwoOpFn
*genfn
;
10660 bool is_sub
= opcode
== 0x4;
10663 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10665 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10667 if (opcode
== 0x8) {
10670 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10671 genfn
= fns
[size
- 1][is_sub
];
10672 genfn(tcg_res
, tcg_op
, tcg_res
);
10675 case 0x5: /* FMLS */
10676 /* As usual for ARM, separate negation for fused multiply-add */
10677 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10679 case 0x1: /* FMLA */
10680 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10681 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10683 case 0x9: /* FMUL, FMULX */
10685 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10687 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10690 case 0xc: /* SQDMULH */
10692 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10695 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10699 case 0xd: /* SQRDMULH */
10701 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10704 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10709 g_assert_not_reached();
10713 write_fp_sreg(s
, rd
, tcg_res
);
10715 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10718 tcg_temp_free_i32(tcg_op
);
10719 tcg_temp_free_i32(tcg_res
);
10722 tcg_temp_free_i32(tcg_idx
);
10725 clear_vec_high(s
, rd
);
10728 /* long ops: 16x16->32 or 32x32->64 */
10729 TCGv_i64 tcg_res
[2];
10731 bool satop
= extract32(opcode
, 0, 1);
10732 TCGMemOp memop
= MO_32
;
10739 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10741 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10743 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10744 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10745 TCGv_i64 tcg_passres
;
10751 passelt
= pass
+ (is_q
* 2);
10754 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10756 tcg_res
[pass
] = tcg_temp_new_i64();
10758 if (opcode
== 0xa || opcode
== 0xb) {
10759 /* Non-accumulating ops */
10760 tcg_passres
= tcg_res
[pass
];
10762 tcg_passres
= tcg_temp_new_i64();
10765 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10766 tcg_temp_free_i64(tcg_op
);
10769 /* saturating, doubling */
10770 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10771 tcg_passres
, tcg_passres
);
10774 if (opcode
== 0xa || opcode
== 0xb) {
10778 /* Accumulating op: handle accumulate step */
10779 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10782 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10783 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10785 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10786 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10788 case 0x7: /* SQDMLSL, SQDMLSL2 */
10789 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10791 case 0x3: /* SQDMLAL, SQDMLAL2 */
10792 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10797 g_assert_not_reached();
10799 tcg_temp_free_i64(tcg_passres
);
10801 tcg_temp_free_i64(tcg_idx
);
10804 clear_vec_high(s
, rd
);
10807 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10810 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10813 /* The simplest way to handle the 16x16 indexed ops is to
10814 * duplicate the index into both halves of the 32 bit tcg_idx
10815 * and then use the usual Neon helpers.
10817 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10820 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10821 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10822 TCGv_i64 tcg_passres
;
10825 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10827 read_vec_element_i32(s
, tcg_op
, rn
,
10828 pass
+ (is_q
* 2), MO_32
);
10831 tcg_res
[pass
] = tcg_temp_new_i64();
10833 if (opcode
== 0xa || opcode
== 0xb) {
10834 /* Non-accumulating ops */
10835 tcg_passres
= tcg_res
[pass
];
10837 tcg_passres
= tcg_temp_new_i64();
10840 if (memop
& MO_SIGN
) {
10841 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10843 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10846 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10847 tcg_passres
, tcg_passres
);
10849 tcg_temp_free_i32(tcg_op
);
10851 if (opcode
== 0xa || opcode
== 0xb) {
10855 /* Accumulating op: handle accumulate step */
10856 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10859 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10860 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10863 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10864 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10867 case 0x7: /* SQDMLSL, SQDMLSL2 */
10868 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10870 case 0x3: /* SQDMLAL, SQDMLAL2 */
10871 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10876 g_assert_not_reached();
10878 tcg_temp_free_i64(tcg_passres
);
10880 tcg_temp_free_i32(tcg_idx
);
10883 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10888 tcg_res
[1] = tcg_const_i64(0);
10891 for (pass
= 0; pass
< 2; pass
++) {
10892 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10893 tcg_temp_free_i64(tcg_res
[pass
]);
10897 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10898 tcg_temp_free_ptr(fpst
);
10902 /* C3.6.19 Crypto AES
10903 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10904 * +-----------------+------+-----------+--------+-----+------+------+
10905 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10906 * +-----------------+------+-----------+--------+-----+------+------+
10908 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10910 int size
= extract32(insn
, 22, 2);
10911 int opcode
= extract32(insn
, 12, 5);
10912 int rn
= extract32(insn
, 5, 5);
10913 int rd
= extract32(insn
, 0, 5);
10915 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10916 CryptoThreeOpEnvFn
*genfn
;
10918 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10920 unallocated_encoding(s
);
10925 case 0x4: /* AESE */
10927 genfn
= gen_helper_crypto_aese
;
10929 case 0x6: /* AESMC */
10931 genfn
= gen_helper_crypto_aesmc
;
10933 case 0x5: /* AESD */
10935 genfn
= gen_helper_crypto_aese
;
10937 case 0x7: /* AESIMC */
10939 genfn
= gen_helper_crypto_aesmc
;
10942 unallocated_encoding(s
);
10946 /* Note that we convert the Vx register indexes into the
10947 * index within the vfp.regs[] array, so we can share the
10948 * helper with the AArch32 instructions.
10950 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10951 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10952 tcg_decrypt
= tcg_const_i32(decrypt
);
10954 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10956 tcg_temp_free_i32(tcg_rd_regno
);
10957 tcg_temp_free_i32(tcg_rn_regno
);
10958 tcg_temp_free_i32(tcg_decrypt
);
10961 /* C3.6.20 Crypto three-reg SHA
10962 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10963 * +-----------------+------+---+------+---+--------+-----+------+------+
10964 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10965 * +-----------------+------+---+------+---+--------+-----+------+------+
10967 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10969 int size
= extract32(insn
, 22, 2);
10970 int opcode
= extract32(insn
, 12, 3);
10971 int rm
= extract32(insn
, 16, 5);
10972 int rn
= extract32(insn
, 5, 5);
10973 int rd
= extract32(insn
, 0, 5);
10974 CryptoThreeOpEnvFn
*genfn
;
10975 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
10976 int feature
= ARM_FEATURE_V8_SHA256
;
10979 unallocated_encoding(s
);
10984 case 0: /* SHA1C */
10985 case 1: /* SHA1P */
10986 case 2: /* SHA1M */
10987 case 3: /* SHA1SU0 */
10989 feature
= ARM_FEATURE_V8_SHA1
;
10991 case 4: /* SHA256H */
10992 genfn
= gen_helper_crypto_sha256h
;
10994 case 5: /* SHA256H2 */
10995 genfn
= gen_helper_crypto_sha256h2
;
10997 case 6: /* SHA256SU1 */
10998 genfn
= gen_helper_crypto_sha256su1
;
11001 unallocated_encoding(s
);
11005 if (!arm_dc_feature(s
, feature
)) {
11006 unallocated_encoding(s
);
11010 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11011 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11012 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
11015 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
11017 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
11019 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
11020 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
11021 tcg_temp_free_i32(tcg_opcode
);
11024 tcg_temp_free_i32(tcg_rd_regno
);
11025 tcg_temp_free_i32(tcg_rn_regno
);
11026 tcg_temp_free_i32(tcg_rm_regno
);
11029 /* C3.6.21 Crypto two-reg SHA
11030 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
11031 * +-----------------+------+-----------+--------+-----+------+------+
11032 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
11033 * +-----------------+------+-----------+--------+-----+------+------+
11035 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
11037 int size
= extract32(insn
, 22, 2);
11038 int opcode
= extract32(insn
, 12, 5);
11039 int rn
= extract32(insn
, 5, 5);
11040 int rd
= extract32(insn
, 0, 5);
11041 CryptoTwoOpEnvFn
*genfn
;
11043 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
11046 unallocated_encoding(s
);
11051 case 0: /* SHA1H */
11052 feature
= ARM_FEATURE_V8_SHA1
;
11053 genfn
= gen_helper_crypto_sha1h
;
11055 case 1: /* SHA1SU1 */
11056 feature
= ARM_FEATURE_V8_SHA1
;
11057 genfn
= gen_helper_crypto_sha1su1
;
11059 case 2: /* SHA256SU0 */
11060 feature
= ARM_FEATURE_V8_SHA256
;
11061 genfn
= gen_helper_crypto_sha256su0
;
11064 unallocated_encoding(s
);
11068 if (!arm_dc_feature(s
, feature
)) {
11069 unallocated_encoding(s
);
11073 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11074 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11076 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
11078 tcg_temp_free_i32(tcg_rd_regno
);
11079 tcg_temp_free_i32(tcg_rn_regno
);
11082 /* C3.6 Data processing - SIMD, inc Crypto
11084 * As the decode gets a little complex we are using a table based
11085 * approach for this part of the decode.
11087 static const AArch64DecodeTable data_proc_simd
[] = {
11088 /* pattern , mask , fn */
11089 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
11090 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
11091 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
11092 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
11093 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
11094 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
11095 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
11096 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
11097 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
11098 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
11099 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
11100 { 0x2e000000, 0xbf208400, disas_simd_ext
},
11101 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
11102 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
11103 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
11104 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
11105 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
11106 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
11107 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
11108 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
11109 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
11110 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
11111 { 0x00000000, 0x00000000, NULL
}
11114 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
11116 /* Note that this is called with all non-FP cases from
11117 * table C3-6 so it must UNDEF for entries not specifically
11118 * allocated to instructions in that table.
11120 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
11124 unallocated_encoding(s
);
11128 /* C3.6 Data processing - SIMD and floating point */
11129 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
11131 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
11132 disas_data_proc_fp(s
, insn
);
11134 /* SIMD, including crypto */
11135 disas_data_proc_simd(s
, insn
);
11139 /* C3.1 A64 instruction index by encoding */
11140 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
11144 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
11148 s
->fp_access_checked
= false;
11150 switch (extract32(insn
, 25, 4)) {
11151 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
11152 unallocated_encoding(s
);
11154 case 0x8: case 0x9: /* Data processing - immediate */
11155 disas_data_proc_imm(s
, insn
);
11157 case 0xa: case 0xb: /* Branch, exception generation and system insns */
11158 disas_b_exc_sys(s
, insn
);
11163 case 0xe: /* Loads and stores */
11164 disas_ldst(s
, insn
);
11167 case 0xd: /* Data processing - register */
11168 disas_data_proc_reg(s
, insn
);
11171 case 0xf: /* Data processing - SIMD and floating point */
11172 disas_data_proc_simd_fp(s
, insn
);
11175 assert(FALSE
); /* all 15 cases should be handled above */
11179 /* if we allocated any temporaries, free them here */
11183 void gen_intermediate_code_a64(ARMCPU
*cpu
, TranslationBlock
*tb
)
11185 CPUState
*cs
= CPU(cpu
);
11186 CPUARMState
*env
= &cpu
->env
;
11187 DisasContext dc1
, *dc
= &dc1
;
11188 target_ulong pc_start
;
11189 target_ulong next_page_start
;
11197 dc
->is_jmp
= DISAS_NEXT
;
11199 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
11203 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11204 * there is no secure EL1, so we route exceptions to EL3.
11206 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11207 !arm_el_is_aa64(env
, 3);
11210 dc
->be_data
= ARM_TBFLAG_BE_DATA(tb
->flags
) ? MO_BE
: MO_LE
;
11211 dc
->condexec_mask
= 0;
11212 dc
->condexec_cond
= 0;
11213 dc
->mmu_idx
= ARM_TBFLAG_MMUIDX(tb
->flags
);
11214 dc
->tbi0
= ARM_TBFLAG_TBI0(tb
->flags
);
11215 dc
->tbi1
= ARM_TBFLAG_TBI1(tb
->flags
);
11216 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11217 #if !defined(CONFIG_USER_ONLY)
11218 dc
->user
= (dc
->current_el
== 0);
11220 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(tb
->flags
);
11222 dc
->vec_stride
= 0;
11223 dc
->cp_regs
= cpu
->cp_regs
;
11224 dc
->features
= env
->features
;
11226 /* Single step state. The code-generation logic here is:
11228 * generate code with no special handling for single-stepping (except
11229 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11230 * this happens anyway because those changes are all system register or
11232 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11233 * emit code for one insn
11234 * emit code to clear PSTATE.SS
11235 * emit code to generate software step exception for completed step
11236 * end TB (as usual for having generated an exception)
11237 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11238 * emit code to generate a software step exception
11241 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(tb
->flags
);
11242 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(tb
->flags
);
11243 dc
->is_ldex
= false;
11244 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
11246 init_tmp_a64_array(dc
);
11248 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
11250 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
11251 if (max_insns
== 0) {
11252 max_insns
= CF_COUNT_MASK
;
11254 if (max_insns
> TCG_MAX_INSNS
) {
11255 max_insns
= TCG_MAX_INSNS
;
11260 tcg_clear_temp_count();
11263 dc
->insn_start_idx
= tcg_op_buf_count();
11264 tcg_gen_insn_start(dc
->pc
, 0, 0);
11267 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
11269 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
11270 if (bp
->pc
== dc
->pc
) {
11271 if (bp
->flags
& BP_CPU
) {
11272 gen_a64_set_pc_im(dc
->pc
);
11273 gen_helper_check_breakpoints(cpu_env
);
11274 /* End the TB early; it likely won't be executed */
11275 dc
->is_jmp
= DISAS_UPDATE
;
11277 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
11278 /* The address covered by the breakpoint must be
11279 included in [tb->pc, tb->pc + tb->size) in order
11280 to for it to be properly cleared -- thus we
11281 increment the PC here so that the logic setting
11282 tb->size below does the right thing. */
11284 goto done_generating
;
11291 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
11295 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11296 /* Singlestep state is Active-pending.
11297 * If we're in this state at the start of a TB then either
11298 * a) we just took an exception to an EL which is being debugged
11299 * and this is the first insn in the exception handler
11300 * b) debug exceptions were masked and we just unmasked them
11301 * without changing EL (eg by clearing PSTATE.D)
11302 * In either case we're going to take a swstep exception in the
11303 * "did not step an insn" case, and so the syndrome ISV and EX
11304 * bits should be zero.
11306 assert(num_insns
== 1);
11307 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
11308 default_exception_el(dc
));
11309 dc
->is_jmp
= DISAS_EXC
;
11313 disas_a64_insn(env
, dc
);
11315 if (tcg_check_temp_count()) {
11316 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
11320 /* Translation stops when a conditional branch is encountered.
11321 * Otherwise the subsequent code could get translated several times.
11322 * Also stop translation when a page boundary is reached. This
11323 * ensures prefetch aborts occur at the right place.
11325 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
11326 !cs
->singlestep_enabled
&&
11329 dc
->pc
< next_page_start
&&
11330 num_insns
< max_insns
);
11332 if (tb
->cflags
& CF_LAST_IO
) {
11336 if (unlikely(cs
->singlestep_enabled
|| dc
->ss_active
)
11337 && dc
->is_jmp
!= DISAS_EXC
) {
11338 /* Note that this means single stepping WFI doesn't halt the CPU.
11339 * For conditional branch insns this is harmless unreachable code as
11340 * gen_goto_tb() has already handled emitting the debug exception
11341 * (and thus a tb-jump is not possible when singlestepping).
11343 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
11344 if (dc
->is_jmp
!= DISAS_JUMP
) {
11345 gen_a64_set_pc_im(dc
->pc
);
11347 if (cs
->singlestep_enabled
) {
11348 gen_exception_internal(EXCP_DEBUG
);
11350 gen_step_complete_exception(dc
);
11353 switch (dc
->is_jmp
) {
11355 gen_goto_tb(dc
, 1, dc
->pc
);
11359 gen_a64_set_pc_im(dc
->pc
);
11362 /* indicate that the hash table must be used to find the next TB */
11363 tcg_gen_exit_tb(0);
11365 case DISAS_TB_JUMP
:
11370 gen_a64_set_pc_im(dc
->pc
);
11371 gen_helper_wfe(cpu_env
);
11374 gen_a64_set_pc_im(dc
->pc
);
11375 gen_helper_yield(cpu_env
);
11378 /* This is a special case because we don't want to just halt the CPU
11379 * if trying to debug across a WFI.
11381 gen_a64_set_pc_im(dc
->pc
);
11382 gen_helper_wfi(cpu_env
);
11383 /* The helper doesn't necessarily throw an exception, but we
11384 * must go back to the main loop to check for interrupts anyway.
11386 tcg_gen_exit_tb(0);
11392 gen_tb_end(tb
, num_insns
);
11395 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
) &&
11396 qemu_log_in_addr_range(pc_start
)) {
11398 qemu_log("----------------\n");
11399 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11400 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
,
11401 4 | (bswap_code(dc
->sctlr_b
) ? 2 : 0));
11406 tb
->size
= dc
->pc
- pc_start
;
11407 tb
->icount
= num_insns
;