hw/intc/bcm2835_ic.c

   1 /*
   2  * Raspberry Pi emulation (c) 2012 Gregory Estrade
   3  * This code is licensed under the GNU GPLv2 and later.
   4  * Heavily based on pl190.c, copyright terms below:
   5  *
   6  * Arm PrimeCell PL190 Vector Interrupt Controller
   7  *
   8  * Copyright (c) 2006 CodeSourcery.
   9  * Written by Paul Brook
  10  *
  11  * This code is licensed under the GPL.
  12  */
  13
  14 #include "hw/intc/bcm2835_ic.h"
  15
  16 #define GPU_IRQS 64
  17 #define ARM_IRQS 8
  18
  19 #define IRQ_PENDING_BASIC       0x00 /* IRQ basic pending */
  20 #define IRQ_PENDING_1           0x04 /* IRQ pending 1 */
  21 #define IRQ_PENDING_2           0x08 /* IRQ pending 2 */
  22 #define FIQ_CONTROL             0x0C /* FIQ register */
  23 #define IRQ_ENABLE_1            0x10 /* Interrupt enable register 1 */
  24 #define IRQ_ENABLE_2            0x14 /* Interrupt enable register 2 */
  25 #define IRQ_ENABLE_BASIC        0x18 /* Base interrupt enable register */
  26 #define IRQ_DISABLE_1           0x1C /* Interrupt disable register 1 */
  27 #define IRQ_DISABLE_2           0x20 /* Interrupt disable register 2 */
  28 #define IRQ_DISABLE_BASIC       0x24 /* Base interrupt disable register */
  29
  30 /* Update interrupts.  */
  31 static void bcm2835_ic_update(BCM2835ICState *s)
  32 {
  33     bool set = false;
  34
  35     if (s->fiq_enable) {
  36         if (s->fiq_select >= GPU_IRQS) {
  37             /* ARM IRQ */
  38             set = extract32(s->arm_irq_level, s->fiq_select - GPU_IRQS, 1);
  39         } else {
  40             set = extract64(s->gpu_irq_level, s->fiq_select, 1);
  41         }
  42     }
  43     qemu_set_irq(s->fiq, set);
  44
  45     set = (s->gpu_irq_level & s->gpu_irq_enable)
  46         || (s->arm_irq_level & s->arm_irq_enable);
  47     qemu_set_irq(s->irq, set);
  48
  49 }
  50
  51 static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int level)
  52 {
  53     BCM2835ICState *s = opaque;
  54     assert(irq >= 0 && irq < 64);
  55     s->gpu_irq_level = deposit64(s->gpu_irq_level, irq, 1, level != 0);
  56     bcm2835_ic_update(s);
  57 }
  58
  59 static void bcm2835_ic_set_arm_irq(void *opaque, int irq, int level)
  60 {
  61     BCM2835ICState *s = opaque;
  62     assert(irq >= 0 && irq < 8);
  63     s->arm_irq_level = deposit32(s->arm_irq_level, irq, 1, level != 0);
  64     bcm2835_ic_update(s);
  65 }
  66
  67 static const int irq_dups[] = { 7, 9, 10, 18, 19, 53, 54, 55, 56, 57, 62 };
  68
  69 static uint64_t bcm2835_ic_read(void *opaque, hwaddr offset, unsigned size)
  70 {
  71     BCM2835ICState *s = opaque;
  72     uint32_t res = 0;
  73     uint64_t gpu_pending = s->gpu_irq_level & s->gpu_irq_enable;
  74     int i;
  75
  76     switch (offset) {
  77     case IRQ_PENDING_BASIC:
  78         /* bits 0-7: ARM irqs */
  79         res = s->arm_irq_level & s->arm_irq_enable;
  80
  81         /* bits 8 & 9: pending registers 1 & 2 */
  82         res |= (((uint32_t)gpu_pending) != 0) << 8;
  83         res |= ((gpu_pending >> 32) != 0) << 9;
  84
  85         /* bits 10-20: selected GPU IRQs */
  86         for (i = 0; i < ARRAY_SIZE(irq_dups); i++) {
  87             res |= extract64(gpu_pending, irq_dups[i], 1) << (i + 10);
  88         }
  89         break;
  90     case IRQ_PENDING_1:  /* IRQ pending 1 */
  91         res = gpu_pending;
  92         break;
  93     case IRQ_PENDING_2:  /* IRQ pending 2 */
  94         res = gpu_pending >> 32;
  95         break;
  96     case FIQ_CONTROL:  /* FIQ register */
  97         res = (s->fiq_enable << 7) | s->fiq_select;
  98         break;
  99     case IRQ_ENABLE_1:  /* Interrupt enable register 1 */
 100         res = s->gpu_irq_enable;
 101         break;
 102     case IRQ_ENABLE_2:  /* Interrupt enable register 2 */
 103         res = s->gpu_irq_enable >> 32;
 104         break;
 105     case IRQ_ENABLE_BASIC:  /* Base interrupt enable register */
 106         res = s->arm_irq_enable;
 107         break;
 108     case IRQ_DISABLE_1:  /* Interrupt disable register 1 */
 109         res = ~s->gpu_irq_enable;
 110         break;
 111     case IRQ_DISABLE_2:  /* Interrupt disable register 2 */
 112         res = ~s->gpu_irq_enable >> 32;
 113         break;
 114     case IRQ_DISABLE_BASIC:  /* Base interrupt disable register */
 115         res = ~s->arm_irq_enable;
 116         break;
 117     default:
 118         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 119                       __func__, offset);
 120         return 0;
 121     }
 122
 123     return res;
 124 }
 125
 126 static void bcm2835_ic_write(void *opaque, hwaddr offset, uint64_t val,
 127                              unsigned size)
 128 {
 129     BCM2835ICState *s = opaque;
 130
 131     switch (offset) {
 132     case FIQ_CONTROL:
 133         s->fiq_select = (val & 0x7f);
 134         s->fiq_enable = (val >> 7) & 0x1;
 135         break;
 136     case IRQ_ENABLE_1:
 137         s->gpu_irq_enable |= val;
 138         break;
 139     case IRQ_ENABLE_2:
 140         s->gpu_irq_enable |= val << 32;
 141         break;
 142     case IRQ_ENABLE_BASIC:
 143         s->arm_irq_enable |= val & 0xff;
 144         break;
 145     case IRQ_DISABLE_1:
 146         s->gpu_irq_enable &= ~val;
 147         break;
 148     case IRQ_DISABLE_2:
 149         s->gpu_irq_enable &= ~(val << 32);
 150         break;
 151     case IRQ_DISABLE_BASIC:
 152         s->arm_irq_enable &= ~val & 0xff;
 153         break;
 154     default:
 155         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 156                       __func__, offset);
 157         return;
 158     }
 159     bcm2835_ic_update(s);
 160 }
 161
 162 static const MemoryRegionOps bcm2835_ic_ops = {
 163     .read = bcm2835_ic_read,
 164     .write = bcm2835_ic_write,
 165     .endianness = DEVICE_NATIVE_ENDIAN,
 166     .valid.min_access_size = 4,
 167     .valid.max_access_size = 4,
 168 };
 169
 170 static void bcm2835_ic_reset(DeviceState *d)
 171 {
 172     BCM2835ICState *s = BCM2835_IC(d);
 173
 174     s->gpu_irq_enable = 0;
 175     s->arm_irq_enable = 0;
 176     s->fiq_enable = false;
 177     s->fiq_select = 0;
 178 }
 179
 180 static void bcm2835_ic_init(Object *obj)
 181 {
 182     BCM2835ICState *s = BCM2835_IC(obj);
 183
 184     memory_region_init_io(&s->iomem, obj, &bcm2835_ic_ops, s, TYPE_BCM2835_IC,
 185                           0x200);
 186     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 187
 188     qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_gpu_irq,
 189                             BCM2835_IC_GPU_IRQ, GPU_IRQS);
 190     qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_arm_irq,
 191                             BCM2835_IC_ARM_IRQ, ARM_IRQS);
 192
 193     sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
 194     sysbus_init_irq(SYS_BUS_DEVICE(s), &s->fiq);
 195 }
 196
 197 static const VMStateDescription vmstate_bcm2835_ic = {
 198     .name = TYPE_BCM2835_IC,
 199     .version_id = 1,
 200     .minimum_version_id = 1,
 201     .fields = (VMStateField[]) {
 202         VMSTATE_UINT64(gpu_irq_level, BCM2835ICState),
 203         VMSTATE_UINT64(gpu_irq_enable, BCM2835ICState),
 204         VMSTATE_UINT8(arm_irq_level, BCM2835ICState),
 205         VMSTATE_UINT8(arm_irq_enable, BCM2835ICState),
 206         VMSTATE_BOOL(fiq_enable, BCM2835ICState),
 207         VMSTATE_UINT8(fiq_select, BCM2835ICState),
 208         VMSTATE_END_OF_LIST()
 209     }
 210 };
 211
 212 static void bcm2835_ic_class_init(ObjectClass *klass, void *data)
 213 {
 214     DeviceClass *dc = DEVICE_CLASS(klass);
 215
 216     dc->reset = bcm2835_ic_reset;
 217     dc->vmsd = &vmstate_bcm2835_ic;
 218 }
 219
 220 static TypeInfo bcm2835_ic_info = {
 221     .name          = TYPE_BCM2835_IC,
 222     .parent        = TYPE_SYS_BUS_DEVICE,
 223     .instance_size = sizeof(BCM2835ICState),
 224     .class_init    = bcm2835_ic_class_init,
 225     .instance_init = bcm2835_ic_init,
 226 };
 227
 228 static void bcm2835_ic_register_types(void)
 229 {
 230     type_register_static(&bcm2835_ic_info);
 231 }
 232
 233 type_init(bcm2835_ic_register_types)