hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "apb_pci.h"
  27 #include "pc.h"
  28 #include "nvram.h"
  29 #include "fdc.h"
  30 #include "net.h"
  31 #include "qemu-timer.h"
  32 #include "sysemu.h"
  33 #include "boards.h"
  34 #include "firmware_abi.h"
  35 #include "fw_cfg.h"
  36 #include "sysbus.h"
  37 #include "ide.h"
  38 #include "loader.h"
  39 #include "elf.h"
  40 #include "blockdev.h"
  41 #include "exec-memory.h"
  42 #include "vga-pci.h"
  43
  44 //#define DEBUG_IRQ
  45 //#define DEBUG_EBUS
  46 //#define DEBUG_TIMER
  47
  48 #ifdef DEBUG_IRQ
  49 #define CPUIRQ_DPRINTF(fmt, ...)                                \
  50     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  51 #else
  52 #define CPUIRQ_DPRINTF(fmt, ...)
  53 #endif
  54
  55 #ifdef DEBUG_EBUS
  56 #define EBUS_DPRINTF(fmt, ...)                                  \
  57     do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
  58 #else
  59 #define EBUS_DPRINTF(fmt, ...)
  60 #endif
  61
  62 #ifdef DEBUG_TIMER
  63 #define TIMER_DPRINTF(fmt, ...)                                  \
  64     do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
  65 #else
  66 #define TIMER_DPRINTF(fmt, ...)
  67 #endif
  68
  69 #define KERNEL_LOAD_ADDR     0x00404000
  70 #define CMDLINE_ADDR         0x003ff000
  71 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  72 #define PROM_VADDR           0x000ffd00000ULL
  73 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  74 #define APB_MEM_BASE         0x1ff00000000ULL
  75 #define APB_PCI_IO_BASE      (APB_SPECIAL_BASE + 0x02000000ULL)
  76 #define PROM_FILENAME        "openbios-sparc64"
  77 #define NVRAM_SIZE           0x2000
  78 #define MAX_IDE_BUS          2
  79 #define BIOS_CFG_IOPORT      0x510
  80 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  81 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  82 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  83
  84 #define IVEC_MAX             0x30
  85
  86 #define TICK_MAX             0x7fffffffffffffffULL
  87
  88 struct hwdef {
  89     const char * const default_cpu_model;
  90     uint16_t machine_id;
  91     uint64_t prom_addr;
  92     uint64_t console_serial_base;
  93 };
  94
  95 typedef struct EbusState {
  96     PCIDevice pci_dev;
  97     MemoryRegion bar0;
  98     MemoryRegion bar1;
  99 } EbusState;
 100
 101 int DMA_get_channel_mode (int nchan)
 102 {
 103     return 0;
 104 }
 105 int DMA_read_memory (int nchan, void *buf, int pos, int size)
 106 {
 107     return 0;
 108 }
 109 int DMA_write_memory (int nchan, void *buf, int pos, int size)
 110 {
 111     return 0;
 112 }
 113 void DMA_hold_DREQ (int nchan) {}
 114 void DMA_release_DREQ (int nchan) {}
 115 void DMA_schedule(int nchan) {}
 116
 117 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
 118 {
 119 }
 120
 121 void DMA_register_channel (int nchan,
 122                            DMA_transfer_handler transfer_handler,
 123                            void *opaque)
 124 {
 125 }
 126
 127 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 128 {
 129     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 130     return 0;
 131 }
 132
 133 static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
 134                                   const char *arch, ram_addr_t RAM_size,
 135                                   const char *boot_devices,
 136                                   uint32_t kernel_image, uint32_t kernel_size,
 137                                   const char *cmdline,
 138                                   uint32_t initrd_image, uint32_t initrd_size,
 139                                   uint32_t NVRAM_image,
 140                                   int width, int height, int depth,
 141                                   const uint8_t *macaddr)
 142 {
 143     unsigned int i;
 144     uint32_t start, end;
 145     uint8_t image[0x1ff0];
 146     struct OpenBIOS_nvpart_v1 *part_header;
 147
 148     memset(image, '\0', sizeof(image));
 149
 150     start = 0;
 151
 152     // OpenBIOS nvram variables
 153     // Variable partition
 154     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 155     part_header->signature = OPENBIOS_PART_SYSTEM;
 156     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 157
 158     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 159     for (i = 0; i < nb_prom_envs; i++)
 160         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 161
 162     // End marker
 163     image[end++] = '\0';
 164
 165     end = start + ((end - start + 15) & ~15);
 166     OpenBIOS_finish_partition(part_header, end - start);
 167
 168     // free partition
 169     start = end;
 170     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 171     part_header->signature = OPENBIOS_PART_FREE;
 172     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 173
 174     end = 0x1fd0;
 175     OpenBIOS_finish_partition(part_header, end - start);
 176
 177     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 178
 179     for (i = 0; i < sizeof(image); i++)
 180         m48t59_write(nvram, i, image[i]);
 181
 182     return 0;
 183 }
 184
 185 static uint64_t sun4u_load_kernel(const char *kernel_filename,
 186                                   const char *initrd_filename,
 187                                   ram_addr_t RAM_size, uint64_t *initrd_size,
 188                                   uint64_t *initrd_addr, uint64_t *kernel_addr,
 189                                   uint64_t *kernel_entry)
 190 {
 191     int linux_boot;
 192     unsigned int i;
 193     long kernel_size;
 194     uint8_t *ptr;
 195     uint64_t kernel_top;
 196
 197     linux_boot = (kernel_filename != NULL);
 198
 199     kernel_size = 0;
 200     if (linux_boot) {
 201         int bswap_needed;
 202
 203 #ifdef BSWAP_NEEDED
 204         bswap_needed = 1;
 205 #else
 206         bswap_needed = 0;
 207 #endif
 208         kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
 209                                kernel_addr, &kernel_top, 1, ELF_MACHINE, 0);
 210         if (kernel_size < 0) {
 211             *kernel_addr = KERNEL_LOAD_ADDR;
 212             *kernel_entry = KERNEL_LOAD_ADDR;
 213             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 214                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 215                                     TARGET_PAGE_SIZE);
 216         }
 217         if (kernel_size < 0) {
 218             kernel_size = load_image_targphys(kernel_filename,
 219                                               KERNEL_LOAD_ADDR,
 220                                               RAM_size - KERNEL_LOAD_ADDR);
 221         }
 222         if (kernel_size < 0) {
 223             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 224                     kernel_filename);
 225             exit(1);
 226         }
 227         /* load initrd above kernel */
 228         *initrd_size = 0;
 229         if (initrd_filename) {
 230             *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
 231
 232             *initrd_size = load_image_targphys(initrd_filename,
 233                                                *initrd_addr,
 234                                                RAM_size - *initrd_addr);
 235             if ((int)*initrd_size < 0) {
 236                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 237                         initrd_filename);
 238                 exit(1);
 239             }
 240         }
 241         if (*initrd_size > 0) {
 242             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 243                 ptr = rom_ptr(*kernel_addr + i);
 244                 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 245                     stl_p(ptr + 24, *initrd_addr + *kernel_addr);
 246                     stl_p(ptr + 28, *initrd_size);
 247                     break;
 248                 }
 249             }
 250         }
 251     }
 252     return kernel_size;
 253 }
 254
 255 void cpu_check_irqs(CPUSPARCState *env)
 256 {
 257     uint32_t pil = env->pil_in |
 258                   (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
 259
 260     /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
 261     if (env->ivec_status & 0x20) {
 262         return;
 263     }
 264     /* check if TM or SM in SOFTINT are set
 265        setting these also causes interrupt 14 */
 266     if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
 267         pil |= 1 << 14;
 268     }
 269
 270     /* The bit corresponding to psrpil is (1<< psrpil), the next bit
 271        is (2 << psrpil). */
 272     if (pil < (2 << env->psrpil)){
 273         if (env->interrupt_request & CPU_INTERRUPT_HARD) {
 274             CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
 275                            env->interrupt_index);
 276             env->interrupt_index = 0;
 277             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 278         }
 279         return;
 280     }
 281
 282     if (cpu_interrupts_enabled(env)) {
 283
 284         unsigned int i;
 285
 286         for (i = 15; i > env->psrpil; i--) {
 287             if (pil & (1 << i)) {
 288                 int old_interrupt = env->interrupt_index;
 289                 int new_interrupt = TT_EXTINT | i;
 290
 291                 if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
 292                   && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
 293                     CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
 294                                    "current %x >= pending %x\n",
 295                                    env->tl, cpu_tsptr(env)->tt, new_interrupt);
 296                 } else if (old_interrupt != new_interrupt) {
 297                     env->interrupt_index = new_interrupt;
 298                     CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
 299                                    old_interrupt, new_interrupt);
 300                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 301                 }
 302                 break;
 303             }
 304         }
 305     } else if (env->interrupt_request & CPU_INTERRUPT_HARD) {
 306         CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
 307                        "current interrupt %x\n",
 308                        pil, env->pil_in, env->softint, env->interrupt_index);
 309         env->interrupt_index = 0;
 310         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 311     }
 312 }
 313
 314 static void cpu_kick_irq(CPUSPARCState *env)
 315 {
 316     env->halted = 0;
 317     cpu_check_irqs(env);
 318     qemu_cpu_kick(env);
 319 }
 320
 321 static void cpu_set_ivec_irq(void *opaque, int irq, int level)
 322 {
 323     CPUSPARCState *env = opaque;
 324
 325     if (level) {
 326         if (!(env->ivec_status & 0x20)) {
 327             CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
 328             env->halted = 0;
 329             env->interrupt_index = TT_IVEC;
 330             env->ivec_status |= 0x20;
 331             env->ivec_data[0] = (0x1f << 6) | irq;
 332             env->ivec_data[1] = 0;
 333             env->ivec_data[2] = 0;
 334             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 335         }
 336     } else {
 337         if (env->ivec_status & 0x20) {
 338             CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
 339             env->ivec_status &= ~0x20;
 340             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 341         }
 342     }
 343 }
 344
 345 typedef struct ResetData {
 346     SPARCCPU *cpu;
 347     uint64_t prom_addr;
 348 } ResetData;
 349
 350 void cpu_put_timer(QEMUFile *f, CPUTimer *s)
 351 {
 352     qemu_put_be32s(f, &s->frequency);
 353     qemu_put_be32s(f, &s->disabled);
 354     qemu_put_be64s(f, &s->disabled_mask);
 355     qemu_put_sbe64s(f, &s->clock_offset);
 356
 357     qemu_put_timer(f, s->qtimer);
 358 }
 359
 360 void cpu_get_timer(QEMUFile *f, CPUTimer *s)
 361 {
 362     qemu_get_be32s(f, &s->frequency);
 363     qemu_get_be32s(f, &s->disabled);
 364     qemu_get_be64s(f, &s->disabled_mask);
 365     qemu_get_sbe64s(f, &s->clock_offset);
 366
 367     qemu_get_timer(f, s->qtimer);
 368 }
 369
 370 static CPUTimer* cpu_timer_create(const char* name, CPUSPARCState *env,
 371                                   QEMUBHFunc *cb, uint32_t frequency,
 372                                   uint64_t disabled_mask)
 373 {
 374     CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
 375
 376     timer->name = name;
 377     timer->frequency = frequency;
 378     timer->disabled_mask = disabled_mask;
 379
 380     timer->disabled = 1;
 381     timer->clock_offset = qemu_get_clock_ns(vm_clock);
 382
 383     timer->qtimer = qemu_new_timer_ns(vm_clock, cb, env);
 384
 385     return timer;
 386 }
 387
 388 static void cpu_timer_reset(CPUTimer *timer)
 389 {
 390     timer->disabled = 1;
 391     timer->clock_offset = qemu_get_clock_ns(vm_clock);
 392
 393     qemu_del_timer(timer->qtimer);
 394 }
 395
 396 static void main_cpu_reset(void *opaque)
 397 {
 398     ResetData *s = (ResetData *)opaque;
 399     CPUSPARCState *env = &s->cpu->env;
 400     static unsigned int nr_resets;
 401
 402     cpu_reset(CPU(s->cpu));
 403
 404     cpu_timer_reset(env->tick);
 405     cpu_timer_reset(env->stick);
 406     cpu_timer_reset(env->hstick);
 407
 408     env->gregs[1] = 0; // Memory start
 409     env->gregs[2] = ram_size; // Memory size
 410     env->gregs[3] = 0; // Machine description XXX
 411     if (nr_resets++ == 0) {
 412         /* Power on reset */
 413         env->pc = s->prom_addr + 0x20ULL;
 414     } else {
 415         env->pc = s->prom_addr + 0x40ULL;
 416     }
 417     env->npc = env->pc + 4;
 418 }
 419
 420 static void tick_irq(void *opaque)
 421 {
 422     CPUSPARCState *env = opaque;
 423
 424     CPUTimer* timer = env->tick;
 425
 426     if (timer->disabled) {
 427         CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
 428         return;
 429     } else {
 430         CPUIRQ_DPRINTF("tick: fire\n");
 431     }
 432
 433     env->softint |= SOFTINT_TIMER;
 434     cpu_kick_irq(env);
 435 }
 436
 437 static void stick_irq(void *opaque)
 438 {
 439     CPUSPARCState *env = opaque;
 440
 441     CPUTimer* timer = env->stick;
 442
 443     if (timer->disabled) {
 444         CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
 445         return;
 446     } else {
 447         CPUIRQ_DPRINTF("stick: fire\n");
 448     }
 449
 450     env->softint |= SOFTINT_STIMER;
 451     cpu_kick_irq(env);
 452 }
 453
 454 static void hstick_irq(void *opaque)
 455 {
 456     CPUSPARCState *env = opaque;
 457
 458     CPUTimer* timer = env->hstick;
 459
 460     if (timer->disabled) {
 461         CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
 462         return;
 463     } else {
 464         CPUIRQ_DPRINTF("hstick: fire\n");
 465     }
 466
 467     env->softint |= SOFTINT_STIMER;
 468     cpu_kick_irq(env);
 469 }
 470
 471 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
 472 {
 473     return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
 474 }
 475
 476 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
 477 {
 478     return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
 479 }
 480
 481 void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
 482 {
 483     uint64_t real_count = count & ~timer->disabled_mask;
 484     uint64_t disabled_bit = count & timer->disabled_mask;
 485
 486     int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) -
 487                     cpu_to_timer_ticks(real_count, timer->frequency);
 488
 489     TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
 490                   timer->name, real_count,
 491                   timer->disabled?"disabled":"enabled", timer);
 492
 493     timer->disabled = disabled_bit ? 1 : 0;
 494     timer->clock_offset = vm_clock_offset;
 495 }
 496
 497 uint64_t cpu_tick_get_count(CPUTimer *timer)
 498 {
 499     uint64_t real_count = timer_to_cpu_ticks(
 500                     qemu_get_clock_ns(vm_clock) - timer->clock_offset,
 501                     timer->frequency);
 502
 503     TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
 504            timer->name, real_count,
 505            timer->disabled?"disabled":"enabled", timer);
 506
 507     if (timer->disabled)
 508         real_count |= timer->disabled_mask;
 509
 510     return real_count;
 511 }
 512
 513 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
 514 {
 515     int64_t now = qemu_get_clock_ns(vm_clock);
 516
 517     uint64_t real_limit = limit & ~timer->disabled_mask;
 518     timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
 519
 520     int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
 521                     timer->clock_offset;
 522
 523     if (expires < now) {
 524         expires = now + 1;
 525     }
 526
 527     TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
 528                   "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
 529                   timer->name, real_limit,
 530                   timer->disabled?"disabled":"enabled",
 531                   timer, limit,
 532                   timer_to_cpu_ticks(now - timer->clock_offset,
 533                                      timer->frequency),
 534                   timer_to_cpu_ticks(expires - now, timer->frequency));
 535
 536     if (!real_limit) {
 537         TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
 538                 timer->name);
 539         qemu_del_timer(timer->qtimer);
 540     } else if (timer->disabled) {
 541         qemu_del_timer(timer->qtimer);
 542     } else {
 543         qemu_mod_timer(timer->qtimer, expires);
 544     }
 545 }
 546
 547 static void isa_irq_handler(void *opaque, int n, int level)
 548 {
 549     static const int isa_irq_to_ivec[16] = {
 550         [1] = 0x29, /* keyboard */
 551         [4] = 0x2b, /* serial */
 552         [6] = 0x27, /* floppy */
 553         [7] = 0x22, /* parallel */
 554         [12] = 0x2a, /* mouse */
 555     };
 556     qemu_irq *irqs = opaque;
 557     int ivec;
 558
 559     assert(n < 16);
 560     ivec = isa_irq_to_ivec[n];
 561     EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec);
 562     if (ivec) {
 563         qemu_set_irq(irqs[ivec], level);
 564     }
 565 }
 566
 567 /* EBUS (Eight bit bus) bridge */
 568 static ISABus *
 569 pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs)
 570 {
 571     qemu_irq *isa_irq;
 572     PCIDevice *pci_dev;
 573     ISABus *isa_bus;
 574
 575     pci_dev = pci_create_simple(bus, devfn, "ebus");
 576     isa_bus = DO_UPCAST(ISABus, qbus,
 577                         qdev_get_child_bus(&pci_dev->qdev, "isa.0"));
 578     isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16);
 579     isa_bus_irqs(isa_bus, isa_irq);
 580     return isa_bus;
 581 }
 582
 583 static int
 584 pci_ebus_init1(PCIDevice *pci_dev)
 585 {
 586     EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
 587
 588     isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev));
 589
 590     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 591     pci_dev->config[0x05] = 0x00;
 592     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 593     pci_dev->config[0x07] = 0x03; // status = medium devsel
 594     pci_dev->config[0x09] = 0x00; // programming i/f
 595     pci_dev->config[0x0D] = 0x0a; // latency_timer
 596
 597     isa_mmio_setup(&s->bar0, 0x1000000);
 598     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 599     isa_mmio_setup(&s->bar1, 0x800000);
 600     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
 601     return 0;
 602 }
 603
 604 static void ebus_class_init(ObjectClass *klass, void *data)
 605 {
 606     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 607
 608     k->init = pci_ebus_init1;
 609     k->vendor_id = PCI_VENDOR_ID_SUN;
 610     k->device_id = PCI_DEVICE_ID_SUN_EBUS;
 611     k->revision = 0x01;
 612     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 613 }
 614
 615 static TypeInfo ebus_info = {
 616     .name          = "ebus",
 617     .parent        = TYPE_PCI_DEVICE,
 618     .instance_size = sizeof(EbusState),
 619     .class_init    = ebus_class_init,
 620 };
 621
 622 typedef struct PROMState {
 623     SysBusDevice busdev;
 624     MemoryRegion prom;
 625 } PROMState;
 626
 627 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 628 {
 629     target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
 630     return addr + *base_addr - PROM_VADDR;
 631 }
 632
 633 /* Boot PROM (OpenBIOS) */
 634 static void prom_init(target_phys_addr_t addr, const char *bios_name)
 635 {
 636     DeviceState *dev;
 637     SysBusDevice *s;
 638     char *filename;
 639     int ret;
 640
 641     dev = qdev_create(NULL, "openprom");
 642     qdev_init_nofail(dev);
 643     s = sysbus_from_qdev(dev);
 644
 645     sysbus_mmio_map(s, 0, addr);
 646
 647     /* load boot prom */
 648     if (bios_name == NULL) {
 649         bios_name = PROM_FILENAME;
 650     }
 651     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 652     if (filename) {
 653         ret = load_elf(filename, translate_prom_address, &addr,
 654                        NULL, NULL, NULL, 1, ELF_MACHINE, 0);
 655         if (ret < 0 || ret > PROM_SIZE_MAX) {
 656             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 657         }
 658         g_free(filename);
 659     } else {
 660         ret = -1;
 661     }
 662     if (ret < 0 || ret > PROM_SIZE_MAX) {
 663         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 664         exit(1);
 665     }
 666 }
 667
 668 static int prom_init1(SysBusDevice *dev)
 669 {
 670     PROMState *s = FROM_SYSBUS(PROMState, dev);
 671
 672     memory_region_init_ram(&s->prom, "sun4u.prom", PROM_SIZE_MAX);
 673     vmstate_register_ram_global(&s->prom);
 674     memory_region_set_readonly(&s->prom, true);
 675     sysbus_init_mmio(dev, &s->prom);
 676     return 0;
 677 }
 678
 679 static Property prom_properties[] = {
 680     {/* end of property list */},
 681 };
 682
 683 static void prom_class_init(ObjectClass *klass, void *data)
 684 {
 685     DeviceClass *dc = DEVICE_CLASS(klass);
 686     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 687
 688     k->init = prom_init1;
 689     dc->props = prom_properties;
 690 }
 691
 692 static TypeInfo prom_info = {
 693     .name          = "openprom",
 694     .parent        = TYPE_SYS_BUS_DEVICE,
 695     .instance_size = sizeof(PROMState),
 696     .class_init    = prom_class_init,
 697 };
 698
 699
 700 typedef struct RamDevice
 701 {
 702     SysBusDevice busdev;
 703     MemoryRegion ram;
 704     uint64_t size;
 705 } RamDevice;
 706
 707 /* System RAM */
 708 static int ram_init1(SysBusDevice *dev)
 709 {
 710     RamDevice *d = FROM_SYSBUS(RamDevice, dev);
 711
 712     memory_region_init_ram(&d->ram, "sun4u.ram", d->size);
 713     vmstate_register_ram_global(&d->ram);
 714     sysbus_init_mmio(dev, &d->ram);
 715     return 0;
 716 }
 717
 718 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
 719 {
 720     DeviceState *dev;
 721     SysBusDevice *s;
 722     RamDevice *d;
 723
 724     /* allocate RAM */
 725     dev = qdev_create(NULL, "memory");
 726     s = sysbus_from_qdev(dev);
 727
 728     d = FROM_SYSBUS(RamDevice, s);
 729     d->size = RAM_size;
 730     qdev_init_nofail(dev);
 731
 732     sysbus_mmio_map(s, 0, addr);
 733 }
 734
 735 static Property ram_properties[] = {
 736     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 737     DEFINE_PROP_END_OF_LIST(),
 738 };
 739
 740 static void ram_class_init(ObjectClass *klass, void *data)
 741 {
 742     DeviceClass *dc = DEVICE_CLASS(klass);
 743     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 744
 745     k->init = ram_init1;
 746     dc->props = ram_properties;
 747 }
 748
 749 static TypeInfo ram_info = {
 750     .name          = "memory",
 751     .parent        = TYPE_SYS_BUS_DEVICE,
 752     .instance_size = sizeof(RamDevice),
 753     .class_init    = ram_class_init,
 754 };
 755
 756 static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
 757 {
 758     SPARCCPU *cpu;
 759     CPUSPARCState *env;
 760     ResetData *reset_info;
 761
 762     uint32_t   tick_frequency = 100*1000000;
 763     uint32_t  stick_frequency = 100*1000000;
 764     uint32_t hstick_frequency = 100*1000000;
 765
 766     if (cpu_model == NULL) {
 767         cpu_model = hwdef->default_cpu_model;
 768     }
 769     cpu = cpu_sparc_init(cpu_model);
 770     if (cpu == NULL) {
 771         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 772         exit(1);
 773     }
 774     env = &cpu->env;
 775
 776     env->tick = cpu_timer_create("tick", env, tick_irq,
 777                                   tick_frequency, TICK_NPT_MASK);
 778
 779     env->stick = cpu_timer_create("stick", env, stick_irq,
 780                                    stick_frequency, TICK_INT_DIS);
 781
 782     env->hstick = cpu_timer_create("hstick", env, hstick_irq,
 783                                     hstick_frequency, TICK_INT_DIS);
 784
 785     reset_info = g_malloc0(sizeof(ResetData));
 786     reset_info->cpu = cpu;
 787     reset_info->prom_addr = hwdef->prom_addr;
 788     qemu_register_reset(main_cpu_reset, reset_info);
 789
 790     return cpu;
 791 }
 792
 793 static void sun4uv_init(MemoryRegion *address_space_mem,
 794                         ram_addr_t RAM_size,
 795                         const char *boot_devices,
 796                         const char *kernel_filename, const char *kernel_cmdline,
 797                         const char *initrd_filename, const char *cpu_model,
 798                         const struct hwdef *hwdef)
 799 {
 800     SPARCCPU *cpu;
 801     CPUSPARCState *env;
 802     M48t59State *nvram;
 803     unsigned int i;
 804     uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
 805     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 806     ISABus *isa_bus;
 807     qemu_irq *ivec_irqs, *pbm_irqs;
 808     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 809     DriveInfo *fd[MAX_FD];
 810     void *fw_cfg;
 811
 812     /* init CPUs */
 813     cpu = cpu_devinit(cpu_model, hwdef);
 814     env = &cpu->env;
 815
 816     /* set up devices */
 817     ram_init(0, RAM_size);
 818
 819     prom_init(hwdef->prom_addr, bios_name);
 820
 821     ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, env, IVEC_MAX);
 822     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2,
 823                            &pci_bus3, &pbm_irqs);
 824     pci_vga_init(pci_bus);
 825
 826     // XXX Should be pci_bus3
 827     isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
 828
 829     i = 0;
 830     if (hwdef->console_serial_base) {
 831         serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
 832                        NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
 833         i++;
 834     }
 835     for(; i < MAX_SERIAL_PORTS; i++) {
 836         if (serial_hds[i]) {
 837             serial_isa_init(isa_bus, i, serial_hds[i]);
 838         }
 839     }
 840
 841     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 842         if (parallel_hds[i]) {
 843             parallel_init(isa_bus, i, parallel_hds[i]);
 844         }
 845     }
 846
 847     for(i = 0; i < nb_nics; i++)
 848         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 849
 850     ide_drive_get(hd, MAX_IDE_BUS);
 851
 852     pci_cmd646_ide_init(pci_bus, hd, 1);
 853
 854     isa_create_simple(isa_bus, "i8042");
 855     for(i = 0; i < MAX_FD; i++) {
 856         fd[i] = drive_get(IF_FLOPPY, 0, i);
 857     }
 858     fdctrl_init_isa(isa_bus, fd);
 859     nvram = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
 860
 861     initrd_size = 0;
 862     initrd_addr = 0;
 863     kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
 864                                     ram_size, &initrd_size, &initrd_addr,
 865                                     &kernel_addr, &kernel_entry);
 866
 867     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 868                            kernel_addr, kernel_size,
 869                            kernel_cmdline,
 870                            initrd_addr, initrd_size,
 871                            /* XXX: need an option to load a NVRAM image */
 872                            0,
 873                            graphic_width, graphic_height, graphic_depth,
 874                            (uint8_t *)&nd_table[0].macaddr);
 875
 876     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 877     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 878     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 879     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 880     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
 881     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 882     if (kernel_cmdline) {
 883         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 884                        strlen(kernel_cmdline) + 1);
 885         fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 886                          (uint8_t*)strdup(kernel_cmdline),
 887                          strlen(kernel_cmdline) + 1);
 888     } else {
 889         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 890     }
 891     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 892     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 893     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
 894
 895     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 896     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 897     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 898
 899     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 900 }
 901
 902 enum {
 903     sun4u_id = 0,
 904     sun4v_id = 64,
 905     niagara_id,
 906 };
 907
 908 static const struct hwdef hwdefs[] = {
 909     /* Sun4u generic PC-like machine */
 910     {
 911         .default_cpu_model = "TI UltraSparc IIi",
 912         .machine_id = sun4u_id,
 913         .prom_addr = 0x1fff0000000ULL,
 914         .console_serial_base = 0,
 915     },
 916     /* Sun4v generic PC-like machine */
 917     {
 918         .default_cpu_model = "Sun UltraSparc T1",
 919         .machine_id = sun4v_id,
 920         .prom_addr = 0x1fff0000000ULL,
 921         .console_serial_base = 0,
 922     },
 923     /* Sun4v generic Niagara machine */
 924     {
 925         .default_cpu_model = "Sun UltraSparc T1",
 926         .machine_id = niagara_id,
 927         .prom_addr = 0xfff0000000ULL,
 928         .console_serial_base = 0xfff0c2c000ULL,
 929     },
 930 };
 931
 932 /* Sun4u hardware initialisation */
 933 static void sun4u_init(ram_addr_t RAM_size,
 934                        const char *boot_devices,
 935                        const char *kernel_filename, const char *kernel_cmdline,
 936                        const char *initrd_filename, const char *cpu_model)
 937 {
 938     sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
 939                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 940 }
 941
 942 /* Sun4v hardware initialisation */
 943 static void sun4v_init(ram_addr_t RAM_size,
 944                        const char *boot_devices,
 945                        const char *kernel_filename, const char *kernel_cmdline,
 946                        const char *initrd_filename, const char *cpu_model)
 947 {
 948     sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
 949                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 950 }
 951
 952 /* Niagara hardware initialisation */
 953 static void niagara_init(ram_addr_t RAM_size,
 954                          const char *boot_devices,
 955                          const char *kernel_filename, const char *kernel_cmdline,
 956                          const char *initrd_filename, const char *cpu_model)
 957 {
 958     sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
 959                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
 960 }
 961
 962 static QEMUMachine sun4u_machine = {
 963     .name = "sun4u",
 964     .desc = "Sun4u platform",
 965     .init = sun4u_init,
 966     .max_cpus = 1, // XXX for now
 967     .is_default = 1,
 968 };
 969
 970 static QEMUMachine sun4v_machine = {
 971     .name = "sun4v",
 972     .desc = "Sun4v platform",
 973     .init = sun4v_init,
 974     .max_cpus = 1, // XXX for now
 975 };
 976
 977 static QEMUMachine niagara_machine = {
 978     .name = "Niagara",
 979     .desc = "Sun4v platform, Niagara",
 980     .init = niagara_init,
 981     .max_cpus = 1, // XXX for now
 982 };
 983
 984 static void sun4u_register_types(void)
 985 {
 986     type_register_static(&ebus_info);
 987     type_register_static(&prom_info);
 988     type_register_static(&ram_info);
 989 }
 990
 991 static void sun4u_machine_init(void)
 992 {
 993     qemu_register_machine(&sun4u_machine);
 994     qemu_register_machine(&sun4v_machine);
 995     qemu_register_machine(&niagara_machine);
 996 }
 997
 998 type_init(sun4u_register_types)
 999 machine_init(sun4u_machine_init);