spapr: Clean up RMA size calculation
[qemu/ar7.git] / hw / block / nvme.h
blob557194ee1954008cabd85391624d99cfae7d26e4
1 #ifndef HW_NVME_H
2 #define HW_NVME_H
3 #include "block/nvme.h"
5 typedef struct NvmeAsyncEvent {
6 QSIMPLEQ_ENTRY(NvmeAsyncEvent) entry;
7 NvmeAerResult result;
8 } NvmeAsyncEvent;
10 typedef struct NvmeRequest {
11 struct NvmeSQueue *sq;
12 BlockAIOCB *aiocb;
13 uint16_t status;
14 bool has_sg;
15 NvmeCqe cqe;
16 BlockAcctCookie acct;
17 QEMUSGList qsg;
18 QEMUIOVector iov;
19 QTAILQ_ENTRY(NvmeRequest)entry;
20 } NvmeRequest;
22 typedef struct NvmeSQueue {
23 struct NvmeCtrl *ctrl;
24 uint16_t sqid;
25 uint16_t cqid;
26 uint32_t head;
27 uint32_t tail;
28 uint32_t size;
29 uint64_t dma_addr;
30 QEMUTimer *timer;
31 NvmeRequest *io_req;
32 QTAILQ_HEAD(, NvmeRequest) req_list;
33 QTAILQ_HEAD(, NvmeRequest) out_req_list;
34 QTAILQ_ENTRY(NvmeSQueue) entry;
35 } NvmeSQueue;
37 typedef struct NvmeCQueue {
38 struct NvmeCtrl *ctrl;
39 uint8_t phase;
40 uint16_t cqid;
41 uint16_t irq_enabled;
42 uint32_t head;
43 uint32_t tail;
44 uint32_t vector;
45 uint32_t size;
46 uint64_t dma_addr;
47 QEMUTimer *timer;
48 QTAILQ_HEAD(, NvmeSQueue) sq_list;
49 QTAILQ_HEAD(, NvmeRequest) req_list;
50 } NvmeCQueue;
52 typedef struct NvmeNamespace {
53 NvmeIdNs id_ns;
54 } NvmeNamespace;
56 #define TYPE_NVME "nvme"
57 #define NVME(obj) \
58 OBJECT_CHECK(NvmeCtrl, (obj), TYPE_NVME)
60 typedef struct NvmeCtrl {
61 PCIDevice parent_obj;
62 MemoryRegion iomem;
63 MemoryRegion ctrl_mem;
64 NvmeBar bar;
65 BlockConf conf;
67 uint32_t page_size;
68 uint16_t page_bits;
69 uint16_t max_prp_ents;
70 uint16_t cqe_size;
71 uint16_t sqe_size;
72 uint32_t reg_size;
73 uint32_t num_namespaces;
74 uint32_t num_queues;
75 uint32_t max_q_ents;
76 uint64_t ns_size;
77 uint32_t cmb_size_mb;
78 uint32_t cmbsz;
79 uint32_t cmbloc;
80 uint8_t *cmbuf;
81 uint64_t irq_status;
82 uint64_t host_timestamp; /* Timestamp sent by the host */
83 uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */
85 char *serial;
86 NvmeNamespace *namespaces;
87 NvmeSQueue **sq;
88 NvmeCQueue **cq;
89 NvmeSQueue admin_sq;
90 NvmeCQueue admin_cq;
91 NvmeIdCtrl id_ctrl;
92 } NvmeCtrl;
94 #endif /* HW_NVME_H */