target/mips/cpu.c

   1 /*
   2  * QEMU MIPS CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "cpu.h"
  24 #include "internal.h"
  25 #include "kvm_mips.h"
  26 #include "qemu/module.h"
  27 #include "sysemu/kvm.h"
  28 #include "exec/exec-all.h"
  29
  30
  31 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
  32 {
  33     MIPSCPU *cpu = MIPS_CPU(cs);
  34     CPUMIPSState *env = &cpu->env;
  35
  36     env->active_tc.PC = value & ~(target_ulong)1;
  37     if (value & 1) {
  38         env->hflags |= MIPS_HFLAG_M16;
  39     } else {
  40         env->hflags &= ~(MIPS_HFLAG_M16);
  41     }
  42 }
  43
  44 static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  45 {
  46     MIPSCPU *cpu = MIPS_CPU(cs);
  47     CPUMIPSState *env = &cpu->env;
  48
  49     env->active_tc.PC = tb->pc;
  50     env->hflags &= ~MIPS_HFLAG_BMASK;
  51     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
  52 }
  53
  54 static bool mips_cpu_has_work(CPUState *cs)
  55 {
  56     MIPSCPU *cpu = MIPS_CPU(cs);
  57     CPUMIPSState *env = &cpu->env;
  58     bool has_work = false;
  59
  60     /*
  61      * Prior to MIPS Release 6 it is implementation dependent if non-enabled
  62      * interrupts wake-up the CPU, however most of the implementations only
  63      * check for interrupts that can be taken.
  64      */
  65     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
  66         cpu_mips_hw_interrupts_pending(env)) {
  67         if (cpu_mips_hw_interrupts_enabled(env) ||
  68             (env->insn_flags & ISA_MIPS32R6)) {
  69             has_work = true;
  70         }
  71     }
  72
  73     /* MIPS-MT has the ability to halt the CPU.  */
  74     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
  75         /*
  76          * The QEMU model will issue an _WAKE request whenever the CPUs
  77          * should be woken up.
  78          */
  79         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
  80             has_work = true;
  81         }
  82
  83         if (!mips_vpe_active(env)) {
  84             has_work = false;
  85         }
  86     }
  87     /* MIPS Release 6 has the ability to halt the CPU.  */
  88     if (env->CP0_Config5 & (1 << CP0C5_VP)) {
  89         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
  90             has_work = true;
  91         }
  92         if (!mips_vp_active(env)) {
  93             has_work = false;
  94         }
  95     }
  96     return has_work;
  97 }
  98
  99 static void mips_cpu_reset(DeviceState *dev)
 100 {
 101     CPUState *s = CPU(dev);
 102     MIPSCPU *cpu = MIPS_CPU(s);
 103     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
 104     CPUMIPSState *env = &cpu->env;
 105
 106     mcc->parent_reset(dev);
 107
 108     memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
 109
 110     cpu_state_reset(env);
 111
 112 #ifndef CONFIG_USER_ONLY
 113     if (kvm_enabled()) {
 114         kvm_mips_reset_vcpu(cpu);
 115     }
 116 #endif
 117 }
 118
 119 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 120 {
 121     MIPSCPU *cpu = MIPS_CPU(s);
 122     CPUMIPSState *env = &cpu->env;
 123
 124     if (!(env->insn_flags & ISA_NANOMIPS32)) {
 125 #ifdef TARGET_WORDS_BIGENDIAN
 126         info->print_insn = print_insn_big_mips;
 127 #else
 128         info->print_insn = print_insn_little_mips;
 129 #endif
 130     } else {
 131 #if defined(CONFIG_NANOMIPS_DIS)
 132         info->print_insn = print_insn_nanomips;
 133 #endif
 134     }
 135 }
 136
 137 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
 138 {
 139     CPUState *cs = CPU(dev);
 140     MIPSCPU *cpu = MIPS_CPU(dev);
 141     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
 142     Error *local_err = NULL;
 143
 144     cpu_exec_realizefn(cs, &local_err);
 145     if (local_err != NULL) {
 146         error_propagate(errp, local_err);
 147         return;
 148     }
 149
 150     cpu_mips_realize_env(&cpu->env);
 151
 152     cpu_reset(cs);
 153     qemu_init_vcpu(cs);
 154
 155     mcc->parent_realize(dev, errp);
 156 }
 157
 158 static void mips_cpu_initfn(Object *obj)
 159 {
 160     MIPSCPU *cpu = MIPS_CPU(obj);
 161     CPUMIPSState *env = &cpu->env;
 162     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
 163
 164     cpu_set_cpustate_pointers(cpu);
 165     env->cpu_model = mcc->cpu_def;
 166 }
 167
 168 static char *mips_cpu_type_name(const char *cpu_model)
 169 {
 170     return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model);
 171 }
 172
 173 static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
 174 {
 175     ObjectClass *oc;
 176     char *typename;
 177
 178     typename = mips_cpu_type_name(cpu_model);
 179     oc = object_class_by_name(typename);
 180     g_free(typename);
 181     return oc;
 182 }
 183
 184 static void mips_cpu_class_init(ObjectClass *c, void *data)
 185 {
 186     MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
 187     CPUClass *cc = CPU_CLASS(c);
 188     DeviceClass *dc = DEVICE_CLASS(c);
 189
 190     device_class_set_parent_realize(dc, mips_cpu_realizefn,
 191                                     &mcc->parent_realize);
 192     device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
 193
 194     cc->class_by_name = mips_cpu_class_by_name;
 195     cc->has_work = mips_cpu_has_work;
 196     cc->do_interrupt = mips_cpu_do_interrupt;
 197     cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
 198     cc->dump_state = mips_cpu_dump_state;
 199     cc->set_pc = mips_cpu_set_pc;
 200     cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
 201     cc->gdb_read_register = mips_cpu_gdb_read_register;
 202     cc->gdb_write_register = mips_cpu_gdb_write_register;
 203 #ifndef CONFIG_USER_ONLY
 204     cc->do_transaction_failed = mips_cpu_do_transaction_failed;
 205     cc->do_unaligned_access = mips_cpu_do_unaligned_access;
 206     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
 207     cc->vmsd = &vmstate_mips_cpu;
 208 #endif
 209     cc->disas_set_info = mips_cpu_disas_set_info;
 210 #ifdef CONFIG_TCG
 211     cc->tcg_initialize = mips_tcg_init;
 212     cc->tlb_fill = mips_cpu_tlb_fill;
 213 #endif
 214
 215     cc->gdb_num_core_regs = 73;
 216     cc->gdb_stop_before_watchpoint = true;
 217 }
 218
 219 static const TypeInfo mips_cpu_type_info = {
 220     .name = TYPE_MIPS_CPU,
 221     .parent = TYPE_CPU,
 222     .instance_size = sizeof(MIPSCPU),
 223     .instance_init = mips_cpu_initfn,
 224     .abstract = true,
 225     .class_size = sizeof(MIPSCPUClass),
 226     .class_init = mips_cpu_class_init,
 227 };
 228
 229 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)
 230 {
 231     MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);
 232     mcc->cpu_def = data;
 233 }
 234
 235 static void mips_register_cpudef_type(const struct mips_def_t *def)
 236 {
 237     char *typename = mips_cpu_type_name(def->name);
 238     TypeInfo ti = {
 239         .name = typename,
 240         .parent = TYPE_MIPS_CPU,
 241         .class_init = mips_cpu_cpudef_class_init,
 242         .class_data = (void *)def,
 243     };
 244
 245     type_register(&ti);
 246     g_free(typename);
 247 }
 248
 249 static void mips_cpu_register_types(void)
 250 {
 251     int i;
 252
 253     type_register_static(&mips_cpu_type_info);
 254     for (i = 0; i < mips_defs_number; i++) {
 255         mips_register_cpudef_type(&mips_defs[i]);
 256     }
 257 }
 258
 259 type_init(mips_cpu_register_types)