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docs/system/deprecated: Mark the 'moxie' CPU as deprecated
[qemu/ar7.git] / target / i386 / kvm.c
blob8b12387d30af3bae79d411fd2ca5bba378a37674
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/qapi-events-run-state.h"
17 #include "qapi/error.h"
18 #include <sys/ioctl.h>
19 #include <sys/utsname.h>
20
21 #include <linux/kvm.h>
22 #include "standard-headers/asm-x86/kvm_para.h"
23
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "sysemu/runstate.h"
29 #include "kvm_i386.h"
30 #include "hyperv.h"
31 #include "hyperv-proto.h"
32
33 #include "exec/gdbstub.h"
34 #include "qemu/host-utils.h"
35 #include "qemu/main-loop.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #include "hw/i386/x86.h"
39 #include "hw/i386/apic.h"
40 #include "hw/i386/apic_internal.h"
41 #include "hw/i386/apic-msidef.h"
42 #include "hw/i386/intel_iommu.h"
43 #include "hw/i386/x86-iommu.h"
44 #include "hw/i386/e820_memory_layout.h"
45
46 #include "hw/pci/pci.h"
47 #include "hw/pci/msi.h"
48 #include "hw/pci/msix.h"
49 #include "migration/blocker.h"
50 #include "exec/memattrs.h"
51 #include "trace.h"
52
53 //#define DEBUG_KVM
54
55 #ifdef DEBUG_KVM
56 #define DPRINTF(fmt, ...) \
57 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
58 #else
59 #define DPRINTF(fmt, ...) \
60 do { } while (0)
61 #endif
62
63 /* From arch/x86/kvm/lapic.h */
64 #define KVM_APIC_BUS_CYCLE_NS 1
65 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
66
67 #define MSR_KVM_WALL_CLOCK 0x11
68 #define MSR_KVM_SYSTEM_TIME 0x12
69
70 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
71 * 255 kvm_msr_entry structs */
72 #define MSR_BUF_SIZE 4096
73
74 static void kvm_init_msrs(X86CPU *cpu);
75
76 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
77 KVM_CAP_INFO(SET_TSS_ADDR),
78 KVM_CAP_INFO(EXT_CPUID),
79 KVM_CAP_INFO(MP_STATE),
80 KVM_CAP_LAST_INFO
81 };
82
83 static bool has_msr_star;
84 static bool has_msr_hsave_pa;
85 static bool has_msr_tsc_aux;
86 static bool has_msr_tsc_adjust;
87 static bool has_msr_tsc_deadline;
88 static bool has_msr_feature_control;
89 static bool has_msr_misc_enable;
90 static bool has_msr_smbase;
91 static bool has_msr_bndcfgs;
92 static int lm_capable_kernel;
93 static bool has_msr_hv_hypercall;
94 static bool has_msr_hv_crash;
95 static bool has_msr_hv_reset;
96 static bool has_msr_hv_vpindex;
97 static bool hv_vpindex_settable;
98 static bool has_msr_hv_runtime;
99 static bool has_msr_hv_synic;
100 static bool has_msr_hv_stimer;
101 static bool has_msr_hv_frequencies;
102 static bool has_msr_hv_reenlightenment;
103 static bool has_msr_xss;
104 static bool has_msr_umwait;
105 static bool has_msr_spec_ctrl;
106 static bool has_msr_tsx_ctrl;
107 static bool has_msr_virt_ssbd;
108 static bool has_msr_smi_count;
109 static bool has_msr_arch_capabs;
110 static bool has_msr_core_capabs;
111 static bool has_msr_vmx_vmfunc;
112 static bool has_msr_ucode_rev;
113 static bool has_msr_vmx_procbased_ctls2;
114 static bool has_msr_perf_capabs;
115
116 static uint32_t has_architectural_pmu_version;
117 static uint32_t num_architectural_pmu_gp_counters;
118 static uint32_t num_architectural_pmu_fixed_counters;
119
120 static int has_xsave;
121 static int has_xcrs;
122 static int has_pit_state2;
123 static int has_exception_payload;
124
125 static bool has_msr_mcg_ext_ctl;
126
127 static struct kvm_cpuid2 *cpuid_cache;
128 static struct kvm_msr_list *kvm_feature_msrs;
129
130 int kvm_has_pit_state2(void)
131 {
132 return has_pit_state2;
133 }
134
135 bool kvm_has_smm(void)
136 {
137 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
138 }
139
140 bool kvm_has_adjust_clock_stable(void)
141 {
142 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
143
144 return (ret == KVM_CLOCK_TSC_STABLE);
145 }
146
147 bool kvm_has_adjust_clock(void)
148 {
149 return kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
150 }
151
152 bool kvm_has_exception_payload(void)
153 {
154 return has_exception_payload;
155 }
156
157 bool kvm_allows_irq0_override(void)
158 {
159 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
160 }
161
162 static bool kvm_x2apic_api_set_flags(uint64_t flags)
163 {
164 KVMState *s = KVM_STATE(current_accel());
165
166 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
167 }
168
169 #define MEMORIZE(fn, _result) \
170 ({ \
171 static bool _memorized; \
172 \
173 if (_memorized) { \
174 return _result; \
175 } \
176 _memorized = true; \
177 _result = fn; \
178 })
179
180 static bool has_x2apic_api;
181
182 bool kvm_has_x2apic_api(void)
183 {
184 return has_x2apic_api;
185 }
186
187 bool kvm_enable_x2apic(void)
188 {
189 return MEMORIZE(
190 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
191 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
192 has_x2apic_api);
193 }
194
195 bool kvm_hv_vpindex_settable(void)
196 {
197 return hv_vpindex_settable;
198 }
199
200 static int kvm_get_tsc(CPUState *cs)
201 {
202 X86CPU *cpu = X86_CPU(cs);
203 CPUX86State *env = &cpu->env;
204 struct {
205 struct kvm_msrs info;
206 struct kvm_msr_entry entries[1];
207 } msr_data = {};
208 int ret;
209
210 if (env->tsc_valid) {
211 return 0;
212 }
213
214 memset(&msr_data, 0, sizeof(msr_data));
215 msr_data.info.nmsrs = 1;
216 msr_data.entries[0].index = MSR_IA32_TSC;
217 env->tsc_valid = !runstate_is_running();
218
219 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
220 if (ret < 0) {
221 return ret;
222 }
223
224 assert(ret == 1);
225 env->tsc = msr_data.entries[0].data;
226 return 0;
227 }
228
229 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
230 {
231 kvm_get_tsc(cpu);
232 }
233
234 void kvm_synchronize_all_tsc(void)
235 {
236 CPUState *cpu;
237
238 if (kvm_enabled()) {
239 CPU_FOREACH(cpu) {
240 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
241 }
242 }
243 }
244
245 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
246 {
247 struct kvm_cpuid2 *cpuid;
248 int r, size;
249
250 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
251 cpuid = g_malloc0(size);
252 cpuid->nent = max;
253 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
254 if (r == 0 && cpuid->nent >= max) {
255 r = -E2BIG;
256 }
257 if (r < 0) {
258 if (r == -E2BIG) {
259 g_free(cpuid);
260 return NULL;
261 } else {
262 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
263 strerror(-r));
264 exit(1);
265 }
266 }
267 return cpuid;
268 }
269
270 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
271 * for all entries.
272 */
273 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
274 {
275 struct kvm_cpuid2 *cpuid;
276 int max = 1;
277
278 if (cpuid_cache != NULL) {
279 return cpuid_cache;
280 }
281 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
282 max *= 2;
283 }
284 cpuid_cache = cpuid;
285 return cpuid;
286 }
287
288 static bool host_tsx_broken(void)
289 {
290 int family, model, stepping;\
291 char vendor[CPUID_VENDOR_SZ + 1];
292
293 host_vendor_fms(vendor, &family, &model, &stepping);
294
295 /* Check if we are running on a Haswell host known to have broken TSX */
296 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
297 (family == 6) &&
298 ((model == 63 && stepping < 4) ||
299 model == 60 || model == 69 || model == 70);
300 }
301
302 /* Returns the value for a specific register on the cpuid entry
303 */
304 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
305 {
306 uint32_t ret = 0;
307 switch (reg) {
308 case R_EAX:
309 ret = entry->eax;
310 break;
311 case R_EBX:
312 ret = entry->ebx;
313 break;
314 case R_ECX:
315 ret = entry->ecx;
316 break;
317 case R_EDX:
318 ret = entry->edx;
319 break;
320 }
321 return ret;
322 }
323
324 /* Find matching entry for function/index on kvm_cpuid2 struct
325 */
326 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
327 uint32_t function,
328 uint32_t index)
329 {
330 int i;
331 for (i = 0; i < cpuid->nent; ++i) {
332 if (cpuid->entries[i].function == function &&
333 cpuid->entries[i].index == index) {
334 return &cpuid->entries[i];
335 }
336 }
337 /* not found: */
338 return NULL;
339 }
340
341 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
342 uint32_t index, int reg)
343 {
344 struct kvm_cpuid2 *cpuid;
345 uint32_t ret = 0;
346 uint32_t cpuid_1_edx;
347
348 cpuid = get_supported_cpuid(s);
349
350 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
351 if (entry) {
352 ret = cpuid_entry_get_reg(entry, reg);
353 }
354
355 /* Fixups for the data returned by KVM, below */
356
357 if (function == 1 && reg == R_EDX) {
358 /* KVM before 2.6.30 misreports the following features */
359 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
360 } else if (function == 1 && reg == R_ECX) {
361 /* We can set the hypervisor flag, even if KVM does not return it on
362 * GET_SUPPORTED_CPUID
363 */
364 ret |= CPUID_EXT_HYPERVISOR;
365 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
366 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
367 * and the irqchip is in the kernel.
368 */
369 if (kvm_irqchip_in_kernel() &&
370 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
371 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
372 }
373
374 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
375 * without the in-kernel irqchip
376 */
377 if (!kvm_irqchip_in_kernel()) {
378 ret &= ~CPUID_EXT_X2APIC;
379 }
380
381 if (enable_cpu_pm) {
382 int disable_exits = kvm_check_extension(s,
383 KVM_CAP_X86_DISABLE_EXITS);
384
385 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
386 ret |= CPUID_EXT_MONITOR;
387 }
388 }
389 } else if (function == 6 && reg == R_EAX) {
390 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
391 } else if (function == 7 && index == 0 && reg == R_EBX) {
392 if (host_tsx_broken()) {
393 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
394 }
395 } else if (function == 7 && index == 0 && reg == R_EDX) {
396 /*
397 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
398 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
399 * returned by KVM_GET_MSR_INDEX_LIST.
400 */
401 if (!has_msr_arch_capabs) {
402 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
403 }
404 } else if (function == 0x80000001 && reg == R_ECX) {
405 /*
406 * It's safe to enable TOPOEXT even if it's not returned by
407 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
408 * us to keep CPU models including TOPOEXT runnable on older kernels.
409 */
410 ret |= CPUID_EXT3_TOPOEXT;
411 } else if (function == 0x80000001 && reg == R_EDX) {
412 /* On Intel, kvm returns cpuid according to the Intel spec,
413 * so add missing bits according to the AMD spec:
414 */
415 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
416 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
417 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
418 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
419 * be enabled without the in-kernel irqchip
420 */
421 if (!kvm_irqchip_in_kernel()) {
422 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
423 }
424 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
425 ret |= 1U << KVM_HINTS_REALTIME;
426 }
427
428 return ret;
429 }
430
431 uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
432 {
433 struct {
434 struct kvm_msrs info;
435 struct kvm_msr_entry entries[1];
436 } msr_data = {};
437 uint64_t value;
438 uint32_t ret, can_be_one, must_be_one;
439
440 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
441 return 0;
442 }
443
444 /* Check if requested MSR is supported feature MSR */
445 int i;
446 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
447 if (kvm_feature_msrs->indices[i] == index) {
448 break;
449 }
450 if (i == kvm_feature_msrs->nmsrs) {
451 return 0; /* if the feature MSR is not supported, simply return 0 */
452 }
453
454 msr_data.info.nmsrs = 1;
455 msr_data.entries[0].index = index;
456
457 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
458 if (ret != 1) {
459 error_report("KVM get MSR (index=0x%x) feature failed, %s",
460 index, strerror(-ret));
461 exit(1);
462 }
463
464 value = msr_data.entries[0].data;
465 switch (index) {
466 case MSR_IA32_VMX_PROCBASED_CTLS2:
467 if (!has_msr_vmx_procbased_ctls2) {
468 /* KVM forgot to add these bits for some time, do this ourselves. */
469 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
470 CPUID_XSAVE_XSAVES) {
471 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
472 }
473 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
474 CPUID_EXT_RDRAND) {
475 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
476 }
477 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
478 CPUID_7_0_EBX_INVPCID) {
479 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
480 }
481 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
482 CPUID_7_0_EBX_RDSEED) {
483 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
484 }
485 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
486 CPUID_EXT2_RDTSCP) {
487 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
488 }
489 }
490 /* fall through */
491 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
492 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
493 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
494 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
495 /*
496 * Return true for bits that can be one, but do not have to be one.
497 * The SDM tells us which bits could have a "must be one" setting,
498 * so we can do the opposite transformation in make_vmx_msr_value.
499 */
500 must_be_one = (uint32_t)value;
501 can_be_one = (uint32_t)(value >> 32);
502 return can_be_one & ~must_be_one;
503
504 default:
505 return value;
506 }
507 }
508
509 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
510 int *max_banks)
511 {
512 int r;
513
514 r = kvm_check_extension(s, KVM_CAP_MCE);
515 if (r > 0) {
516 *max_banks = r;
517 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
518 }
519 return -ENOSYS;
520 }
521
522 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
523 {
524 CPUState *cs = CPU(cpu);
525 CPUX86State *env = &cpu->env;
526 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
527 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
528 uint64_t mcg_status = MCG_STATUS_MCIP;
529 int flags = 0;
530
531 if (code == BUS_MCEERR_AR) {
532 status |= MCI_STATUS_AR | 0x134;
533 mcg_status |= MCG_STATUS_EIPV;
534 } else {
535 status |= 0xc0;
536 mcg_status |= MCG_STATUS_RIPV;
537 }
538
539 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
540 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
541 * guest kernel back into env->mcg_ext_ctl.
542 */
543 cpu_synchronize_state(cs);
544 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
545 mcg_status |= MCG_STATUS_LMCE;
546 flags = 0;
547 }
548
549 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
550 (MCM_ADDR_PHYS << 6) | 0xc, flags);
551 }
552
553 static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
554 {
555 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
556
557 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
558 &mff);
559 }
560
561 static void hardware_memory_error(void *host_addr)
562 {
563 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
564 error_report("QEMU got Hardware memory error at addr %p", host_addr);
565 exit(1);
566 }
567
568 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
569 {
570 X86CPU *cpu = X86_CPU(c);
571 CPUX86State *env = &cpu->env;
572 ram_addr_t ram_addr;
573 hwaddr paddr;
574
575 /* If we get an action required MCE, it has been injected by KVM
576 * while the VM was running. An action optional MCE instead should
577 * be coming from the main thread, which qemu_init_sigbus identifies
578 * as the "early kill" thread.
579 */
580 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
581
582 if ((env->mcg_cap & MCG_SER_P) && addr) {
583 ram_addr = qemu_ram_addr_from_host(addr);
584 if (ram_addr != RAM_ADDR_INVALID &&
585 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
586 kvm_hwpoison_page_add(ram_addr);
587 kvm_mce_inject(cpu, paddr, code);
588
589 /*
590 * Use different logging severity based on error type.
591 * If there is additional MCE reporting on the hypervisor, QEMU VA
592 * could be another source to identify the PA and MCE details.
593 */
594 if (code == BUS_MCEERR_AR) {
595 error_report("Guest MCE Memory Error at QEMU addr %p and "
596 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
597 addr, paddr, "BUS_MCEERR_AR");
598 } else {
599 warn_report("Guest MCE Memory Error at QEMU addr %p and "
600 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
601 addr, paddr, "BUS_MCEERR_AO");
602 }
603
604 return;
605 }
606
607 if (code == BUS_MCEERR_AO) {
608 warn_report("Hardware memory error at addr %p of type %s "
609 "for memory used by QEMU itself instead of guest system!",
610 addr, "BUS_MCEERR_AO");
611 }
612 }
613
614 if (code == BUS_MCEERR_AR) {
615 hardware_memory_error(addr);
616 }
617
618 /* Hope we are lucky for AO MCE, just notify a event */
619 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
620 }
621
622 static void kvm_reset_exception(CPUX86State *env)
623 {
624 env->exception_nr = -1;
625 env->exception_pending = 0;
626 env->exception_injected = 0;
627 env->exception_has_payload = false;
628 env->exception_payload = 0;
629 }
630
631 static void kvm_queue_exception(CPUX86State *env,
632 int32_t exception_nr,
633 uint8_t exception_has_payload,
634 uint64_t exception_payload)
635 {
636 assert(env->exception_nr == -1);
637 assert(!env->exception_pending);
638 assert(!env->exception_injected);
639 assert(!env->exception_has_payload);
640
641 env->exception_nr = exception_nr;
642
643 if (has_exception_payload) {
644 env->exception_pending = 1;
645
646 env->exception_has_payload = exception_has_payload;
647 env->exception_payload = exception_payload;
648 } else {
649 env->exception_injected = 1;
650
651 if (exception_nr == EXCP01_DB) {
652 assert(exception_has_payload);
653 env->dr[6] = exception_payload;
654 } else if (exception_nr == EXCP0E_PAGE) {
655 assert(exception_has_payload);
656 env->cr[2] = exception_payload;
657 } else {
658 assert(!exception_has_payload);
659 }
660 }
661 }
662
663 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
664 {
665 CPUX86State *env = &cpu->env;
666
667 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
668 unsigned int bank, bank_num = env->mcg_cap & 0xff;
669 struct kvm_x86_mce mce;
670
671 kvm_reset_exception(env);
672
673 /*
674 * There must be at least one bank in use if an MCE is pending.
675 * Find it and use its values for the event injection.
676 */
677 for (bank = 0; bank < bank_num; bank++) {
678 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
679 break;
680 }
681 }
682 assert(bank < bank_num);
683
684 mce.bank = bank;
685 mce.status = env->mce_banks[bank * 4 + 1];
686 mce.mcg_status = env->mcg_status;
687 mce.addr = env->mce_banks[bank * 4 + 2];
688 mce.misc = env->mce_banks[bank * 4 + 3];
689
690 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
691 }
692 return 0;
693 }
694
695 static void cpu_update_state(void *opaque, int running, RunState state)
696 {
697 CPUX86State *env = opaque;
698
699 if (running) {
700 env->tsc_valid = false;
701 }
702 }
703
704 unsigned long kvm_arch_vcpu_id(CPUState *cs)
705 {
706 X86CPU *cpu = X86_CPU(cs);
707 return cpu->apic_id;
708 }
709
710 #ifndef KVM_CPUID_SIGNATURE_NEXT
711 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
712 #endif
713
714 static bool hyperv_enabled(X86CPU *cpu)
715 {
716 CPUState *cs = CPU(cpu);
717 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
718 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
719 cpu->hyperv_features || cpu->hyperv_passthrough);
720 }
721
722 /*
723 * Check whether target_freq is within conservative
724 * ntp correctable bounds (250ppm) of freq
725 */
726 static inline bool freq_within_bounds(int freq, int target_freq)
727 {
728 int max_freq = freq + (freq * 250 / 1000000);
729 int min_freq = freq - (freq * 250 / 1000000);
730
731 if (target_freq >= min_freq && target_freq <= max_freq) {
732 return true;
733 }
734
735 return false;
736 }
737
738 static int kvm_arch_set_tsc_khz(CPUState *cs)
739 {
740 X86CPU *cpu = X86_CPU(cs);
741 CPUX86State *env = &cpu->env;
742 int r, cur_freq;
743 bool set_ioctl = false;
744
745 if (!env->tsc_khz) {
746 return 0;
747 }
748
749 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
750 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
751
752 /*
753 * If TSC scaling is supported, attempt to set TSC frequency.
754 */
755 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
756 set_ioctl = true;
757 }
758
759 /*
760 * If desired TSC frequency is within bounds of NTP correction,
761 * attempt to set TSC frequency.
762 */
763 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
764 set_ioctl = true;
765 }
766
767 r = set_ioctl ?
768 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
769 -ENOTSUP;
770
771 if (r < 0) {
772 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
773 * TSC frequency doesn't match the one we want.
774 */
775 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
776 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
777 -ENOTSUP;
778 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
779 warn_report("TSC frequency mismatch between "
780 "VM (%" PRId64 " kHz) and host (%d kHz), "
781 "and TSC scaling unavailable",
782 env->tsc_khz, cur_freq);
783 return r;
784 }
785 }
786
787 return 0;
788 }
789
790 static bool tsc_is_stable_and_known(CPUX86State *env)
791 {
792 if (!env->tsc_khz) {
793 return false;
794 }
795 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
796 || env->user_tsc_khz;
797 }
798
799 static struct {
800 const char *desc;
801 struct {
802 uint32_t fw;
803 uint32_t bits;
804 } flags[2];
805 uint64_t dependencies;
806 } kvm_hyperv_properties[] = {
807 [HYPERV_FEAT_RELAXED] = {
808 .desc = "relaxed timing (hv-relaxed)",
809 .flags = {
810 {.fw = FEAT_HYPERV_EAX,
811 .bits = HV_HYPERCALL_AVAILABLE},
812 {.fw = FEAT_HV_RECOMM_EAX,
813 .bits = HV_RELAXED_TIMING_RECOMMENDED}
814 }
815 },
816 [HYPERV_FEAT_VAPIC] = {
817 .desc = "virtual APIC (hv-vapic)",
818 .flags = {
819 {.fw = FEAT_HYPERV_EAX,
820 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
821 {.fw = FEAT_HV_RECOMM_EAX,
822 .bits = HV_APIC_ACCESS_RECOMMENDED}
823 }
824 },
825 [HYPERV_FEAT_TIME] = {
826 .desc = "clocksources (hv-time)",
827 .flags = {
828 {.fw = FEAT_HYPERV_EAX,
829 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
830 HV_REFERENCE_TSC_AVAILABLE}
831 }
832 },
833 [HYPERV_FEAT_CRASH] = {
834 .desc = "crash MSRs (hv-crash)",
835 .flags = {
836 {.fw = FEAT_HYPERV_EDX,
837 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
838 }
839 },
840 [HYPERV_FEAT_RESET] = {
841 .desc = "reset MSR (hv-reset)",
842 .flags = {
843 {.fw = FEAT_HYPERV_EAX,
844 .bits = HV_RESET_AVAILABLE}
845 }
846 },
847 [HYPERV_FEAT_VPINDEX] = {
848 .desc = "VP_INDEX MSR (hv-vpindex)",
849 .flags = {
850 {.fw = FEAT_HYPERV_EAX,
851 .bits = HV_VP_INDEX_AVAILABLE}
852 }
853 },
854 [HYPERV_FEAT_RUNTIME] = {
855 .desc = "VP_RUNTIME MSR (hv-runtime)",
856 .flags = {
857 {.fw = FEAT_HYPERV_EAX,
858 .bits = HV_VP_RUNTIME_AVAILABLE}
859 }
860 },
861 [HYPERV_FEAT_SYNIC] = {
862 .desc = "synthetic interrupt controller (hv-synic)",
863 .flags = {
864 {.fw = FEAT_HYPERV_EAX,
865 .bits = HV_SYNIC_AVAILABLE}
866 }
867 },
868 [HYPERV_FEAT_STIMER] = {
869 .desc = "synthetic timers (hv-stimer)",
870 .flags = {
871 {.fw = FEAT_HYPERV_EAX,
872 .bits = HV_SYNTIMERS_AVAILABLE}
873 },
874 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
875 },
876 [HYPERV_FEAT_FREQUENCIES] = {
877 .desc = "frequency MSRs (hv-frequencies)",
878 .flags = {
879 {.fw = FEAT_HYPERV_EAX,
880 .bits = HV_ACCESS_FREQUENCY_MSRS},
881 {.fw = FEAT_HYPERV_EDX,
882 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
883 }
884 },
885 [HYPERV_FEAT_REENLIGHTENMENT] = {
886 .desc = "reenlightenment MSRs (hv-reenlightenment)",
887 .flags = {
888 {.fw = FEAT_HYPERV_EAX,
889 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
890 }
891 },
892 [HYPERV_FEAT_TLBFLUSH] = {
893 .desc = "paravirtualized TLB flush (hv-tlbflush)",
894 .flags = {
895 {.fw = FEAT_HV_RECOMM_EAX,
896 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
897 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
898 },
899 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
900 },
901 [HYPERV_FEAT_EVMCS] = {
902 .desc = "enlightened VMCS (hv-evmcs)",
903 .flags = {
904 {.fw = FEAT_HV_RECOMM_EAX,
905 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
906 },
907 .dependencies = BIT(HYPERV_FEAT_VAPIC)
908 },
909 [HYPERV_FEAT_IPI] = {
910 .desc = "paravirtualized IPI (hv-ipi)",
911 .flags = {
912 {.fw = FEAT_HV_RECOMM_EAX,
913 .bits = HV_CLUSTER_IPI_RECOMMENDED |
914 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
915 },
916 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
917 },
918 [HYPERV_FEAT_STIMER_DIRECT] = {
919 .desc = "direct mode synthetic timers (hv-stimer-direct)",
920 .flags = {
921 {.fw = FEAT_HYPERV_EDX,
922 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
923 },
924 .dependencies = BIT(HYPERV_FEAT_STIMER)
925 },
926 };
927
928 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
929 {
930 struct kvm_cpuid2 *cpuid;
931 int r, size;
932
933 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
934 cpuid = g_malloc0(size);
935 cpuid->nent = max;
936
937 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
938 if (r == 0 && cpuid->nent >= max) {
939 r = -E2BIG;
940 }
941 if (r < 0) {
942 if (r == -E2BIG) {
943 g_free(cpuid);
944 return NULL;
945 } else {
946 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
947 strerror(-r));
948 exit(1);
949 }
950 }
951 return cpuid;
952 }
953
954 /*
955 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
956 * for all entries.
957 */
958 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
959 {
960 struct kvm_cpuid2 *cpuid;
961 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
962
963 /*
964 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
965 * -E2BIG, however, it doesn't report back the right size. Keep increasing
966 * it and re-trying until we succeed.
967 */
968 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
969 max++;
970 }
971 return cpuid;
972 }
973
974 /*
975 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
976 * leaves from KVM_CAP_HYPERV* and present MSRs data.
977 */
978 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
979 {
980 X86CPU *cpu = X86_CPU(cs);
981 struct kvm_cpuid2 *cpuid;
982 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
983
984 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
985 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
986 cpuid->nent = 2;
987
988 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
989 entry_feat = &cpuid->entries[0];
990 entry_feat->function = HV_CPUID_FEATURES;
991
992 entry_recomm = &cpuid->entries[1];
993 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
994 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
995
996 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
997 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
998 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
999 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1000 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1001 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1002 }
1003
1004 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1005 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1006 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
1007 }
1008
1009 if (has_msr_hv_frequencies) {
1010 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1011 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
1012 }
1013
1014 if (has_msr_hv_crash) {
1015 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
1016 }
1017
1018 if (has_msr_hv_reenlightenment) {
1019 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
1020 }
1021
1022 if (has_msr_hv_reset) {
1023 entry_feat->eax |= HV_RESET_AVAILABLE;
1024 }
1025
1026 if (has_msr_hv_vpindex) {
1027 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
1028 }
1029
1030 if (has_msr_hv_runtime) {
1031 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
1032 }
1033
1034 if (has_msr_hv_synic) {
1035 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1036 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1037
1038 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1039 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1040 }
1041 }
1042
1043 if (has_msr_hv_stimer) {
1044 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
1045 }
1046
1047 if (kvm_check_extension(cs->kvm_state,
1048 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1049 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1050 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1051 }
1052
1053 if (kvm_check_extension(cs->kvm_state,
1054 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1055 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1056 }
1057
1058 if (kvm_check_extension(cs->kvm_state,
1059 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1060 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1061 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1062 }
1063
1064 return cpuid;
1065 }
1066
1067 static int hv_cpuid_get_fw(struct kvm_cpuid2 *cpuid, int fw, uint32_t *r)
1068 {
1069 struct kvm_cpuid_entry2 *entry;
1070 uint32_t func;
1071 int reg;
1072
1073 switch (fw) {
1074 case FEAT_HYPERV_EAX:
1075 reg = R_EAX;
1076 func = HV_CPUID_FEATURES;
1077 break;
1078 case FEAT_HYPERV_EDX:
1079 reg = R_EDX;
1080 func = HV_CPUID_FEATURES;
1081 break;
1082 case FEAT_HV_RECOMM_EAX:
1083 reg = R_EAX;
1084 func = HV_CPUID_ENLIGHTMENT_INFO;
1085 break;
1086 default:
1087 return -EINVAL;
1088 }
1089
1090 entry = cpuid_find_entry(cpuid, func, 0);
1091 if (!entry) {
1092 return -ENOENT;
1093 }
1094
1095 switch (reg) {
1096 case R_EAX:
1097 *r = entry->eax;
1098 break;
1099 case R_EDX:
1100 *r = entry->edx;
1101 break;
1102 default:
1103 return -EINVAL;
1104 }
1105
1106 return 0;
1107 }
1108
1109 static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
1110 int feature)
1111 {
1112 X86CPU *cpu = X86_CPU(cs);
1113 CPUX86State *env = &cpu->env;
1114 uint32_t r, fw, bits;
1115 uint64_t deps;
1116 int i, dep_feat;
1117
1118 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
1119 return 0;
1120 }
1121
1122 deps = kvm_hyperv_properties[feature].dependencies;
1123 while (deps) {
1124 dep_feat = ctz64(deps);
1125 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1126 fprintf(stderr,
1127 "Hyper-V %s requires Hyper-V %s\n",
1128 kvm_hyperv_properties[feature].desc,
1129 kvm_hyperv_properties[dep_feat].desc);
1130 return 1;
1131 }
1132 deps &= ~(1ull << dep_feat);
1133 }
1134
1135 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1136 fw = kvm_hyperv_properties[feature].flags[i].fw;
1137 bits = kvm_hyperv_properties[feature].flags[i].bits;
1138
1139 if (!fw) {
1140 continue;
1141 }
1142
1143 if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) != bits) {
1144 if (hyperv_feat_enabled(cpu, feature)) {
1145 fprintf(stderr,
1146 "Hyper-V %s is not supported by kernel\n",
1147 kvm_hyperv_properties[feature].desc);
1148 return 1;
1149 } else {
1150 return 0;
1151 }
1152 }
1153
1154 env->features[fw] |= bits;
1155 }
1156
1157 if (cpu->hyperv_passthrough) {
1158 cpu->hyperv_features |= BIT(feature);
1159 }
1160
1161 return 0;
1162 }
1163
1164 /*
1165 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1166 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1167 * extentions are enabled.
1168 */
1169 static int hyperv_handle_properties(CPUState *cs,
1170 struct kvm_cpuid_entry2 *cpuid_ent)
1171 {
1172 X86CPU *cpu = X86_CPU(cs);
1173 CPUX86State *env = &cpu->env;
1174 struct kvm_cpuid2 *cpuid;
1175 struct kvm_cpuid_entry2 *c;
1176 uint32_t signature[3];
1177 uint32_t cpuid_i = 0;
1178 int r;
1179
1180 if (!hyperv_enabled(cpu))
1181 return 0;
1182
1183 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1184 cpu->hyperv_passthrough) {
1185 uint16_t evmcs_version;
1186
1187 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1188 (uintptr_t)&evmcs_version);
1189
1190 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
1191 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1192 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1193 return -ENOSYS;
1194 }
1195
1196 if (!r) {
1197 env->features[FEAT_HV_RECOMM_EAX] |=
1198 HV_ENLIGHTENED_VMCS_RECOMMENDED;
1199 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
1200 }
1201 }
1202
1203 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1204 cpuid = get_supported_hv_cpuid(cs);
1205 } else {
1206 cpuid = get_supported_hv_cpuid_legacy(cs);
1207 }
1208
1209 if (cpu->hyperv_passthrough) {
1210 memcpy(cpuid_ent, &cpuid->entries[0],
1211 cpuid->nent * sizeof(cpuid->entries[0]));
1212
1213 c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0);
1214 if (c) {
1215 env->features[FEAT_HYPERV_EAX] = c->eax;
1216 env->features[FEAT_HYPERV_EBX] = c->ebx;
1217 env->features[FEAT_HYPERV_EDX] = c->eax;
1218 }
1219 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1220 if (c) {
1221 env->features[FEAT_HV_RECOMM_EAX] = c->eax;
1222
1223 /* hv-spinlocks may have been overriden */
1224 if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) {
1225 c->ebx = cpu->hyperv_spinlock_attempts;
1226 }
1227 }
1228 c = cpuid_find_entry(cpuid, HV_CPUID_NESTED_FEATURES, 0);
1229 if (c) {
1230 env->features[FEAT_HV_NESTED_EAX] = c->eax;
1231 }
1232 }
1233
1234 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1235 env->features[FEAT_HV_RECOMM_EAX] |= HV_NO_NONARCH_CORESHARING;
1236 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
1237 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1238 if (c) {
1239 env->features[FEAT_HV_RECOMM_EAX] |=
1240 c->eax & HV_NO_NONARCH_CORESHARING;
1241 }
1242 }
1243
1244 /* Features */
1245 r = hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED);
1246 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC);
1247 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME);
1248 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH);
1249 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RESET);
1250 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VPINDEX);
1251 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RUNTIME);
1252 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_SYNIC);
1253 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER);
1254 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_FREQUENCIES);
1255 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_REENLIGHTENMENT);
1256 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH);
1257 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS);
1258 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI);
1259 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER_DIRECT);
1260
1261 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1262 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1263 !cpu->hyperv_synic_kvm_only &&
1264 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
1265 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
1266 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1267 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1268 r |= 1;
1269 }
1270
1271 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1272 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1273
1274 if (r) {
1275 r = -ENOSYS;
1276 goto free;
1277 }
1278
1279 if (cpu->hyperv_passthrough) {
1280 /* We already copied all feature words from KVM as is */
1281 r = cpuid->nent;
1282 goto free;
1283 }
1284
1285 c = &cpuid_ent[cpuid_i++];
1286 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1287 if (!cpu->hyperv_vendor_id) {
1288 memcpy(signature, "Microsoft Hv", 12);
1289 } else {
1290 size_t len = strlen(cpu->hyperv_vendor_id);
1291
1292 if (len > 12) {
1293 error_report("hv-vendor-id truncated to 12 characters");
1294 len = 12;
1295 }
1296 memset(signature, 0, 12);
1297 memcpy(signature, cpu->hyperv_vendor_id, len);
1298 }
1299 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1300 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1301 c->ebx = signature[0];
1302 c->ecx = signature[1];
1303 c->edx = signature[2];
1304
1305 c = &cpuid_ent[cpuid_i++];
1306 c->function = HV_CPUID_INTERFACE;
1307 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
1308 c->eax = signature[0];
1309 c->ebx = 0;
1310 c->ecx = 0;
1311 c->edx = 0;
1312
1313 c = &cpuid_ent[cpuid_i++];
1314 c->function = HV_CPUID_VERSION;
1315 c->eax = 0x00001bbc;
1316 c->ebx = 0x00060001;
1317
1318 c = &cpuid_ent[cpuid_i++];
1319 c->function = HV_CPUID_FEATURES;
1320 c->eax = env->features[FEAT_HYPERV_EAX];
1321 c->ebx = env->features[FEAT_HYPERV_EBX];
1322 c->edx = env->features[FEAT_HYPERV_EDX];
1323
1324 c = &cpuid_ent[cpuid_i++];
1325 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1326 c->eax = env->features[FEAT_HV_RECOMM_EAX];
1327 c->ebx = cpu->hyperv_spinlock_attempts;
1328
1329 c = &cpuid_ent[cpuid_i++];
1330 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1331 c->eax = cpu->hv_max_vps;
1332 c->ebx = 0x40;
1333
1334 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1335 __u32 function;
1336
1337 /* Create zeroed 0x40000006..0x40000009 leaves */
1338 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1339 function < HV_CPUID_NESTED_FEATURES; function++) {
1340 c = &cpuid_ent[cpuid_i++];
1341 c->function = function;
1342 }
1343
1344 c = &cpuid_ent[cpuid_i++];
1345 c->function = HV_CPUID_NESTED_FEATURES;
1346 c->eax = env->features[FEAT_HV_NESTED_EAX];
1347 }
1348 r = cpuid_i;
1349
1350 free:
1351 g_free(cpuid);
1352
1353 return r;
1354 }
1355
1356 static Error *hv_passthrough_mig_blocker;
1357 static Error *hv_no_nonarch_cs_mig_blocker;
1358
1359 static int hyperv_init_vcpu(X86CPU *cpu)
1360 {
1361 CPUState *cs = CPU(cpu);
1362 Error *local_err = NULL;
1363 int ret;
1364
1365 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1366 error_setg(&hv_passthrough_mig_blocker,
1367 "'hv-passthrough' CPU flag prevents migration, use explicit"
1368 " set of hv-* flags instead");
1369 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1370 if (local_err) {
1371 error_report_err(local_err);
1372 error_free(hv_passthrough_mig_blocker);
1373 return ret;
1374 }
1375 }
1376
1377 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1378 hv_no_nonarch_cs_mig_blocker == NULL) {
1379 error_setg(&hv_no_nonarch_cs_mig_blocker,
1380 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1381 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1382 " make sure SMT is disabled and/or that vCPUs are properly"
1383 " pinned)");
1384 ret = migrate_add_blocker(hv_no_nonarch_cs_mig_blocker, &local_err);
1385 if (local_err) {
1386 error_report_err(local_err);
1387 error_free(hv_no_nonarch_cs_mig_blocker);
1388 return ret;
1389 }
1390 }
1391
1392 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
1393 /*
1394 * the kernel doesn't support setting vp_index; assert that its value
1395 * is in sync
1396 */
1397 struct {
1398 struct kvm_msrs info;
1399 struct kvm_msr_entry entries[1];
1400 } msr_data = {
1401 .info.nmsrs = 1,
1402 .entries[0].index = HV_X64_MSR_VP_INDEX,
1403 };
1404
1405 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
1406 if (ret < 0) {
1407 return ret;
1408 }
1409 assert(ret == 1);
1410
1411 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
1412 error_report("kernel's vp_index != QEMU's vp_index");
1413 return -ENXIO;
1414 }
1415 }
1416
1417 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1418 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1419 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1420 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
1421 if (ret < 0) {
1422 error_report("failed to turn on HyperV SynIC in KVM: %s",
1423 strerror(-ret));
1424 return ret;
1425 }
1426
1427 if (!cpu->hyperv_synic_kvm_only) {
1428 ret = hyperv_x86_synic_add(cpu);
1429 if (ret < 0) {
1430 error_report("failed to create HyperV SynIC: %s",
1431 strerror(-ret));
1432 return ret;
1433 }
1434 }
1435 }
1436
1437 return 0;
1438 }
1439
1440 static Error *invtsc_mig_blocker;
1441
1442 #define KVM_MAX_CPUID_ENTRIES 100
1443
1444 int kvm_arch_init_vcpu(CPUState *cs)
1445 {
1446 struct {
1447 struct kvm_cpuid2 cpuid;
1448 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
1449 } cpuid_data;
1450 /*
1451 * The kernel defines these structs with padding fields so there
1452 * should be no extra padding in our cpuid_data struct.
1453 */
1454 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1455 sizeof(struct kvm_cpuid2) +
1456 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1457
1458 X86CPU *cpu = X86_CPU(cs);
1459 CPUX86State *env = &cpu->env;
1460 uint32_t limit, i, j, cpuid_i;
1461 uint32_t unused;
1462 struct kvm_cpuid_entry2 *c;
1463 uint32_t signature[3];
1464 int kvm_base = KVM_CPUID_SIGNATURE;
1465 int max_nested_state_len;
1466 int r;
1467 Error *local_err = NULL;
1468
1469 memset(&cpuid_data, 0, sizeof(cpuid_data));
1470
1471 cpuid_i = 0;
1472
1473 r = kvm_arch_set_tsc_khz(cs);
1474 if (r < 0) {
1475 return r;
1476 }
1477
1478 /* vcpu's TSC frequency is either specified by user, or following
1479 * the value used by KVM if the former is not present. In the
1480 * latter case, we query it from KVM and record in env->tsc_khz,
1481 * so that vcpu's TSC frequency can be migrated later via this field.
1482 */
1483 if (!env->tsc_khz) {
1484 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1485 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1486 -ENOTSUP;
1487 if (r > 0) {
1488 env->tsc_khz = r;
1489 }
1490 }
1491
1492 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
1493
1494 /* Paravirtualization CPUIDs */
1495 r = hyperv_handle_properties(cs, cpuid_data.entries);
1496 if (r < 0) {
1497 return r;
1498 } else if (r > 0) {
1499 cpuid_i = r;
1500 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
1501 has_msr_hv_hypercall = true;
1502 }
1503
1504 if (cpu->expose_kvm) {
1505 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1506 c = &cpuid_data.entries[cpuid_i++];
1507 c->function = KVM_CPUID_SIGNATURE | kvm_base;
1508 c->eax = KVM_CPUID_FEATURES | kvm_base;
1509 c->ebx = signature[0];
1510 c->ecx = signature[1];
1511 c->edx = signature[2];
1512
1513 c = &cpuid_data.entries[cpuid_i++];
1514 c->function = KVM_CPUID_FEATURES | kvm_base;
1515 c->eax = env->features[FEAT_KVM];
1516 c->edx = env->features[FEAT_KVM_HINTS];
1517 }
1518
1519 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1520
1521 for (i = 0; i <= limit; i++) {
1522 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1523 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1524 abort();
1525 }
1526 c = &cpuid_data.entries[cpuid_i++];
1527
1528 switch (i) {
1529 case 2: {
1530 /* Keep reading function 2 till all the input is received */
1531 int times;
1532
1533 c->function = i;
1534 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1535 KVM_CPUID_FLAG_STATE_READ_NEXT;
1536 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1537 times = c->eax & 0xff;
1538
1539 for (j = 1; j < times; ++j) {
1540 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1541 fprintf(stderr, "cpuid_data is full, no space for "
1542 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1543 abort();
1544 }
1545 c = &cpuid_data.entries[cpuid_i++];
1546 c->function = i;
1547 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1548 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1549 }
1550 break;
1551 }
1552 case 0x1f:
1553 if (env->nr_dies < 2) {
1554 break;
1555 }
1556 /* fallthrough */
1557 case 4:
1558 case 0xb:
1559 case 0xd:
1560 for (j = 0; ; j++) {
1561 if (i == 0xd && j == 64) {
1562 break;
1563 }
1564
1565 if (i == 0x1f && j == 64) {
1566 break;
1567 }
1568
1569 c->function = i;
1570 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1571 c->index = j;
1572 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1573
1574 if (i == 4 && c->eax == 0) {
1575 break;
1576 }
1577 if (i == 0xb && !(c->ecx & 0xff00)) {
1578 break;
1579 }
1580 if (i == 0x1f && !(c->ecx & 0xff00)) {
1581 break;
1582 }
1583 if (i == 0xd && c->eax == 0) {
1584 continue;
1585 }
1586 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1587 fprintf(stderr, "cpuid_data is full, no space for "
1588 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1589 abort();
1590 }
1591 c = &cpuid_data.entries[cpuid_i++];
1592 }
1593 break;
1594 case 0x7:
1595 case 0x14: {
1596 uint32_t times;
1597
1598 c->function = i;
1599 c->index = 0;
1600 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1601 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1602 times = c->eax;
1603
1604 for (j = 1; j <= times; ++j) {
1605 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1606 fprintf(stderr, "cpuid_data is full, no space for "
1607 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1608 abort();
1609 }
1610 c = &cpuid_data.entries[cpuid_i++];
1611 c->function = i;
1612 c->index = j;
1613 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1614 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1615 }
1616 break;
1617 }
1618 default:
1619 c->function = i;
1620 c->flags = 0;
1621 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1622 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1623 /*
1624 * KVM already returns all zeroes if a CPUID entry is missing,
1625 * so we can omit it and avoid hitting KVM's 80-entry limit.
1626 */
1627 cpuid_i--;
1628 }
1629 break;
1630 }
1631 }
1632
1633 if (limit >= 0x0a) {
1634 uint32_t eax, edx;
1635
1636 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1637
1638 has_architectural_pmu_version = eax & 0xff;
1639 if (has_architectural_pmu_version > 0) {
1640 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1641
1642 /* Shouldn't be more than 32, since that's the number of bits
1643 * available in EBX to tell us _which_ counters are available.
1644 * Play it safe.
1645 */
1646 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1647 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1648 }
1649
1650 if (has_architectural_pmu_version > 1) {
1651 num_architectural_pmu_fixed_counters = edx & 0x1f;
1652
1653 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1654 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1655 }
1656 }
1657 }
1658 }
1659
1660 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1661
1662 for (i = 0x80000000; i <= limit; i++) {
1663 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1664 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1665 abort();
1666 }
1667 c = &cpuid_data.entries[cpuid_i++];
1668
1669 switch (i) {
1670 case 0x8000001d:
1671 /* Query for all AMD cache information leaves */
1672 for (j = 0; ; j++) {
1673 c->function = i;
1674 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1675 c->index = j;
1676 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1677
1678 if (c->eax == 0) {
1679 break;
1680 }
1681 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1682 fprintf(stderr, "cpuid_data is full, no space for "
1683 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1684 abort();
1685 }
1686 c = &cpuid_data.entries[cpuid_i++];
1687 }
1688 break;
1689 default:
1690 c->function = i;
1691 c->flags = 0;
1692 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1693 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1694 /*
1695 * KVM already returns all zeroes if a CPUID entry is missing,
1696 * so we can omit it and avoid hitting KVM's 80-entry limit.
1697 */
1698 cpuid_i--;
1699 }
1700 break;
1701 }
1702 }
1703
1704 /* Call Centaur's CPUID instructions they are supported. */
1705 if (env->cpuid_xlevel2 > 0) {
1706 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1707
1708 for (i = 0xC0000000; i <= limit; i++) {
1709 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1710 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1711 abort();
1712 }
1713 c = &cpuid_data.entries[cpuid_i++];
1714
1715 c->function = i;
1716 c->flags = 0;
1717 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1718 }
1719 }
1720
1721 cpuid_data.cpuid.nent = cpuid_i;
1722
1723 if (((env->cpuid_version >> 8)&0xF) >= 6
1724 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1725 (CPUID_MCE | CPUID_MCA)
1726 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1727 uint64_t mcg_cap, unsupported_caps;
1728 int banks;
1729 int ret;
1730
1731 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1732 if (ret < 0) {
1733 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1734 return ret;
1735 }
1736
1737 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1738 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1739 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1740 return -ENOTSUP;
1741 }
1742
1743 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1744 if (unsupported_caps) {
1745 if (unsupported_caps & MCG_LMCE_P) {
1746 error_report("kvm: LMCE not supported");
1747 return -ENOTSUP;
1748 }
1749 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1750 unsupported_caps);
1751 }
1752
1753 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1754 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1755 if (ret < 0) {
1756 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1757 return ret;
1758 }
1759 }
1760
1761 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
1762
1763 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1764 if (c) {
1765 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1766 !!(c->ecx & CPUID_EXT_SMX);
1767 }
1768
1769 if (env->mcg_cap & MCG_LMCE_P) {
1770 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1771 }
1772
1773 if (!env->user_tsc_khz) {
1774 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1775 invtsc_mig_blocker == NULL) {
1776 error_setg(&invtsc_mig_blocker,
1777 "State blocked by non-migratable CPU device"
1778 " (invtsc flag)");
1779 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1780 if (local_err) {
1781 error_report_err(local_err);
1782 error_free(invtsc_mig_blocker);
1783 return r;
1784 }
1785 }
1786 }
1787
1788 if (cpu->vmware_cpuid_freq
1789 /* Guests depend on 0x40000000 to detect this feature, so only expose
1790 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1791 && cpu->expose_kvm
1792 && kvm_base == KVM_CPUID_SIGNATURE
1793 /* TSC clock must be stable and known for this feature. */
1794 && tsc_is_stable_and_known(env)) {
1795
1796 c = &cpuid_data.entries[cpuid_i++];
1797 c->function = KVM_CPUID_SIGNATURE | 0x10;
1798 c->eax = env->tsc_khz;
1799 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
1800 c->ecx = c->edx = 0;
1801
1802 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1803 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1804 }
1805
1806 cpuid_data.cpuid.nent = cpuid_i;
1807
1808 cpuid_data.cpuid.padding = 0;
1809 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1810 if (r) {
1811 goto fail;
1812 }
1813
1814 if (has_xsave) {
1815 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1816 memset(env->xsave_buf, 0, sizeof(struct kvm_xsave));
1817 }
1818
1819 max_nested_state_len = kvm_max_nested_state_length();
1820 if (max_nested_state_len > 0) {
1821 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
1822
1823 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
1824 struct kvm_vmx_nested_state_hdr *vmx_hdr;
1825
1826 env->nested_state = g_malloc0(max_nested_state_len);
1827 env->nested_state->size = max_nested_state_len;
1828 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1829
1830 if (cpu_has_vmx(env)) {
1831 vmx_hdr = &env->nested_state->hdr.vmx;
1832 vmx_hdr->vmxon_pa = -1ull;
1833 vmx_hdr->vmcs12_pa = -1ull;
1834 }
1835 }
1836 }
1837
1838 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1839
1840 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1841 has_msr_tsc_aux = false;
1842 }
1843
1844 kvm_init_msrs(cpu);
1845
1846 r = hyperv_init_vcpu(cpu);
1847 if (r) {
1848 goto fail;
1849 }
1850
1851 return 0;
1852
1853 fail:
1854 migrate_del_blocker(invtsc_mig_blocker);
1855
1856 return r;
1857 }
1858
1859 int kvm_arch_destroy_vcpu(CPUState *cs)
1860 {
1861 X86CPU *cpu = X86_CPU(cs);
1862 CPUX86State *env = &cpu->env;
1863
1864 if (cpu->kvm_msr_buf) {
1865 g_free(cpu->kvm_msr_buf);
1866 cpu->kvm_msr_buf = NULL;
1867 }
1868
1869 if (env->nested_state) {
1870 g_free(env->nested_state);
1871 env->nested_state = NULL;
1872 }
1873
1874 qemu_del_vm_change_state_handler(cpu->vmsentry);
1875
1876 return 0;
1877 }
1878
1879 void kvm_arch_reset_vcpu(X86CPU *cpu)
1880 {
1881 CPUX86State *env = &cpu->env;
1882
1883 env->xcr0 = 1;
1884 if (kvm_irqchip_in_kernel()) {
1885 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1886 KVM_MP_STATE_UNINITIALIZED;
1887 } else {
1888 env->mp_state = KVM_MP_STATE_RUNNABLE;
1889 }
1890
1891 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1892 int i;
1893 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1894 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1895 }
1896
1897 hyperv_x86_synic_reset(cpu);
1898 }
1899 /* enabled by default */
1900 env->poll_control_msr = 1;
1901 }
1902
1903 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1904 {
1905 CPUX86State *env = &cpu->env;
1906
1907 /* APs get directly into wait-for-SIPI state. */
1908 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1909 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1910 }
1911 }
1912
1913 static int kvm_get_supported_feature_msrs(KVMState *s)
1914 {
1915 int ret = 0;
1916
1917 if (kvm_feature_msrs != NULL) {
1918 return 0;
1919 }
1920
1921 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1922 return 0;
1923 }
1924
1925 struct kvm_msr_list msr_list;
1926
1927 msr_list.nmsrs = 0;
1928 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1929 if (ret < 0 && ret != -E2BIG) {
1930 error_report("Fetch KVM feature MSR list failed: %s",
1931 strerror(-ret));
1932 return ret;
1933 }
1934
1935 assert(msr_list.nmsrs > 0);
1936 kvm_feature_msrs = (struct kvm_msr_list *) \
1937 g_malloc0(sizeof(msr_list) +
1938 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1939
1940 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1941 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1942
1943 if (ret < 0) {
1944 error_report("Fetch KVM feature MSR list failed: %s",
1945 strerror(-ret));
1946 g_free(kvm_feature_msrs);
1947 kvm_feature_msrs = NULL;
1948 return ret;
1949 }
1950
1951 return 0;
1952 }
1953
1954 static int kvm_get_supported_msrs(KVMState *s)
1955 {
1956 int ret = 0;
1957 struct kvm_msr_list msr_list, *kvm_msr_list;
1958
1959 /*
1960 * Obtain MSR list from KVM. These are the MSRs that we must
1961 * save/restore.
1962 */
1963 msr_list.nmsrs = 0;
1964 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1965 if (ret < 0 && ret != -E2BIG) {
1966 return ret;
1967 }
1968 /*
1969 * Old kernel modules had a bug and could write beyond the provided
1970 * memory. Allocate at least a safe amount of 1K.
1971 */
1972 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1973 msr_list.nmsrs *
1974 sizeof(msr_list.indices[0])));
1975
1976 kvm_msr_list->nmsrs = msr_list.nmsrs;
1977 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1978 if (ret >= 0) {
1979 int i;
1980
1981 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1982 switch (kvm_msr_list->indices[i]) {
1983 case MSR_STAR:
1984 has_msr_star = true;
1985 break;
1986 case MSR_VM_HSAVE_PA:
1987 has_msr_hsave_pa = true;
1988 break;
1989 case MSR_TSC_AUX:
1990 has_msr_tsc_aux = true;
1991 break;
1992 case MSR_TSC_ADJUST:
1993 has_msr_tsc_adjust = true;
1994 break;
1995 case MSR_IA32_TSCDEADLINE:
1996 has_msr_tsc_deadline = true;
1997 break;
1998 case MSR_IA32_SMBASE:
1999 has_msr_smbase = true;
2000 break;
2001 case MSR_SMI_COUNT:
2002 has_msr_smi_count = true;
2003 break;
2004 case MSR_IA32_MISC_ENABLE:
2005 has_msr_misc_enable = true;
2006 break;
2007 case MSR_IA32_BNDCFGS:
2008 has_msr_bndcfgs = true;
2009 break;
2010 case MSR_IA32_XSS:
2011 has_msr_xss = true;
2012 break;
2013 case MSR_IA32_UMWAIT_CONTROL:
2014 has_msr_umwait = true;
2015 break;
2016 case HV_X64_MSR_CRASH_CTL:
2017 has_msr_hv_crash = true;
2018 break;
2019 case HV_X64_MSR_RESET:
2020 has_msr_hv_reset = true;
2021 break;
2022 case HV_X64_MSR_VP_INDEX:
2023 has_msr_hv_vpindex = true;
2024 break;
2025 case HV_X64_MSR_VP_RUNTIME:
2026 has_msr_hv_runtime = true;
2027 break;
2028 case HV_X64_MSR_SCONTROL:
2029 has_msr_hv_synic = true;
2030 break;
2031 case HV_X64_MSR_STIMER0_CONFIG:
2032 has_msr_hv_stimer = true;
2033 break;
2034 case HV_X64_MSR_TSC_FREQUENCY:
2035 has_msr_hv_frequencies = true;
2036 break;
2037 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2038 has_msr_hv_reenlightenment = true;
2039 break;
2040 case MSR_IA32_SPEC_CTRL:
2041 has_msr_spec_ctrl = true;
2042 break;
2043 case MSR_IA32_TSX_CTRL:
2044 has_msr_tsx_ctrl = true;
2045 break;
2046 case MSR_VIRT_SSBD:
2047 has_msr_virt_ssbd = true;
2048 break;
2049 case MSR_IA32_ARCH_CAPABILITIES:
2050 has_msr_arch_capabs = true;
2051 break;
2052 case MSR_IA32_CORE_CAPABILITY:
2053 has_msr_core_capabs = true;
2054 break;
2055 case MSR_IA32_PERF_CAPABILITIES:
2056 has_msr_perf_capabs = true;
2057 break;
2058 case MSR_IA32_VMX_VMFUNC:
2059 has_msr_vmx_vmfunc = true;
2060 break;
2061 case MSR_IA32_UCODE_REV:
2062 has_msr_ucode_rev = true;
2063 break;
2064 case MSR_IA32_VMX_PROCBASED_CTLS2:
2065 has_msr_vmx_procbased_ctls2 = true;
2066 break;
2067 }
2068 }
2069 }
2070
2071 g_free(kvm_msr_list);
2072
2073 return ret;
2074 }
2075
2076 static Notifier smram_machine_done;
2077 static KVMMemoryListener smram_listener;
2078 static AddressSpace smram_address_space;
2079 static MemoryRegion smram_as_root;
2080 static MemoryRegion smram_as_mem;
2081
2082 static void register_smram_listener(Notifier *n, void *unused)
2083 {
2084 MemoryRegion *smram =
2085 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2086
2087 /* Outer container... */
2088 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2089 memory_region_set_enabled(&smram_as_root, true);
2090
2091 /* ... with two regions inside: normal system memory with low
2092 * priority, and...
2093 */
2094 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2095 get_system_memory(), 0, ~0ull);
2096 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2097 memory_region_set_enabled(&smram_as_mem, true);
2098
2099 if (smram) {
2100 /* ... SMRAM with higher priority */
2101 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2102 memory_region_set_enabled(smram, true);
2103 }
2104
2105 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2106 kvm_memory_listener_register(kvm_state, &smram_listener,
2107 &smram_address_space, 1);
2108 }
2109
2110 int kvm_arch_init(MachineState *ms, KVMState *s)
2111 {
2112 uint64_t identity_base = 0xfffbc000;
2113 uint64_t shadow_mem;
2114 int ret;
2115 struct utsname utsname;
2116
2117 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
2118 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
2119 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
2120
2121 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
2122
2123 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
2124 if (has_exception_payload) {
2125 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2126 if (ret < 0) {
2127 error_report("kvm: Failed to enable exception payload cap: %s",
2128 strerror(-ret));
2129 return ret;
2130 }
2131 }
2132
2133 ret = kvm_get_supported_msrs(s);
2134 if (ret < 0) {
2135 return ret;
2136 }
2137
2138 kvm_get_supported_feature_msrs(s);
2139
2140 uname(&utsname);
2141 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2142
2143 /*
2144 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2145 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2146 * Since these must be part of guest physical memory, we need to allocate
2147 * them, both by setting their start addresses in the kernel and by
2148 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2149 *
2150 * Older KVM versions may not support setting the identity map base. In
2151 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2152 * size.
2153 */
2154 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2155 /* Allows up to 16M BIOSes. */
2156 identity_base = 0xfeffc000;
2157
2158 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2159 if (ret < 0) {
2160 return ret;
2161 }
2162 }
2163
2164 /* Set TSS base one page after EPT identity map. */
2165 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
2166 if (ret < 0) {
2167 return ret;
2168 }
2169
2170 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2171 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
2172 if (ret < 0) {
2173 fprintf(stderr, "e820_add_entry() table is full\n");
2174 return ret;
2175 }
2176
2177 shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort);
2178 if (shadow_mem != -1) {
2179 shadow_mem /= 4096;
2180 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2181 if (ret < 0) {
2182 return ret;
2183 }
2184 }
2185
2186 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
2187 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
2188 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
2189 smram_machine_done.notify = register_smram_listener;
2190 qemu_add_machine_init_done_notifier(&smram_machine_done);
2191 }
2192
2193 if (enable_cpu_pm) {
2194 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2195 int ret;
2196
2197 /* Work around for kernel header with a typo. TODO: fix header and drop. */
2198 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2199 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2200 #endif
2201 if (disable_exits) {
2202 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2203 KVM_X86_DISABLE_EXITS_HLT |
2204 KVM_X86_DISABLE_EXITS_PAUSE |
2205 KVM_X86_DISABLE_EXITS_CSTATE);
2206 }
2207
2208 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2209 disable_exits);
2210 if (ret < 0) {
2211 error_report("kvm: guest stopping CPU not supported: %s",
2212 strerror(-ret));
2213 }
2214 }
2215
2216 return 0;
2217 }
2218
2219 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2220 {
2221 lhs->selector = rhs->selector;
2222 lhs->base = rhs->base;
2223 lhs->limit = rhs->limit;
2224 lhs->type = 3;
2225 lhs->present = 1;
2226 lhs->dpl = 3;
2227 lhs->db = 0;
2228 lhs->s = 1;
2229 lhs->l = 0;
2230 lhs->g = 0;
2231 lhs->avl = 0;
2232 lhs->unusable = 0;
2233 }
2234
2235 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2236 {
2237 unsigned flags = rhs->flags;
2238 lhs->selector = rhs->selector;
2239 lhs->base = rhs->base;
2240 lhs->limit = rhs->limit;
2241 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2242 lhs->present = (flags & DESC_P_MASK) != 0;
2243 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
2244 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2245 lhs->s = (flags & DESC_S_MASK) != 0;
2246 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2247 lhs->g = (flags & DESC_G_MASK) != 0;
2248 lhs->avl = (flags & DESC_AVL_MASK) != 0;
2249 lhs->unusable = !lhs->present;
2250 lhs->padding = 0;
2251 }
2252
2253 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2254 {
2255 lhs->selector = rhs->selector;
2256 lhs->base = rhs->base;
2257 lhs->limit = rhs->limit;
2258 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2259 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2260 (rhs->dpl << DESC_DPL_SHIFT) |
2261 (rhs->db << DESC_B_SHIFT) |
2262 (rhs->s * DESC_S_MASK) |
2263 (rhs->l << DESC_L_SHIFT) |
2264 (rhs->g * DESC_G_MASK) |
2265 (rhs->avl * DESC_AVL_MASK);
2266 }
2267
2268 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2269 {
2270 if (set) {
2271 *kvm_reg = *qemu_reg;
2272 } else {
2273 *qemu_reg = *kvm_reg;
2274 }
2275 }
2276
2277 static int kvm_getput_regs(X86CPU *cpu, int set)
2278 {
2279 CPUX86State *env = &cpu->env;
2280 struct kvm_regs regs;
2281 int ret = 0;
2282
2283 if (!set) {
2284 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
2285 if (ret < 0) {
2286 return ret;
2287 }
2288 }
2289
2290 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2291 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2292 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2293 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2294 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2295 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2296 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2297 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2298 #ifdef TARGET_X86_64
2299 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2300 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2301 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2302 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2303 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2304 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2305 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2306 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2307 #endif
2308
2309 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2310 kvm_getput_reg(&regs.rip, &env->eip, set);
2311
2312 if (set) {
2313 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
2314 }
2315
2316 return ret;
2317 }
2318
2319 static int kvm_put_fpu(X86CPU *cpu)
2320 {
2321 CPUX86State *env = &cpu->env;
2322 struct kvm_fpu fpu;
2323 int i;
2324
2325 memset(&fpu, 0, sizeof fpu);
2326 fpu.fsw = env->fpus & ~(7 << 11);
2327 fpu.fsw |= (env->fpstt & 7) << 11;
2328 fpu.fcw = env->fpuc;
2329 fpu.last_opcode = env->fpop;
2330 fpu.last_ip = env->fpip;
2331 fpu.last_dp = env->fpdp;
2332 for (i = 0; i < 8; ++i) {
2333 fpu.ftwx |= (!env->fptags[i]) << i;
2334 }
2335 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
2336 for (i = 0; i < CPU_NB_REGS; i++) {
2337 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2338 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
2339 }
2340 fpu.mxcsr = env->mxcsr;
2341
2342 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
2343 }
2344
2345 #define XSAVE_FCW_FSW 0
2346 #define XSAVE_FTW_FOP 1
2347 #define XSAVE_CWD_RIP 2
2348 #define XSAVE_CWD_RDP 4
2349 #define XSAVE_MXCSR 6
2350 #define XSAVE_ST_SPACE 8
2351 #define XSAVE_XMM_SPACE 40
2352 #define XSAVE_XSTATE_BV 128
2353 #define XSAVE_YMMH_SPACE 144
2354 #define XSAVE_BNDREGS 240
2355 #define XSAVE_BNDCSR 256
2356 #define XSAVE_OPMASK 272
2357 #define XSAVE_ZMM_Hi256 288
2358 #define XSAVE_Hi16_ZMM 416
2359 #define XSAVE_PKRU 672
2360
2361 #define XSAVE_BYTE_OFFSET(word_offset) \
2362 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
2363
2364 #define ASSERT_OFFSET(word_offset, field) \
2365 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2366 offsetof(X86XSaveArea, field))
2367
2368 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2369 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2370 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2371 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2372 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2373 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2374 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2375 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2376 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2377 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2378 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2379 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2380 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2381 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2382 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2383
2384 static int kvm_put_xsave(X86CPU *cpu)
2385 {
2386 CPUX86State *env = &cpu->env;
2387 X86XSaveArea *xsave = env->xsave_buf;
2388
2389 if (!has_xsave) {
2390 return kvm_put_fpu(cpu);
2391 }
2392 x86_cpu_xsave_all_areas(cpu, xsave);
2393
2394 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
2395 }
2396
2397 static int kvm_put_xcrs(X86CPU *cpu)
2398 {
2399 CPUX86State *env = &cpu->env;
2400 struct kvm_xcrs xcrs = {};
2401
2402 if (!has_xcrs) {
2403 return 0;
2404 }
2405
2406 xcrs.nr_xcrs = 1;
2407 xcrs.flags = 0;
2408 xcrs.xcrs[0].xcr = 0;
2409 xcrs.xcrs[0].value = env->xcr0;
2410 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
2411 }
2412
2413 static int kvm_put_sregs(X86CPU *cpu)
2414 {
2415 CPUX86State *env = &cpu->env;
2416 struct kvm_sregs sregs;
2417
2418 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2419 if (env->interrupt_injected >= 0) {
2420 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2421 (uint64_t)1 << (env->interrupt_injected % 64);
2422 }
2423
2424 if ((env->eflags & VM_MASK)) {
2425 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2426 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2427 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2428 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2429 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2430 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
2431 } else {
2432 set_seg(&sregs.cs, &env->segs[R_CS]);
2433 set_seg(&sregs.ds, &env->segs[R_DS]);
2434 set_seg(&sregs.es, &env->segs[R_ES]);
2435 set_seg(&sregs.fs, &env->segs[R_FS]);
2436 set_seg(&sregs.gs, &env->segs[R_GS]);
2437 set_seg(&sregs.ss, &env->segs[R_SS]);
2438 }
2439
2440 set_seg(&sregs.tr, &env->tr);
2441 set_seg(&sregs.ldt, &env->ldt);
2442
2443 sregs.idt.limit = env->idt.limit;
2444 sregs.idt.base = env->idt.base;
2445 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
2446 sregs.gdt.limit = env->gdt.limit;
2447 sregs.gdt.base = env->gdt.base;
2448 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
2449
2450 sregs.cr0 = env->cr[0];
2451 sregs.cr2 = env->cr[2];
2452 sregs.cr3 = env->cr[3];
2453 sregs.cr4 = env->cr[4];
2454
2455 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2456 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
2457
2458 sregs.efer = env->efer;
2459
2460 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
2461 }
2462
2463 static void kvm_msr_buf_reset(X86CPU *cpu)
2464 {
2465 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2466 }
2467
2468 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2469 {
2470 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2471 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2472 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2473
2474 assert((void *)(entry + 1) <= limit);
2475
2476 entry->index = index;
2477 entry->reserved = 0;
2478 entry->data = value;
2479 msrs->nmsrs++;
2480 }
2481
2482 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2483 {
2484 kvm_msr_buf_reset(cpu);
2485 kvm_msr_entry_add(cpu, index, value);
2486
2487 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2488 }
2489
2490 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2491 {
2492 int ret;
2493
2494 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2495 assert(ret == 1);
2496 }
2497
2498 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2499 {
2500 CPUX86State *env = &cpu->env;
2501 int ret;
2502
2503 if (!has_msr_tsc_deadline) {
2504 return 0;
2505 }
2506
2507 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
2508 if (ret < 0) {
2509 return ret;
2510 }
2511
2512 assert(ret == 1);
2513 return 0;
2514 }
2515
2516 /*
2517 * Provide a separate write service for the feature control MSR in order to
2518 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2519 * before writing any other state because forcibly leaving nested mode
2520 * invalidates the VCPU state.
2521 */
2522 static int kvm_put_msr_feature_control(X86CPU *cpu)
2523 {
2524 int ret;
2525
2526 if (!has_msr_feature_control) {
2527 return 0;
2528 }
2529
2530 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2531 cpu->env.msr_ia32_feature_control);
2532 if (ret < 0) {
2533 return ret;
2534 }
2535
2536 assert(ret == 1);
2537 return 0;
2538 }
2539
2540 static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
2541 {
2542 uint32_t default1, can_be_one, can_be_zero;
2543 uint32_t must_be_one;
2544
2545 switch (index) {
2546 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2547 default1 = 0x00000016;
2548 break;
2549 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2550 default1 = 0x0401e172;
2551 break;
2552 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2553 default1 = 0x000011ff;
2554 break;
2555 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2556 default1 = 0x00036dff;
2557 break;
2558 case MSR_IA32_VMX_PROCBASED_CTLS2:
2559 default1 = 0;
2560 break;
2561 default:
2562 abort();
2563 }
2564
2565 /* If a feature bit is set, the control can be either set or clear.
2566 * Otherwise the value is limited to either 0 or 1 by default1.
2567 */
2568 can_be_one = features | default1;
2569 can_be_zero = features | ~default1;
2570 must_be_one = ~can_be_zero;
2571
2572 /*
2573 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
2574 * Bit 32:63 -> 1 if the control bit can be one.
2575 */
2576 return must_be_one | (((uint64_t)can_be_one) << 32);
2577 }
2578
2579 #define VMCS12_MAX_FIELD_INDEX (0x17)
2580
2581 static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
2582 {
2583 uint64_t kvm_vmx_basic =
2584 kvm_arch_get_supported_msr_feature(kvm_state,
2585 MSR_IA32_VMX_BASIC);
2586
2587 if (!kvm_vmx_basic) {
2588 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
2589 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
2590 */
2591 return;
2592 }
2593
2594 uint64_t kvm_vmx_misc =
2595 kvm_arch_get_supported_msr_feature(kvm_state,
2596 MSR_IA32_VMX_MISC);
2597 uint64_t kvm_vmx_ept_vpid =
2598 kvm_arch_get_supported_msr_feature(kvm_state,
2599 MSR_IA32_VMX_EPT_VPID_CAP);
2600
2601 /*
2602 * If the guest is 64-bit, a value of 1 is allowed for the host address
2603 * space size vmexit control.
2604 */
2605 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
2606 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
2607
2608 /*
2609 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
2610 * not change them for backwards compatibility.
2611 */
2612 uint64_t fixed_vmx_basic = kvm_vmx_basic &
2613 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
2614 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
2615 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
2616
2617 /*
2618 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
2619 * change in the future but are always zero for now, clear them to be
2620 * future proof. Bits 32-63 in theory could change, though KVM does
2621 * not support dual-monitor treatment and probably never will; mask
2622 * them out as well.
2623 */
2624 uint64_t fixed_vmx_misc = kvm_vmx_misc &
2625 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
2626 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
2627
2628 /*
2629 * EPT memory types should not change either, so we do not bother
2630 * adding features for them.
2631 */
2632 uint64_t fixed_vmx_ept_mask =
2633 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
2634 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
2635 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
2636
2637 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2638 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2639 f[FEAT_VMX_PROCBASED_CTLS]));
2640 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2641 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2642 f[FEAT_VMX_PINBASED_CTLS]));
2643 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
2644 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
2645 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
2646 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2647 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2648 f[FEAT_VMX_ENTRY_CTLS]));
2649 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
2650 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
2651 f[FEAT_VMX_SECONDARY_CTLS]));
2652 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
2653 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
2654 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
2655 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
2656 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
2657 f[FEAT_VMX_MISC] | fixed_vmx_misc);
2658 if (has_msr_vmx_vmfunc) {
2659 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
2660 }
2661
2662 /*
2663 * Just to be safe, write these with constant values. The CRn_FIXED1
2664 * MSRs are generated by KVM based on the vCPU's CPUID.
2665 */
2666 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
2667 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
2668 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
2669 CR4_VMXE_MASK);
2670 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM,
2671 VMCS12_MAX_FIELD_INDEX << 1);
2672 }
2673
2674 static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
2675 {
2676 uint64_t kvm_perf_cap =
2677 kvm_arch_get_supported_msr_feature(kvm_state,
2678 MSR_IA32_PERF_CAPABILITIES);
2679
2680 if (kvm_perf_cap) {
2681 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
2682 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
2683 }
2684 }
2685
2686 static int kvm_buf_set_msrs(X86CPU *cpu)
2687 {
2688 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2689 if (ret < 0) {
2690 return ret;
2691 }
2692
2693 if (ret < cpu->kvm_msr_buf->nmsrs) {
2694 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2695 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2696 (uint32_t)e->index, (uint64_t)e->data);
2697 }
2698
2699 assert(ret == cpu->kvm_msr_buf->nmsrs);
2700 return 0;
2701 }
2702
2703 static void kvm_init_msrs(X86CPU *cpu)
2704 {
2705 CPUX86State *env = &cpu->env;
2706
2707 kvm_msr_buf_reset(cpu);
2708 if (has_msr_arch_capabs) {
2709 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2710 env->features[FEAT_ARCH_CAPABILITIES]);
2711 }
2712
2713 if (has_msr_core_capabs) {
2714 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2715 env->features[FEAT_CORE_CAPABILITY]);
2716 }
2717
2718 if (has_msr_perf_capabs && cpu->enable_pmu) {
2719 kvm_msr_entry_add_perf(cpu, env->features);
2720 }
2721
2722 if (has_msr_ucode_rev) {
2723 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
2724 }
2725
2726 /*
2727 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
2728 * all kernels with MSR features should have them.
2729 */
2730 if (kvm_feature_msrs && cpu_has_vmx(env)) {
2731 kvm_msr_entry_add_vmx(cpu, env->features);
2732 }
2733
2734 assert(kvm_buf_set_msrs(cpu) == 0);
2735 }
2736
2737 static int kvm_put_msrs(X86CPU *cpu, int level)
2738 {
2739 CPUX86State *env = &cpu->env;
2740 int i;
2741
2742 kvm_msr_buf_reset(cpu);
2743
2744 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2745 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2746 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2747 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
2748 if (has_msr_star) {
2749 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
2750 }
2751 if (has_msr_hsave_pa) {
2752 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
2753 }
2754 if (has_msr_tsc_aux) {
2755 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
2756 }
2757 if (has_msr_tsc_adjust) {
2758 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
2759 }
2760 if (has_msr_misc_enable) {
2761 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
2762 env->msr_ia32_misc_enable);
2763 }
2764 if (has_msr_smbase) {
2765 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
2766 }
2767 if (has_msr_smi_count) {
2768 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2769 }
2770 if (has_msr_bndcfgs) {
2771 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
2772 }
2773 if (has_msr_xss) {
2774 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
2775 }
2776 if (has_msr_umwait) {
2777 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
2778 }
2779 if (has_msr_spec_ctrl) {
2780 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2781 }
2782 if (has_msr_tsx_ctrl) {
2783 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
2784 }
2785 if (has_msr_virt_ssbd) {
2786 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2787 }
2788
2789 #ifdef TARGET_X86_64
2790 if (lm_capable_kernel) {
2791 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2792 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2793 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2794 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
2795 }
2796 #endif
2797
2798 /*
2799 * The following MSRs have side effects on the guest or are too heavy
2800 * for normal writeback. Limit them to reset or full state updates.
2801 */
2802 if (level >= KVM_PUT_RESET_STATE) {
2803 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2804 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2805 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
2806 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
2807 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
2808 }
2809 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2810 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
2811 }
2812 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2813 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
2814 }
2815 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2816 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
2817 }
2818
2819 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
2820 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
2821 }
2822
2823 if (has_architectural_pmu_version > 0) {
2824 if (has_architectural_pmu_version > 1) {
2825 /* Stop the counter. */
2826 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2827 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2828 }
2829
2830 /* Set the counter values. */
2831 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2832 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
2833 env->msr_fixed_counters[i]);
2834 }
2835 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2836 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
2837 env->msr_gp_counters[i]);
2838 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
2839 env->msr_gp_evtsel[i]);
2840 }
2841 if (has_architectural_pmu_version > 1) {
2842 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2843 env->msr_global_status);
2844 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2845 env->msr_global_ovf_ctrl);
2846
2847 /* Now start the PMU. */
2848 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2849 env->msr_fixed_ctr_ctrl);
2850 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2851 env->msr_global_ctrl);
2852 }
2853 }
2854 /*
2855 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2856 * only sync them to KVM on the first cpu
2857 */
2858 if (current_cpu == first_cpu) {
2859 if (has_msr_hv_hypercall) {
2860 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2861 env->msr_hv_guest_os_id);
2862 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2863 env->msr_hv_hypercall);
2864 }
2865 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
2866 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2867 env->msr_hv_tsc);
2868 }
2869 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
2870 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2871 env->msr_hv_reenlightenment_control);
2872 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2873 env->msr_hv_tsc_emulation_control);
2874 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2875 env->msr_hv_tsc_emulation_status);
2876 }
2877 }
2878 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
2879 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
2880 env->msr_hv_vapic);
2881 }
2882 if (has_msr_hv_crash) {
2883 int j;
2884
2885 for (j = 0; j < HV_CRASH_PARAMS; j++)
2886 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
2887 env->msr_hv_crash_params[j]);
2888
2889 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
2890 }
2891 if (has_msr_hv_runtime) {
2892 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
2893 }
2894 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2895 && hv_vpindex_settable) {
2896 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2897 hyperv_vp_index(CPU(cpu)));
2898 }
2899 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2900 int j;
2901
2902 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2903
2904 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
2905 env->msr_hv_synic_control);
2906 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
2907 env->msr_hv_synic_evt_page);
2908 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
2909 env->msr_hv_synic_msg_page);
2910
2911 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
2912 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
2913 env->msr_hv_synic_sint[j]);
2914 }
2915 }
2916 if (has_msr_hv_stimer) {
2917 int j;
2918
2919 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
2920 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
2921 env->msr_hv_stimer_config[j]);
2922 }
2923
2924 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
2925 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
2926 env->msr_hv_stimer_count[j]);
2927 }
2928 }
2929 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2930 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2931
2932 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2933 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2934 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2935 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2936 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2937 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2938 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2939 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2940 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2941 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2942 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2943 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
2944 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2945 /* The CPU GPs if we write to a bit above the physical limit of
2946 * the host CPU (and KVM emulates that)
2947 */
2948 uint64_t mask = env->mtrr_var[i].mask;
2949 mask &= phys_mask;
2950
2951 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2952 env->mtrr_var[i].base);
2953 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
2954 }
2955 }
2956 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2957 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2958 0x14, 1, R_EAX) & 0x7;
2959
2960 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2961 env->msr_rtit_ctrl);
2962 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2963 env->msr_rtit_status);
2964 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2965 env->msr_rtit_output_base);
2966 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2967 env->msr_rtit_output_mask);
2968 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2969 env->msr_rtit_cr3_match);
2970 for (i = 0; i < addr_num; i++) {
2971 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2972 env->msr_rtit_addrs[i]);
2973 }
2974 }
2975
2976 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2977 * kvm_put_msr_feature_control. */
2978 }
2979
2980 if (env->mcg_cap) {
2981 int i;
2982
2983 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2984 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
2985 if (has_msr_mcg_ext_ctl) {
2986 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2987 }
2988 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2989 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
2990 }
2991 }
2992
2993 return kvm_buf_set_msrs(cpu);
2994 }
2995
2996
2997 static int kvm_get_fpu(X86CPU *cpu)
2998 {
2999 CPUX86State *env = &cpu->env;
3000 struct kvm_fpu fpu;
3001 int i, ret;
3002
3003 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
3004 if (ret < 0) {
3005 return ret;
3006 }
3007
3008 env->fpstt = (fpu.fsw >> 11) & 7;
3009 env->fpus = fpu.fsw;
3010 env->fpuc = fpu.fcw;
3011 env->fpop = fpu.last_opcode;
3012 env->fpip = fpu.last_ip;
3013 env->fpdp = fpu.last_dp;
3014 for (i = 0; i < 8; ++i) {
3015 env->fptags[i] = !((fpu.ftwx >> i) & 1);
3016 }
3017 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
3018 for (i = 0; i < CPU_NB_REGS; i++) {
3019 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
3020 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
3021 }
3022 env->mxcsr = fpu.mxcsr;
3023
3024 return 0;
3025 }
3026
3027 static int kvm_get_xsave(X86CPU *cpu)
3028 {
3029 CPUX86State *env = &cpu->env;
3030 X86XSaveArea *xsave = env->xsave_buf;
3031 int ret;
3032
3033 if (!has_xsave) {
3034 return kvm_get_fpu(cpu);
3035 }
3036
3037 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
3038 if (ret < 0) {
3039 return ret;
3040 }
3041 x86_cpu_xrstor_all_areas(cpu, xsave);
3042
3043 return 0;
3044 }
3045
3046 static int kvm_get_xcrs(X86CPU *cpu)
3047 {
3048 CPUX86State *env = &cpu->env;
3049 int i, ret;
3050 struct kvm_xcrs xcrs;
3051
3052 if (!has_xcrs) {
3053 return 0;
3054 }
3055
3056 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
3057 if (ret < 0) {
3058 return ret;
3059 }
3060
3061 for (i = 0; i < xcrs.nr_xcrs; i++) {
3062 /* Only support xcr0 now */
3063 if (xcrs.xcrs[i].xcr == 0) {
3064 env->xcr0 = xcrs.xcrs[i].value;
3065 break;
3066 }
3067 }
3068 return 0;
3069 }
3070
3071 static int kvm_get_sregs(X86CPU *cpu)
3072 {
3073 CPUX86State *env = &cpu->env;
3074 struct kvm_sregs sregs;
3075 int bit, i, ret;
3076
3077 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
3078 if (ret < 0) {
3079 return ret;
3080 }
3081
3082 /* There can only be one pending IRQ set in the bitmap at a time, so try
3083 to find it and save its number instead (-1 for none). */
3084 env->interrupt_injected = -1;
3085 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
3086 if (sregs.interrupt_bitmap[i]) {
3087 bit = ctz64(sregs.interrupt_bitmap[i]);
3088 env->interrupt_injected = i * 64 + bit;
3089 break;
3090 }
3091 }
3092
3093 get_seg(&env->segs[R_CS], &sregs.cs);
3094 get_seg(&env->segs[R_DS], &sregs.ds);
3095 get_seg(&env->segs[R_ES], &sregs.es);
3096 get_seg(&env->segs[R_FS], &sregs.fs);
3097 get_seg(&env->segs[R_GS], &sregs.gs);
3098 get_seg(&env->segs[R_SS], &sregs.ss);
3099
3100 get_seg(&env->tr, &sregs.tr);
3101 get_seg(&env->ldt, &sregs.ldt);
3102
3103 env->idt.limit = sregs.idt.limit;
3104 env->idt.base = sregs.idt.base;
3105 env->gdt.limit = sregs.gdt.limit;
3106 env->gdt.base = sregs.gdt.base;
3107
3108 env->cr[0] = sregs.cr0;
3109 env->cr[2] = sregs.cr2;
3110 env->cr[3] = sregs.cr3;
3111 env->cr[4] = sregs.cr4;
3112
3113 env->efer = sregs.efer;
3114
3115 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
3116 x86_update_hflags(env);
3117
3118 return 0;
3119 }
3120
3121 static int kvm_get_msrs(X86CPU *cpu)
3122 {
3123 CPUX86State *env = &cpu->env;
3124 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
3125 int ret, i;
3126 uint64_t mtrr_top_bits;
3127
3128 kvm_msr_buf_reset(cpu);
3129
3130 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
3131 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
3132 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
3133 kvm_msr_entry_add(cpu, MSR_PAT, 0);
3134 if (has_msr_star) {
3135 kvm_msr_entry_add(cpu, MSR_STAR, 0);
3136 }
3137 if (has_msr_hsave_pa) {
3138 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
3139 }
3140 if (has_msr_tsc_aux) {
3141 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
3142 }
3143 if (has_msr_tsc_adjust) {
3144 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
3145 }
3146 if (has_msr_tsc_deadline) {
3147 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
3148 }
3149 if (has_msr_misc_enable) {
3150 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
3151 }
3152 if (has_msr_smbase) {
3153 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
3154 }
3155 if (has_msr_smi_count) {
3156 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
3157 }
3158 if (has_msr_feature_control) {
3159 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
3160 }
3161 if (has_msr_bndcfgs) {
3162 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
3163 }
3164 if (has_msr_xss) {
3165 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
3166 }
3167 if (has_msr_umwait) {
3168 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
3169 }
3170 if (has_msr_spec_ctrl) {
3171 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
3172 }
3173 if (has_msr_tsx_ctrl) {
3174 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
3175 }
3176 if (has_msr_virt_ssbd) {
3177 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
3178 }
3179 if (!env->tsc_valid) {
3180 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
3181 env->tsc_valid = !runstate_is_running();
3182 }
3183
3184 #ifdef TARGET_X86_64
3185 if (lm_capable_kernel) {
3186 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
3187 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
3188 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
3189 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
3190 }
3191 #endif
3192 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
3193 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
3194 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
3195 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
3196 }
3197 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
3198 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
3199 }
3200 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
3201 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
3202 }
3203 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
3204 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
3205 }
3206 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3207 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
3208 }
3209 if (has_architectural_pmu_version > 0) {
3210 if (has_architectural_pmu_version > 1) {
3211 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3212 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3213 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
3214 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
3215 }
3216 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
3217 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
3218 }
3219 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
3220 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
3221 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
3222 }
3223 }
3224
3225 if (env->mcg_cap) {
3226 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
3227 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
3228 if (has_msr_mcg_ext_ctl) {
3229 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
3230 }
3231 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
3232 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
3233 }
3234 }
3235
3236 if (has_msr_hv_hypercall) {
3237 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
3238 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
3239 }
3240 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
3241 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
3242 }
3243 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
3244 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
3245 }
3246 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
3247 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
3248 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
3249 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
3250 }
3251 if (has_msr_hv_crash) {
3252 int j;
3253
3254 for (j = 0; j < HV_CRASH_PARAMS; j++) {
3255 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
3256 }
3257 }
3258 if (has_msr_hv_runtime) {
3259 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
3260 }
3261 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
3262 uint32_t msr;
3263
3264 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
3265 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
3266 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
3267 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
3268 kvm_msr_entry_add(cpu, msr, 0);
3269 }
3270 }
3271 if (has_msr_hv_stimer) {
3272 uint32_t msr;
3273
3274 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
3275 msr++) {
3276 kvm_msr_entry_add(cpu, msr, 0);
3277 }
3278 }
3279 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
3280 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
3281 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
3282 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
3283 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
3284 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
3285 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
3286 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
3287 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
3288 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
3289 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
3290 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
3291 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
3292 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
3293 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
3294 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
3295 }
3296 }
3297
3298 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3299 int addr_num =
3300 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
3301
3302 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
3303 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
3304 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
3305 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
3306 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
3307 for (i = 0; i < addr_num; i++) {
3308 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
3309 }
3310 }
3311
3312 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
3313 if (ret < 0) {
3314 return ret;
3315 }
3316
3317 if (ret < cpu->kvm_msr_buf->nmsrs) {
3318 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3319 error_report("error: failed to get MSR 0x%" PRIx32,
3320 (uint32_t)e->index);
3321 }
3322
3323 assert(ret == cpu->kvm_msr_buf->nmsrs);
3324 /*
3325 * MTRR masks: Each mask consists of 5 parts
3326 * a 10..0: must be zero
3327 * b 11 : valid bit
3328 * c n-1.12: actual mask bits
3329 * d 51..n: reserved must be zero
3330 * e 63.52: reserved must be zero
3331 *
3332 * 'n' is the number of physical bits supported by the CPU and is
3333 * apparently always <= 52. We know our 'n' but don't know what
3334 * the destinations 'n' is; it might be smaller, in which case
3335 * it masks (c) on loading. It might be larger, in which case
3336 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3337 * we're migrating to.
3338 */
3339
3340 if (cpu->fill_mtrr_mask) {
3341 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3342 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3343 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3344 } else {
3345 mtrr_top_bits = 0;
3346 }
3347
3348 for (i = 0; i < ret; i++) {
3349 uint32_t index = msrs[i].index;
3350 switch (index) {
3351 case MSR_IA32_SYSENTER_CS:
3352 env->sysenter_cs = msrs[i].data;
3353 break;
3354 case MSR_IA32_SYSENTER_ESP:
3355 env->sysenter_esp = msrs[i].data;
3356 break;
3357 case MSR_IA32_SYSENTER_EIP:
3358 env->sysenter_eip = msrs[i].data;
3359 break;
3360 case MSR_PAT:
3361 env->pat = msrs[i].data;
3362 break;
3363 case MSR_STAR:
3364 env->star = msrs[i].data;
3365 break;
3366 #ifdef TARGET_X86_64
3367 case MSR_CSTAR:
3368 env->cstar = msrs[i].data;
3369 break;
3370 case MSR_KERNELGSBASE:
3371 env->kernelgsbase = msrs[i].data;
3372 break;
3373 case MSR_FMASK:
3374 env->fmask = msrs[i].data;
3375 break;
3376 case MSR_LSTAR:
3377 env->lstar = msrs[i].data;
3378 break;
3379 #endif
3380 case MSR_IA32_TSC:
3381 env->tsc = msrs[i].data;
3382 break;
3383 case MSR_TSC_AUX:
3384 env->tsc_aux = msrs[i].data;
3385 break;
3386 case MSR_TSC_ADJUST:
3387 env->tsc_adjust = msrs[i].data;
3388 break;
3389 case MSR_IA32_TSCDEADLINE:
3390 env->tsc_deadline = msrs[i].data;
3391 break;
3392 case MSR_VM_HSAVE_PA:
3393 env->vm_hsave = msrs[i].data;
3394 break;
3395 case MSR_KVM_SYSTEM_TIME:
3396 env->system_time_msr = msrs[i].data;
3397 break;
3398 case MSR_KVM_WALL_CLOCK:
3399 env->wall_clock_msr = msrs[i].data;
3400 break;
3401 case MSR_MCG_STATUS:
3402 env->mcg_status = msrs[i].data;
3403 break;
3404 case MSR_MCG_CTL:
3405 env->mcg_ctl = msrs[i].data;
3406 break;
3407 case MSR_MCG_EXT_CTL:
3408 env->mcg_ext_ctl = msrs[i].data;
3409 break;
3410 case MSR_IA32_MISC_ENABLE:
3411 env->msr_ia32_misc_enable = msrs[i].data;
3412 break;
3413 case MSR_IA32_SMBASE:
3414 env->smbase = msrs[i].data;
3415 break;
3416 case MSR_SMI_COUNT:
3417 env->msr_smi_count = msrs[i].data;
3418 break;
3419 case MSR_IA32_FEATURE_CONTROL:
3420 env->msr_ia32_feature_control = msrs[i].data;
3421 break;
3422 case MSR_IA32_BNDCFGS:
3423 env->msr_bndcfgs = msrs[i].data;
3424 break;
3425 case MSR_IA32_XSS:
3426 env->xss = msrs[i].data;
3427 break;
3428 case MSR_IA32_UMWAIT_CONTROL:
3429 env->umwait = msrs[i].data;
3430 break;
3431 default:
3432 if (msrs[i].index >= MSR_MC0_CTL &&
3433 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3434 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
3435 }
3436 break;
3437 case MSR_KVM_ASYNC_PF_EN:
3438 env->async_pf_en_msr = msrs[i].data;
3439 break;
3440 case MSR_KVM_ASYNC_PF_INT:
3441 env->async_pf_int_msr = msrs[i].data;
3442 break;
3443 case MSR_KVM_PV_EOI_EN:
3444 env->pv_eoi_en_msr = msrs[i].data;
3445 break;
3446 case MSR_KVM_STEAL_TIME:
3447 env->steal_time_msr = msrs[i].data;
3448 break;
3449 case MSR_KVM_POLL_CONTROL: {
3450 env->poll_control_msr = msrs[i].data;
3451 break;
3452 }
3453 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3454 env->msr_fixed_ctr_ctrl = msrs[i].data;
3455 break;
3456 case MSR_CORE_PERF_GLOBAL_CTRL:
3457 env->msr_global_ctrl = msrs[i].data;
3458 break;
3459 case MSR_CORE_PERF_GLOBAL_STATUS:
3460 env->msr_global_status = msrs[i].data;
3461 break;
3462 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3463 env->msr_global_ovf_ctrl = msrs[i].data;
3464 break;
3465 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3466 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3467 break;
3468 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3469 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3470 break;
3471 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3472 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3473 break;
3474 case HV_X64_MSR_HYPERCALL:
3475 env->msr_hv_hypercall = msrs[i].data;
3476 break;
3477 case HV_X64_MSR_GUEST_OS_ID:
3478 env->msr_hv_guest_os_id = msrs[i].data;
3479 break;
3480 case HV_X64_MSR_APIC_ASSIST_PAGE:
3481 env->msr_hv_vapic = msrs[i].data;
3482 break;
3483 case HV_X64_MSR_REFERENCE_TSC:
3484 env->msr_hv_tsc = msrs[i].data;
3485 break;
3486 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3487 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3488 break;
3489 case HV_X64_MSR_VP_RUNTIME:
3490 env->msr_hv_runtime = msrs[i].data;
3491 break;
3492 case HV_X64_MSR_SCONTROL:
3493 env->msr_hv_synic_control = msrs[i].data;
3494 break;
3495 case HV_X64_MSR_SIEFP:
3496 env->msr_hv_synic_evt_page = msrs[i].data;
3497 break;
3498 case HV_X64_MSR_SIMP:
3499 env->msr_hv_synic_msg_page = msrs[i].data;
3500 break;
3501 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3502 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
3503 break;
3504 case HV_X64_MSR_STIMER0_CONFIG:
3505 case HV_X64_MSR_STIMER1_CONFIG:
3506 case HV_X64_MSR_STIMER2_CONFIG:
3507 case HV_X64_MSR_STIMER3_CONFIG:
3508 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3509 msrs[i].data;
3510 break;
3511 case HV_X64_MSR_STIMER0_COUNT:
3512 case HV_X64_MSR_STIMER1_COUNT:
3513 case HV_X64_MSR_STIMER2_COUNT:
3514 case HV_X64_MSR_STIMER3_COUNT:
3515 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3516 msrs[i].data;
3517 break;
3518 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3519 env->msr_hv_reenlightenment_control = msrs[i].data;
3520 break;
3521 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3522 env->msr_hv_tsc_emulation_control = msrs[i].data;
3523 break;
3524 case HV_X64_MSR_TSC_EMULATION_STATUS:
3525 env->msr_hv_tsc_emulation_status = msrs[i].data;
3526 break;
3527 case MSR_MTRRdefType:
3528 env->mtrr_deftype = msrs[i].data;
3529 break;
3530 case MSR_MTRRfix64K_00000:
3531 env->mtrr_fixed[0] = msrs[i].data;
3532 break;
3533 case MSR_MTRRfix16K_80000:
3534 env->mtrr_fixed[1] = msrs[i].data;
3535 break;
3536 case MSR_MTRRfix16K_A0000:
3537 env->mtrr_fixed[2] = msrs[i].data;
3538 break;
3539 case MSR_MTRRfix4K_C0000:
3540 env->mtrr_fixed[3] = msrs[i].data;
3541 break;
3542 case MSR_MTRRfix4K_C8000:
3543 env->mtrr_fixed[4] = msrs[i].data;
3544 break;
3545 case MSR_MTRRfix4K_D0000:
3546 env->mtrr_fixed[5] = msrs[i].data;
3547 break;
3548 case MSR_MTRRfix4K_D8000:
3549 env->mtrr_fixed[6] = msrs[i].data;
3550 break;
3551 case MSR_MTRRfix4K_E0000:
3552 env->mtrr_fixed[7] = msrs[i].data;
3553 break;
3554 case MSR_MTRRfix4K_E8000:
3555 env->mtrr_fixed[8] = msrs[i].data;
3556 break;
3557 case MSR_MTRRfix4K_F0000:
3558 env->mtrr_fixed[9] = msrs[i].data;
3559 break;
3560 case MSR_MTRRfix4K_F8000:
3561 env->mtrr_fixed[10] = msrs[i].data;
3562 break;
3563 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3564 if (index & 1) {
3565 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3566 mtrr_top_bits;
3567 } else {
3568 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3569 }
3570 break;
3571 case MSR_IA32_SPEC_CTRL:
3572 env->spec_ctrl = msrs[i].data;
3573 break;
3574 case MSR_IA32_TSX_CTRL:
3575 env->tsx_ctrl = msrs[i].data;
3576 break;
3577 case MSR_VIRT_SSBD:
3578 env->virt_ssbd = msrs[i].data;
3579 break;
3580 case MSR_IA32_RTIT_CTL:
3581 env->msr_rtit_ctrl = msrs[i].data;
3582 break;
3583 case MSR_IA32_RTIT_STATUS:
3584 env->msr_rtit_status = msrs[i].data;
3585 break;
3586 case MSR_IA32_RTIT_OUTPUT_BASE:
3587 env->msr_rtit_output_base = msrs[i].data;
3588 break;
3589 case MSR_IA32_RTIT_OUTPUT_MASK:
3590 env->msr_rtit_output_mask = msrs[i].data;
3591 break;
3592 case MSR_IA32_RTIT_CR3_MATCH:
3593 env->msr_rtit_cr3_match = msrs[i].data;
3594 break;
3595 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3596 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3597 break;
3598 }
3599 }
3600
3601 return 0;
3602 }
3603
3604 static int kvm_put_mp_state(X86CPU *cpu)
3605 {
3606 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
3607
3608 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
3609 }
3610
3611 static int kvm_get_mp_state(X86CPU *cpu)
3612 {
3613 CPUState *cs = CPU(cpu);
3614 CPUX86State *env = &cpu->env;
3615 struct kvm_mp_state mp_state;
3616 int ret;
3617
3618 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
3619 if (ret < 0) {
3620 return ret;
3621 }
3622 env->mp_state = mp_state.mp_state;
3623 if (kvm_irqchip_in_kernel()) {
3624 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
3625 }
3626 return 0;
3627 }
3628
3629 static int kvm_get_apic(X86CPU *cpu)
3630 {
3631 DeviceState *apic = cpu->apic_state;
3632 struct kvm_lapic_state kapic;
3633 int ret;
3634
3635 if (apic && kvm_irqchip_in_kernel()) {
3636 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
3637 if (ret < 0) {
3638 return ret;
3639 }
3640
3641 kvm_get_apic_state(apic, &kapic);
3642 }
3643 return 0;
3644 }
3645
3646 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
3647 {
3648 CPUState *cs = CPU(cpu);
3649 CPUX86State *env = &cpu->env;
3650 struct kvm_vcpu_events events = {};
3651
3652 if (!kvm_has_vcpu_events()) {
3653 return 0;
3654 }
3655
3656 events.flags = 0;
3657
3658 if (has_exception_payload) {
3659 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3660 events.exception.pending = env->exception_pending;
3661 events.exception_has_payload = env->exception_has_payload;
3662 events.exception_payload = env->exception_payload;
3663 }
3664 events.exception.nr = env->exception_nr;
3665 events.exception.injected = env->exception_injected;
3666 events.exception.has_error_code = env->has_error_code;
3667 events.exception.error_code = env->error_code;
3668
3669 events.interrupt.injected = (env->interrupt_injected >= 0);
3670 events.interrupt.nr = env->interrupt_injected;
3671 events.interrupt.soft = env->soft_interrupt;
3672
3673 events.nmi.injected = env->nmi_injected;
3674 events.nmi.pending = env->nmi_pending;
3675 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3676
3677 events.sipi_vector = env->sipi_vector;
3678
3679 if (has_msr_smbase) {
3680 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3681 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3682 if (kvm_irqchip_in_kernel()) {
3683 /* As soon as these are moved to the kernel, remove them
3684 * from cs->interrupt_request.
3685 */
3686 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3687 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3688 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3689 } else {
3690 /* Keep these in cs->interrupt_request. */
3691 events.smi.pending = 0;
3692 events.smi.latched_init = 0;
3693 }
3694 /* Stop SMI delivery on old machine types to avoid a reboot
3695 * on an inward migration of an old VM.
3696 */
3697 if (!cpu->kvm_no_smi_migration) {
3698 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3699 }
3700 }
3701
3702 if (level >= KVM_PUT_RESET_STATE) {
3703 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3704 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3705 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3706 }
3707 }
3708
3709 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
3710 }
3711
3712 static int kvm_get_vcpu_events(X86CPU *cpu)
3713 {
3714 CPUX86State *env = &cpu->env;
3715 struct kvm_vcpu_events events;
3716 int ret;
3717
3718 if (!kvm_has_vcpu_events()) {
3719 return 0;
3720 }
3721
3722 memset(&events, 0, sizeof(events));
3723 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
3724 if (ret < 0) {
3725 return ret;
3726 }
3727
3728 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3729 env->exception_pending = events.exception.pending;
3730 env->exception_has_payload = events.exception_has_payload;
3731 env->exception_payload = events.exception_payload;
3732 } else {
3733 env->exception_pending = 0;
3734 env->exception_has_payload = false;
3735 }
3736 env->exception_injected = events.exception.injected;
3737 env->exception_nr =
3738 (env->exception_pending || env->exception_injected) ?
3739 events.exception.nr : -1;
3740 env->has_error_code = events.exception.has_error_code;
3741 env->error_code = events.exception.error_code;
3742
3743 env->interrupt_injected =
3744 events.interrupt.injected ? events.interrupt.nr : -1;
3745 env->soft_interrupt = events.interrupt.soft;
3746
3747 env->nmi_injected = events.nmi.injected;
3748 env->nmi_pending = events.nmi.pending;
3749 if (events.nmi.masked) {
3750 env->hflags2 |= HF2_NMI_MASK;
3751 } else {
3752 env->hflags2 &= ~HF2_NMI_MASK;
3753 }
3754
3755 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3756 if (events.smi.smm) {
3757 env->hflags |= HF_SMM_MASK;
3758 } else {
3759 env->hflags &= ~HF_SMM_MASK;
3760 }
3761 if (events.smi.pending) {
3762 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3763 } else {
3764 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3765 }
3766 if (events.smi.smm_inside_nmi) {
3767 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3768 } else {
3769 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3770 }
3771 if (events.smi.latched_init) {
3772 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3773 } else {
3774 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3775 }
3776 }
3777
3778 env->sipi_vector = events.sipi_vector;
3779
3780 return 0;
3781 }
3782
3783 static int kvm_guest_debug_workarounds(X86CPU *cpu)
3784 {
3785 CPUState *cs = CPU(cpu);
3786 CPUX86State *env = &cpu->env;
3787 int ret = 0;
3788 unsigned long reinject_trap = 0;
3789
3790 if (!kvm_has_vcpu_events()) {
3791 if (env->exception_nr == EXCP01_DB) {
3792 reinject_trap = KVM_GUESTDBG_INJECT_DB;
3793 } else if (env->exception_injected == EXCP03_INT3) {
3794 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3795 }
3796 kvm_reset_exception(env);
3797 }
3798
3799 /*
3800 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3801 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3802 * by updating the debug state once again if single-stepping is on.
3803 * Another reason to call kvm_update_guest_debug here is a pending debug
3804 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3805 * reinject them via SET_GUEST_DEBUG.
3806 */
3807 if (reinject_trap ||
3808 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
3809 ret = kvm_update_guest_debug(cs, reinject_trap);
3810 }
3811 return ret;
3812 }
3813
3814 static int kvm_put_debugregs(X86CPU *cpu)
3815 {
3816 CPUX86State *env = &cpu->env;
3817 struct kvm_debugregs dbgregs;
3818 int i;
3819
3820 if (!kvm_has_debugregs()) {
3821 return 0;
3822 }
3823
3824 memset(&dbgregs, 0, sizeof(dbgregs));
3825 for (i = 0; i < 4; i++) {
3826 dbgregs.db[i] = env->dr[i];
3827 }
3828 dbgregs.dr6 = env->dr[6];
3829 dbgregs.dr7 = env->dr[7];
3830 dbgregs.flags = 0;
3831
3832 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
3833 }
3834
3835 static int kvm_get_debugregs(X86CPU *cpu)
3836 {
3837 CPUX86State *env = &cpu->env;
3838 struct kvm_debugregs dbgregs;
3839 int i, ret;
3840
3841 if (!kvm_has_debugregs()) {
3842 return 0;
3843 }
3844
3845 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
3846 if (ret < 0) {
3847 return ret;
3848 }
3849 for (i = 0; i < 4; i++) {
3850 env->dr[i] = dbgregs.db[i];
3851 }
3852 env->dr[4] = env->dr[6] = dbgregs.dr6;
3853 env->dr[5] = env->dr[7] = dbgregs.dr7;
3854
3855 return 0;
3856 }
3857
3858 static int kvm_put_nested_state(X86CPU *cpu)
3859 {
3860 CPUX86State *env = &cpu->env;
3861 int max_nested_state_len = kvm_max_nested_state_length();
3862
3863 if (!env->nested_state) {
3864 return 0;
3865 }
3866
3867 /*
3868 * Copy flags that are affected by reset from env->hflags and env->hflags2.
3869 */
3870 if (env->hflags & HF_GUEST_MASK) {
3871 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
3872 } else {
3873 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
3874 }
3875
3876 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
3877 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
3878 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
3879 } else {
3880 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
3881 }
3882
3883 assert(env->nested_state->size <= max_nested_state_len);
3884 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
3885 }
3886
3887 static int kvm_get_nested_state(X86CPU *cpu)
3888 {
3889 CPUX86State *env = &cpu->env;
3890 int max_nested_state_len = kvm_max_nested_state_length();
3891 int ret;
3892
3893 if (!env->nested_state) {
3894 return 0;
3895 }
3896
3897 /*
3898 * It is possible that migration restored a smaller size into
3899 * nested_state->hdr.size than what our kernel support.
3900 * We preserve migration origin nested_state->hdr.size for
3901 * call to KVM_SET_NESTED_STATE but wish that our next call
3902 * to KVM_GET_NESTED_STATE will use max size our kernel support.
3903 */
3904 env->nested_state->size = max_nested_state_len;
3905
3906 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
3907 if (ret < 0) {
3908 return ret;
3909 }
3910
3911 /*
3912 * Copy flags that are affected by reset to env->hflags and env->hflags2.
3913 */
3914 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
3915 env->hflags |= HF_GUEST_MASK;
3916 } else {
3917 env->hflags &= ~HF_GUEST_MASK;
3918 }
3919
3920 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
3921 if (cpu_has_svm(env)) {
3922 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
3923 env->hflags2 |= HF2_GIF_MASK;
3924 } else {
3925 env->hflags2 &= ~HF2_GIF_MASK;
3926 }
3927 }
3928
3929 return ret;
3930 }
3931
3932 int kvm_arch_put_registers(CPUState *cpu, int level)
3933 {
3934 X86CPU *x86_cpu = X86_CPU(cpu);
3935 int ret;
3936
3937 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
3938
3939 /* must be before kvm_put_nested_state so that EFER.SVME is set */
3940 ret = kvm_put_sregs(x86_cpu);
3941 if (ret < 0) {
3942 return ret;
3943 }
3944
3945 if (level >= KVM_PUT_RESET_STATE) {
3946 ret = kvm_put_nested_state(x86_cpu);
3947 if (ret < 0) {
3948 return ret;
3949 }
3950
3951 ret = kvm_put_msr_feature_control(x86_cpu);
3952 if (ret < 0) {
3953 return ret;
3954 }
3955 }
3956
3957 if (level == KVM_PUT_FULL_STATE) {
3958 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3959 * because TSC frequency mismatch shouldn't abort migration,
3960 * unless the user explicitly asked for a more strict TSC
3961 * setting (e.g. using an explicit "tsc-freq" option).
3962 */
3963 kvm_arch_set_tsc_khz(cpu);
3964 }
3965
3966 ret = kvm_getput_regs(x86_cpu, 1);
3967 if (ret < 0) {
3968 return ret;
3969 }
3970 ret = kvm_put_xsave(x86_cpu);
3971 if (ret < 0) {
3972 return ret;
3973 }
3974 ret = kvm_put_xcrs(x86_cpu);
3975 if (ret < 0) {
3976 return ret;
3977 }
3978 /* must be before kvm_put_msrs */
3979 ret = kvm_inject_mce_oldstyle(x86_cpu);
3980 if (ret < 0) {
3981 return ret;
3982 }
3983 ret = kvm_put_msrs(x86_cpu, level);
3984 if (ret < 0) {
3985 return ret;
3986 }
3987 ret = kvm_put_vcpu_events(x86_cpu, level);
3988 if (ret < 0) {
3989 return ret;
3990 }
3991 if (level >= KVM_PUT_RESET_STATE) {
3992 ret = kvm_put_mp_state(x86_cpu);
3993 if (ret < 0) {
3994 return ret;
3995 }
3996 }
3997
3998 ret = kvm_put_tscdeadline_msr(x86_cpu);
3999 if (ret < 0) {
4000 return ret;
4001 }
4002 ret = kvm_put_debugregs(x86_cpu);
4003 if (ret < 0) {
4004 return ret;
4005 }
4006 /* must be last */
4007 ret = kvm_guest_debug_workarounds(x86_cpu);
4008 if (ret < 0) {
4009 return ret;
4010 }
4011 return 0;
4012 }
4013
4014 int kvm_arch_get_registers(CPUState *cs)
4015 {
4016 X86CPU *cpu = X86_CPU(cs);
4017 int ret;
4018
4019 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
4020
4021 ret = kvm_get_vcpu_events(cpu);
4022 if (ret < 0) {
4023 goto out;
4024 }
4025 /*
4026 * KVM_GET_MPSTATE can modify CS and RIP, call it before
4027 * KVM_GET_REGS and KVM_GET_SREGS.
4028 */
4029 ret = kvm_get_mp_state(cpu);
4030 if (ret < 0) {
4031 goto out;
4032 }
4033 ret = kvm_getput_regs(cpu, 0);
4034 if (ret < 0) {
4035 goto out;
4036 }
4037 ret = kvm_get_xsave(cpu);
4038 if (ret < 0) {
4039 goto out;
4040 }
4041 ret = kvm_get_xcrs(cpu);
4042 if (ret < 0) {
4043 goto out;
4044 }
4045 ret = kvm_get_sregs(cpu);
4046 if (ret < 0) {
4047 goto out;
4048 }
4049 ret = kvm_get_msrs(cpu);
4050 if (ret < 0) {
4051 goto out;
4052 }
4053 ret = kvm_get_apic(cpu);
4054 if (ret < 0) {
4055 goto out;
4056 }
4057 ret = kvm_get_debugregs(cpu);
4058 if (ret < 0) {
4059 goto out;
4060 }
4061 ret = kvm_get_nested_state(cpu);
4062 if (ret < 0) {
4063 goto out;
4064 }
4065 ret = 0;
4066 out:
4067 cpu_sync_bndcs_hflags(&cpu->env);
4068 return ret;
4069 }
4070
4071 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
4072 {
4073 X86CPU *x86_cpu = X86_CPU(cpu);
4074 CPUX86State *env = &x86_cpu->env;
4075 int ret;
4076
4077 /* Inject NMI */
4078 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
4079 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
4080 qemu_mutex_lock_iothread();
4081 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
4082 qemu_mutex_unlock_iothread();
4083 DPRINTF("injected NMI\n");
4084 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
4085 if (ret < 0) {
4086 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
4087 strerror(-ret));
4088 }
4089 }
4090 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
4091 qemu_mutex_lock_iothread();
4092 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
4093 qemu_mutex_unlock_iothread();
4094 DPRINTF("injected SMI\n");
4095 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
4096 if (ret < 0) {
4097 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
4098 strerror(-ret));
4099 }
4100 }
4101 }
4102
4103 if (!kvm_pic_in_kernel()) {
4104 qemu_mutex_lock_iothread();
4105 }
4106
4107 /* Force the VCPU out of its inner loop to process any INIT requests
4108 * or (for userspace APIC, but it is cheap to combine the checks here)
4109 * pending TPR access reports.
4110 */
4111 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
4112 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
4113 !(env->hflags & HF_SMM_MASK)) {
4114 cpu->exit_request = 1;
4115 }
4116 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
4117 cpu->exit_request = 1;
4118 }
4119 }
4120
4121 if (!kvm_pic_in_kernel()) {
4122 /* Try to inject an interrupt if the guest can accept it */
4123 if (run->ready_for_interrupt_injection &&
4124 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
4125 (env->eflags & IF_MASK)) {
4126 int irq;
4127
4128 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
4129 irq = cpu_get_pic_interrupt(env);
4130 if (irq >= 0) {
4131 struct kvm_interrupt intr;
4132
4133 intr.irq = irq;
4134 DPRINTF("injected interrupt %d\n", irq);
4135 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
4136 if (ret < 0) {
4137 fprintf(stderr,
4138 "KVM: injection failed, interrupt lost (%s)\n",
4139 strerror(-ret));
4140 }
4141 }
4142 }
4143
4144 /* If we have an interrupt but the guest is not ready to receive an
4145 * interrupt, request an interrupt window exit. This will
4146 * cause a return to userspace as soon as the guest is ready to
4147 * receive interrupts. */
4148 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
4149 run->request_interrupt_window = 1;
4150 } else {
4151 run->request_interrupt_window = 0;
4152 }
4153
4154 DPRINTF("setting tpr\n");
4155 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4156
4157 qemu_mutex_unlock_iothread();
4158 }
4159 }
4160
4161 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
4162 {
4163 X86CPU *x86_cpu = X86_CPU(cpu);
4164 CPUX86State *env = &x86_cpu->env;
4165
4166 if (run->flags & KVM_RUN_X86_SMM) {
4167 env->hflags |= HF_SMM_MASK;
4168 } else {
4169 env->hflags &= ~HF_SMM_MASK;
4170 }
4171 if (run->if_flag) {
4172 env->eflags |= IF_MASK;
4173 } else {
4174 env->eflags &= ~IF_MASK;
4175 }
4176
4177 /* We need to protect the apic state against concurrent accesses from
4178 * different threads in case the userspace irqchip is used. */
4179 if (!kvm_irqchip_in_kernel()) {
4180 qemu_mutex_lock_iothread();
4181 }
4182 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
4183 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4184 if (!kvm_irqchip_in_kernel()) {
4185 qemu_mutex_unlock_iothread();
4186 }
4187 return cpu_get_mem_attrs(env);
4188 }
4189
4190 int kvm_arch_process_async_events(CPUState *cs)
4191 {
4192 X86CPU *cpu = X86_CPU(cs);
4193 CPUX86State *env = &cpu->env;
4194
4195 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
4196 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4197 assert(env->mcg_cap);
4198
4199 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
4200
4201 kvm_cpu_synchronize_state(cs);
4202
4203 if (env->exception_nr == EXCP08_DBLE) {
4204 /* this means triple fault */
4205 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
4206 cs->exit_request = 1;
4207 return 0;
4208 }
4209 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
4210 env->has_error_code = 0;
4211
4212 cs->halted = 0;
4213 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
4214 env->mp_state = KVM_MP_STATE_RUNNABLE;
4215 }
4216 }
4217
4218 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
4219 !(env->hflags & HF_SMM_MASK)) {
4220 kvm_cpu_synchronize_state(cs);
4221 do_cpu_init(cpu);
4222 }
4223
4224 if (kvm_irqchip_in_kernel()) {
4225 return 0;
4226 }
4227
4228 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
4229 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
4230 apic_poll_irq(cpu->apic_state);
4231 }
4232 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4233 (env->eflags & IF_MASK)) ||
4234 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4235 cs->halted = 0;
4236 }
4237 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
4238 kvm_cpu_synchronize_state(cs);
4239 do_cpu_sipi(cpu);
4240 }
4241 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
4242 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
4243 kvm_cpu_synchronize_state(cs);
4244 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
4245 env->tpr_access_type);
4246 }
4247
4248 return cs->halted;
4249 }
4250
4251 static int kvm_handle_halt(X86CPU *cpu)
4252 {
4253 CPUState *cs = CPU(cpu);
4254 CPUX86State *env = &cpu->env;
4255
4256 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4257 (env->eflags & IF_MASK)) &&
4258 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4259 cs->halted = 1;
4260 return EXCP_HLT;
4261 }
4262
4263 return 0;
4264 }
4265
4266 static int kvm_handle_tpr_access(X86CPU *cpu)
4267 {
4268 CPUState *cs = CPU(cpu);
4269 struct kvm_run *run = cs->kvm_run;
4270
4271 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
4272 run->tpr_access.is_write ? TPR_ACCESS_WRITE
4273 : TPR_ACCESS_READ);
4274 return 1;
4275 }
4276
4277 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
4278 {
4279 static const uint8_t int3 = 0xcc;
4280
4281 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
4282 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
4283 return -EINVAL;
4284 }
4285 return 0;
4286 }
4287
4288 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
4289 {
4290 uint8_t int3;
4291
4292 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
4293 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
4294 return -EINVAL;
4295 }
4296 return 0;
4297 }
4298
4299 static struct {
4300 target_ulong addr;
4301 int len;
4302 int type;
4303 } hw_breakpoint[4];
4304
4305 static int nb_hw_breakpoint;
4306
4307 static int find_hw_breakpoint(target_ulong addr, int len, int type)
4308 {
4309 int n;
4310
4311 for (n = 0; n < nb_hw_breakpoint; n++) {
4312 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
4313 (hw_breakpoint[n].len == len || len == -1)) {
4314 return n;
4315 }
4316 }
4317 return -1;
4318 }
4319
4320 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
4321 target_ulong len, int type)
4322 {
4323 switch (type) {
4324 case GDB_BREAKPOINT_HW:
4325 len = 1;
4326 break;
4327 case GDB_WATCHPOINT_WRITE:
4328 case GDB_WATCHPOINT_ACCESS:
4329 switch (len) {
4330 case 1:
4331 break;
4332 case 2:
4333 case 4:
4334 case 8:
4335 if (addr & (len - 1)) {
4336 return -EINVAL;
4337 }
4338 break;
4339 default:
4340 return -EINVAL;
4341 }
4342 break;
4343 default:
4344 return -ENOSYS;
4345 }
4346
4347 if (nb_hw_breakpoint == 4) {
4348 return -ENOBUFS;
4349 }
4350 if (find_hw_breakpoint(addr, len, type) >= 0) {
4351 return -EEXIST;
4352 }
4353 hw_breakpoint[nb_hw_breakpoint].addr = addr;
4354 hw_breakpoint[nb_hw_breakpoint].len = len;
4355 hw_breakpoint[nb_hw_breakpoint].type = type;
4356 nb_hw_breakpoint++;
4357
4358 return 0;
4359 }
4360
4361 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
4362 target_ulong len, int type)
4363 {
4364 int n;
4365
4366 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
4367 if (n < 0) {
4368 return -ENOENT;
4369 }
4370 nb_hw_breakpoint--;
4371 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
4372
4373 return 0;
4374 }
4375
4376 void kvm_arch_remove_all_hw_breakpoints(void)
4377 {
4378 nb_hw_breakpoint = 0;
4379 }
4380
4381 static CPUWatchpoint hw_watchpoint;
4382
4383 static int kvm_handle_debug(X86CPU *cpu,
4384 struct kvm_debug_exit_arch *arch_info)
4385 {
4386 CPUState *cs = CPU(cpu);
4387 CPUX86State *env = &cpu->env;
4388 int ret = 0;
4389 int n;
4390
4391 if (arch_info->exception == EXCP01_DB) {
4392 if (arch_info->dr6 & DR6_BS) {
4393 if (cs->singlestep_enabled) {
4394 ret = EXCP_DEBUG;
4395 }
4396 } else {
4397 for (n = 0; n < 4; n++) {
4398 if (arch_info->dr6 & (1 << n)) {
4399 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
4400 case 0x0:
4401 ret = EXCP_DEBUG;
4402 break;
4403 case 0x1:
4404 ret = EXCP_DEBUG;
4405 cs->watchpoint_hit = &hw_watchpoint;
4406 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4407 hw_watchpoint.flags = BP_MEM_WRITE;
4408 break;
4409 case 0x3:
4410 ret = EXCP_DEBUG;
4411 cs->watchpoint_hit = &hw_watchpoint;
4412 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4413 hw_watchpoint.flags = BP_MEM_ACCESS;
4414 break;
4415 }
4416 }
4417 }
4418 }
4419 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
4420 ret = EXCP_DEBUG;
4421 }
4422 if (ret == 0) {
4423 cpu_synchronize_state(cs);
4424 assert(env->exception_nr == -1);
4425
4426 /* pass to guest */
4427 kvm_queue_exception(env, arch_info->exception,
4428 arch_info->exception == EXCP01_DB,
4429 arch_info->dr6);
4430 env->has_error_code = 0;
4431 }
4432
4433 return ret;
4434 }
4435
4436 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
4437 {
4438 const uint8_t type_code[] = {
4439 [GDB_BREAKPOINT_HW] = 0x0,
4440 [GDB_WATCHPOINT_WRITE] = 0x1,
4441 [GDB_WATCHPOINT_ACCESS] = 0x3
4442 };
4443 const uint8_t len_code[] = {
4444 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4445 };
4446 int n;
4447
4448 if (kvm_sw_breakpoints_active(cpu)) {
4449 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
4450 }
4451 if (nb_hw_breakpoint > 0) {
4452 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4453 dbg->arch.debugreg[7] = 0x0600;
4454 for (n = 0; n < nb_hw_breakpoint; n++) {
4455 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4456 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4457 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
4458 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
4459 }
4460 }
4461 }
4462
4463 static bool host_supports_vmx(void)
4464 {
4465 uint32_t ecx, unused;
4466
4467 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4468 return ecx & CPUID_EXT_VMX;
4469 }
4470
4471 #define VMX_INVALID_GUEST_STATE 0x80000021
4472
4473 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
4474 {
4475 X86CPU *cpu = X86_CPU(cs);
4476 uint64_t code;
4477 int ret;
4478
4479 switch (run->exit_reason) {
4480 case KVM_EXIT_HLT:
4481 DPRINTF("handle_hlt\n");
4482 qemu_mutex_lock_iothread();
4483 ret = kvm_handle_halt(cpu);
4484 qemu_mutex_unlock_iothread();
4485 break;
4486 case KVM_EXIT_SET_TPR:
4487 ret = 0;
4488 break;
4489 case KVM_EXIT_TPR_ACCESS:
4490 qemu_mutex_lock_iothread();
4491 ret = kvm_handle_tpr_access(cpu);
4492 qemu_mutex_unlock_iothread();
4493 break;
4494 case KVM_EXIT_FAIL_ENTRY:
4495 code = run->fail_entry.hardware_entry_failure_reason;
4496 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4497 code);
4498 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4499 fprintf(stderr,
4500 "\nIf you're running a guest on an Intel machine without "
4501 "unrestricted mode\n"
4502 "support, the failure can be most likely due to the guest "
4503 "entering an invalid\n"
4504 "state for Intel VT. For example, the guest maybe running "
4505 "in big real mode\n"
4506 "which is not supported on less recent Intel processors."
4507 "\n\n");
4508 }
4509 ret = -1;
4510 break;
4511 case KVM_EXIT_EXCEPTION:
4512 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4513 run->ex.exception, run->ex.error_code);
4514 ret = -1;
4515 break;
4516 case KVM_EXIT_DEBUG:
4517 DPRINTF("kvm_exit_debug\n");
4518 qemu_mutex_lock_iothread();
4519 ret = kvm_handle_debug(cpu, &run->debug.arch);
4520 qemu_mutex_unlock_iothread();
4521 break;
4522 case KVM_EXIT_HYPERV:
4523 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4524 break;
4525 case KVM_EXIT_IOAPIC_EOI:
4526 ioapic_eoi_broadcast(run->eoi.vector);
4527 ret = 0;
4528 break;
4529 default:
4530 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4531 ret = -1;
4532 break;
4533 }
4534
4535 return ret;
4536 }
4537
4538 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4539 {
4540 X86CPU *cpu = X86_CPU(cs);
4541 CPUX86State *env = &cpu->env;
4542
4543 kvm_cpu_synchronize_state(cs);
4544 return !(env->cr[0] & CR0_PE_MASK) ||
4545 ((env->segs[R_CS].selector & 3) != 3);
4546 }
4547
4548 void kvm_arch_init_irq_routing(KVMState *s)
4549 {
4550 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
4551 /* If kernel can't do irq routing, interrupt source
4552 * override 0->2 cannot be set up as required by HPET.
4553 * So we have to disable it.
4554 */
4555 no_hpet = 1;
4556 }
4557 /* We know at this point that we're using the in-kernel
4558 * irqchip, so we can use irqfds, and on x86 we know
4559 * we can use msi via irqfd and GSI routing.
4560 */
4561 kvm_msi_via_irqfd_allowed = true;
4562 kvm_gsi_routing_allowed = true;
4563
4564 if (kvm_irqchip_is_split()) {
4565 int i;
4566
4567 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4568 MSI routes for signaling interrupts to the local apics. */
4569 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
4570 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
4571 error_report("Could not enable split IRQ mode.");
4572 exit(1);
4573 }
4574 }
4575 }
4576 }
4577
4578 int kvm_arch_irqchip_create(KVMState *s)
4579 {
4580 int ret;
4581 if (kvm_kernel_irqchip_split()) {
4582 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4583 if (ret) {
4584 error_report("Could not enable split irqchip mode: %s",
4585 strerror(-ret));
4586 exit(1);
4587 } else {
4588 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4589 kvm_split_irqchip = true;
4590 return 1;
4591 }
4592 } else {
4593 return 0;
4594 }
4595 }
4596
4597 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
4598 uint64_t address, uint32_t data, PCIDevice *dev)
4599 {
4600 X86IOMMUState *iommu = x86_iommu_get_default();
4601
4602 if (iommu) {
4603 int ret;
4604 MSIMessage src, dst;
4605 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
4606
4607 if (!class->int_remap) {
4608 return 0;
4609 }
4610
4611 src.address = route->u.msi.address_hi;
4612 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4613 src.address |= route->u.msi.address_lo;
4614 src.data = route->u.msi.data;
4615
4616 ret = class->int_remap(iommu, &src, &dst, dev ? \
4617 pci_requester_id(dev) : \
4618 X86_IOMMU_SID_INVALID);
4619 if (ret) {
4620 trace_kvm_x86_fixup_msi_error(route->gsi);
4621 return 1;
4622 }
4623
4624 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4625 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4626 route->u.msi.data = dst.data;
4627 }
4628
4629 return 0;
4630 }
4631
4632 typedef struct MSIRouteEntry MSIRouteEntry;
4633
4634 struct MSIRouteEntry {
4635 PCIDevice *dev; /* Device pointer */
4636 int vector; /* MSI/MSIX vector index */
4637 int virq; /* Virtual IRQ index */
4638 QLIST_ENTRY(MSIRouteEntry) list;
4639 };
4640
4641 /* List of used GSI routes */
4642 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4643 QLIST_HEAD_INITIALIZER(msi_route_list);
4644
4645 static void kvm_update_msi_routes_all(void *private, bool global,
4646 uint32_t index, uint32_t mask)
4647 {
4648 int cnt = 0, vector;
4649 MSIRouteEntry *entry;
4650 MSIMessage msg;
4651 PCIDevice *dev;
4652
4653 /* TODO: explicit route update */
4654 QLIST_FOREACH(entry, &msi_route_list, list) {
4655 cnt++;
4656 vector = entry->vector;
4657 dev = entry->dev;
4658 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4659 msg = msix_get_message(dev, vector);
4660 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4661 msg = msi_get_message(dev, vector);
4662 } else {
4663 /*
4664 * Either MSI/MSIX is disabled for the device, or the
4665 * specific message was masked out. Skip this one.
4666 */
4667 continue;
4668 }
4669 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
4670 }
4671 kvm_irqchip_commit_routes(kvm_state);
4672 trace_kvm_x86_update_msi_routes(cnt);
4673 }
4674
4675 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4676 int vector, PCIDevice *dev)
4677 {
4678 static bool notify_list_inited = false;
4679 MSIRouteEntry *entry;
4680
4681 if (!dev) {
4682 /* These are (possibly) IOAPIC routes only used for split
4683 * kernel irqchip mode, while what we are housekeeping are
4684 * PCI devices only. */
4685 return 0;
4686 }
4687
4688 entry = g_new0(MSIRouteEntry, 1);
4689 entry->dev = dev;
4690 entry->vector = vector;
4691 entry->virq = route->gsi;
4692 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4693
4694 trace_kvm_x86_add_msi_route(route->gsi);
4695
4696 if (!notify_list_inited) {
4697 /* For the first time we do add route, add ourselves into
4698 * IOMMU's IEC notify list if needed. */
4699 X86IOMMUState *iommu = x86_iommu_get_default();
4700 if (iommu) {
4701 x86_iommu_iec_register_notifier(iommu,
4702 kvm_update_msi_routes_all,
4703 NULL);
4704 }
4705 notify_list_inited = true;
4706 }
4707 return 0;
4708 }
4709
4710 int kvm_arch_release_virq_post(int virq)
4711 {
4712 MSIRouteEntry *entry, *next;
4713 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4714 if (entry->virq == virq) {
4715 trace_kvm_x86_remove_msi_route(virq);
4716 QLIST_REMOVE(entry, list);
4717 g_free(entry);
4718 break;
4719 }
4720 }
4721 return 0;
4722 }
4723
4724 int kvm_arch_msi_data_to_gsi(uint32_t data)
4725 {
4726 abort();
4727 }
4728
4729 bool kvm_has_waitpkg(void)
4730 {
4731 return has_msr_umwait;
4732 }
AR7 emulation for QEMU